LE75183DDSC [MICROSEMI]

Telecom Circuit, 1-Func, PDSO20, GREEN, PLASTIC, SOIC-20;


型号：	LE75183DDSC
厂家：	Microsemi
描述：	Telecom Circuit, 1-Func, PDSO20, GREEN, PLASTIC, SOIC-20 电信光电二极管电信集成电路
文件：	总26页 (文件大小：470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

™

Le75183

Line Card Access Switch

VE750 Series

Voice Solution

APPLICATIONS

Central office

DLC

PBX

DAML

DESCRIPTION

The VoiceEdge™ family VE750 series of Line Card Access

Switches (LCAS), which includes the Le75181, Le75282 and

Le75183 devices, is a family of monolithic solid-state switches

that is designed to provide both power ringing access and test

access on the analog line card. These devices, while not a pin-

for-pin replacement for the traditional electromechanical relay

(EMR) solution, provide the equivalent switching functionality.

The VE750 series of LCAS is meant as a solid-state alternative

to the EMRs.

HFC/FITL

FEATURES

Small size/surface-mount packaging

Monolithic IC reliability

The Le75183A/B/C/D devices are pin-for-pin compatible with

Legerity’s L7583A/B/C/D devices.

Legerity also offers a range of compatible SLIC devices and

codec/filters that can be used with the VE750 series LCAS for

complete line card solutions that can be used worldwide in

analog line card applications.

Low impulse noise

Make-before-break, break-before-make operation

Clean, bounce-free switching

Low, matched ON-resistance

ORDERING INFORMATION

Built-in current limiting, thermal shutdown, and SLIC

Device

Package Type¹

Packing²

protection

Le75183ADSC

Le75183BDSC

Le75183CDSC

Le75183DDSC

LE75183AFQC

Le75183BFQC

Le75183CFQC

Le75183DFQC

Le75183AFSC

Le75183BFSC

Le75183CFSC

Le75183CZFSC

Le75183DFSC

5-V only operation, very low power consumption

Battery monitor, all OFF state upon loss of battery

No EMI

Latched logic level inputs, no drive circuitry

Only one external protector required

TTL logic control compatible

20-Pin SOIC (GULL)

Tube

Tray

32-Pin QFN

Default power up state

RELATED LITERATURE

28-pin SOIC (GULL)

Tube

081123 Le75282 Dual Intelligent Line Card Access

Switch Data Sheet

081105 Le75181 Ringing Access Switch Data Sheet

080754 Le58QL061/063 QLSLAC Data Sheet

080676 Le5711 Dual SLIC Data Sheet

1. The green package meets RoHS Directive 2002/95/EC of the

European Council to minimize the environmental impact of

electrical equipment.

081047 Le5712 Dual SLIC Data Sheet

2. For delivery using a tape and reel packing system, add a "T" suffix

to the OPN (Ordering Part Number) when placing an order.

Document ID# 081105 Date:

Sep 18, 2007

NOTE: On August 3, 2007, Zarlink Semiconductor acquired the products and

technology of Legerity Holdings.

Rev:

Version:

Distribution:

Public Document

Le75183

Data Sheet

TABLE OF CONTENTS

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Descriptions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Handling Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Summary of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Zero Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Loss of Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Impulse Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Integrated SLIC Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

28-Pin, Plastic SOIC (GULL) (Le75183AESC/BESC/CESC/CZESC/DESC) . . . . . . . . . . . . . . . .22

20-Pin, Plastic SOIC (GULL) (Le75183ASC/BSC/CSC/DSC). . . . . . . . . . . . . . . . . . . . . . . . . . . .23

32-Pin QFN (Le75183QC/BEQC/CQC/DQC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Revision C1 to C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Zarlink Semiconductor Inc.

Le75183

Data Sheet

PRODUCT DESCRIPTION

The Le75183A/B/C/D Line Card Access Switch is a monolithic solid-state device providing the equivalent switching functionality

of three 2 form C switches. The Le75183 is designed to provide power ringing access, line test access (test out), and SLIC test

access (test in) to tip and ring in central office, digital loop carrier, private branch exchange, digitally added main line, and hybrid

fiber coax/fiber-in-the-loop analog line card applications. An additional pair of solid-state contacts are also available to provide

access for testing of the ringing generator.

The Le75183A/B has seven states: the idle talk state (line break switches closed, all other switches open), the power ringing state

(ringing access switches closed, all other switches open), loop access (test out) state (loop access (test out) switches closed, all

other switches open), SLIC test state (test in switches closed, all other switches open), simultaneous loop and SLIC access state

(loop and test in switches closed, all others open), ringing generator test state (ring test switches closed, all others open), and

an all OFF state. The seven states in the Le75183A/B are also in the Le75183C/D, with an additional simultaneous test-out and

ring-test state, making the Le75183C/D appropriate for digital loop carrier and other Telcordia TR-57 applications.

The Le75183 offers break-before-make or make-before-break switching, with simple logic level input control. Because of the

solid-state construction, voltage transients generated when switching into an inductive ringing lead during ring cadence or ring

trip are minimized, possibly eliminating the need for external zero cross switching circuitry. State control is via logic level inputs,

so no additional driver circuitry is required.

The line break switch is a linear switch that has exceptionally low ON-resistance and an excellent ON-resistance matching

characteristic. The ringing access switch has a breakdown voltage rating >480 V which is sufficiently high, with proper protection,

to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator).

Incorporated into the Le75183A and Le75183C is a diode bridge/SCR clamping circuit, current-limiting circuitry, and a thermal

shutdown mechanism to provide protection to the SLIC device and subsequent circuitry during fault conditions. This is shown in

block diagram as version A/C. Positive and negative lightning is reduced by the current-limiting circuitry and steered to ground

via diodes and the integrated SCR. Power cross is also reduced by the current-limiting and thermal shutdown circuits.

The Le75183B and Le75183D versions provide only an integrated diode bridge along with current limiting and thermal shutdown

(see block diagram for version B/D). This will cause positive faults to be directed to ground and negative faults to battery. In either

polarity, faults are reduced by the current-limit and/or thermal shutdown mechanisms.

To protect the Le75183 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector

must limit the voltage seen at the tip/ring terminals to prevent the breakdown voltage of the switches from being exceeded. To

minimize stress on the solid-state contacts, use of a foldback- or crowbar- type secondary protector is recommended. With proper

choice of secondary protection, a line card using the Le75183 will meet all relevant ITU-T, LSSGR, FCC, or UL* protection

requirements.

The Le75183 operates off of a 5-V supply only. This gives the device extremely low idle and active power dissipation and allows

use with virtually any range of battery voltage. This makes the Le75183 especially appropriate for remote power applications

such as DAML or FOC/FITL or other Telcordia TA 909 applications where power dissipation is particularly critical.

A battery voltage is also used by the Le75183, only as a reference for the integrated protection circuit. The Le75183 will enter an

all OFF state upon loss of battery.

During power ringing, to turn on and maintain the ON state, the ring access switch and ring test switch will draw a nominal 2 mA

from the ring generator.

The default power up state of Le75183 is in all OFF state, unless otherwise being overwritten by external controls.

The Le75183 device is packaged in a 20-pin, plastic SOIC (GULL) (Le75183ASC/BSC/CSC/DSC), a 32-pin QFN (Le75183AQC/

BQC/CQC/DQC), and a 28-pin, plastic SOIC (GULL) (Le75183AESC/BESC/CESC/CZESC/DESC). The 28-pin package is

available to support existing designs. For new designs, it may be advantageous to use the other two packages for smaller in size.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

BLOCK DIAGRAMS

Figure 1. Le75183A/C

Le75183A/C

VBAT

FGND

SCR

& Trip

Circuit

SW1

SW2

SW6

RTESTin

RBAT

TTESTin

TBAT

SW3

SW4

RLINE

TLINE

SW5

TRINGING

RRINGING

SW7

SW8

RTESTout

LATCH

TTESTout

SW10

SW9

INTESTin

INRING

VDD

TSD

Control

Logic

INTESTout

DGND

Figure 2. Le75183B/D

Le75183B/D

VBAT

FGND

SW1

SW2

SW6

RTESTin

RBAT

TTESTin

TBAT

SW3

SW5

SW4

RLINE

TLINE

RRINGING

TRINGING

SW7

SW8

RTESTout

LATCH

TTESTout

SW9

SW10

INTESTin

INRING

VDD

TSD

Control

Logic

INTESTout

DGND

Zarlink Semiconductor Inc.

Le75183

Data Sheet

CONNECTION DIAGRAMS

Top View

32 31 30 29 28 27 26 25

RBAT

TBAT

RLINE

TLINE

32-pin QFN

RRINGING

TRINGING

EXPOSED PAD

RTESTout

TTESTout

10 11 12 13 14 15 16

FGND

VBAT

FGND

TTESTin

TBAT

VBAT

RTESTin

RBAT

TLINE

RLINE

TTESTin

TBAT

RTESTin

RBAT

RLINE

TRINGING

TTESTout

RRINGING

RTESTout

LATCH

20-Pin SOIC

TLINE

TRINGING

28-Pin SOIC

VDD

INTESTin

INRING

TSD

RRINGING

DGND

INTESTout

TTESTout

RTESTout

LATCH

VDD

INTESTin

INRING

TSD

DGND

INTESTout

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Pin Descriptions .

Pin Name

DGND

FGND

INRING

Type

Ground

Input

Description

Digital ground.

Fault ground.

Logic level switch input control. Internally 75 kΩ typical pull up.

Logic level switch input control. Internally 75 kΩ typical pull down.

Logic level switch input control. Internally 75 kΩ typical pull up.

Input

INTESTIN

INTESTOUT

LATCH

Input

—

Data input control, active-high, transparent low. Internally 75 kΩ typical pull down.

No connection.

RBAT

RLINE

RRINGING

RTESTin

RTESTout

TBAT

Input/Output

Connect to RING on SLIC side.

Connect to RING on line side.

Connect to ringing generator.

Test (in) access on RING.

Test (out) access on RING.

Connect to TIP on SLIC side.

Connect to TIP on line side.

Connect to return ground for ringing generator.

Test (in) access on TIP.

Test (out) access on TIP.

TLINE

TRINGING

TTESTin

TTESTout

Temperature shutdown pin. Can be used as a logic level input or an output. See Tables 12

and 13, Truth Tables, and the Switching Behavior section of this data sheet for input pin

description. As an output flag, will read HIGH when the device is in its operational mode

and LOW in the thermal shutdown mode. To disable the thermal shutdown mechanism, tie

this pin to HIGH (not recommended)

TSD

Input/Output

VBAT

VDD

Battery

Power

Battery voltage. Used as a reference for protection circuit.

5 V supply.

Exposed pad in QFN package. No internal electrical connection. Not recommended to

make any external electrical connection (such as VBAT or ground) to the EPAD.

EPAD

—

D: Internally 75 kΩ typical pull down.

U: Internally 75 kΩ typical pull up.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above

these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

Parameter

Operating Temperature Range

Storage Temperature Range

Relative Humidity Range

Pin Soldering Temperature (t=10s max)

5 V Power Supply

Min

–40

Max

110

150

260

–85

VDD+0.3

330

480

260

Unit

°C

—

-0.3

—

-0.3

—

Battery Supply

Logic Input Voltage

Input-to-output Isolation

Pole-to-pole Isolation (All except SW6, SW8)

Pole-to-pole Isolation (Ringing Access Switch, SW8)

Pole-to-pole Isolation (Ringing Test Swtich, SW6)

ESD Immunity (Human Body Model)

—

JESD22 Class 1C compliant

Note:

For LCAS in the QFN package, it is desirable that the exposed pad be soldered to an equally sized exposed copper surface (with no

further electrical connection such as VBAT or ground) for mechanical stability.

OPERATING RANGES

Package Assembly

Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free

materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-

free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.

Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.

Environmental Ranges

Legerity guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges

by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to

periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component

Reliability Assurance Requirements for Telecommunications Equipment.

Ambient Temperature

−40° to 85°C

Electrical Ranges

Supply

Min

4.5

Typ

Max

5.5

Unit

–19

—

–72

BAT

*VBAT is used only as a reference for internal protection circuitry. If VBAT rises above typically –10 V, the device will enter an all OFF state and

remain in this state until the battery voltage drops below typically –15 V.

*Applied voltage is 100 Vp-p square wave at 100 Hz.

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to elec-

trostatic discharge (ESD) during handling and mounting. Legerity employs a human-body model (HBM) and a charged-device

model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the

circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM

(resistance = 1500Ω , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD

threshold presented here was obtained by using these circuit parameters.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

ELECTRICAL CHARACTERISTICS

Summary of Assumptions

Unless otherwise noted, the test conditions are defined by the Le75183 device application circuit shown in Figure 8, on page 19

with:

V_BAT= −48 V, V_DD= 5.0 V.

Supply Currents and Power Dissipation

_DDmA

I_BATµA

Typ

LCAS Device Power mW

Operational State

Condition

Min.

Typ

Max

Min.

Max

Min.

Typ

Max

All OFF

VDD=5V, VBAT=-48V

—

0.760

1.1

—

3.8

Power Ringing or

Access

Idle/Talk

VDD=5V, VBAT=-48V

—

0.850

0.860

2.1

1.3

—

4.4

4.5

SPECIFICATIONS

Device Specifications

Table 1. Test-In Switches, 1 and 2

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

OFF-state Leakage Current:

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

I_SWITCH

+25°C

+85°C

–40°C

—

µA

ON-resistance (SW1, SW2):

+25 °C

+85 °C

I_SWITCH(on) = ±5 mA, ±10 mA

—

∆ VON

_SWITCH(on) = ±5 mA, ±10 mA

Ω

–40 °C

—

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

—

200

—

V/µs

dV/dt Sensitivity

*Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 2. Break Switches, 3 and 4

Parameter

Test Condition

Measure

Min

Typ Max

Unit

OFF-state Leakage Current:

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

I_SWITCH

+25°C

—

+85°C

–40°C

µA

ON-resistance (SW3, SW4):

+25 °C

—

21.5

—

TLINE = ±10 mA, ±40 mA, TBAT = –2 V

∆ VON

+85 °C

–40 °C

Ω

ON-resistance Match

All except Le75183CZESC

ON-resistance Match

Le75183CZESC

ON-state Voltage*

(Figure 2, Switch 3)

Magnitude

Per ON-resistance test condition of SW3, SW4

—

0.2

—

1.0

0.55

220

Ω

R^ON_SW3– RON_SW4

Magnitude

R^ON_SW3– RON_SW4

Per ON-resistance test condition of SW3, SW4

Iswitch = I_LIMIT@ 50 Hz/60 Hz

VON

Maximum Differential Voltage (Vmax)

Foldback Voltage Breakpoint 1 (V1)

Foldback Voltage Breakpoint 2 (V2)

—

100

V1+0.5

—

320

—

VON

ON-state Voltage*

(Figure 3, Switch 4)

DC Current Limit

(Figure 2, Switch 3):

+85 °C

—

250

Vswitch (on) = ±10 V

I_LIMIT1

I_LIMIT2

Iswitch

–40 °C

DC Current Limit

(Figure 3, Switch 4):

Iswitch

—

Break switches in ON state; ringing access

switches off; apply ±1000 V at 10/1000 µs pulse;

appropriate secondary protection in place

Dynamic Current Limit

(t = <0.5 µs)

Iswitch

—

2.5

—

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

dV/dt Sensitivity^†

—

200

—

V/µs

*This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

†Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 3. Ring Test Return Switch, 5

Parameter

Test Condition

Measure

Min

Typ

Max Unit

OFF-state Leakage Current:

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 V to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 V to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

Iswitch (on) = ±0 mA, ±10 mA

I_SWITCH

+25°C

—

+85°C

–40°C

µA

I_SWITCH

—

ON-resistance

Isolation:

∆ VON

100

Ω

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

—

µA

dV/dt Sensitivity*

200

—

V/µs

*Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 4. Ringing Test Switch, 6

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

OFF-state Leakage Current:

Vswitch (differential) = –60 to +190 V

Vswitch (differential) = +60 to –190 V

Vswitch (differential) = –60 to +200 V

Vswitch (differential) = +60 to –200 V

Vswitch (differential) = –60 to +180 V

Vswitch (differential) = +60 to –180 V

Iswitch (on) = ±70 mA, ±80 mA

Iswitch (on) = ±1 mA

I_SWITCH

+25°C

—

+85°C

–40°C

µA

ON-resistance

ON Voltage

Steady-state Current*

Release Current

Isolation:

∆ VON

—

1.5

100

—

Ω

µA

—

500

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

dV/dt Sensitivity^†

—

200

—

V/µs

*Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.

†Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Table 5. Ring Return Switch, 7

Parameter

Test Condition

Measure

Min

Typ Max Unit

OFF-state Leakage Current:

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 to +250 V

Vswitch (on) = ±20 V

I_SWITCH

+25°C

+85°C

–40°C

—

µA

DC Current Limit

ON-resistance

ON-state Voltage*

Isolation:

Iswitch

∆ VON

VON

—

200

—

100

130

Ω

Iswitch (on) = ±0 mA, ±10 mA

Iswitch = ILIMIT @ 50 Hz/60 Hz

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

†

—

200

—

V/µs

dV/dt Sensitivity

*This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

†Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 6. Ringing Access Switch, 8

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

OFF-state Leakage Current:

Vswitch (differential) = –255 to +210 V

Vswitch (differential) =+255 to –210 V

Vswitch (differential) = –270 to +210 V

Vswitch (differential) = +270 to –210 V

Vswitch (differential) = –245 to +210 V

Vswitch (differential) = +245 to –210 V

Iswitch (on) = ±1 mA

I_SWITCH

—

+25°C

—

+85°C

µA

–40°C

—

ON Voltage

VCC = 5 V

INRING = 1

INTESTin = 0

Ring Generator Current

During Ring

IRINGSOURCE

—

INTESTout = 0

—

150

Steady-state Current

Surge Current

Release Current

ON-resistance

Isolation:

—

∆ VON

—

500

—

µA

Ω

Iswitch (on) = ±70 mA, ±80 mA

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

†

—

200

—

V/µs

dV/dt Sensitivity

*Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.

†Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Table 7. Loop Access (Test Out) Switches, 9 and 10

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

OFF-state Leakage Current:

Vswitch (differential) = –320 V to Gnd

Vswitch (differential) = –60 to +260 V

Vswitch (differential) = –330 V to Gnd

Vswitch (differential) = –60 to +270 V

Vswitch (differential) = –310 V to Gnd

Vswitch (differential) = –60 V to +250 V

I_SWITCH

+25°C

+85°C

–40°C

—

µA

ON-resistance:

+25 °C

—

Iswitch (on) = ±5 mA, ±10 mA

∆ Von

+85 °C

–40 °C

ON-state Voltage*

DC Current Limit:

+85 °C

Ω

Iswitch = ILIMIT @ 50 Hz/60 Hz

VON

130

—

250

Vswitch (on) = ±10 V

Iswitch

–40 °C

Break switches in ON state; ringing access switches OFF;

apply ±1000 V at 10/1000 µs pulse; appropriate secondary

protection in place

Dynamic Current Limit

(t = <0.5 µs)

Iswitch

—

2.5

—

Isolation:

+25 °C

+85 °C

–40 °C

Vswitch (both poles) = ±320 V, Logic inputs = Gnd

Vswitch (both poles) = ±330 V, Logic inputs = Gnd

Vswitch (both poles) = ±310 V, Logic inputs = Gnd

—

Iswitch

µA

†

—

200

—

V/µs

dV/dt Sensitivity

*This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.

†Applied voltage is 100 Vp-p square wave at 100 Hz. Not tested in production.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 8. Additional Electrical Characteristics

Parameter

Digital Input Characteristics:

Test Condition

Measure

Min

Typ

Max Unit

Input Low Voltage

Input High Voltage

—

2.2

—

0.8

—

VDD = 5.5 V, VBAT = –75 V,

Vlogicin = 5 V

VDD = 5.5 V, VBAT = –75 V,

Vlogicin = 0 V

VDD = 5.5 V, VBAT = –58 V,

Vlogicin = 5 V

VDD = 5.5 V, VBAT = –58 V,

Vlogicin = 0 V

VDD = 5.5 V, VBAT = –58 V,

Vlogicin = 5 V

VDD = 5.5 V, VBAT = –58 V,

Vlogicin = 0 V

Input Leakage Current (high)

Input Leakage Current (low)

llogicin

—

500

—

Input Leakage Current (high)

INTESTOUT, INRING

Input Leakage Current (low)

INTESTOUT, INRING

Input Leakage Current (high)

INTESTIN, LATCH

Input Leakage Current (low)

INTESTIN, LATCH

0.5

100

0.5

µA

—

Temperature Shutdown Requirements*:

Shutdown Activation Temperature

Shutdown Circuit Hysteresis

—

110

125

—

150

°C

*Temperature shutdown flag (TSD) will be HIGH during normal operation and LOW during temperature shutdown state.

ZERO CROSS CURRENT TURN OFF

The ring access switch (SW8) is designed to turn off on the next zero current crossing after application of the appropriate logic

input control. This switch requires a current zero cross to turn off. Switch 8, once on, will remain in the ON state (regardless of

logic input) until a current zero cross. Therefore, to ensure proper operation of switch 8, this switch should be connected, via

proper impedance, to the ringing generator or some other ac source. Do not attempt to switch pure DC with switch 8. The ringing

test access switch, SW6, also has similar characteristics to switch 8 and should also only be used to switch signals with zero

current crossings.

For a detailed explanation of the operation of switches 6 and 8, please refer to the An Introduction to Le758X Series of Line Card

Access Switches application note.

SWITCHING BEHAVIOR

When switching from the power ringing state to the idle/talk state via simple logic level input control, the Le75183 is able to provide

control with respect to the timing when the ringing access contacts are released relative to the state of the line break contacts.

Make-before-break operation occurs when the line break switch contacts are closed (or made) before the ringing access switch

contact is opened (or broken). Break-before-make operation occurs when the ringing access contact is opened (broke) before

the line break switch contacts are closed (made).

Using the logic level input pins INRING, INTESTin, and INTESTout, either make-before-break or break-before-make operation of

the Le75183 is easily achieved. The logic sequences for either mode of operation are given in Table 13 and Table 14. See the

Truth Tables (Table 16 and Table 17) for an explanation of logic states.

When using an Le75183 in the make-before-break mode, during the ring-to-idle transition, for a period of up to one-half the

ringing frequency, the ring break switch and the pnpn-type ring access switch can both be in the ON state. This is the maximum

time after the logic signal at INRING has transitioned that the ring access switch is waiting for the next zero current cross, so it

can close. During this interval, current that is limited to the dc break switch current-limit value will be source from the ring node

of the SLIC.

This current is presented to the internal protection circuit. If the SCR-type protector is used (A or C codes), if by random probability

the ring-to-idle transition occurs during a portion of the ring cycle when the ringing voltage exceeds the protection circuit SCR

turn-on voltage, and if current in excess of the SCR’s turn-on current is also available, the SCR may turn on. Once the SCR is

triggered on, if the SLIC is capable of supplying current in excess of the holding current, the SCR may be latched on by the SLIC.

The probability of this event depends on the characteristics of the given SLIC and of the holding current of the Le75183 A or C

device. The SCR hold current distribution is designed to be safely away from the test limit of 80 mA. The higher the distribution,

the lower the probability of the latch.

If this situation is of concern for a given board design, either use the A or C series device in the break-before-make mode

(eliminates the original 25 ms current pulse) or use a B or D series device (eliminates the SCR).

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 9. Make-Before-Break Operation

Break

Switches

3 & 4

Ring

Access

All Other

Return

Access

INRING

INTESTin

INTESTout

TSD

State

Timing

Switch 7 Switch 8 Switches

Power

1/Float

—

Open

Closed

Open

Closed

Open

Ringing

SW8 waiting for next zero

current crossing to turn off

maximum time—one-half

of ringing. In this transition

state, current that is limited

to the dc break switch

current-limit value will be

sourced from the ring node

of the SLIC.

Make-

1/Float before-

break

Zero cross current has

occurred.

1/Float Idle/Talk

Table 10. Break-Before-Make Operation

Break

Switches

3 & 4

Ring

Return

Switch 7

Access

Switch 8

All Other

Switches

INRING

INTESTin

INTESTout

TSD

State

Timing

Power

Ringing

1/Float

—

Open

Closed

Open

Hold this state for

≤25 ms. SW8 waiting for

zero current to turn off.

1/Float All Off

Open

Closed

Open

Zero current has occurred

and SW8 has opened.

Release break switches.

1/Float All Off

Open

1/Float Idle/Talk

Closed

Notes:

Break-before-make operation can be achieved using TSD as an input. In lines two and three of Table 10, instead of using the logic input pins to

force the all OFF state, force TSD to logic 0. This will override the logic inputs and also force the all OFF state. Hold this state for 25 ms. During

this 25 ms all OFF state, toggle the inputs from 10 (ringing state) to 00 (idle/talk state). After 25 ms, release TSD to return switch control to the

input pins which will set the idle talk state.

When using the Le75183A/B/C/D in this mode, forcing TSD to logic 0 will override the INPUT pins and force an all OFF state. Setting TSD to logic

1 will allow switch control via the logic INPUT pins. However, setting TSD to logic 1 will also disable the thermal shutdown mechanism. This is

not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float.

Thus, when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all OFF state) and float (allows switch

control via logic input pins and thermal shutdown mechanism is active). This may require use of an open-collector buffer.

Also note that TSD operation in Le75183 is different than TSD operation of the L75181, where application of logic 1 does not disable the thermal

shutdown mechanism.

POWER SUPPLIES

Though both the 5-V and battery supplies are brought onto the Le75183 device, only the 5-V supply is required for switch

operation; that is, state control is powered exclusively off of the 5-V supply. Because of this, the Le75183 device offers extremely

low power dissipation, both in the Idle and Active states.

The battery voltage is not used for switch state control, but rather as a reference voltage by the integrated secondary protection

circuit. When the voltage at TBAT or RBAT drops 2 V to 4 V below the battery, the integrated SCR will trigger, thus preventing

fault-induced overvoltage situations at the TBAT/RBAT nodes.

LOSS OF BATTERY VOLTAGE

As an additional protection feature, the Le75183 device monitors the battery voltage. Upon loss of battery voltage, the Le75183

will automatically enter an all OFF state and remain in that state until the battery voltage is restored. The Le75183 is designed so

that the device will enter the all OFF state if the battery rises above typically –10 V and will remain off until the battery drops below

typically –15 V.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Monitoring the battery for the automatic shutdown feature will draw a small current from the battery, typically 4 µA. This will add

slightly to the overall power dissipation of the device.

IMPULSE NOISE

Using the Le75183 will minimize and possibly eliminate the contribution to the overall system impulse noise that is associated

with ringing access switches. Because of this characteristic of the Le75183 device, it may not be necessary to incorporate a zero

cross switching scheme. This ultimately depends upon the characteristics of the individual system and is best evaluated at the

board level.

PROTECTION

Integrated SLIC Device Protection

Diode Bridge/SCR

In the Le75183A and the Le75183C versions, protection to the SLIC device or other subsequent circuitry is provided by a

combination of current-limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism. In the

Le75183B and the Le75183D versions, protection to the SLIC device or other subsequent circuitry is provided by a combination

of current-limited break switches, a diode bridge, and a thermal shutdown mechanism.

In both protection versions, during a positive lightning event, fault current is directed to ground via steering diodes in the diode

bridge. Voltage is clamped to a diode drop above ground. In the A version, negative lightning causes the SCR to conduct when

the voltage goes 2 V to 4 V more negative than the battery. Fault currents are then directed to ground via the SCR and steering

diodes in the diode bridge.

Note that for the SCR to foldback or crowbar, the ON voltage (see Table 14) of the SCR must be less negative than the battery

reference voltage. If the battery voltage is less negative than the SCR ON voltage, the SCR will conduct fault currents to ground;

however, it will not crowbar.

In the B/D version, negative lightning is directed to battery via steering diodes in the diode bridge.

For power cross and power induction faults, in both protection versions, the positive cycle of the fault is clamped a diode drop

above ground and fault currents steered to ground. In the A/C version, the negative cycle will cause the SCR to trigger when the

voltage exceeds the battery reference voltage by 2 V to 4 V. When the SCR triggers, fault current is steered to ground. In the B/

D version, the negative cycle of the power cross is steered to battery.

Current Limiting

During a lightning event, the current that is passed through the break switches and presented to the integrated protection circuit

and subsequent circuitry is limited by the dynamic current-limit response of the break switches (assuming idle/talk state). When

the voltage seen at the TLINE/RLINE nodes is properly clamped by an external secondary protector, upon application of a 1000

V, 10 x 1000 pulse (LSSGR lightning), the current seen at the TBAT/RBAT nodes will typically be a pulse of magnitude 2.5 A and

duration less than 0.5 µs.

During a power cross event, the current that is passed through the break switches and presented to the integrated protection

circuit and subsequent circuitry is limited by the dc current-limit response of the break switches (assuming idle/talk state). The dc

current limit is specified over temperature between 100 mA and

250 mA. Note that the current-limit circuitry has a negative temperature coefficient. Thus, if the device is subjected to an extended

power cross, the value of current seen at TBAT/RBAT will decrease as the device heats due to the fault current. If sufficient

heating occurs, the temperature shutdown mechanism will activate and the device will enter an all off mode.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Temperature Shutdown Mechanism

When the device temperature reaches a minimum of 110 °C, the thermal shutdown mechanism will activate and force the device

into an all OFF state, regardless of the logic input pins. Pin TSD, when used as an output, will read LOW when

the device is in the thermal shutdown mode and HIGH during normal operation.

During a lightning event, due to the relatively short duration, the thermal shutdown will not typically activate.

During an extended power cross, the device temperature will rise and cause the device to enter the thermal shutdown mode. This

forces an all off mode, and the current seen at TBAT/RBAT drops to zero. Once in the thermal shutdown mode, the device will

cool and exit the thermal shutdown mode, thus reentering the state it was in prior to thermal shutdown. Current, limited to the dc

current-limit value, will again begin to flow and device heating will begin again. This cycle of entering and exiting thermal shutdown

will last as long as the power cross fault is present. The frequency of entering and exiting thermal shutdown will depend on the

magnitude of the power cross. If the magnitude of the power cross is great enough, the external secondary protector may trigger

shunting all current to ground.

In the Le75183, the thermal shutdown mechanism can be disabled by forcing the TSD pin to HIGH. This functionality is different

from the Le75181, whose thermal shutdown mechanism cannot be disabled.

Electrical specifications relating to the integrated overvoltage clamping circuit are outlined in Table 15.

External Secondary Protector

With the above integrated protection features, only one overvoltage secondary protection device on the loop side of the Le75183

is required. The purpose of this device is to limit fault voltages seen by the Le75183 so as not to exceed the breakdown voltage

or input-output isolation rating of the device. To minimize stress on the Le75183, use of a foldback- or crowbar-type device is

recommended. A detailed explanation and design equations on the choice of the external secondary protection device are given

in the An Introduction to Le758X Series of Line Card Access Switches application note. Basic design equations governing the

choice of external secondary protector are given below.

•

|Vringingpeakmax| + |VBATmax| + |Vbreakovermax| < |Vbreakdownmin(ring)|

where:

VBATmax—Maximum magnitude of battery voltage.

Vbreakovermax—Maximum magnitude breakover voltage of external secondary protector.

Vbreakovermin—Minimum magnitude breakover voltage of external secondary protector.

Vbreakdownmin(break)—Minimum magnitude breakdown voltage of Le75183 break switch.

Vbreakdownmin(ring)—Minimum magnitude breakdown voltage of Le75183 ring access switch.

Vringingpeakmax—Maximum magnitude peak voltage of ringing signal.

Series current-limiting fused resistors or PTC resistors should be chosen so as not to exceed the current rating of the external

secondary protector. Refer to the manufacturer’s data sheet for specifications.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 11. Electrical Specifications, Protection Circuitry

Parameters Related to Diodes (in Diode Bridge)

Parameter

Test Condition

Measure

Min

Typ

Max

Unit

Voltage Drop at Continuous Current

(50 Hz/60 Hz)

Apply ±dc current limit of

break switches

Apply ±dynamic current

limit of break switches

Forward

Voltage

Forward

Voltage

—

3.5

—

Voltage Drop at Surge Current

—

Parameters Related to Protection SCR

‡

Surge Current

—

†

—

Gate Trigger Current*

†

Gate Trigger Current Temperature

—

–0.5

—

%/°C

Coefficient

Hold Current

_BAT– 4

—

V_BAT– 2

Gate Trigger Voltage

Trigger current

—

V_BAT

Reverse Leakage Current

—

1.0

µA

—

0.5 A, t = 0.5 µs

2.0 A, t = 0.5 µs

VON

—

–3

–5

—

ON-State Voltage^§

* Trigger Current is defined as the minimum current drawn from tip and ring to turn on the SCR. The specification in this data sheet is Gate

Trigger Current, which is defined as the maximum current that can flow into the battery before the SCR turns on.

† Typical at 25 °C

‡ Twice ± dynamic current limit of break switches.

§ In some instances, the typical ON-state voltage can range as low as –25 V.

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. Protection Circuits

Le75183B/D

Le75183A/C

dc CURRENT-LIMIT

BREAK SWITCHES

dc CURRENT-LIMIT

BREAK SWITCHES

– 2

VB^BAAT^T– 4

VBAT – 3

VBAT

VON

<1 µA

3 V

50 mA

dc CURRENT LIMIT

(OF BREAK SWITCHES)

dc CURRENT LIMIT

(OF BREAK SWITCHES)

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Figure 4. Switches 3, 7, 9, and 10

CURRENT

LIMITING

ILIMIT

2/3 RON

RON

1.5 V

–1.5 V

–V

RON

2/3 RON

ILIMIT

CURRENT

LIMITING

–I

Figure 5. Switch 4

ISW

ILIM1

2/3 R^ON

ILIM2

–VMAX –V2 –V1

–ILIM2

–1.5

RON

VSW

1.5

V2 VMAX

–I^LIM1

Figure 6. Switches 1, 2, and 5

2/3 RON

RON

1.5 V

–1.5 V

–V

RON

2/3 RON

–I

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Figure 7. Switches 6, 8

RON

–VOS

+VOS

–V

–I

APPLICATION

Figure 8. Typical LCAS Application, A/C Versions, Idle or Talk State Shown

VBAT

(Reference)

Ringing

Test Return

SW5

SW9

Test Out

SW7

Ringing

SW1

Test In

TIP

Return

TIP

SW3 Break

SCR

& Trip

Circuit

Crowbar

Protection

Battery Feed

RING

SW4 Break

SW8

Ringing

Access

RING

SW10

Test Out

SW2

Test In

SW6

Ringing Test

Ring

Generator

Battery

*Contact a Legerity Sales/Application representative for recommendations.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 12. Truth Table for the Le75183A/B Devices

TESTin

Break

Ring Test

Switches

Ring

TESTout

Switches

INRING

INTESTin

INTESTout

TSD

Switches

1/Float¹

1Float¹

0²

Off³

On⁴

Off⁵

Off⁶

Off⁷

On⁸

Off^{9, 10}

Off⁹

Off

Don’t Care Don’t Care Don’t Care

1. If TSD is logic 1, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.

2. Forcing TSD to logic 0 overrides the logic input pins and forces an all OFF state.

3. Idle/Talk state.

4. TESTout state.

5. TESTin state

6. Power ringing state.

7. Ringing generator test state.

8. Simultaneous TESTout and TESTin state.

9. All OFF state.

10. Default power up state.

A parallel in/parallel out data latch is integrated into the Le75183A/B. Operation of the data latch is controlled by the logic level

input pin LATCH. The data input to the latch is the INPUT pin of the Le75183A/B, and the output of the data latch is an internal

node used for state control.

When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through

the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.

When the LATCH control pin is at logic 1, the data latch is active—the Le75183A/B will no longer react to changes at the INPUT

control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH

input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.

Note that the TSD input is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override state control

via INPUT and LATCH.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

Table 13. Truth Table for the Le75183C/D Devices

TESTin

Break

Ring Test

Switches

Ring

TESTout

Switches

INRING

INTESTin

INTESTout

TSD

Switches

1/Float¹

Off³

On⁴

Off⁵

Off⁶

Off⁷

On⁸

Off^{9, 11}

On¹⁰

Off

Don’t

Care

Don’t

Care

0²

Off⁹

Don’t Care

Off

1. If TSD is logic 1, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.

2. Forcing TSD to logic 0 overrides the logic input pins and forces an all OFF state.

3. Idle/Talk state.

4. TESTout state.

5. TESTin state

6. Power ringing state.

7. Ringing generator test state.

8. Simultaneous TESTout and TESTin state.

9. All OFF state.

10. Simultaneous TESTout—Ring Test state.

11. Default power up state.

A parallel in/parallel out data latch is integrated into the Le75183C/D. Operation of the data latch is controlled by the logic level

input pin LATCH. The data input to the latch is the INPUT pin of the Le75183C/D and the output of the data latch is an internal

node used for state control.

When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through

the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.

When the LATCH control pin is at logic 1, the data latch is active; the Le75183C/D will no longer react to changes at the INPUT

control pin. The state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH

input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.

Note that the TSD input is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override state control

via INPUT and LATCH.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

PHYSICAL DIMENSIONS

28-Pin, Plastic SOIC (GULL) (Le75183AESC/BESC/CESC/CZESC/DESC)

Small Outline Package (28 SOIC)

Millimeter

Nom

2.54

Inch

Nom

0.100

0.006

0.016

0.010

0.295

0.050 BSC

0.406

0.020

0.028

Symbol

Min

2.35

0.10

0.33

0.23

7.40

Max

2.65

0.30

0.51

0.32

7.60

Min

Max

0.104

0.012

0.020

0.012

0.299

0.092

0.004

0.013

0.009

0.291

0.17

0.42

0.25

7.50

1.27 BSC

10.30

0.50

10.00

0.25

0.40

0 deg

0.00

17.70

10.65

0.75

1.27

8 deg

0.01

18.10

0.394

0.009

0.015

0 deg

0.000

0.697

0.419

0.029

0.050

8 deg

0.004

0.712

0.70

17.90

0.705

NOTE:

Option: Square dotted line is E-Pad outline

Size dependent on die attach pad

28-Pin SOIC

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

20-Pin, Plastic SOIC (GULL) (Le75183ASC/BSC/CSC/DSC)

Small Outline Package (20 SOIC)

Millimeter

Inch

Nom

0.100

0.006

0.016

0.010

0.295

0.050 BSC

0.406

0.020

0.028

Symbol

Min

2.35

0.10

0.33

0.23

7.40

Nom

2.54

0.17

0.42

0.25

Max

2.65

0.30

0.51

0.32

7.60

Min

Max

0.104

0.012

0.020

0.012

0.299

0.092

0.004

0.013

0.009

0.291

7.50

1.27 BSC

10.30

0.50

10.00

0.25

0.40

0 deg

0.00

12.60

10.65

0.75

1.27

8 deg

0.01

13.00

0.394

0.009

0.015

0 deg

0.000

0.496

0.419

0.029

0.050

8 deg

0.004

0.512

0.70

12.80

0.504

NOTE:

Option: Square dotted line is E-Pad outline

Size dependent on die attach pad

20-Pin SOIC

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le75183

32-Pin QFN (Le75183QC/BEQC/CQC/DQC)

Data Sheet

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

32 LEAD QFN

Nom

Symbol

Min

Max

2. All dimensions are in millimeters.

3. N is the total number of terminals.

is in degrees.

0.80

0.90

1.00

0.57 REF

0.23

The Terminal #1 identifier and terminal numbering convention

0.18

5.70

0.43

0.00

0.28

5.90

0.63

0.05

shall conform to JEP 95-1 and SSP-012. Details of the erminal #1

8.00 BSC

5.80

identifier are optional, but must be located within the zone

indicated. The Terminal #1 identifier may be either a mold or

marked feature.

8.00 BSC

5.80

5. Coplanarity applies to the exposed pad as well as the terminals.

6. Reference Document: JEDEC MO-220.

7. Lead width deviates from the JEDEC MO-220 standard.

0.80 BSC

0.53

aaa

bbb

ccc

0.02

0.20 REF

0.20

0.10

32-Pin QFN

Note:

Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the

device. Markings will vary with the mold tool used in manufacturing.

Zarlink Semiconductor Inc.

Le75183

Data Sheet

REVISION HISTORY

Revision A1 to B1

•

Added new product offering, Le75183CZESC.

Page 10, Table 5 Ring Return Switch DC Current Limit test condition from Vswitch(on)=+/-10V to +/-20V.

Page 5, Pin Descriptions about EPAD, from "internally connected to digital ground" to "no internal electrical connection".

Revision B1 to C1

•

Added green package OPNs in Ordering Information, on page 1; removed non-green OPNs.

Added notes to table in Ordering Information, on page 1.

Added Package Assembly, on page 7

Revision C1 to C2

•

Enhanced format of package drawings in Physical Dimensions, on page 22

Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007

Zarlink Semiconductor Inc.

™

For more information about all Zarlink products

visit our Web Site at:

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively

“Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the

application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may

result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

LE75183DDSC [MICROSEMI]

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