LX5240CPW [MICROSEMI]
MULTIMODE, PLUG AND PLAY SCSI TERMINATOR; 多模，即插即用SCSI终结
| 型号： | LX5240CPW |
| 厂家： | 
Microsemi |
| 描述： | MULTIMODE, PLUG AND PLAY SCSI TERMINATOR |
| 文件： | 总5页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LIN DOC #: 5240
TM
LX5240
MU LT I M O D E , PL U G A N D P L AY SCSI T E R M I N AT O R
UltraMAX
T H E I N F I N I T E P O W E R O F I N N O V A T I O N
P R O D U C T I O N D A T A S H E E T
DESCRIPTION
KEY FEATURES
The LX5240 is a multimode SCSI terminator with
is tied to the DIFFSENSE input of the corre-
sponding LVD transceivers. This action enables
■ Auto-Selectable LVD Or
Single-Ended Termination
■ 3.0pF Maximum Disabled Output
Capacitance
■ Fast Response, No External Capacitors
Required
■ Compatible With Active Negation
Drivers
■ 15µA Supply Current In Disconnect
Mode
■ Logic Command Disconnects All
Termination Lines
■ Diffsense Line Driver
■ Ground Driver Integrated For Single-
Ended Operation
■ Current Limit And Thermal Protection
■ Hot-Swap Compatible
(Single-Ended)
plug-and-play capability that conforms to the
SCSI Parallel Interconnect-2 (SPI-2) specification
developed by the T10 standards committee for
lowvoltagedifferential(LVD)termination, while
providing backwards compatibility to the SCSI,
SCSI-2, and SPI single-ended specifications.
Multimode compatibility permits the use of
legacy devices on the bus without hardware
alterations. Automatic mode selection is
achieved through voltage detection on the
diffsense line.
The LX5240 utilizes Linfinity’s UltraMAX tech-
nology which delivers the ultimate in SCSI bus
performance while saving component cost and
board area. Elimination of the external capaci-
tors also mitigates the need for a lengthy ca-
pacitor selection process. The individual high
bandwidth drivers also maximize channel sepa-
ration and reduce channel to channel noise and
cross talk. The high bandwidth architecture
insures ULTRA2 performance while providing
a clear migration path to ULTRA3 and beyond.
When the LX5240 is enabled, the differential
sense (DIFFSENSE) pin supplies a voltage be-
tween 1.2V and 1.4V. In application, this pin
the LVD transceiver function. DIFFSENSE is
capable of supplying a maximum of 15mA.
Tying the DIFFSENSE pin high places the
LX5240 in a HI Z state indicating the presence
of an HVD device. Tying the pin low places
the part in a single-ended mode while also
signaling the multimode transceiver to operate
in a single-ended mode.
The LX5240 supports full Plug and Play
functionality with the DISCONNECT A and B
pins. These logic compatible pins place the
device in operational or sleep modes. During
sleep mode, power dissipation is reduced to
a meager 15µA while also placing all outputs
in a HI Z state. Also during sleep mode, the
DIFFSENSE function is disabled and is placed
in a HI Z state.
■ Compatible With SCSI 1, 2, 3, Fast-20,
And The Pending SPI-2 LVD
■ Plug And Play Compatible
■ See LX5245/5246, LVD Termination Only
Another key feature of the LX5240 is the
master / slave function. Driving this pin high
or floating the pin enables the 1.3V DIFFSENSE
reference. Driving the pin low disables the on
board DIFFSENSE reference and enables use
of an external master reference device.
NOTE: For current data & package dimensions, visit our web site: http://www.linfinity.com.
PRODUCT HIGHLIGHT
B U S V O L T A G E
V O D
VOD = V(-) - V(+), Logic = 0
NEGATED
V(+)
100mV
0V
V(-)
-100mV
LX5240
LX5240
PACKAGE ORDER INFO
Plastic SSOP
36-pin
Plastic TSSOP
TA (°C)
DB
PW
24-pin
0 to 70
LX5240CDB
LX5240CPW
Note: All surface-mount packages are available in Tape & Reel.
Append the letter "T" to part number. (i.e. LX5240CDBT)
L I N F I N I T Y M I C R O E L E C T R O N I C S I N C .
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
Copyright © 1999
Rev. 1.1 10/00
1
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX5240
UltraMAX
MU LT I M O D E , PL U G A N D P L AY SCSI T E R M I N AT O R
P R O D U C T I O N D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS (Note 1)
PACKAGE PIN OUTS
TermPwr Voltage .................................................................................................+7V
Operating Junction Temperature
Plastic (DB, PW Packages) .......................................................................... 150°C
Storage Temperature Range ..............................................................-65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................................................... 300°C
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
N.C.
N.C.
DISCONNECT A
VTERM
HVD
LVD
SE
9-
9+
8-
8+
HEATSINK
HEATSINK
HEATSINK
7-
7+
6-
6+
DIFF B
DIFFSENSE
MASTER/SLAVE
2
3
4
1+
1-
2+
2-
5
6
7
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of the specified
terminal.
8
HEATSINK
HEATSINK
HEATSINK
9
10
11
12
13
14
15
16
17
18
3+
3-
4+
4-
5+
5-
THERMAL DATA
DB PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
PW PACKAGE:
50°C/W
DISCONNECT B
GND
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
100°C/W
DB PACKAGE (Top View)
("N.C." = No Internal Connection)
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
1+
1-
2+
2-
3+
3-
4+
4-
1
24
23
22
21
20
19
18
17
16
15
14
13
VTERM
DISCONNECT A
9-
9+
8-
8+
7-
7+
2
3
4
MASTER / SLAVE FUNCTION TABLE
5
6
MASTER /
SLAVE
DIFFSENSE
Status
Output
Current
7
8
9
5+
5-
6-
6+
L*
H
HI Z
1.3V
1.3V
0mA
15mA Source
15mA Source
10
11
12
DISCONNECT B
GND
DIFFSENSE
MASTER/SLAVE
Open (Pull-up)
PW PACKAGE (Top View)
("N.C." = No Internal Connection)
* When in Low state, terminator will detect state of DIFFSENSE line.
DIFFSENSE / POWER UP / POWER DOWN FUNCTION TABLE
DIFF
SENSE
Outputs
Quiescent
Current
DISCONNECT A DISCONNECT B
Status
Type
H
L
L
H
L < 0.5V
0.7 to 1.9V
H > 2.4V
Enable
Enable
Disable
S.E.
7mA
21mA
1mA
H
L
L
H
LVD
HI Z
H
L
L
H
L
H
Open
L
H
Open
X
Disable
HI Z
10µA
Copyright © 1999
Rev. 1.1 10/00
2
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX5240
UltraMAX
MU LT I M O D E , PL U G A N D P L AY SCSI T E R M I N AT O R
P R O D U C T I O N D A T A S H E E T
RECOMMENDED OPERATING CONDITIONS
(Note 2)
Recommended Operating Conditions
Parameter
Symbol
Units
Min.
Typ.
Max.
Termpwr Voltage
LVD
SE
VTERM
3.0
3.5
0
5.25
5.25
5.0
V
V
V
V
Signal Line Voltage
0
VTERM
Disconnect Input Voltage
Operating Virtual Junction Temperature Range
LX5240C
0
70
°C
Note 2. Range over which the device is functional.
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0°C ≤ TA ≤ 70°C. TermPwr = 4.75V,
DISCONNECT A or B = L. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
LX5240
Min. Typ.
Parameter
Symbol
Test Conditions
Units
Max.
LVD Terminator Section
TermPwr Supply Current
LVD ICC All term lines = Open
25
15
30
35
mA
µA
V
mV
Ω
DISCONNECT A or B = LOW
Common Mode Voltage
Offset Voltage
Differential Terminator Impedance
Common Mode Impedance
Output Capacitance
VCM
VFSB
ZD
1.125
100
1.25
112
105
200
2.5
1.375
125
110
300
Open circuit between - and + (see Note 3)
VOUT Differential = -1V to 1V
100
100
ZCM
CO
0V to 2.5V
DISCONNECT A or B = LOW
Ω
pF
µA
µA
ms
Output Leakage
ILEAK
DISCONNECT A or B = LOW, VLINE = 0 to 4V, TA = 25°C
DISCONNECT A or B = LOW, VTERM = 0V, VLINE = 2.7V
DIFFSENSE = 1.4V to 0V
2
1
Mode Change Delay
tDF
115
DIFFSENSE Section
DIFFSENSE Output Voltage
DIFFSENSE Output Source Current
DIFFSENSE Sink Current
VDIFF
IDIFF
1.2
5.0
1.3
1.4
15.0
200
10
V
VDIFF = 0V
mA
µA
µA
ISINK(DIFF) VDIFF = 2.75V
ILEAK(DIFF) DISCONNECT A or B = LOW, TA = 25°C
DIFFSENSE Output Leakage
Single-Ended Termination Section
Termpwr Supply Current
SE ICC All term lines = Open, Master/Slave = 0V
All term lines = 0.2V, Master/Slave = 0V
DISCONNECT A or B = LOW
VO
7
214
15
2.85
23
65
10
226
35
mA
mA
µA
V
Terminator Output High Volt
Output Current
2.6
21
45
IO
VOUT = 0.2V
24
mA
mA
pF
µA
µA
Ω
Sink Current
Output Capacitance
Leakage Current
ISINK
CO
VOUT = 4V, All lines
DISCONNECT A or B = LOW
DISCONNECT A or B = LOW, VOUT = 0 to 4V, TA = 25°C
DISCONNECT A or B = LOW, VTERM = 0V, VLINE = 2.7V
I = 1mA
2.5
ILEAK
2
1
Ground Driver Impedance
Thermal Shutdown
ZG
100
150
°C
Note 3. Open circuit failsafe voltage.
Copyright © 1999
Rev. 1.1 10/00
3
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX5240
UltraMAX
MU LT I M O D E , PL U G A N D P L AY SCSI T E R M I N AT O R
P R O D U C T I O N D A T A S H E E T
ELECTRICAL CHARACTERISTICS
LX5240
Min. Typ.
Parameter
Symbol
Test Conditions
Units
Max.
DISCONNECT Section (Plug n' Play)
DISCONNECT A/B Thresholds
Input Current
VTH
IIL
0.8
2.0
10
V
µA
nA
DISCONNECT A/B = 0V
IIH
DISCONNECT A/B = 2.4V
100
MASTER / SLAVE Section
MASTER / SLAVE Thresholds
Input Current
VTH (MS)
IIL (MS)
IIH (MS)
0.8
2.0
10
V
MASTER / SLAVE = 0V
MASTER / SLAVE = 2.4V
µA
nA
100
BLOCK DIAGRAM
DISCONNECT
(-)
RSE
RLVD
(+)
RLVD
VBG
Ground Driver
FIGURE 1 — LX5240 Block Diagram
Copyright © 1999
Rev. 1.1 10/00
4
P R O D U C T D A T A B O O K 1 9 9 6 / 1 9 9 7
LX5240
UltraMAX
MU LT I M O D E , PL U G A N D P L AY SCSI T E R M I N AT O R
P R O D U C T I O N D A T A S H E E T
APPLICATION SCHEMATIC
HOST
PERIPHERAL
TERM POWER
TERM POWER
5V
5V
DIFFSENSE (1.3V)
DIFFSENSE
VTERM
DIFFSENSE
VTERM
DB (0) -
DB (0) +
DB (0) -
DB (0) +
2.2µF
2.2µF
LX5240
LX5240
DB (7)-
DB (7)+
DB (7)-
DB (7)+
M/S*
M/S
TERMPWR
DIFFSENSE
DIFFSENSE
TERMPWR
DIFFSENSE
VTERM
DIFFSENSE
VTERM
ATN -
ATN +
ATN -
ATN +
SCSI CABLE
LX5240
LX5240
ACK -
ACK +
ACK -
ACK +
M/S
M/S
Note: Single-ended the + signals become ground, DIFFSENSE < 0.5V.
* M/S = MASTER/SLAVE
FIGURE 2 — LX5240 Application Schematic
UltraMAX is a trademark of LinFinity Microelectronics Inc.
PRELIMINARY DATA - Information contained in this document is pre-production data, and is proprietary to LinFinity. It may
not modified in any way without the express written consent of LinFinity. Product referred to herein is offered in sample form
only, and Linfinity reserves the right to change or discontinue this proposed product at any time.
Copyright © 1999
Rev. 1.1 10/00
5
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