M1AFS250M1AFS600-2FGG256I

1 – Fusion Device Family Overview

Introduction

The Fusion mixed signal FPGA satisfies the demand from system architects for a device that simplifies

design and unleashes their creativity. As the world’s first mixed signal programmable logic family, Fusion

integrates mixed signal analog, flash memory, and FPGA fabric in a monolithic device. Fusion devices

enable designers to quickly move from concept to completed design and then deliver feature-rich

systems to market. This new technology takes advantage of the unique properties of Microsemi flash-

based FPGAs, including a high-isolation, triple-well process and the ability to support high-voltage

transistors to meet the demanding requirements of mixed signal system design.

Fusion mixed signal FPGAs bring the benefits of programmable logic to many application areas,

including power management, smart battery charging, clock generation and management, and motor

control. Until now, these applications have only been implemented with costly and space-consuming

discrete analog components or mixed signal ASIC solutions. Fusion mixed signal FPGAs present new

capabilities for system development by allowing designers to integrate a wide range of functionality into a

single device, while at the same time offering the flexibility of upgrades late in the manufacturing process

or after the device is in the field. Fusion devices provide an excellent alternative to costly and time-

consuming mixed signal ASIC designs. In addition, when used in conjunction with the ARM Cortex-M1

processor, Fusion technology represents the definitive mixed signal FPGA platform.

Flash-based Fusion devices are Instant On. As soon as system power is applied and within normal

operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-based lock and

industry-leading AES decryption, used to secure programmed intellectual property (IP) and configuration

data. Fusion devices are the most comprehensive single-chip analog and digital programmable logic

solution available today.

To support this new ground-breaking technology, Microsemi has developed a series of major tool

innovations to help maximize designer productivity. Implemented as extensions to the popular Microsemi

Libero^®System-on-Chip (SoC) software, these new tools allow designers to easily instantiate and

configure peripherals within a design, establish links between peripherals, create or import building

blocks or reference designs, and perform hardware verification. This tool suite will also add

comprehensive hardware/software debug capability as well as a suite of utilities to simplify development

of embedded soft-processor-based solutions.

General Description

The Fusion family, based on the highly successful ProASIC^®3 and ProASIC3E flash FPGA architecture,

has been designed as a high-performance, programmable, mixed signal platform. By combining an

advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion devices

dramatically simplify system design and, as a result, dramatically reduce overall system cost and board

space.

The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,

enabling savings in cost, power, and board area relative to external flash solutions, while providing

increased flexibility and performance. The flash memory blocks and integrated analog peripherals enable

true mixed-mode programmable logic designs. Two examples are using an on-chip soft processor to

implement a fully functional flash MCU and using high-speed FPGA logic to offer system and power

supervisory capabilities. Instant On, and capable of operating from a single 3.3 V supply, the Fusion

family is ideally suited for system management and control applications.

The devices in the Fusion family are categorized by FPGA core density. Each family member contains

many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC), high-drive

outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the user with a

high level of flexibility and integration to support a wide variety of mixed signal applications. The flash

memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-bit ADC supports up to 30

independently configurable input channels.

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Fusion Device Family Overview

The on-chip crystal and RC oscillators work in conjunction with the integrated phase-locked loops (PLLs)

to provide clocking support to the FPGA array and on-chip resources. In addition to supporting typical

RTC uses such as watchdog timer, the Fusion RTC can control the on-chip voltage regulator to power

down the device (FPGA fabric, flash memory block, and ADC), enabling a low power standby mode.

The Fusion family offers revolutionary features, never before available in an FPGA. The nonvolatile flash

technology gives the Fusion solution the advantage of being a highly secure, low power, single-chip

solution that is Instant On. Fusion is reprogrammable and offers time-to-market benefits at an ASIC-level

unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA

design flows and tools.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-

based Fusion devices are Instant On and do not need to be loaded from an external boot PROM. On-

board security mechanisms prevent access to the programming information and enable remote updates

of the FPGA logic that are protected with high level security. Designers can perform remote in-system

reprogramming to support future design iterations and field upgrades, with confidence that valuable IP is

highly unlikely to be compromised or copied. ISP can be performed using the industry-standard AES

algorithm with MAC data authentication on the device. The Fusion family device architecture mitigates

the need for ASIC migration at higher user volumes. This makes the Fusion family a cost-effective ASIC

replacement solution for applications in the consumer, networking and communications, computing, and

avionics markets.

Security

As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable external

bitstream. Fusion devices incorporate FlashLock, which provides

a unique combination of

reprogrammability and design security without external overhead, advantages that only an FPGA with

nonvolatile flash programming can offer.

Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to provide the highest level

of protection in the FPGA industry for programmed IP and configuration data. The FlashROM data in

Fusion devices can also be encrypted prior to loading. Additionally, the flash memory blocks can be

programmed during runtime using the industry-leading AES-128 block cipher encryption standard (FIPS

Publication 192). The AES standard was adopted by the National Institute of Standards and Technology

(NIST) in 2000 and replaces the DES standard, which was adopted in 1977. Fusion devices have a built-

in AES decryption engine and a flash-based AES key that make Fusion devices the most comprehensive

programmable logic device security solution available today. Fusion devices with AES-based security

provide a high level of protection for remote field updates over public networks, such as the Internet, and

are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners,

and IP thieves. As an additional security measure, the FPGA configuration data of a programmed Fusion

device cannot be read back, although secure design verification is possible. During design, the user

controls and defines both internal and external access to the flash memory blocks.

Security, built into the FPGA fabric, is an inherent component of the Fusion family. The flash cells are

located beneath seven metal layers, and many device design and layout techniques have been used to

make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique in being

highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-

standard security, making remote ISP possible. A Fusion device provides the best available security for

programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Fusion FPGAs do

not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

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Fusion Family of Mixed Signal FPGAs

Instant On

Flash-based Fusion devices are Level 0 Instant On. Instant On Fusion devices greatly simplify total

system design and reduce total system cost by eliminating the need for CPLDs. The Fusion Instant On

clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of Instant On clocking and analog

resources makes these devices an excellent choice for both system supervisor and system management

functions. Instant On from a single 3.3 V source enables Fusion devices to initiate, control, and monitor

multiple voltage supplies while also providing system clocks. In addition, glitches and brownouts in

system power will not corrupt the Fusion device flash configuration. Unlike SRAM-based FPGAs, the

device will not have to be reloaded when system power is restored. This enables reduction or complete

removal of expensive voltage monitor and brownout detection devices from the PCB design. Flash-

based Fusion devices simplify total system design and reduce cost and design risk, while increasing

system reliability.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. Another

source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft or firm error, its

source must be in very close proximity to the affected circuit. The alpha source must be in the package

molding compound or in the die itself. While low-alpha molding compounds are being used increasingly,

this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not occur in Fusion flash-based FPGAs. Once it is programmed,

the flash cell configuration element of Fusion FPGAs cannot be altered by high-energy neutrons and is

therefore immune to errors from them.

Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be

mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making them an

ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current surge

and no high current transition, both of which occur on many FPGAs.

Fusion devices also have low dynamic power consumption and support both low power standby mode

and very low power sleep mode, offering further power savings.

Advanced Flash Technology

The Fusion family offers many benefits, including nonvolatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows very high logic utilization (much

higher than competing SRAM technologies) without compromising device routability or performance.

Logic functions within the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The Fusion

device consists of several distinct and programmable architectural features, including the following

(Figure 1-1 on page 1-5):

•

Embedded memories

–

Flash memory blocks

FlashROM

SRAM and FIFO

•

Clocking resources

PLL and CCC

–

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Fusion Device Family Overview

–

RC oscillator

Crystal oscillator

No-Glitch MUX (NGMUX)

•

Digital I/Os with advanced I/O standards

FPGA VersaTiles

Analog components

–

ADC

Analog I/Os supporting voltage, current, and temperature monitoring

1.5 V on-board voltage regulator

Real-time counter

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) by programming the

appropriate flash switch interconnections. This versatility allows efficient use of the FPGA fabric. The

VersaTile capability is unique to the Microsemi families of flash-based FPGAs. VersaTiles and larger

functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid (3.3 V) single-voltage programming

of Fusion devices via an IEEE 1532 JTAG interface.

Unprecedented Integration

Integrated Analog Blocks and Analog I/Os

Fusion devices offer robust and flexible analog mixed signal capability in addition to the high-

performance flash FPGA fabric and flash memory block. The many built-in analog peripherals include a

configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs, and a

configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with a cumulative sample

rate up to 600 k samples per second (Ksps), differential nonlinearity (DNL) < 1.0 LSB, and Total

Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used for characterization of the

conversion error and includes errors from all sources, such as offset and linearity. Internal bandgap

circuitry offers 1% voltage reference accuracy with the flexibility of utilizing an external reference voltage.

The ADC channel sampling sequence and sampling rate are programmable and implemented in the

FPGA logic using Designer and Libero SoC software tool support.

Two channels of the 32-channel ADCMUX are dedicated. Channel 0 is connected internally to VCC and

can be used to monitor core power supply. Channel 31 is connected to an internal temperature diode

which can be used to monitor device temperature. The 30 remaining channels can be connected to

external analog signals. The exact number of I/Os available for external connection signals is device-

dependent (refer to the "Fusion Family" table on page I for details).

With Fusion, Microsemi also introduces the Analog Quad I/O structure (Figure 1-1 on page 1-5). Each

quad consists of three analog inputs and one gate driver. Each quad can be configured in various built-in

circuit combinations, such as three prescaler circuits, three digital input circuits, a current monitor circuit,

or a temperature monitor circuit. Each prescaler has multiple scaling factors programmed by FPGA

signals to support a large range of analog inputs with positive or negative polarity. When the current

monitor circuit is selected, two adjacent analog inputs measure the voltage drop across a small external

sense resistor. For more information, refer to the "Analog System Characteristics" section on

page 2-120. Built-in operational amplifiers amplify small voltage signals for accurate current

measurement. One analog input in each quad can be connected to an external temperature monitor

diode. In addition to the external temperature monitor diode(s), a Fusion device can monitor an internal

temperature diode using dedicated channel 31 of the ADCMUX.

Figure 1-1 on page 1-5 illustrates a typical use of the Analog Quad I/O structure. The Analog Quad

shown is configured to monitor and control an external power supply. The AV pad measures the source

of the power supply. The AC pad measures the voltage drop across an external sense resistor to

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Fusion Family of Mixed Signal FPGAs

calculate current. The AG MOSFET gate driver pad turns the external MOSFET on and off. The AT pad

measures the load-side voltage level.

Power

Line Side

Load Side

Off-Chip

R_pullup

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Pre-

scaler

Pre-

scaler

Pre-

scaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor/Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 1-1 • Analog Quad

Embedded Memories

Flash Memory Blocks

The flash memory available in each Fusion device is composed of one to four flash blocks, each 2 Mbits

in density. Each block operates independently with a dedicated flash controller and interface. Fusion

flash memory blocks combine fast access times (60 ns random access and 10 ns access in Read-Ahead

mode) with a configurable 8-, 16-, or 32-bit datapath, enabling high-speed flash operation without wait

states. The memory block is organized in pages and sectors. Each page has 128 bytes, with 33 pages

comprising one sector and 64 sectors per block. The flash block can support multiple partitions. The only

constraint on size is that partition boundaries must coincide with page boundaries. The flexibility and

granularity enable many use models and allow added granularity in programming updates.

Fusion devices support two methods of external access to the flash memory blocks. The first method is a

serial interface that features a built-in JTAG-compliant port, which allows in-system programmability

during user or monitor/test modes. This serial interface supports programming of an AES-encrypted

stream. Data protected with security measures can be passed through the JTAG interface, decrypted,

and then programmed in the flash block. The second method is a soft parallel interface.

FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel interface.

Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be customized to

meet special user requirements. For more information, refer to the CoreCFI Handbook. The flash

memory parallel interface provides configurable byte-wide (×8), word-wide (×16), or dual-word-wide

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Fusion Device Family Overview

(×32) data-port options. Through the programmable flash parallel interface, the on-chip and off-chip

memories can be cascaded for wider or deeper configurations.

The flash memory has built-in security. The user can configure either the entire flash block or the small

blocks to protect against unintentional or intrusive attempts to change or destroy the storage contents.

Each on-chip flash memory block has a dedicated controller, enabling each block to operate

independently.

The flash block logic consists of the following sub-blocks:

•

Flash block – Contains all stored data. The flash block contains 64 sectors and each sector

contains 33 pages of data.

•

Page Buffer – Contains the contents of the current page being modified. A page contains 8 blocks

of data.

•

Block Buffer – Contains the contents of the last block accessed. A block contains 128 data bits.

ECC Logic – The flash memory stores error correction information with each block to perform

single-bit error correction and double-bit error detection on all data blocks.

User Nonvolatile FlashROM

In addition to the flash blocks, Fusion devices have 1 Kbit of user-accessible, nonvolatile FlashROM on-

chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in diverse system

applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for communications algorithms protected by security

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard IEEE 1532 JTAG programming interface. Pages can be

individually programmed (erased and written). On-chip AES decryption can be used selectively over

public networks to load data such as security keys stored in the FlashROM for a user design.

The FlashROM can be programmed (erased and written) via the JTAG programming interface, and its

contents can be read back either through the JTAG programming interface or via direct FPGA core

addressing.

The FlashPoint tool in the Fusion development software solutions, Libero SoC and Designer, has

extensive support for flash memory blocks and FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part. Another

feature allows the inclusion of static data for system version control. Data for the FlashROM can be

generated quickly and easily using the Libero SoC and Designer software tools. Comprehensive

programming file support is also included to allow for easy programming of large numbers of parts with

differing FlashROM contents.

SRAM and FIFO

Fusion devices have embedded SRAM blocks along the north and south sides of the device. Each

variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,

512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can

be configured with different bit widths on each port. For example, data can be written through a 4-bit port

and read as a single bitstream. The SRAM blocks can be initialized from the flash memory blocks or via

the device JTAG port (ROM emulation mode), using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The embedded FIFO control

unit contains the counters necessary for the generation of the read and write address pointers. The

SRAM/FIFO blocks can be cascaded to create larger configurations.

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Fusion Family of Mixed Signal FPGAs

Clock Resources

PLLs and Clock Conditioning Circuits (CCCs)

Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of the

Fusion family contains six CCCs. In the two larger family members, two of these CCCs also include a

PLL; the smaller devices support one PLL.

The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with

dedicated CCC block connections.

The CCC block has the following key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock phase adjustment via programmable and fixed delays from –6.275 ns to +8.75 ns

Clock skew minimization (PLL)

Clock frequency synthesis (PLL)

On-chip analog clocking resources usable as inputs:

–

100 MHz on-chip RC oscillator

Crystal oscillator

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°

Output duty cycle = 50% ± 1.5%

Low output jitter. Samples of peak-to-peak period jitter when a single global network is used:

–

70 ps at 350 MHz

90 ps at 100 MHz

180 ps at 24 MHz

Worst case < 2.5% × clock period

•

Maximum acquisition time = 150 µs

Low power consumption of 5 mW

Global Clocking

Fusion devices have extensive support for multiple clocking domains. In addition to the CCC and PLL

support described above, there are on-chip oscillators as well as a comprehensive global clock

distribution network.

The integrated RC oscillator generates a 100 MHz clock. It is used internally to provide a known clock

source to the flash memory read and write control. It can also be used as a source for the PLLs.

The crystal oscillator supports the following operating modes:

•

Crystal (32.768 KHz to 20 MHz)

Ceramic (500 KHz to 8 MHz)

RC (32.768 KHz to 4 MHz)

Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant global

networks. The VersaNets can be driven by the CCC or directly accessed from the core via MUXes. The

VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.

Digital I/Os with Advanced I/O Standards

The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages (1.5 V,

1.8 V, 2.5 V, and 3.3 V). Fusion FPGAs support many different digital I/O standards, both single-ended

and differential.

The I/Os are organized into banks, with four or five banks per device. The configuration of these banks

determines the I/O standards supported. The banks along the east and west sides of the device support

the full range of I/O standards (single-ended and differential). The south bank supports the Analog Quads

(analog I/O). In the family's two smaller devices, the north bank supports multiple single-ended digital I/O

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Fusion Device Family Overview

standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os,

supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following applications:

•

Single-Data-Rate (SDR) applications

Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications

Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.

VersaTiles

The Fusion core consists of VersaTiles, which are also used in the successful ProASIC3 family. The

Fusion VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set and optional enable

Refer to Figure 1-2 for the VersaTile configuration arrangement.

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

Data

CLK

CLR

Y

X1

X2

X3

Data

CLK

Enable

Y

D-FF

LUT-3

D-FFE

Y

CLR

Figure 1-2 • VersaTile Configurations

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog

pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate

driver in software v9.0.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States

During Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-3 on page 1-9).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

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Fusion Family of Mixed Signal FPGAs

Figure 1-3 • I/O States During Programming Window

6. Click OK to return to the FlashPoint – Programming File Generator window.

I/O States During programming are saved to the ADB and resulting programming files after completing

programming file generation.

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Fusion Device Family Overview

Read Next Operation

The Read Next operation is a feature by which the next block relative to the block in the Block Buffer is

read from the FB Array while performing reads from the Block Buffer. The goal is to minimize wait states

during consecutive sequential Read operations.

The Read Next operation is performed in a predetermined manner because it does look-ahead reads.

The general look-ahead function is as follows:

•

Within a page, the next block fetched will be the next in linear address.

When reading the last data block of a page, it will fetch the first block of the next page.

When reading spare pages, it will read the first block of the next sector's spare page.

Reads of the last sector will wrap around to sector 0.

Reads of Auxiliary blocks will read the next linear page's Auxiliary block.

When an address on the ADDR input does not agree with the predetermined look-ahead address, there

is a time penalty for this access. The FB will be busy finishing the current look-ahead read before it can

start the next read. The worst case is a total of nine BUSY cycles before data is delivered.

The Non-Pipe Mode and Pipe Mode waveforms for Read Next operations are illustrated in Figure 2-40

and Figure 2-41.

CLK

REN

READNEXT

ADDR[17:0]

DATAWIDTH[1:0]

BUSY

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

STATUS[1:0]

RD[31:0]

0

S0 S1 S2 S3

D0 D1 D2 D3

0

S4 S5 S6

S7

0

S8 S9

D8 D9

D4 D5 D6 D7

Figure 2-40 • Read Next Waveform (Non-Pipe Mode, 32-bit access)

CLK

REN

READNEXT

A0

A1

A2

A3

A4

A5

A6

A7

A8

ADDR[17:0]

BUSY

S0

D0

S1

D1

S2

D2

S3

D3

0

S4

D4

S5

D5

S6

D6

S7

D7

0

STATUS[1:0]

RD[31:0]

0

Figure 2-41 • Read Next WaveForm (Pipe Mode, 32-bit access)

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Unprotect Page Operation

An Unprotect Page operation will clear the protection for a page addressed on the ADDR input. It is

initiated by setting the UNPROTECTPAGE signal on the interface along with the page address on

ADDR.

If the page is not in the Page Buffer, the Unprotect Page operation will copy the page into the Page

Buffer. The Copy Page operation occurs only if the current page in the Page Buffer is not Page Loss

Protected.

The waveform for an Unprotect Page operation is shown in Figure 2-42.

CLK

UNPROTECTPAGE

Page

ADDR[17:0]

BUSY

STATUS[1:0]

Valid

Figure 2-42 • FB Unprotected Page Waveform

The Unprotect Page operation can incur the following error conditions:

1. If the copy of the page to the Page Buffer determines that the page has a single-bit correctable

error in the data, it will report a STATUS = '01'.

2. If the address on ADDR does not match the address of the Page Buffer, PAGELOSSPROTECT is

asserted, and the Page Buffer has been modified, then STATUS = '11' and the addressed page is

not loaded into the Page Buffer.

3. If the copy of the page to the Page Buffer determines that at least one block in the page has a

double-bit uncorrectable error, STATUS = '10' and the Page Buffer will contain the corrupted data.

Discard Page Operation

If the contents of the modified Page Buffer have to be discarded, the DISCARDPAGE signal should be

asserted. This command results in the Page Buffer being marked as unmodified.

The timing for the operation is shown in Figure 2-43. The BUSY signal will remain asserted until the

operation has completed.

CLK

DISCARDPAGE

BUSY

Figure 2-43 • FB Discard Page Waveform

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Device Architecture

Flash Memory Block Characteristics

CLK

RESET

Active Low, Asynchronous

BUSY

Figure 2-44 • Reset Timing Diagram

Table 2-25 • Flash Memory Block Timing

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std. Units

t_CLK2RD

Clock-to-Q in 5-cycle read mode of the Read Data

Clock-to-Q in 6-cycle read mode of the Read Data

Clock-to-Q in 5-cycle read mode of BUSY

Clock-to-Q in 6-cycle read mode of BUSY

Clock-to-Status in 5-cycle read mode

7.99

5.03

4.95

4.45

11.24

4.48

1.92

0.00

2.76

0.00

1.85

0.00

3.85

0.00

2.37

0.00

2.16

0.00

3.74

0.00

3.74

0.00

2.17

0.00

3.76

0.00

2.01

0.00

1.88

0.00

1.64

0.00

9.10

5.73

5.63

5.07

10.70

6.74

6.62

5.96

ns

t_CLK2BUSY

t_CLK2STATUS

12.81 15.06

Clock-to-Status in 6-cycle read mode

5.10

2.19

0.00

3.14

0.00

2.11

0.00

4.39

0.00

2.69

0.00

2.46

0.00

4.26

0.00

4.26

0.00

2.47

0.00

4.28

0.00

2.29

0.00

2.14

0.00

1.86

0.00

6.00

2.57

0.00

3.69

0.00

2.48

0.00

5.16

0.00

3.17

0.00

2.89

0.00

5.01

0.00

5.00

0.00

2.90

0.00

5.03

0.00

2.69

0.00

2.52

0.00

2.19

0.00

t_DSUNVM

Data Input Setup time for the Control Logic

Data Input Hold time for the Control Logic

Address Input Setup time for the Control Logic

Address Input Hold time for the Control Logic

Data Width Setup time for the Control Logic

Data Width Hold time for the Control Logic

Read Enable Setup time for the Control Logic

Read Enable Hold Time for the Control Logic

Write Enable Setup time for the Control Logic

Write Enable Hold Time for the Control Logic

Program Setup time for the Control Logic

Program Hold time for the Control Logic

t_DHNVM

t_ASUNVM

t_AHNVM

t_SUDWNVM

t_HDDWNVM

t_SURENNVM

t_HDRENNVM

t_SUWENNVM

t_HDWENNVM

t_SUPROGNVM

t_HDPROGNVM

t_SUSPAREPAGE

t_HDSPAREPAGE

t_SUAUXBLK

SparePage Setup time for the Control Logic

SparePage Hold time for the Control Logic

Auxiliary Block Setup Time for the Control Logic

Auxiliary Block Hold Time for the Control Logic

ReadNext Setup Time for the Control Logic

ReadNext Hold Time for the Control Logic

Erase Page Setup Time for the Control Logic

Erase Page Hold Time for the Control Logic

Unprotect Page Setup Time for the Control Logic

Unprotect Page Hold Time for the Control Logic

Discard Page Setup Time for the Control Logic

Discard Page Hold Time for the Control Logic

Overwrite Protect Setup Time for the Control Logic

Overwrite Protect Hold Time for the Control Logic

t_HDAUXBLK

t_SURDNEXT

t_HDRDNEXT

t_SUERASEPG

t_HDERASEPG

t_{SUUNPROTECTPG}

t_{HDUNPROTECTPG}

t_SUDISCARDPG

t_HDDISCARDPG

t_SUOVERWRPRO

t_HDOVERWRPRO

2-54

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-25 • Flash Memory Block Timing (continued)

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std. Units

t_SUPGLOSSPRO

t_HDPGLOSSPRO

t_SUPGSTAT

Page Loss Protect Setup Time for the Control Logic

Page Loss Protect Hold Time for the Control Logic

Page Status Setup Time for the Control Logic

Page Status Hold Time for the Control Logic

Over Write Page Setup Time for the Control Logic

Over Write Page Hold Time for the Control Logic

Lock Request Setup Time for the Control Logic

Lock Request Hold Time for the Control Logic

Reset Recovery Time

1.69

0.00

2.49

0.00

1.88

0.00

0.87

0.00

0.94

0.00

1.93

0.00

2.83

0.00

2.14

0.00

0.99

0.00

1.07

0.00

2.27

0.00

3.33

0.00

2.52

0.00

1.16

0.00

1.25

0.00

ns

t_HDPGSTAT

t_SUOVERWRPG

t_HDOVERWRPG

t_{SULOCKREQUEST}

t_{HDLOCKREQUEST}

t_RECARNVM

t_REMARNVM

Reset Removal Time

t_MPWARNVM

Asynchronous Reset Minimum Pulse Width for the 10.00

Control Logic

12.50 12.50

t_MPWCLKNVM

t_FMAXCLKNVM

Clock Minimum Pulse Width for the Control Logic

4.00

5.00 5.00

ns

Maximum Frequency for Clock for the Control Logic – for 80.00

AFS1500/AFS600

80.00 80.00 MHz

Maximum Frequency for Clock for the Control Logic – for 100.00 80.00 80.00 MHz

AFS250/AFS090

Revision 4

2-55

Device Architecture

FlashROM

Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core

fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each

bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core (Figure 2-

45).

The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly

from the FPGA core. When programming, each of the eight 128-bit banks can be selectively

reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves

an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports a

synchronous read and can be read on byte boundaries. The upper three bits of the FlashROM address

from the FPGA core define the bank that is being accessed. The lower four bits of the FlashROM

address from the FPGA core define which of the 16 bytes in the bank is being accessed.

The maximum FlashROM access clock is given in Table 2-26 on page 2-57. Figure 2-46 shows the

timing behavior of the FlashROM access cycle—the address has to be set up on the rising edge of the

clock for DOUT to be valid on the next falling edge of the clock.

If the address is unchanged for two cycles:

•

D0 becomes invalid t_CK2Qns after the second rising edge of the clock.

D0 becomes valid again t_CK2Qns after the second falling edge.

If the address unchanged for three cycles:

•

D0 becomes invalid t_CK2Qns after the second rising edge of the clock.

D0 becomes valid again t_CK2Qns after the second falling edge.

D0 becomes invalid t_CK2Qns after the third rising edge of the clock.

D0 becomes valid again t_CK2Qns after the third falling edge.

Byte Number in Bank

4 LSB of ADDR (READ)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Figure 2-45 • FlashROM Architecture

2-56

Revision 4

Fusion Family of Mixed Signal FPGAs

FlashROM Characteristics

t

SU

t

HOLD

Address

A0

A1

t

CK2Q

D0

D1

Figure 2-46 • FlashROM Timing Diagram

Table 2-26 • FlashROM Access Time

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_SU

Description

Address Setup Time

Address Hold Time

Clock to Out

–2

–1

Std.

0.71

Units

ns

0.53

0.61

0.00

24.40

15.00

t_HOLD

t_CK2Q

0.00

ns

21.42

15.00

28.68

15.00

ns

F_MAX

Maximum Clock frequency

MHz

Revision 4

2-57

Device Architecture

SRAM and FIFO

All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and

AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high-

performance designs, the memory blocks operate strictly in synchronous mode for both read and write

operations. The read and write clocks are completely independent, and each may operate at any desired

frequency less than or equal to 350 MHz. The following configurations are available:

•

4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two read, two write or one read, one write)

512×9, 256×18 (two-port RAM—one read and one write)

Sync write, sync pipelined/nonpipelined read

The Fusion SRAM memory block includes dedicated FIFO control logic to generate internal addresses

and external flag logic (FULL, EMPTY, AFULL, AEMPTY).

During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored. In

FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by

internal MUXes. Refer to Figure 2-47 for more information about the implementation of the embedded

FIFO controller.

The Fusion architecture enables the read and write sizes of RAMs to be organized independently,

allowing for bus conversion. This is done with the WW (write width) and RW (read width) pins. The

different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. For example, the write size can

be set to 256×18 and the read size to 512×9.

Both the write and read widths for the RAM blocks can be specified independently with the WW (write

width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and

4k×1.

Refer to the allowable RW and WW values supported for each of the RAM macro types in Table 2-27 on

page 2-61.

When a width of one, two, or four is selected, the ninth bit is unused. For example, when writing 9-bit

values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit value are

addressable for read operations. The ninth bit is not accessible.

2-58

Revision 4

Fusion Family of Mixed Signal FPGAs

Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be

undefined. The RAM blocks employ little-endian byte order for read and write operations.

RD

RD[17:0]

WD[17:0]

RCLK

WD

RCLK

WCLK

RAM

RADD[J:0]

WADD[J:0]

REN

WEN

FREN

FWEN

CNT 12

E

RBLK

REN

=

FULL

ESTOP

AFVAL

AFULL

AEVAL

AEMPTY

EMPTY

CNT 12

E

SUB 12

WBLK

WEN

=

FSTOP

Reset

Figure 2-47 • Fusion RAM Block with Embedded FIFO Controller

Revision 4

2-59

Device Architecture

RAM4K9 Description

RAM4K9

ADDRA11 DOUTA8

DOUTA7

ADDRA10

DOUTA0

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

ADDRB0

DOUTB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RESET

Figure 2-48 • RAM4K9

2-60

Revision 4

Fusion Family of Mixed Signal FPGAs

The following signals are used to configure the RAM4K9 memory element:

WIDTHA and WIDTHB

These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-27).

Table 2-27 • Allowable Aspect Ratio Settings for WIDTHA[1:0]

WIDTHA1, WIDTHA0

WIDTHB1, WIDTHB0

D×W

4k×1

2k×2

1k×4

512×9

00

01

10

11

00

01

10

11

Note: The aspect ratio settings are constant and cannot be changed on the fly.

BLKA and BLKB

These signals are active low and will enable the respective ports when asserted. When a BLKx signal is

deasserted, the corresponding port’s outputs hold the previous value.

WENA and WENB

These signals switch the RAM between read and write mode for the respective ports. A Low on these

signals indicates a write operation, and a High indicates a read.

CLKA and CLKB

These are the clock signals for the synchronous read and write operations. These can be driven

independently or with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the output. A Low on PIPEA or PIPEB indicates a

nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A High

indicates a pipelined, read and data appears on the corresponding output in the next clock cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the output when the RAM is in write mode. A Low on

these signals makes the output retain data from the previous read. A High indicates pass-through

behavior, wherein the data being written will appear immediately on the output. This signal is overridden

when the RAM is being read.

RESET

This active low signal resets the output to zero, disables reads and writes from the SRAM block, and

clears the data hold registers when asserted. It does not reset the contents of the memory.

ADDRA and ADDRB

These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is

specified, the unused high-order bits must be grounded (Table 2-28).

Table 2-28 • Address Pins Unused/Used for Various Supported Bus Widths

ADDRx

D×W

4k×1

2k×2

1k×4

512×9

Unused

None

[11]

Used

[11:0]

[10:0]

[9:0]

[11:10]

[11:9]

[8:0]

Note: The "x" in ADDRx implies A or B.

Revision 4

2-61

Device Architecture

DINA and DINB

These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all

configurations. When a data width less than nine is specified, unused high-order signals must be

grounded (Table 2-29).

DOUTA and DOUTB

These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA

and DINB, high-order bits may not be used (Table 2-29). The output data on unused pins is undefined.

Table 2-29 • Unused/Used Input and Output Data Pins for Various Supported Bus Widths

DINx/DOUTx

D×W

4k×1

2k×2

1k×4

512×9

Unused

[8:1]

Used

[0]

[8:2]

[1:0]

[3:0]

[8:0]

[8:4]

None

Note: The "x" in DINx and DOUTx implies A or B.

2-62

Revision 4

Fusion Family of Mixed Signal FPGAs

RAM512X18 Description

RAM512X18

RADDR8

RADDR7

RD17

RD16

RADDR0

RD0

RW1

RW0

PIPE

REN

RCLK

WADDR8

WADDR7

WADDR0

WD17

WD16

WD0

WW1

WW0

WEN

WCLK

RESET

Figure 2-49 • RAM512X18

Revision 4

2-63

Device Architecture

RAM512X18 exhibits slightly different behavior from RAM4K9, as it has dedicated read and write ports.

WW and RW

These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 2-30).

Table 2-30 • Aspect Ratio Settings for WW[1:0]

WW[1:0]

01

RW[1:0]

01

D×W

512×9

10

256×18

Reserved

00, 11

WD and RD

These are the input and output data signals, and they are 18 bits wide. When a 512×9 aspect ratio is

used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then

RD[17:9] are undefined.

WADDR and RADDR

These are read and write addresses, and they are nine bits wide. When the 256×18 aspect ratio is used

for write or read, WADDR[8] or RADDR[8] are unused and must be grounded.

WCLK and RCLK

These signals are the write and read clocks, respectively. They are both active high.

WEN and REN

These signals are the write and read enables, respectively. They are both active low by default. These

signals can be configured as active high.

RESET

This active low signal resets the output to zero, disables reads and/or writes from the SRAM block, and

clears the data hold registers when asserted. It does not reset the contents of the memory.

PIPE

This signal is used to specify pipelined read on the output. A Low on PIPE indicates a nonpipelined read,

and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and data

appears on the output in the next clock cycle.

Clocking

The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edge-triggered

clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on

either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge or by

separate clocks, by port.

Fusion devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock

input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the

HDL code will be automatically accounted for during design compile without incurring additional delay in

the clock path.

The two-port SRAM can be clocked on the rising edge or falling edge of WCLK and RCLK.

If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion

management (bubble pushing) is automatically used within the Fusion development tools, without

performance penalty.

2-64

Revision 4

Fusion Family of Mixed Signal FPGAs

Modes of Operation

There are two read modes and one write mode:

•

Read Nonpipelined (synchronous—1 clock edge): In the standard read mode, new data is driven

onto the RD bus in the same clock cycle following RA and REN valid. The read address is

registered on the read port clock active edge, and data appears at RD after the RAM access time.

Setting PIPE to OFF enables this mode.

Read Pipelined (synchronous—2 clock edges): The pipelined mode incurs an additional clock

delay from the address to the data but enables operation at a much higher frequency. The read

address is registered on the read port active clock edge, and the read data is registered and

appears at RD after the second read clock edge. Setting PIPE to ON enables this mode.

Write (synchronous—1 clock edge): On the write clock active edge, the write data is written into

the SRAM at the write address when WEN is High. The setup times of the write address, write

enables, and write data are minimal with respect to the write clock. Write and read transfers are

described with timing requirements in the "SRAM Characteristics" section on page 2-66 and the

"FIFO Characteristics" section on page 2-75.

RAM Initialization

Each SRAM block can be individually initialized on power-up by means of the JTAG port using the

UJTAG mechanism (refer to the "JTAG IEEE 1532" section on page 2-232 and the Fusion SRAM/FIFO

Blocks application note). The shift register for a target block can be selected and loaded with the proper

bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation.

Revision 4

2-65

Device Architecture

SRAM Characteristics

Timing Waveforms

t_CYC

t_CKH

t_CKL

CLK

t_ASt_AH

A₀

t_BKS

A₁

A₂

[R|W]ADDR

BLK

t_BKH

t_ENS

t_ENH

WEN

t_CKQ1

D_n

D₀

D₁

D₂

DOUT|RD

t_DOH1

Figure 2-50 • RAM Read for Flow-Through Output. Applicable to both RAM4K9 and RAM512x18.

t

CYC

t

CKL

CKH

CLK

[R|W]ADDR

BLK

t

AH

AS

A

0

1

2

t

BKS

ENS

t

BKH

t

ENH

WEN

t

CKQ2

D

1

DOUT|RD

n

0

t

DOH2

Figure 2-51 • RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18.

2-66

Revision 4

Fusion Family of Mixed Signal FPGAs

t

CYC

t

CKL

CKH

CLK

[R|W]ADDR

BLK

t

AH

AS

A

0

1

2

t

BKS

ENS

t

BKH

t

ENH

WEN

t

DH

DS

DI

DIN|WD

DOUT|RD

0

1

D

n

2

Figure 2-52 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

ADDR

BLK

t_ASt_AH

A₀

t_BKS

A₁

A₂

t_BKH

t_ENS

WEN

DIN

t_DS

t_DH

DI₁

D₀

DI₂

DOUT

DI₀

D_n

DI₁

(flow-through)

DOUT

DI₀

D_n

DI₁

(pipelined)

Figure 2-53 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.

Revision 4

2-67

Device Architecture

CLK1

ADDR1

DIN1

t

AH

AS

A

D

A

3

0

2

t

DH

DS

D

3

0

2

t

WRO

CLK2

t

AH

AS

A

ADDR2

DOUT2

0

1

4

t

CKQ1

D

n

0

1

0

(flow-through)

t

CKQ2

DOUT2

(Pipelined)

D

n

Figure 2-54 • One Port Write / Other Port Read Same

t_CYC

t_CKH

t_CKL

CLK

RESET

t_RSTBQ

D_m

D_n

DOUT|RD

Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.

2-68

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-31 • RAM4K9

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description –2 –1

Std. Units

Address setup time

Address hold time

0.25 0.28 0.33

0.00 0.00 0.00

0.14 0.16 0.19

0.10 0.11 0.13

0.23 0.27 0.31

0.02 0.02 0.02

0.18 0.21 0.25

0.00 0.00 0.00

1.79 2.03 2.39

2.36 2.68 3.15

0.89 1.02 1.20

ns

t_AH

t_ENS

t_ENH

t_BKS

t_BKH

t_DS

REN, WEN setup time

REN, WEN hold time

BLK setup time

BL hold time

Input data (DIN) setup time

Input data (DIN) hold time

t_DH

t_CKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

Clock High to new data valid on DOUT (pipelined)

t_CKQ2

1

t_C2CWWH

Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23

address—Applicable to Rising Edge

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on 0.45 0.38 0.34

same address—Applicable to Opening Edge

ns

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on 0.49 0.42 0.37

same address— Applicable to Opening Edge

t_RSTBQ

RESET Low to data out Low on DOUT (flow-through)

RESET Low to Data Out Low on DOUT (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET recovery

RESET minimum pulse width

Clock cycle time

F_MAX

Maximum frequency

310 272 231 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Revision 4

2-69

Device Architecture

Table 2-32 • RAM512X18

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description –2 –1

Std. Units

Address setup time

0.25 0.28 0.33

0.00 0.00 0.00

0.09 0.10 0.12

0.06 0.07 0.08

0.18 0.21 0.25

0.00 0.00 0.00

2.16 2.46 2.89

0.90 1.02 1.20

ns

t_AH

Address hold time

t_ENS

REN, WEN setup time

REN, WEN hold time

Input data (WD) setup time

Input data (WD) hold time

t_ENH

t_DS

t_DH

t_CKQ1

t_CKQ2

Clock High to new data valid on RD (output retained)

Clock High to new data valid on RD (pipelined)

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on 0.50 0.43 0.38

same address—Applicable to Opening Edge

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on 0.59 0.50 0.44

same address— Applicable to Opening Edge

ns

1

t_RSTBQ

RESET Low to data out Low on RD (flow-through)

RESET Low to data out Low on RD (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET recovery

ns

RESET minimum pulse width

Clock cycle time

ns

F_MAX

Maximum frequency

310 272

231

MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-70

Revision 4

Fusion Family of Mixed Signal FPGAs

FIFO4K18 Description

FIFO4K18

RD17

RW2

RD16

RW1

RW0

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEMPTY

AEVAL11

AEVAL10

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-56 • FIFO4KX18

Revision 4

2-71

Device Architecture

The following signals are used to configure the FIFO4K18 memory element:

WW and RW

These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-33).

Table 2-33 • Aspect Ratio Settings for WW[2:0]

WW2, WW1, WW0

RW2, RW1, RW0

D×W

4k×1

000

001

2k×2

010

1k×4

011

512×9

256×18

Reserved

100

101, 110, 111

WBLK and RBLK

These signals are active low and will enable the respective ports when Low. When the RBLK signal is

High, the corresponding port’s outputs hold the previous value.

WEN and REN

Read and write enables. WEN is active low and REN is active high by default. These signals can be

configured as active high or low.

WCLK and RCLK

These are the clock signals for the synchronous read and write operations. These can be driven

independently or with the same driver.

RPIPE

This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined

read, and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and

data appears on the output in the next clock cycle.

RESET

This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all

the RD pins Low, the FULL and AFULL pins Low, and the EMPTY and AEMPTY pins High (Table 2-34).

Table 2-34 • Input Data Signal Usage for Different Aspect Ratios

D×W

WD/RD Unused

WD[17:1], RD[17:1]

WD[17:2], RD[17:2]

WD[17:4], RD[17:4]

WD[17:9], RD[17:9]

–

4k×1

2k×2

1k×4

512×9

256×18

WD

This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data

width less than 18 is specified, unused higher-order signals must be grounded (Table 2-34).

RD

This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD

bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is

undefined (Table 2-34).

ESTOP, FSTOP

ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the

EMPTY flag goes High). A High on this signal inhibits the counting.

2-72

Revision 4

Fusion Family of Mixed Signal FPGAs

FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the FULL

flag goes High). A High on this signal inhibits the counting.

For more information on these signals, refer to the "ESTOP and FSTOP Usage" section on page 2-73.

FULL, EMPTY

When the FIFO is full and no more data can be written, the FULL flag asserts High. The FULL flag is

synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent

overflows. Since the write address is compared to a resynchronized (and thus time-delayed) version of

the read address, the FULL flag will remain asserted until two WCLK active edges after a read operation

eliminates the full condition.

When the FIFO is empty and no more data can be read, the EMPTY flag asserts High. The EMPTY flag

is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to

prevent underflows. Since the read address is compared to a resynchronized (and thus time-delayed)

version of the write address, the EMPTY flag will remain asserted until two RCLK active edges after a

write operation removes the empty condition.

For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on

page 2-74.

AFULL, AEMPTY

These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL,

respectively.

When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading,

the AEMPTY output will go High. Likewise, when the number of words stored in the FIFO reaches the

amount specified by AFVAL while writing, the AFULL output will go High.

AFVAL, AEVAL

The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values,

respectively. They are 12-bit signals. For more information on these signals, refer to "FIFO Flag

Usage Considerations" section.

ESTOP and FSTOP Usage

The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e.,

the EMPTY flag goes High). Likewise, the FSTOP pin is used to stop the write counter from counting any

further once the FIFO is full (i.e., the FULL flag goes High).

The FIFO counters in the Fusion device start the count at 0, reach the maximum depth for the

configuration (e.g., 511 for a 512×9 configuration), and then restart at 0. An example application for the

ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same

content over and over without doing another write.

Revision 4

2-73

Device Architecture

FIFO Flag Usage Considerations

The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values,

respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR)

counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented

every time a read operation is performed. Whenever the difference between WADDR and RADDR is

greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference

between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To

handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits

instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the

SmartGen tool translates them into bit addresses and configures these signals automatically. SmartGen

configures the AFULL flag to assert when the write address exceeds the read address by at least a

predefined value. In a 2k×8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag

will be asserted after a write when the difference between the write address and the read address

reaches 1,500 (there have been at least 1500 more writes than reads). It will stay asserted until the

difference between the write and read addresses drops below 1,500.

The AEMPTY flag is asserted when the difference between the write address and the read address is

less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY

flag will be asserted when a read causes the difference between the write address and the read address

to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be

configured with different read and write widths; in this case, the AFVAL setting is based on the number of

write data entries and the AEVAL setting is based on the number of read data entries. For aspect ratios of

512×9 and 256×18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The number

of words must be multiplied by 8 and 16, instead of 9 and 18. The SmartGen tool automatically uses the

proper values. To avoid halfwords being written or read, which could happen if different read and write

aspect ratios are specified, the FIFO will assert FULL or EMPTY as soon as at least a minimum of one

word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read,

the FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not

completely empty, because in this case, a complete word cannot be read. The same is applicable in the

full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The

FULL flag will remain asserted because a complete word cannot be written at this point.

2-74

Revision 4

Fusion Family of Mixed Signal FPGAs

FIFO Characteristics

Timing Waveforms

t_CYC

RCLK

t_ENH

t_ENS

REN

t_BKS

t_BKH

RBLK

t_CKQ1

RD

D₁

D_n

D₀

D₂

(flow-through)

t_CKQ2

RD

(pipelined)

D_n

D₀

D₁

Figure 2-57 • FIFO Read

t_CYC

WCLK

t_ENS

t_ENH

WEN

t_BKS

t_BKH

WBLK

t_DS

t_DH

DI₁

DI₀

WD

Figure 2-58 • FIFO Write

Revision 4

2-75

Device Architecture

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET

EF

t_RSTFG

t_RSTAF

AEF

FF

t_RSTFG

t_RSTAF

AFF

WA/RA

MATCH (A₀)

(Address Counter)

Figure 2-59 • FIFO Reset

t_CYC

RCLK

EF

t_RCKEF

t_CKAF

AEF

WA/RA

(Address Counter)

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

Figure 2-60 • FIFO EMPTY Flag and AEMPTY Flag Assertion

2-76

Revision 4

Fusion Family of Mixed Signal FPGAs

t

CYC

WCLK

FF

t

WCKFF

t

CKAF

AFF

WA/RA

Dist = AFF_TH

MATCH (FULL)

NO MATCH

(Address Counter)

Figure 2-61 • FIFO FULL and AFULL Flag Assertion

WCLK

MATCH

WA/RA

Dist = AEF_TH + 1

NO MATCH

(EMPTY)

(Address Counter)

1st rising

2nd rising

edge

after 1st

write

edge

after 1st

write

RCLK

EF

t

RCKEF

t

CKAF

AEF

Figure 2-62 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter) MATCH (FULL)

NO MATCH

Dist = AFF_TH – 1

1st Rising

Edge

After 1st

Read

Edge

After 2nd

Read

WCLK

FF

t

WCKF

t

CKAF

AFF

Figure 2-63 • FIFO FULL Flag and AFULL Flag Deassertion

Revision 4

2-77

Device Architecture

Timing Characteristics

Table 2-35 • FIFO

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ENS

Description

REN, WEN Setup time

–2

–1

Std.

1.79

0.00

0.26

0.00

0.25

0.00

2.90

1.26

2.30

2.18

8.29

2.27

8.20

1.23

0.38

2.01

0.29

4.32

231

Units

ns

1.34

0.00

0.19

0.00

0.18

0.00

2.17

0.94

1.72

1.63

6.19

1.69

6.13

0.92

0.29

1.50

0.21

3.23

310

1.52

0.00

0.22

0.00

0.21

0.00

2.47

1.07

1.96

1.86

7.05

1.93

6.98

1.05

0.33

1.71

0.24

3.68

272

t_ENH

REN, WEN Hold time

t_BKS

BLK Setup time

t_BKH

BLK Hold time

t_DS

Input data (WD) Setup time

t_DH

Input data (WD) Hold time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost-Empty/Full Flag Valid

RESET Low to Data out Low on RD (flow-through)

RESET Low to Data out Low on RD (pipelined)

RESET Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET Recovery

RESET Minimum Pulse Width

Clock Cycle time

F_MAX

Maximum Frequency for FIFO

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-78

Revision 4

Fusion Family of Mixed Signal FPGAs

Analog Block

With the Fusion family, Microsemi has introduced the world's first mixed-mode FPGA solution.

Supporting a robust analog peripheral mix, Fusion devices will support a wide variety of applications. It is

this Analog Block that separates Fusion from all other FPGA solutions on the market today.

By combining both flash and high-speed CMOS processes in a single chip, these devices offer the best

of both worlds. The high-performance CMOS is used for building RAM resources. These high-

performance structures support device operation up to 350 MHz. Additionally, the advanced Microsemi

0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both

of these are suited for the flash-based programmable logic and nonvolatile memory structures.

High-voltage transistors support the integration of analog technology in several ways. They aid in noise

immunity so that the analog portions of the chip can be better isolated from the digital portions,

increasing analog accuracy. Because they support high voltages, Microsemi flash FPGAs can be

connected directly to high-voltage input signals, eliminating the need for external resistor divider

networks, reducing component count, and increasing accuracy. By supporting higher internal voltages,

the Microsemi advanced flash process enables high dynamic range on analog circuitry, increasing

precision and signal–noise ratio. Microsemi flash FPGAs also drive high-voltage outputs, eliminating the

need for external level shifters and drivers.

The unique triple-well process enables the integration of high-performance analog features with

increased noise immunity and better isolation. By increasing the efficiency of analog design, the triple-

well process also enables a smaller overall design size, reducing die size and cost.

The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the "Real-Time

Counter System" section on page 2-33), ADC, and ACM. All of these elements are combined in the

single Analog Block macro, with which the user implements this functionality (Figure 2-64).

The Analog Block needs to be reset/reinitialized after the core powers up or the device is programmed.

An external reset/initialize signal, which can come from the internal voltage regulator when it powers up,

must be applied.

Revision 4

2-79

Device Architecture

VAREF

ADCGNDREF

AV0

AC0

AT0

DAVOUT0

DACOUT0

DATOUT0

AV9

DAVOUT9

DACOUT9

DATOUT9

AC9

AT9

ATRETURN01

AG0

AG1

ATRETURN9

DENAV0

DENAC0

DENAT0

AG9

DENAV0

DENAC0

DENAT0

CMSTB0

CSMTB9

GDON0

GDON9

TMSTB0

TMSTB9

MODE[3:0]

TVC[7:0]

BUSY

CALIBRATE

DATAVALID

SAMPLE

STC[7:0]

CHNUMBER[4:0]

TMSTINT

RESULT[11:0]

RTCMATCH

RTCXTLMODE

RTCXTLSEL

ADCSTART

VAREFSEL

PWRDWN

ADCRESET

RTCPSMMATCH

RTCCLK

SYSCLK

ACMWEN

ACMRESET

ACMWDATA

ACMADDR

ACMCLK

ACMRDATA[7:0]

AB

Figure 2-64 • Analog Block Macro

2-80

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-36 describes each pin in the Analog Block. Each function within the Analog Block will be

explained in detail in the following sections.

Table 2-36 • Analog Block Pin Description

Number

of Bits

Location of

Details

Signal Name

VAREF

Direction

Function

1

4

1

8

1

Input/Output Voltage reference for ADC

ADC

ADCGNDREF

MODE[3:0]

SYSCLK

Input

External ground reference

ADC operating mode

External system clock

Clock divide control

Sample time control

Start of conversion

TVC[7:0]

ADC

STC[7:0]

ADCSTART

PWRDWN

ADC comparator power-down if 1.

When asserted, the ADC will stop

functioning, and the digital portion of

the analog block will continue

operating. This may result in invalid

status flags from the analog block.

Therefore,

Microsemi

does

not

recommend asserting the PWRDWN

pin.

ADCRESET

1

Input

ADC resets and disables Analog Quad

– active high

ADC

BUSY

1

Output

Input

1 – Running conversion

1 – Power-up calibration

1 – Valid conversion result

Conversion result

ADC

CALIBRATE

DATAVALID

RESULT[11:0]

TMSTBINT

SAMPLE

1

12

1

Internal temp. monitor strobe

1

Output

1 – An analog signal is actively being

sampled (stays high during signal

acquisition only)

0 – No analog signal is being sampled

VAREFSEL

1

5

Input

0 = Output internal voltage reference

(2.56 V) to VAREF

ADC

1 = Input external voltage reference

from VAREF and ADCGNDREF

CHNUMBER[4:0]

Analog input channel select

Input

multiplexer

ACMCLK

1

Input

Output

Input

ACM clock

ACM

ACMWEN

ACM write enable – active high

ACM reset – active low

ACM write data

ACMRESET

1

ACMWDATA[7:0]

ACMRDATA[7:0]

ACMADDR[7:0]

CMSTB0 to CMSTB9

8

ACM read data

8

ACM address

10

Current monitor strobe – 1 per quad, Analog Quad

active high

Revision 4

2-81

Device Architecture

Table 2-36 • Analog Block Pin Description (continued)

Number

of Bits

Location of

Details

Signal Name

Direction

Input

Function

GDON0 to GDON9

TMSTB0 to TMSTB9

10

Control to power MOS – 1 per quad

Analog Quad

10

Input

Temperature monitor strobe – 1 per Analog Quad

quad; active high

DAVOUT0, DACOUT0, DATOUT0

to

DAVOUT9, DACOUT9, DATOUT9

30

Output

Input

Digital outputs – 3 per quad

Analog Quad

DENAV0, DENAC0, DENAT0 to

DENAV9, DENAC9, DENAT9

Digital input enables – 3 per quad

Analog Quad 0

Analog Quad

AV0

1

Input

Analog Quad

AC0

AG0

Output

Input

AT0

ATRETURN01

Input

Temperature monitor return shared by Analog Quad

Analog Quads 0 and 1

AV1

1

Input

Output

Input

Output

Input

Analog Quad 1

Analog Quad

AC1

AG1

AT1

AV2

Analog Quad 2

AC2

AG2

AT2

ATRETURN23

Temperature monitor return shared by Analog Quad

Analog Quads 2 and 3

AV3

1

Input

Output

Input

Output

Input

Analog Quad 3

Analog Quad

AC3

AG3

AT3

AV4

Analog Quad 4

AC4

AG4

AT4

ATRETURN45

Temperature monitor return shared by Analog Quad

Analog Quads 4 and 5

AV5

AC5

AG5

AT5

AV6

AC6

1

Input

Output

Input

Analog Quad 5

Analog Quad

Analog Quad 6

2-82

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-36 • Analog Block Pin Description (continued)

Number

Location of

Signal Name

AG6

of Bits

Direction

Output

Input

Function

Details

1

Analog Quad

AT6

ATRETURN67

Input

Temperature monitor return shared by Analog Quad

Analog Quads 6 and 7

AV7

1

Input

Output

Input

Output

Input

Analog Quad 7

Analog Quad

AC7

AG7

AT7

AV8

Analog Quad 8

AC8

AG8

AT8

ATRETURN89

Temperature monitor return shared by Analog Quad

Analog Quads 8 and 9

AV9

1

2

1

Input

Analog Quad 9

Analog Quad

RTC

AC9

AG9

Output

Input

AT9

RTCMATCH

RTCPSMMATCH

RTCXTLMODE[1:0]

RTCXTLSEL

RTCCLK

Output

Input

MATCH

MATCH connected to VRPSM

Drives XTLOSC RTCMODE[1:0] pins

Drives XTLOSC MODESEL pin

RTC clock input

RTC

Analog Quad

With the Fusion family, Microsemi introduces the Analog Quad, shown in Figure 2-65 on page 2-84, as

the basic analog I/O structure. The Analog Quad is a four-channel system used to precondition a set of

analog signals before sending it to the ADC for conversion into a digital signal. To maximize the

usefulness of the Analog Quad, the analog input signals can also be configured as LVTTL digital input

signals. The Analog Quad is divided into four sections.

The first section is called the Voltage Monitor Block, and its input pin is named AV. It contains a two-

channel analog multiplexer that allows an incoming analog signal to be routed directly to the ADC or

allows the signal to be routed to a prescaler circuit before being sent to the ADC. The prescaler can be

configured to accept analog signals between –12 V and 0 or between 0 and +12 V. The prescaler circuit

scales the voltage applied to the ADC input pad such that it is compatible with the ADC input voltage

range. The AV pin can also be used as a digital input pin.

The second section of the Analog Quad is called the Current Monitor Block. Its input pin is named AC.

The Current Monitor Block contains all the same functions as the Voltage Monitor Block with one

addition, which is a current monitoring function. A small external current sensing resistor (typically less

than 1 ) is connected between the AV and AC pins and is in series with a power source. The Current

Monitor Block contains a current monitor circuit that converts the current through the external resistor to

a voltage that can then be read using the ADC.

Revision 4

2-83

Device Architecture

The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG. This

section is used to drive an external FET. There are two modes available: a High Current Drive mode and

a Current Source Control mode. Both negative and positive voltage polarities are available, and in the

current source control mode, four different current levels are available.

The fourth section of the Analog Quad is called the Temperature Monitor Block, and its input pin name is

AT. This block is similar to the Voltage Monitor Block, except that it has an additional function: it can be

used to monitor the temperature of an external diode-connected transistor. It has a modified prescaler

and is limited to positive voltages only.

The Analog Quad can be configured during design time by Libero SoC; however, the ACM can be used

to change the parameters of any of these I/Os during runtime. This type of change is referred to as a

context switch. The Analog Quad is a modular structure that is replicated to generate the analog I/O

resources. Each Fusion device supports between 5 and 10 Analog Quads.

The analog pads are numbered to clearly identify both the type of pad (voltage, current, gate driver, or

temperature pad) and its corresponding Analog Quad (AV0, AC0, AG0, AT0, AV1, …, AC9, AG9, and

AT9). There are three types of input pads (AVx, ACx, and ATx) and one type of analog output pad (AGx).

Since there can be up to 10 Analog Quads on a device, there can be a maximum of 30 analog input pads

and 10 analog output pads.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor/Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-65 • Analog Quad

2-84

Revision 4

Fusion Family of Mixed Signal FPGAs

Voltage Monitor

The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA

industry. The Analog Quad comprises three analog input pads— Analog Voltage (AV), Analog Current

(AC), and Analog Temperature (AT)—and a single gate driver output pad, Analog Gate (AG). There are

many common characteristics among the analog input pads. Each analog input can be configured to

connect directly to the input MUX of the ADC. When configured in this manner (Figure 2-66), there will be

no prescaling of the input signal. Care must be taken in this mode not to drive the ADC into saturation by

applying an input voltage greater than the reference voltage. The internal reference voltage of the ADC is

2.56 V. Optionally, an external reference can be supplied by the user. The external reference can be a

maximum of 3.3 V DC.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-66 • Analog Quad Direct Connect

Revision 4

2-85

Device Architecture

The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input

signals. Figure 2-67 shows the path through the Analog Quad for a signal that is to be prescaled prior to

conversion. The ADC internal reference voltage and the prescaler factors were selected to make both

prescaling and postscaling of the signals easy binary calculations (refer to Table 2-57 on page 2-133 for

details). When an analog input pad is configured with a prescaler, there will be a 1 M resistor to ground.

This occurs even when the device is in power-down mode. In low power standby or sleep mode (VCC is

OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, analog inputs are pulled down to

ground through a 1 M resistor. The gate driver output is floating (or tristated), and there is no extra

current on VCC33A.

These scaling factors hold true whether the particular pad is configured to accept a positive or negative

voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad

supports a reduced set of prescaling factors and supports positive voltages only.

Typical scaling factors are given in Table 2-57 on page 2-133, and the gain error (which contributes to the

minimum and maximum) is in Table 2-49 on page 2-120.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

From FPGA

(GDONx)

To FPGA

(DATOUTx)

(DACOUTx)

To Analog MUX

Figure 2-67 • Analog Quad Prescaler Input Configuration

2-86

Revision 4

Fusion Family of Mixed Signal FPGAs

Terminology

BW – Bandwidth

BW is a range of frequencies that a Channel can handle.

Channel

A channel is define as an analog input configured as one of the Prescaler range shown in Table 2-57 on

page 2-133. The channel includes the Prescaler circuit and the ADC.

Channel Gain

Channel Gain is a measured of the deviation of the actual slope from the ideal slope. The slope is

measured from the 20% and 80% point.

Gain_actual

------------------------

Gain =

Gain_ideal

EQ 1

Channel Gain Error

Channel Gain Error is a deviation from the ideal slope of the transfer function. The Prescaler Gain Error

is expressed as the percent difference between the actual and ideal, as shown in EQ 2.

Error_Gain= (1-Gain)  100%

EQ 2

Channel Input Offset Error

Channel Offset error is measured as the input voltage that causes the transition from zero to a count of

one. An Ideal Prescaler will have offset equal to ½ of LSB voltage. Offset error is a positive or negative

when the first transition point is higher or lower than ideal. Offset error is expressed in LSB or input

voltage.

Total Channel Error

Total Channel Error is defined as the total error measured compared to the ideal value. Total Channel

Error is the sum of gain error and offset error combined. Figure 2-68 shows how Total Channel Error is

measured.

Total Channel Error is defined as the difference between the actual ADC output and ideal ADC output. In

the example shown in Figure 2-68, the Total Channel Error would be a negative number.

Channel Gain

Actual Output

Ideal Output

Total Channel Error

Channel Input

Offset Error

Input Voltage to Prescaler

Figure 2-68 • Total Channel Error Example

Revision 4

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Device Architecture

Direct Digital Input

The AV, AC, and AT pads can also be configured as high-voltage digital inputs (Figure 2-69). As these

pads are 12 V–tolerant, the digital input can also be up to 12 V. However, the frequency at which these

pads can operate is limited to 10 MHz.

To enable one of these analog input pads to operate as a digital input, its corresponding Digital Input

Enable (DENAxy) pin on the Analog Block must be pulled High, where x is either V, C, or T (for AV, AC,

or AT pads, respectively) and y is in the range 0 to 9, corresponding to the appropriate Analog Quad.

When the pad is configured as a digital input, the signal will come out of the Analog Block macro on the

appropriate DAxOUTy pin, where x represents the pad type (V for AV pad, C for AC pad, or T for AT pad)

and y represents the appropriate Analog Quad number. Example: If the AT pad in Analog Quad 5 is

configured as a digital input, it will come out on the DATOUT5 pin of the Analog Block macro.

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-69 • Analog Quad Direct Digital Input Configuration

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Revision 4

Fusion Family of Mixed Signal FPGAs

Current Monitor

The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications. In

addition to supporting the same functionality offered by the AV pad, the AC pad can be configured to

monitor current across an external sense resistor (Figure 2-70). To support this current monitor function,

a differential amplifier with 10x gain passes the amplified voltage drop between the AV and AC pads to

the ADC. The amplifier enables the user to use very small resistor values, thereby limiting any impact on

the circuit. This function of the AC pad does not limit AV pad operation. The AV pad can still be

configured for use as a direct voltage input or scaled through the AV prescaler independently of it’s use

as an input to the AC pad’s differential amplifier.

Power

Off-Chip

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-70 • Analog Quad Current Monitor Configuration

Revision 4

2-89

Device Architecture

To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB

macro must be asserted low for at least t_CMSLOin order to discharge the previous measurement. Then

CMSTB must be asserted high for at least t_CMSETprior to asserting the ADCSTART signal. The CMSTB

must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that the minimum

sample time cannot be less than t_CMSHI. Figure 2-71 shows the timing diagram of CMSTB in relationship

with the ADC control signals.

t_CMSHI

CMSTBx

t

CMSLO

CMSET

VADC

ADCSTART can be asserted

after this point to start ADC

sampling.

ADCSTART

Figure 2-71 • Timing Diagram for Current Monitor Strobe

Figure 2-72 illustrates positive current monitor operation. The differential voltage between AV and AC

goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is drawn

from a 10 V supply and is measured by the voltage drop across a 0.050  sense resistor, The voltage

drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A current creates

a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after amplification. Thus,

the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit resolution and VAREF of 2.56

V, the ADC result is decimal 75. EQ 3 shows how to compute the current from the ADC result.

I = ADC  V_AREF  10  2^N R_sense



EQ 3

where

I is the current flowing through the sense resistor

ADC is the result from the ADC

VAREF is the Reference voltage

N is the number of bits

Rsense is the resistance of the sense resistor

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Revision 4

Fusion Family of Mixed Signal FPGAs

I

R_SENSE

0-12 V

AVx

ACx

CMSTBx

to Analog MUX

VADC

10 X

(refer Table 2-36

for MUX channel

number)

Current Monitor

Figure 2-72 • Positive Current Monitor

Care must be taken when choosing the right resistor for current measurement application. Note that

because of the 10× amplification, the maximum measurable difference between the AV and AC pads is

V_AREF/ 10. A larger AV-to-AC voltage drop will result in ADC saturation; that is, the digital code put out by

the ADC will stay fixed at the full scale value. Therefore, the user must select the external sense resistor

appropriately. Table 2-38 shows recommended resistor values for different current measurement ranges.

When choosing resistor values for a system, there is a trade-off between measurement accuracy and

power consumption. Choosing a large resistor will increase the voltage drop and hence increase

accuracy of the measurement; however the larger voltage drop dissipates more power (P = I²× R).

The Current Monitor is a unipolar system, meaning that the differential voltage swing must be from 0 V to

V_AREF/10. Therefore, the Current Monitor only supports differential voltage where |V_AV-V_AC| is greater

than 0 V. This results in the requirement that the potential of the AV pad must be larger than the potential

of the AC pad. This is straightforward for positive voltage systems. For a negative voltage system, it

means that the AV pad must be "more negative" than the AC pad. This is shown in Figure 2-73.

In this case, both the AV pad and the AC pad are configured for negative operations and the output of the

differential amplifier still falls between 0 V and V_AREFas required.

Revision 4

2-91

Device Architecture

Table 2-37 • Recommended Resistor for Different Current Range Measurement

Current Range

> 5 mA – 10 mA

> 10 mA – 20 mA

> 20 mA – 50 mA

> 50 mA – 100 mA

> 100 mA – 200 mA

> 200 mA – 500 mA

> 500 mA – 1 A

> 1 A – 2 A

Recommended Minimum Resistor Value (Ohms)

10 – 20

5 – 10

2.5 – 5

1 – 2

0.5 – 1

0.3 – 0.5

0.1 – 0.2

0.05 – 0.1

0.025 – 0.05

0.0125 – 0.025

0.00625 – 0.02

> 2 A – 4 A

> 4 A – 8 A

> 8 A – 12 A

I

R_SENSE

0 to

–10.5 V

AVx

ACx

CMSTBx

to Analog MUX

VADC

10 X

(see Table 2-36

for MUXchannel

number)

Current Monitor

Figure 2-73 • Negative Current Monitor

Terminology

Accuracy

The accuracy of Fusion Current Monitor is ±2 mV minimum plus 5% of the differential voltage at the

input. The input accuracy can be translated to error at the ADC output by using EQ 4. The 10 V/V gain is

the gain of the Current Monitor Circuit, as described in the "Current Monitor" section on page 2-89. For 8-

bit mode, N = 8, V_AREF= 2.56 V, zero differential voltage between AV and AC, the Error (E_ADC) is equal to

2 LSBs.

2^N

V_AREF

-----------------

E_ADC= 2mV + 0.05 V_AV– V_AC  10V  V 

EQ 4

where

N is the number of bits

V_AREFis the Reference voltage

_AVis the voltage at AV pad

_ACis the voltage at AC pad

V

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Revision 4

Fusion Family of Mixed Signal FPGAs

Gate Driver

The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin (Figure 2-74).

Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink

or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable gate drive

levels: 1 µA, 3 µA, 10 µA, and 30 µA (Figure 2-75 on page 2-94). The AG also supports a High Current

Drive mode in which it can sink 20 mA; in this mode the switching rate is approximately 1.3 MHz with

100 ns turn-on time and 600 ns turn-off time. Modeled on an open-drain-style output, it does not output a

voltage level without an appropriate pull-up or pull-down resistor. If 1 V is forced on the drain, the current

sinking/sourcing will exceed the ability of the transistor, and the device could be damaged.

The AG pad is turned on via the corresponding GDONx pin in the Analog Block macro, where x is the

number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).

Power

Line Side

Load Side

Off-Chip

R_pullup

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-74 • Gate Driver

The gate-to-source voltage (V_gs) of the external MOSFET is limited to the programmable drive current

times the external pull-up or pull-down resistor value (EQ 5).

V_gs I_g× (R_pullupor R_pulldown

)

EQ 5

The rate at which the gate voltage of the external MOSFET slews is determined by the current, I_g,

sourced or sunk by the AG pin and the gate-to-source capacitance, C_GS, of the external MOSFET. As an

approximation, the slew rate is given by EQ 6.

dv/dt = I_g/ C_GS

EQ 6

Revision 4

2-93

Device Architecture

C_GSis not a fixed capacitance but, depending on the circuitry connected to its drain terminal, can vary

significantly during the course of a turn-on or turn-off transient. Thus, EQ 6 on page 2-93 can only be

used for a first-order estimate of the switching speed of the external MOSFET.

High

Current

1 μA

3 μA

10 μA

30 μA

AG

High

Current

1 μA

3 μA

10 μA

30 μA

Figure 2-75 • Gate Driver Example

2-94

Revision 4

Fusion Family of Mixed Signal FPGAs

Temperature Monitor

The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to implement an

accurate temperature monitor in conjunction with an external diode-connected bipolar transistor

(Figure 2-76). For improved temperature measurement accuracy, it is important to use the ATRTN pin for

the return path of the current sourced by the AT pin. Each ATRTN pin is shared between two adjacent

Analog Quads. Additionally, if not used for temperature monitoring, the AT pin can provide functionality

similar to that of the AV pad. However, in this mode only positive voltages can be applied to the AT pin,

and only two prescaler factors are available (16 V and 4 V ranges—refer to Table 2-57 on page 2-133).

Discrete

Bipolar

Transistor

Off-Chip

ATRTN

AV

AC

AG

AT

Voltage

Monitor Block

Current

Monitor Block

Gate

Driver

Temperature

Monitor Block

Pads

On-Chip

Analog Quad

Prescaler

Power

MOSFET

Gate Driver

Digital

Input

Digital

Input

Digital

Input

Current

Monitor / Instr

Amplifier

Temperature

Monitor

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

From FPGA

(GDONx)

To FPGA

(DATOUTx)

To Analog MUX

Figure 2-76 • Temperature Monitor Quad

Revision 4

2-95

Device Architecture

Fusion uses a remote diode as a temperature sensor. The Fusion Temperature Monitor uses a

differential input; the AT pin and ATRTN (AT Return) pin are the differential inputs to the Temperature

Monitor. There is one Temperature Monitor in each Quad. A simplified block diagram is shown in

Figure 2-77.

VDD33A

10 μA

100 μA

TMSTBx

+

–

ATx

to Analog MUX

(refer Table 2-36

for MUX Channel

Number)

+

VADC

∆V

12.5 X

–

ATRTNxy

Figure 2-77 • Block Diagram for Temperature Monitor Circuit

The Fusion approach to measuring temperature is forcing two different currents through the diode with a

ratio of 10:1. The switch that controls the different currents is controlled by the Temperature Monitor

Strobe signal, TMSTB. Setting TMSTB to '1' will initiate a Temperature reading. The TMSTB should

remain '1' until the ADC finishes sampling the voltage from the Temperature Monitor. The minimum

sample time for the Temperature Monitor cannot be less than the minimum strobe high time minus the

setup time. Figure 2-78 shows the timing diagram.

t_TMSHI

TMSTBx

t_TMSLO

t_TMSSET

VADC

ADC should start

sampling at this point

ADCSTART

Figure 2-78 • Timing Diagram for the Temperature Monitor Strobe Signal

Note: When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad drive

strength ceases and becomes a 1 µA sink into the Fusion device.

2-96

Revision 4

Fusion Family of Mixed Signal FPGAs

The diode’s voltage is measured at each current level and the temperature is calculated based on EQ 7.

I_TMSLO

kT

q







------ -----------------

_TMSLO– V_TMSHI= n ln

V



I_TMSHI

EQ 7

where

I

_TMSLOis the current when the Temperature Strobe is Low, typically 100 µA

_TMSHIis the current when the Temperature Strobe is High, typically 10 µA

V

_TMSLOis diode voltage while Temperature Strobe is Low

_TMSHIis diode voltage while Temperature Strobe is High

V

n is the non-ideality factor of the diode-connected transistor. It is typically 1.004 for the Microsemi-

recommended transistor type 2N3904.

K = 1.3806 x 10^-23J/K is the Boltzman constant

Q = 1.602 x 10^-19C is the charge of a proton

When I_TMSLO/ I_TMSHI= 10, the equation can be simplified as shown in EQ 8.

V = V_TMSLO– V_TMSHI= 1.986  10^–4nT

EQ 8

In the Fusion TMB, the ideality factor n for 2N3904 is 1.004 and V is amplified 12.5 times by an internal

amplifier; hence the voltage before entering the ADC is as given in EQ 9.

V_ADC= V  12.5 = 2.5 mV  K  T

EQ 9

This means the temperature to voltage relationship is 2.5 mV per degree Kelvin. The unique design of

Fusion has made the Temperature Monitor System simple for the user. When the 10-bit mode ADC is

used, each LSB represents 1 degree Kelvin, as shown in EQ 10. That is, e. 25°C is equal to 293°K and is

represented by decimal 293 counts from the ADC.

2¹⁰

2.56 V

----------------

1K = 2.5 mV 

= 1 LSB

EQ 10

If 8-bit mode is used for the ADC resolution, each LSB represents 4 degrees Kelvin; however, the

resolution remains as 1 degree Kelvin per LSB, even for 12-bit mode, due to the Temperature Monitor

design. An example of the temperature data format for 10-bit mode is shown in Table 2-38.

Table 2-38 • Temperature Data Format

Digital Output

Temperature

–40°C

–20°C

0°C

Temperature (K)

(ADC 10-bit mode)

00 1110 1001

00 1111 1101

01 0001 0001

01 0001 0010

01 0001 1011

01 0010 1010

01 0100 0011

01 0110 0110

233

253

273

274

283

298

323

358

1°C

10 °C

25°C

50 °C

85 °C

Revision 4

2-97

Device Architecture

Terminology

Resolution

Resolution defines the smallest temperature change Fusion Temperature Monitor can resolve. For ADC

configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12-bit mode,

the Temperature Monitor can still only resolve 1°C due to Temperature Monitor design.

Offset

The Fusion Temperature Monitor has a systematic offset (Table 2-49 on page 2-120), excluding error due

to board resistance and ideality factor of the external diode. Microsemi provides an IP block (CalibIP) that

is required in order to mitigate the systematic temperature offset. For further details on CalibIP, refer to

the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion

FPGA Fabric User's Guide.

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Revision 4

Fusion Family of Mixed Signal FPGAs

Analog-to-Digital Converter Block

At the heart of the Fusion analog system is a programmable Successive Approximation Register (SAR)

ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve

500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input

multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown

in Figure 2-79. The ADC offers multiple self-calibrating modes to ensure consistent high performance

both at power-up and during runtime.

V

_CC(1.5 V)

0

1

Pads

AV0

AC0

AG0

AT0

Analog

Quad 0

These are hardwired

connections within

Analog Quad.

ATRETURN01

AV1

AC1

AG1

AT1

Analog

Quad 1

AV2

AC2

AG2

AT2

Analog

Quad 2

ATRETURN23

AV3

AC3

AG3

AT3

Analog

Quad 3

AV4

AC4

AG4

AT4

Analog

Quad 4

12

Analog MUX

(32 to 1)

ATRETURN45

ADC

AV5

AC5

AG5

AT5

AV6

AC6

AG6

AT6

Analog

Quad 5

Digital Output to FPGA

Analog

Quad 6

ATRETURN67

AV7

AC7

AG7

AT7

Analog

Quad 7

AV8

AC8

AG8

AT8

Analog

Quad 8

ATRETURN89

AV9

AC9

AG9

AT9

Analog

Quad 9

31

Temperature

Monitor

CHNUMBER[4:0]

Internal Diode

Figure 2-79 • ADC Block Diagram

Revision 4

2-99

Device Architecture

ADC Description

The Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use models.

Figure 2-80 shows a block diagram of the Fusion ADC.

•

Configurable resolution: 8-bit, 10-bit, and 12-bit mode

DNL: 0.6 LSB for 10-bit mode

INL: 0.4 LSB for 10-bit mode

No missing code

Internal VAREF = 2.56 V

Maximum Sample Rate = 600 Ksps

Power-up calibration and dynamic calibration after every sample to compensate for temperature

drift over time

CALIBRATE

SAMPLE

BUSY

DATAVALID

VAREF

Analog

STATUS

MUX

32

12

Signals from

Analog Quads

SAR ADC

RESULT

CHNUMBER

SYSCLK

STC

MODE

TVC

ADCCLK

Figure 2-80 • ADC Simplified Block Diagram

ADC Theory of Operation

An analog-to-digital converter is used to capture discrete samples of a continuous analog voltage and

provide a discrete binary representation of the signal. Analog-to-digital converters are generally

characterized in three ways:

•

Input voltage range

Resolution

Bandwidth or conversion rate

The input voltage range of an ADC is determined by its reference voltage (VREF). Fusion devices

include an internal 2.56 V reference, or the user can supply an external reference of up to 3.3 V. The

following examples use the internal 2.56 V reference, so the full-scale input range of the ADC is 0 to

2.56 V.

The resolution (LSB) of the ADC is a function of the number of binary bits in the converter. The ADC

approximates the value of the input voltage using 2n steps, where n is the number of bits in the converter.

Each step therefore represents VREF÷ 2n volts. In the case of the Fusion ADC configured for 12-bit

operation, the LSB is 2.56 V / 4096 = 0.625 mV.

Finally, bandwidth is an indication of the maximum number of conversions the ADC can perform each

second. The bandwidth of an ADC is constrained by its architecture and several key performance

characteristics.

2-100

Revision 4

Fusion Family of Mixed Signal FPGAs

There are several popular ADC architectures, each with advantages and limitations. The analog-to-digital

converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It

supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per

second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external

reference voltage can be used.

As shown in Figure 2-81, a SAR ADC contains N capacitors with binary-weighted values.

Comparator

C / 2^N–2

C / 2^N–1

C

C / 2

C / 4

VREF

VIN

Figure 2-81 • Example SAR ADC Architecture

To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the

capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very

close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the

comparator. Now the conversion process begins. First, C is switched to VREF Because of the binary

.

weighting of the capacitors, the voltage at the input of the comparator is then shown by EQ 11.

Voltage at input of comparator = –VIN + VREF / 2

EQ 11

If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0.

A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched

back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at

the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the

MSB), and the comparator output now indicates the value of the next most significant bit. This bit is

likewise registered, and the process continues for each subsequent bit until a conversion is completed.

The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.

Revision 4

2-101

Device Architecture

This process results in a binary approximation of VIN. Generally, there is a fixed interval T, the sampling

period, between the samples. The inverse of the sampling period is often referred to as the sampling

frequency f_S= 1 / T. The combined effect is illustrated in Figure 2-82.

LSB

T

Figure 2-82 • Conversion Example

Figure 2-82 demonstrates that if the signal changes faster than the sampling rate can accommodate, or if

the actual value of VIN falls between counts in the result, this information is lost during the conversion.

There are several techniques that can be used to address these issues.

First, the sampling rate must be chosen to provide enough samples to adequately represent the input

signal. Based on the Nyquist-Shannon Sampling Theorem, the minimum sampling rate must be at least

twice the frequency of the highest frequency component in the target signal (Nyquist Frequency). For

example, to recreate the frequency content of an audio signal with up to 22 KHz bandwidth, the user

must sample it at a minimum of 44 ksps. However, as shown in Figure 2-82, significant post-processing

of the data is required to interpolate the value of the waveform during the time between each sample.

Similarly, to re-create the amplitude variation of a signal, the signal must be sampled with adequate

resolution. Continuing with the audio example, the dynamic range of the human ear (the ratio of the

amplitude of the threshold of hearing to the threshold of pain) is generally accepted to be 135 dB, and the

dynamic range of a typical symphony orchestra performance is around 85 dB. Most commercial

recording media provide about 96 dB of dynamic range using 16-bit sample resolution. But 16-bit fidelity

does not necessarily mean that you need a 16-bit ADC. As long as the input is sampled at or above the

Nyquist Frequency, post-processing techniques can be used to interpolate intermediate values and

reconstruct the original input signal to within desired tolerances.

If sophisticated digital signal processing (DSP) capabilities are available, the best results are obtained by

implementing a reconstruction filter, which is used to interpolate many intermediate values with higher

resolution than the original data. Interpolating many intermediate values increases the effective number

of samples, and higher resolution increases the effective number of bits in the sample. In many cases,

however, it is not cost-effective or necessary to implement such a sophisticated reconstruction algorithm.

For applications that do not require extremely fine reproduction of the input signal, alternative methods

can enhance digital sampling results with relatively simple post-processing. The details of such

techniques are out of the scope of this chapter; refer to the Improving ADC Results through

Oversampling and Post-Processing of Data white paper for more information.

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Fusion Family of Mixed Signal FPGAs

ADC Terminology

Conversion Time

Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a

track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one LSB

of a new input value.

DNL – Differential Non-Linearity

For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ by

one LSB (DNL = 0). Any deviation from one LSB in defined as DNL (Figure 2-83).

Ideal Output

Actual Output

Error = –0.5 LSB

Error = +1 LSB

Input Voltage to Prescaler

Figure 2-83 • Differential Non-Linearity (DNL)

ENOB – Effective Number of Bits

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An

ideal ADC’s error consists only of quantization of noise. As the input frequency increases, the overall

noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD

(also see “Signal-to-Noise and Distortion Ratio (SINAD)”.) ENOB for a full-scale, sinusoidal input

waveform is computed using EQ 12.

SINAD – 1.76

------------------------------------

ENOB =

6.02

EQ 12

FS Error – Full-Scale Error

Full-scale error is the difference between the actual value that triggers that transition to full-scale and the

ideal analog full-scale transition value. Full-scale error equals offset error plus gain error.

Revision 4

2-103

Device Architecture

Gain Error

The gain error of an ADC indicates how well the slope of an actual transfer function matches the slope of

the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-scale (%FSR).

Gain error is the full-scale error minus the offset error (Figure 2-84).

Gain = 2 LSB

1...11

Ideal Output

Actual Output

0...00

Input Voltage to Prescaler

Figure 2-84 • Gain Error

Gain Error Drift

Gain-error drift is the variation in gain error due to a change in ambient temperature, typically expressed

in ppm/°C.

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Revision 4

Fusion Family of Mixed Signal FPGAs

INL – Integral Non-Linearity

INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain

errors, the straight line is either a best-fit straight line or a line drawn between the end points of the

transfer function (Figure 2-85).

INL = +0.5 LSB

Ideal Output

Actual Output

INL = +1 LSB

Input Voltage to Prescaler

Figure 2-85 • Integral Non-Linearity (INL)

LSB – Least Significant Bit

In a binary number, the LSB is the least weighted bit in the group. Typically, the LSB is the furthest right

bit. For an ADC, the weight of an LSB equals the full-scale voltage range of the converter divided by 2^N,

where N is the converter’s resolution.

EQ 13 shows the calculation for a 10-bit ADC with a unipolar full-scale voltage of 2.56 V:

1 LSB = (2.56 V / 2¹⁰) = 2.5 mV

EQ 13

No Missing Codes

An ADC has no missing codes if it produces all possible digital codes in response to a ramp signal

applied to the analog input.

Offset Error

Offset error indicates how well the actual transfer function matches the ideal transfer function at a single

point. For an ideal ADC, the first transition occurs at 0.5 LSB above zero. The offset voltage is measured

by applying an analog input such that the ADC outputs all zeroes and increases until the first transition

occurs (Figure 2-86 on page 2-106).

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Device Architecture

Ideal Output

Actual Output

0...01

0...00

Offset Error = 1.5 LSB

Input Voltage to Prescaler

Figure 2-86 • Offset Error

Resolution

ADC resolution is the number of bits used to represent an analog input signal. To more accurately

replicate the analog signal, resolution needs to be increased.

Sampling Rate

Sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an ADC

acquires (samples) the analog input.

SNR – Signal-to-Noise Ratio

SNR is the ratio of the amplitude of the desired signal to the amplitude of the noise signals at a given

point in time. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR

(EQ 14) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual

error). The ideal, theoretical minimum ADC noise is caused by quantization error only and results directly

from the ADC’s resolution (N bits):

SNR_dB[MAX]= 6.02_dB N + 1.76_dB

EQ 14

SINAD – Signal-to-Noise and Distortion

SINAD is the ratio of the rms amplitude to the mean value of the root-sum-square of the all other spectral

components, including harmonics, but excluding DC. SINAD is a good indication of the overall dynamic

performance of an ADC because it includes all components which make up noise and distortion.

Total Harmonic Distortion

THD measures the distortion content of a signal, and is specified in decibels relative to the carrier (dBc).

THD is the ratio of the RMS sum of the selected harmonics of the input signal to the fundamental itself.

Only harmonics within the Nyquist limit are included in the measurement.

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Fusion Family of Mixed Signal FPGAs

TUE – Total Unadjusted Error

TUE is a comprehensive specification that includes linearity errors, gain error, and offset error. It is the

worst-case deviation from the ideal device performance. TUE is a static specification (Figure 2-87).

TUE = ±0.5 LSB

IDEAL OUTPUT

Input Voltage to Prescaler

Figure 2-87 • Total Unadjusted Error (TUE)

ADC Operation

Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a

calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust

calibration scheme to reduce integrated offset and linearity errors. The offset and linearity errors of the

main capacitor array are compensated for with an 8-bit calibration capacitor array. The offset/linearity

error calibration is carried out in two ways. First, a power-up calibration is carried out when the ADC

comes out of reset. This is initiated by the CALIBRATE output of the Analog Block macro and is a fixed

number of ADC_CLK cycles (3,840 cycles), as shown in Figure 2-89 on page 2-114. In this mode, the

linearity and offset errors of the capacitors are calibrated.

To further compensate for drift and temperature-dependent effects, every conversion is followed by post-

calibration of either the offset or a bit of the main capacitor array. The post-calibration ensures that, over

time and with temperature, the ADC remains consistent.

After both calibration and the setting of the appropriate configurations, as explained above, the ADC is

ready for operation. Setting the ADCSTART signal high for one clock period will initiate the sample and

conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The status signals

SAMPLE and BUSY will show when the ADC is sampling and converting (Figure 2-91 on page 2-115).

Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held the analog signal,

SAMPLE will go low. After the entire operation has completed and the analog signal is converted, BUSY

will go low and DATAVALID will go high. This indicates that the digital result is available on the

RESULT[11:0] pins.

DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on the

rising edge of SYSCLK as shown in Figure 2-90 on page 2-114. The RESULT signals will be kept

constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available

when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The RESULT

is latched and remains unchanged until the next DATAVLAID rising edge.

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Device Architecture

ADC Input Multiplexer

At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user

definable. Two of these channels are hardwired internally. Channel 31 connects to an internal

temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is wired to

the FPGA’s 1.5 V VCC supply, enabling the Fusion device to monitor its own power supply. Doing this

internally makes it unnecessary to use an analog I/O to support these functions. The balance of the MUX

inputs are connected to Analog Quads (see the "Analog Quad" section on page 2-83). Table 2-40 defines

which Analog Quad inputs are associated with which specific analog MUX channels. The number of

Analog Quads present is device-dependent; refer to the family list in the "Fusion Family" table on page I

of this datasheet for the number of quads per device. Regardless of the number of quads populated in a

device, the internal connections to both VCC and the internal temperature diode remain on Channels 0

and 31, respectively. To sample the internal temperature monitor, it must be strobed (similar to the AT

pads). The TMSTBINT pin on the Analog Block macro is the control for strobing the internal temperature

measurement diode.

To determine which channel is selected for conversion, there is a five-pin interface on the Analog Block,

CHNUMBER[4:0], defined in Table 2-39.

Table 2-39 • Channel Selection

Channel Number

CHNUMBER[4:0]

00000

0

1

2

3

00001

00010

00011

.

30

31

11110

11111

Table 2-40 shows the correlation between the analog MUX input channels and the analog input pins.

Table 2-40 • Analog MUX Channels

Analog MUX Channel

Signal

Vcc_analog

AV0

Analog Quad Number

0

1

Analog Quad 0

2

AC0

3

AT0

4

AV1

Analog Quad 1

Analog Quad 2

Analog Quad 3

Analog Quad 4

5

AC1

6

AT1

7

AV2

8

AC2

9

AT2

10

11

12

13

14

15

AV3

AC3

AT3

AV4

AC4

AT4

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Fusion Family of Mixed Signal FPGAs

Table 2-40 • Analog MUX Channels (continued)

Analog MUX Channel

Signal

AV5

AC5

AT5

AV6

AC6

AT6

AV7

AC7

AT7

AV8

AC8

AT8

AV9

AC9

AT9

Analog Quad Number

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Analog Quad 5

Analog Quad 6

Analog Quad 7

Analog Quad 8

Analog Quad 9

31

Internal temperature

monitor

The ADC can be powered down independently of the FPGA core, as an additional control or for power-

saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the

comparators in the ADC.

ADC Modes

The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion,

and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41 on page 2-109.

The output of the ADC is the RESULT[11:0] signal. In 8-bit mode, the Most Significant 8 Bits

RESULT[11:4] are used as the ADC value and the Least Significant 4 Bits RESULT[3:0] are logical '0's.

In 10-bit mode, RESULT[11:2] are used the ADC value and RESULT[1:0] are logical 0s.

Table 2-41 • Mode Bits Function

Name

Bits

Function

MODE

3

0 – Internal calibration after every conversion; two ADCCLK cycles are used

after the conversion.

1 – No calibration after every conversion

MODE

2

0 – Power-down after conversion

1 – No Power-down after conversion

1:0

00 – 10-bit

01 – 12-bit

10 – 8-bit

11 – Unused

Integrated Voltage Reference

The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this

reference voltage was chosen to make the prescaling and postscaling factors for the prescaler blocks

change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V can be

Revision 4

2-109

Device Architecture

connected between the VAREF and ADCGNDREF pins. The VAREFSEL control pin is used to select the

reference voltage.

Table 2-42 • VAREF Bit Function

Name

Bit

Function

VAREF

0

Reference voltage selection

0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.

1 – Input external voltage reference from VAREF and ADCGNDREF

ADC Clock

The speed of the ADC depends on its internal clock, ADCCLK, which is not accessible to users. The

ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of

the ADCCLK in relationship to SYSCLK, based on EQ 15.

t_ADCCLK= 4  1 + TVC  t_SYSCLK

EQ 15

TVC: Time Divider Control (0–255)

t

_ADCCLKis the period of ADCCLK, and must be between 0.5 MHz and 10 MHz

_SYSCLKis the period of SYSCLK

Table 2-43 • TVC Bits Function

Name

Bits

Function

TVC

[7:0]

SYSCLK divider control

The frequency of ADCCLK, f_ADCCLK, must be within 0.5 Hz to 10 MHz.

The inputs to the ADC are synchronized to SYSCLK. A conversion is initiated by asserting the

ADCSTART signal on a rising edge of SYSCLK. Figure 2-90 on page 2-114 and Figure 2-91 on

page 2-115 show the timing diagram for the ADC.

Acquisition Time or Sample Time Control

Acquisition time (t_SAMPLE) specifies how long an analog input signal has to charge the internal capacitor

array. Figure 2-88 shows a simplified internal input sampling mechanism of a SAR ADC.

Sample and Hold

R

Z

source

INAD

C

INAD

Figure 2-88 • Simplified Sample and Hold Circuitry

The internal impedance (Z_INAD), external source resistance (R_SOURCE), and sample capacitor (C_INAD

)

form a simple RC network. As a result, the accuracy of the ADC can be affected if the ADC is given

insufficient time to charge the capacitor. To resolve this problem, you can either reduce the source

resistance or increase the sampling time by changing the acquisition time using the STC signal.

EQ 16 through EQ 18 can be used to calculate the acquisition time required for a given input. The STC

signal gives the number of sample periods in ADCCLK for the acquisition time of the desired signal. If the

actual acquisition time is higher than the STC value, the settling time error can affect the accuracy of the

ADC, because the sampling capacitor is only partially charged within the given sampling cycle. Example

acquisition times are given in Table 2-44 and Table 2-45. When controlling the sample time for the ADC

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Revision 4

Fusion Family of Mixed Signal FPGAs

along with the use of the active bipolar prescaler, current monitor, or temperature monitor, the minimum

sample time(s) for each must be obeyed. EQ 19 can be used to determine the appropriate value of STC.

You can calculate the minimum actual acquisition time by using EQ 16:

VOUT = VIN(1 – e–^t/RC

)

EQ 16

EQ 17

For 0.5 LSB gain error, VOUT should be replaced with (VIN –(0.5 × LSB Value)):

(VIN – 0.5 × LSB Value) = VIN(1 – e–^t/RC

)

where VIN is the ADC reference voltage (VREF)

Solving EQ 17:

t = RC x ln (VIN / (0.5 x LSB Value))

EQ 18

EQ 19

where R = Z_INAD+ R_SOURCEand C = C_INAD

Calculate the value of STC by using EQ 19.

.

t_SAMPLE= (2 + STC) x (1 / ADCCLK) or t_SAMPLE= (2 + STC) x (ADC Clock Period)

where ADCCLK = ADC clock frequency in MHz.

t_SAMPLE= 0.449 µs from bit resolution in Table 2-44.

ADC Clock frequency = 10 MHz or a 100 ns period.

STC = (t_SAMPLE/ (1 / 10 MHz)) – 2 = 4.49 – 2 = 2.49.

You must round up to 3 to accommodate the minimum sample time.

Table 2-44 • Acquisition Time Example with VAREF = 2.56 V

VIN = 2.56V, R = 4K (R_SOURCE~ 0), C = 18 pF

Resolution

LSB Value (mV)

Min. Sample/Hold Time for 0.5 LSB (µs)

8

10

2.5

0.449

0.549

0.649

10

12

0.625

Table 2-45 • Acquisition Time Example with VAREF = 3.3 V

VIN = 3.3V, R = 4K (R_SOURCE~ 0), C = 18 pF

LSB Value (mV) Min. Sample/Hold time for 0.5 LSB (µs)

Resolution

8

12.891

3.223

0.806

0.449

0.549

0.649

10

12

Sample Phase

A conversion is performed in three phases. In the first phase, the analog input voltage is sampled on the

input capacitor. This phase is called sample phase. During the sample phase, the output signals BUSY

and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the analog signal. The

sample time can be controlled by input signals STC[7:0]. The sample time can be calculated by EQ 20.

When controlling the sample time for the ADC along with the use of Prescaler or Current Monitor or

Temperature Monitor, the minimum sample time for each must be obeyed. Refer to Table 2-46 on

page 2-112 and the "Acquisition Time or Sample Time Control" section on page 2-110

t_sample= 2 + STC  t_ADCCLK

EQ 20

STC: Sample Time Control value (0–255)

t_SAMPLEis the sample time

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2-111

Device Architecture

Table 2-46 • STC Bits Function

Name

Bits

Function

STC

[7:0]

Sample time control

Sample time is computed based on the period of ADCCLK.

Distribution Phase

The second phase is called the distribution phase. During distribution phase, the ADC computes the

equivalent digital value from the value stored in the input capacitor. In this phase, the output signal

SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains '1', indicating

the ADC is still busy for distribution. The distribution time depends strictly on the number of bits. If the

ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed. EQ 8 describes the distribution

time.

t_distrib= N  t_ADCCLK

EQ 21

N: Number of bits

Post-Calibration Phase

The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase takes

two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is completed.

If the post-calibration phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon

as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on

the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Microsemi

recommends enabling post-calibration to compensate for drift and temperature-dependent effects. This

ensures that the ADC remains consistent over time and with temperature. The post-calibration phase is

enabled by bit 3 of the Mode register. EQ 9 describes the post-calibration time.

t_post-cal= MODE3  2  t_ADCCLK



EQ 22

MODE[3]: Bit 3 of the Mode register, described in Table 2-41 on page 2-109.

The calculation for the conversion time for the ADC is summarized in EQ 23.

t_conv= t_{sync_read}+ t_sample+ t_distrib+ t_post-cal+ t_{sync_write}

EQ 23

t

_conv: conversion time

t_{sync_read}: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the

worst case is a period of SYSCLK, t_SYSCLK

_sample: Sample time

t_distrib: Distribution time

.

t

_post-cal: Post-calibration time

_{sync_write}: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the

t

worst case is a period of SYSCLK, t_SYSCLK

.

Intra-Conversion

Performing a conversion during power-up calibration is possible but should be avoided, since the

performance is not guaranteed, as shown in Table 2-49 on page 2-120. This is described as intra-

conversion. Figure 2-92 on page 2-115 shows intra-conversion (conversion that starts during power-up

calibration).

Injected Conversion

A conversion can be interrupted by another conversion. Before the current conversion is finished, a

second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion

is issued before the current conversion is completed, the current conversion would be dropped and the

ADC would start the second conversion on the rising edge of the SYSCLK. This is known as injected

conversion. Since the ADC is synchronous, the minimum time to issue a second conversion is two clock

cycles of SYSCLK after the previous one. Figure 2-93 on page 2-116 shows injected conversion

2-112

Revision 4

Fusion Family of Mixed Signal FPGAs

(conversion that starts before a previously started conversion is finished). The total time for

calibration still remains 3,840 ADCCLK cycles.

ADC Example

This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode

for a system that runs at 66 MHz. Assume the acquisition times defined in Table 2-44 on page 2-111 for

10-bit mode, which gives 0.549 µs as a minimum hold time.

The period of SYSCLK: t_SYSCLK= 1/66 MHz = 0.015 µs

Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK

requirement. A higher TVC leads to a higher ADCCLK period.

The minimum TVC is chosen so that t_distriband t_post-calcan be run faster. The period of ADCCLK with a

TVC of 1 can be computed by EQ 24.

t_ADCCLK= 4  1 + TVC  t_SYSCLK= 4  1 + 1  0.015 µs = 0.12 µs

EQ 24

The STC value can now be computed by using the minimum sample/hold time from Table 2-44 on

page 2-111, as shown in EQ 25.

t_sample

--------------------

t_ADCCLK

0.549 µs

0.12 µs

----------------------

– 2 = 4.575 – 2 = 2.575

STC =

– 2 =

EQ 25

You must round up to 3 to accommodate the minimum sample time requirement. The actual sample time,

t_sample, with an STC of 3, is now equal to 0.6 µs, as shown in EQ 26

t_sample= 2 + STC  t_ADCCLK= 2 + 3  t_ADCCLK= 5  0.12 µs = 0.6 µs

EQ 26

Microsemi recommends post-calibration for temperature drift over time, so post-calibration is enabled.

The post-calibration time, t_post-cal, can be computed by EQ 27. The post-calibration time is 0.24 µs.

t_post-cal= 2  t_ADCCLK= 0.24 µs

EQ 27

The distribution time, t_distrib, is equal to 1.2 µs and can be computed as shown in EQ 28 (N is number of

bits, referring back to EQ 8 on page 2-97).

t_distrib= N  t_ADCCLK= 10  0.12 = 1.2 µs

EQ 28

The total conversion time can now be summated, as shown in EQ 29 (referring to EQ 23 on page 2-112).

t_{sync_read}+ t_sample+ t_distrib+ t_post-cal

+

_{tsync_write}= (0.015 + 0.60 + 1.2 + 0.24 + 0.015) µs = 2.07 µs

EQ 29

The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is shown in

Table 2-47:

Table 2-47 • Optimal Setting at 66 MHz in 10-Bit Mode

TVC[7:0]

STC[7:0]

MODE[3:0]

= 1

= 0x01

= 0x03

= 0x4*

= 3

= b'0100

Note: No power-down after every conversion is chosen in this case; however, if the application is

power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any

performance.

Revision 4

2-113

Device Architecture

Timing Diagrams

t_CAL= 3,840 t_ADCCLK

*

SYSCLK

t_RECCLR

t_REMCLR

ADCRESET

t_SUTVCt_HDTVC

TVC[7:0]

t_CK2QCAL

CALIBRATE

Note: *Refer to EQ 15 on page 2-110 for the calculation on the period of ADCCLK, t_ADCCLK

.

Figure 2-89 • Power-Up Calibration Status Signal Timing Diagram

t_MINSYSCLK

t_MPWSYSCLK

SYSCLK

t_SUADCSTARTt_HDADCSTART

ADCSTART

t_SUMODEt_HDMODE

MODE[3:0]

TVC[7:0]

t_SUTVCt_HDTVC

t_SUSTCt_HDSTC

STC[7:0]

VAREF

t_SUVAREFSELt_HDVAREFSEL

t_SUCHNUMt_HDCHNUM

CHNUMBER[7:0]

Figure 2-90 • Input Setup Time

2-114

Revision 4

Fusion Family of Mixed Signal FPGAs

Standard Conversion

3

t_SAMPLE

1

t_DATA2START

SYSCLK

t_SUADCSTARTt_HDADCSTART

ADCSTART

BUSY

t_CK2QBUSY

t_CK2QSAMPLE

SAMPLE

2

t_CONV

t_CK2QVAL

DATAVALID

ADC_RESULT[11:0]

t_CLK2RESULT

1^stSample Result

2^ndSample Result

Notes:

1. Refer to EQ 20 on page 2-111 for the calculation on the sample time, t

.

SAMPLE

2. See EQ 23 on page 2-112 for calculation of the conversion time, t

.

CONV

3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period

Figure 2-91 • Standard Conversion Status Signal Timing Diagram

Intra-Conversion

SYSCLK

ADCRESET

ADCSTART

t_CK2QBUSY

BUSY

t_CK2QSAMPLEt_CK2QSAMPLE

SAMPLE

DATAVALID

CALIBRATE

t_CLR2QVAL

t_CONV

*

t_CK2QVAL

t_CK2QCAL

Interrupts Power-Up Calibration

Resumes Power-Up Calibration

Note: *t_CONVrepresents the conversion time of the second conversion. See EQ 23 on page 2-112 for calculation of the

conversion time, t_CONV

Figure 2-92 • Intra-Conversion Timing Diagram

.

Revision 4

2-115

Device Architecture

Injected Conversion

SYSCLK

ADCSTART

BUSY

1st Start

2nd Start

t_CK2QBUSY

t_CK2QSAMPLE

t_CK2QVAL

1st Conversion

1st Conversion Cancelled,

2nd Conversion

t_CK2QSAMPLE

SAMPLE

t_CONV

*

t_CK2QVAL

DATAVALID

Note: *See EQ 23 on page 2-112 for calculation on the conversion time, t_CONV

.

Figure 2-93 • Injected Conversion Timing Diagram

2-116

Revision 4

Fusion Family of Mixed Signal FPGAs

ADC Interface Timing

Table 2-48 • ADC Interface Timing

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Description

Mode Pin Setup Time

Parameter

t_SUMODE

–2

0.56

0.26

0.68

0.32

1.58

1.27

0.00

0.67

0.90

0.00

0.75

0.43

1.33

0.63

3.12

0.22

2.53

2.06

2.15

2.41

2.17

2.25

0.00

0.63

4.00

100.00

–1

0.64

0.29

0.77

0.36

1.79

1.45

0.00

0.76

1.03

0.00

0.85

0.49

1.51

0.71

3.55

0.25

2.89

2.35

2.45

2.74

2.48

2.56

0.00

0.72

4.00

100.00

Std.

0.75

0.34

0.90

0.43

2.11

1.71

0.00

0.89

1.21

0.00

1.00

0.57

1.78

0.84

4.17

0.30

3.39

2.76

2.88

3.22

2.91

3.01

0.00

0.84

4.00

100.00

Units

ns

MHz

t_HDMODE

Mode Pin Hold Time

t_SUTVC

Clock Divide Control (TVC) Setup Time

Clock Divide Control (TVC) Hold Time

Sample Time Control (STC) Setup Time

Sample Time Control (STC) Hold Time

Voltage Reference Select (VAREFSEL) Setup Time

Voltage Reference Select (VAREFSEL) Hold Time

Channel Select (CHNUMBER) Setup Time

Channel Select (CHNUMBER) Hold Time

Start of Conversion (ADCSTART) Setup Time

Start of Conversion (ADCSTART) Hold Time

Busy Clock-to-Q

t_HDTVC

t_SUSTC

t_HDSTC

t_SUVAREFSEL

t_HDVAREFSEL

t_SUCHNUM

t_HDCHNUM

t_SUADCSTART

t_HDADCSTART

t_CK2QBUSY

t_CK2QCAL

Power-Up Calibration Clock-to-Q

Valid Conversion Result Clock-to-Q

Sample Clock-to-Q

t_CK2QVAL

t_CK2QSAMPLE

t_CK2QRESULT

t_CLR2QBUSY

t_CLR2QCAL

t_CLR2QVAL

t_CLR2QSAMPLE

t_CLR2QRESULT

t_RECCLR

Conversion Result Clock-to-Q

Busy Clear-to-Q

Power-Up Calibration Clear-to-Q

Valid Conversion Result Clear-to-Q

Sample Clear-to-Q

Conversion result Clear-to-Q

Recovery Time of Clear

t_REMCLR

Removal Time of Clear

t_MPWSYSCLK

t_FMAXSYSCLK

Clock Minimum Pulse Width for the ADC

Clock Maximum Frequency for the ADC

Revision 4

2-117

Device Architecture

Typical Performance Characteristics

Temperature Errror vs. Die Temperature

3.5

3

2.5

2

1.5

1

0.5

0

–40

10

60

110

Temperature (°C)

Figure 2-94 • Temperature Error

Temperature Error vs. Interconnect Capacitance

1

0

-1

-2

-3

-4

-5

-6

-7

0

500

1000

1500

2000

Capacitance (pF)

Figure 2-95 • Effect of External Sensor Capacitance

2-118

Revision 4

Fusion Family of Mixed Signal FPGAs

Temperature Reading Noise RMS vs. Averaging

12

10

8

6

4

2

0

1

10

100

1000

10000

Number of Averages

Figure 2-96 • Temperature Reading Noise When Averaging is Used

Revision 4

2-119

Device Architecture

Analog System Characteristics

Table 2-49 • Analog Channel Specifications

Commercial Temperature Range Conditions, T_J= 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min. Typ.

Max.

Units

Voltage Monitor Using Analog Pads AV, AC and AT (using prescaler)

Input Voltage

(Prescaler)

Refer to Table 3-2 on page 3-3

VINAP

Uncalibrated Gain and

Offset Errors

Refer to Table 2-51 on

page 2-125

Calibrated Gain and

Offset Errors

Refer to Table 2-52 on

page 2-126

Bandwidth1

100

KHz

Input Resistance

Scaling Factor

Refer to Table 3-3 on page 3-4

Prescaler modes (Table 2-57 on

page 2-133)

Sample Time

10

µs

Current Monitor Using Analog Pads AV and AC

VRSM¹

Maximum Differential

Input Voltage

VAREF / 10

mV

Resolution

Refer to "Current Monitor"

section

Common Mode Range

– 10.5 to +12

V

CMRR

Common Mode

Rejection Ratio

DC – 1 KHz

60

dB

1 KHz - 10 KHz

> 10 KHz

50

30

dB

µs

t_CMSHI

Strobe High time

ADC

conv.

time

200

t_CMSHI

Strobe Low time

Settling time

Accuracy

5

µs

0.02

Input differential voltage > 50 mV

–2 –(0.05 x

VRSM) to +2 +

(0.05 x VRSM)

mV

Notes:

1. VRSM is the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no

reliability concern on digital inputs as long as VIND does not exceed these limits.

3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.

4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance

allowed across the AT pins is 500 pF.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer

to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s

Guide.

2-120

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-49 • Analog Channel Specifications (continued)

Commercial Temperature Range Conditions, T_J= 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min. Typ.

Max.

Units

Temperature Monitor Using Analog Pad AT

External

Temperature

Monitor

Resolution

8-bit ADC

10-bit ADC

12-bit ADC

AFS090 uncalibrated⁷

AFS090, AFS250, calibrated⁷

4

1

°C

0.25

5

(external diode

2N3904,

Systematic Offset⁵

T_J= 25°C)⁴

0

AFS250, AFS600, AFS1500,

uncalibrated⁷

11

AFS600, AFS1500, calibrated⁷

0

°C

µA

nF

Accuracy

±3

10

±5

External Sensor Source High level, TMSTBx = 0

Current

Low level, TMSTBx = 1

100

Max Capacitance on AT

pad

1.3

Internal

Temperature

Monitor

Resolution

8-bit ADC

4

1

°C

10-bit ADC

12-bit ADC

0.25

Systematic Offset⁵

AFS090 uncalibrated⁷

AFS090, AFS250, calibrated⁷

5

0

AFS250, AFS600, AFS1500

uncalibrated⁷

11

AFS600, AFS1500 calibrated⁷

0

°C

µs

Accuracy

±3

±5

t_TMSHI

Strobe High time

Strobe Low time

Settling time

10

5

105

t_TMSLO

t_TMSSET

Notes:

5

1. VRSM is the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no

reliability concern on digital inputs as long as VIND does not exceed these limits.

3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.

4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance

allowed across the AT pins is 500 pF.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer

to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s

Guide.

Revision 4

2-121

Device Architecture

Table 2-49 • Analog Channel Specifications (continued)

Commercial Temperature Range Conditions, T_J= 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min. Typ.

Max.

Units

Digital Input using Analog Pads AV, AC and AT

VIND^2,3

VHYSDIN

VIHDIN

VILDIN

VMPWDIN

F_DIN

Input Voltage

Refer to Table 3-2 on page 3-3

Hysteresis

0.3

V

Input High

1.2

Input Low

0.9

50

V

Minimum Pulse With

Maximum Frequency

Input Leakage Current

Dynamic Current

Input Delay

ns

10

MHz

µA

ns

ISTBDIN

IDYNDIN

t_INDIN

2

20

10

Gate Driver Output Using Analog Pad AG

VG

IG

Voltage Range

Refer to Table 3-2 on page 3-3

High Current Mode⁶at 1.0 V

Low Current Mode: ±1 µA

Low Current Mode: ±3 µA

Low Current Mode: ± 10 µA

Low Current Mode: ± 30 µA

Output Current Drive

±20

1.3

mA

µA

0.8

2.0

7.4

1.0

2.7

9.0

3.3

µA

11.5

32.0

100

µA

21.0 27.0

µA

IOFFG

F_G

Maximum Off Current

Maximum switching rate High Current Mode⁶at 1.0 V, 1

nA

1.3

3

MHz

k resistive load

Low Current Mode:

±1 µA, 3 M resistive load

KHz

Low Current Mode:

±3 µA, 1 M resistive load

7

Low Current Mode:

±10 µA, 300 k resistive load

25

78

Low Current Mode:

±30 µA, 105 k resistive load

Notes:

1. VRSM is the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no

reliability concern on digital inputs as long as VIND does not exceed these limits.

3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.

4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance

allowed across the AT pins is 500 pF.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer

to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s

Guide.

2-122

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-50 • ADC Characteristics in Direct Input Mode

Commercial Temperature Range Conditions, T_J= 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min.

Typ.

Max.

Units

Direct Input using Analog Pad AV, AC, AT

VINADC

CINADC

Input Voltage (Direct Input)

Input Capacitance

Refer to Table 3-2 on

page 3-3

Channel not selected

7

8

pF

Channel selected but not

sampling

Channel selected and

sampling

18

pF

ZINADC

Input Impedance

8-bit mode

10-bit mode

12-bit mode

2

k

Analog Reference Voltage VAREF

VAREF

Accuracy

T_J= 25°C

2.537

2.527

2.56

65

2.583

V

Temperature Drift of

Internal Reference

ppm / °C

External Reference

VCC33A + 0.05

V

ADC Accuracy (using external reference) ^1,2

DC Accuracy

TUE

INL

Total Unadjusted Error

Integral Non-Linearity

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

8-bit mode

0.29

LSB

0.72

1.8

0.20

0.32

1.71

0.20

0.25

0.43

1.80

0.24

DNL

Differential Non-Linearity

(no missing code)

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

0.60

2.40

0.01

0.05

0.20

0.65

2.48

LSB

Offset Error

Gain Error

0.17

LSB

0.20

LSB

0.40

LSB

0.0004

0.002

0.007

2

0.003

0.011

0.044

LSB

Gain Error (with internal All modes

reference)

% FSR

Notes:

1. Accuracy of the external reference is 2.56 V ± 4.6 mV.

2. Data is based on characterization.

3. The sample rate is time-shared among active analog inputs.

Revision 4

2-123

Device Architecture

Table 2-50 • ADC Characteristics in Direct Input Mode (continued)

Commercial Temperature Range Conditions, T_J= 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min.

Typ.

Max.

Units

Dynamic Performance

SNR

Signal-to-Noise Ratio

8-bit mode

48.0

58.0

62.9

47.6

57.4

62.0

49.5

60.0

64.5

49.5

59.8

64.2

–74.4

dB

dBc

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

8-bit mode

SINAD

THD

Signal-to-Noise Distortion

Total Harmonic

Distortion

–63.0

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

–78.3

–77.9

7.9

–63.0

–64.4

dBc

bits

ENOB

Effective Number of Bits

7.6

9.5

9.6

10.0

10.4

Conversion Rate

Conversion Time

8-bit mode

10-bit mode

12-bit mode

8-bit mode

10-bit mode

12-bit mode

1.7

1.8

2

µs

Sample Rate

600

550

500

Ksps

Notes:

1. Accuracy of the external reference is 2.56 V ± 4.6 mV.

2. Data is based on characterization.

3. The sample rate is time-shared among active analog inputs.

2-124

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-51 • Uncalibrated Analog Channel Accuracy*

Worst-Case Industrial Conditions, T_J= 85°C

Total Channel

Error (LSB)

Channel Input Offset

Error (LSB)

Channel Input Offset

Channel Gain Error

(%FSR)

Error (mV)

Analog Prescaler Neg.

Pos. Neg

Pos.

Neg.

Max.

Pos.

Max.

Pad

Range (V) Max. Med. Max. Max Med. Max.

Med.

Min. Typ. Max.

Positive Range

ADC in 10-Bit Mode

AV, AC

16

8

–22

–40

–45

–2

–5

–9

12

17

24

33

5

–11

–16

–33

–11

–12

–20

–40

–4

–2

–5

14

21

36

66

26

38

40

88

4

–169

–87

–63

–66

–11

–6

–32

–40

–43

–39

–3

224

166

144

131

26

3

2

3

5

7

1

0

–3

–4

–3

–4

–5

–1

4

–11

–20

–3

0

2

–70 –19

–25 –7

0

1

–1

0

0.5

0.25

0.125

16

4

–41 –12

–53 –14

–89 –29

8

–7

–4

19

24

15

–14

–28

0

–5

–3

10

–5

–4

11

0

AT

–3

9

2

–64

–44

5

64

0

–10

–11

–2

11

–8

44

0

Negative Range

ADC in 10-Bit Mode

AV, AC

16

8

–35 –10

–65 –19

–86 –28

–136 –53

–98 –35

–121 –46

–149 –49

–188 –67

9

–24

–34

–64

–6

9

–383

–268

–254

–230

–39

–96

–99

–96

–83

–8

148

75

76

78

15

9

5

–1

–2

–3

–4

–5

–6

–5

12

21

37

8

–12

–24

9

4

19

39

15

18

40

56

5

–6

2

–115 –42

6

–7

1

–39

–54

–72

–8

10

14

16

–10

–11

–12

–14

0.5

0.25

0.125

7

–14

–16

–27

–7

19

38

–18

–4

10

7

–112 –27

–14

–3

Note: *Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For

8-bit mode, divide the LSB count by 4. Gain remains the same.

Revision 4

2-125

Device Architecture

Table 2-52 • Calibrated Analog Channel Accuracy ^1,2,3

Worst-Case Industrial Conditions, T_J= 85°C

Condition

Total Channel Error (LSB)

Analog

Pad

Prescaler Range (V)

Positive Range

Input Voltage⁴(V)

Negative Max.

Median

Positive Max.

ADC in 10-Bit Mode

AV, AC

16

0.300 to 12.0

0.250 to 8.00

0.200 to 4.00

0.150 to 2.00

0.050 to 1.00

0.300 to 16.0

0.100 to 4.00

–6

–7

–6

–5

–7

1

6

7

6

5

7

8

0

4

–1

2

0

1

–1

AT

16

0

4

–1

Negative Range

ADC in 10-Bit Mode

AV, AC

16

8

–0.400 to –10.5

–0.350 to –8.00

–0.300 to –4.00

–0.250 to –2.00

–0.050 to –1.00

–7

1

9

7

–1

–2

–1

4

–7

9

2

–7

7

1

–16

20

Notes:

1. Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit

mode, divide the LSB count by 4. Overall accuracy remains the same.

2. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the

"Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s Guide.

3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points.

4. The lower limit of the input voltage is determined by the prescaler input offset.

2-126

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages

Typical Conditions, T_A= 25°C

Direct ADC ^2,3

(%FSR)

Calibrated Typical Error per Positive Prescaler Setting ¹(%FSR)

Input Voltage

(V)

16 V (12 V)

(AV/AC)

8 V

4 V

2 V

1 V

16 V (AT)

(AV/AC) 4 V (AT) (AV/AC) (AV/AC) (AV/AC) VAREF = 2.56 V

15

1

2

3

4

5

7

9

14

12

1

2

4

5

6

9

5

1

3.3

2.5

1.8

1.5

1.2

0.9

Notes:

1

2

4

1

2

3

1

2

3

1

1. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the

"Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s Guide.

2. Direct ADC mode using an external VAREF of 2.56V±4.6mV, without Analog Calibration macro.

3. For input greater than 2.56 V, the ADC output will saturate. A higher VAREF or prescaler usage is recommended.

Examples

Calculating Accuracy for an Uncalibrated Analog Channel

Formula

For a given prescaler range, EQ 30 gives the output voltage.

Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain)

EQ 30

where

Channel Output offset in V = Channel Input offset in LSBs x Equivalent voltage per LSB

Channel Gain Factor = 1+ (% Channel Gain / 100)

Example

Input Voltage = 5 V

Chosen Prescaler range = 8 V range

Refer to Table 2-51 on page 2-125.

Max. Output Voltage = (Max Positive input offset) + (Input Voltage x Max Positive Channel Gain)

Max. Positive input offset = (21 LSB) x (8 mV per LSB in 10-bit mode)

Max. Positive input offset = 166 mV

Max. Positive Gain Error = +3%

Max. Positive Channel Gain = 1 + (+3% / 100)

Max. Positive Channel Gain = 1.03

Max. Output Voltage = (166 mV) + (5 V x 1.03)

Max. Output Voltage = 5.316 V

Revision 4

2-127

Device Architecture

Similarly,

Min. Output Voltage = (Max. Negative input offset) + (Input Voltage x Max. Negative Channel Gain)

= (–88 mV) + (5 V x 0.96) = 4.712 V

Calculating Accuracy for a Calibrated Analog Channel

Formula

For a given prescaler range, EQ 31 gives the output voltage.

Output Voltage = Channel Error in V + Input Voltage

EQ 31

where

Channel Error in V = Total Channel Error in LSBs x Equivalent voltage per LSB

Example

Input Voltage = 5 V

Chosen Prescaler range = 8 V range

Refer to Table 2-52 on page 2-126.

Max. Output Voltage = Max. Positive Channel Error in V + Input Voltage

Max. Positive Channel Error in V = (6 LSB) × (8 mV per LSB in 10-bit mode) = 48 mV

Max. Output Voltage = 48 mV + 5 V = 5.048 V

Similarly,

Min. Output Voltage = Max. Negative Channel Error in V + Input Voltage = (–48 mV) + 5 V = 4.952 V

Calculating LSBs from a Given Error Budget

Formula

For a given prescaler range,

LSB count = ± (Input Voltage × Required % error) / (Equivalent voltage per LSB)

Example

Input Voltage = 3.3 V

Required error margin= 1%

Refer to Table 2-52 on page 2-126.

Equivalent voltage per LSB = 16 mV for a 16V prescaler, with ADC in 10-bit mode

LSB Count = ± (5.0 V × 1%) / (0.016)

LSB Count = ± 3.125

Equivalent voltage per LSB = 8 mV for an 8 V prescaler, with ADC in 10-bit mode

LSB Count = ± (5.0 V × 1%) / (0.008)

LSB Count = ± 6.25

The 8 V prescaler satisfies the calculated LSB count accuracy requirement (see Table 2-52 on

page 2-126).

2-128

Revision 4

Fusion Family of Mixed Signal FPGAs

Analog Configuration MUX

The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter.

Microsemi Libero SoC will generate IP that will load and configure the Analog Block via the ACM.

However, users are not limited to using the Libero SoC IP. This section provides a detailed description of

the ACM's register map, truth tables for proper configuration of the Analog Block and RTC, as well as

timing waveforms so users can access and control the ACM directly from their designs.

The Analog Block contains four 8-bit latches per Analog Quad that are initialized through the ACM.

These latches act as configuration bits for Analog Quads. The ACM block runs from the core voltage

supply (1.5 V).

Access to the ACM is achieved via 8-bit address and data busses with enables. The pin list is provided in

Table 2-36 on page 2-81. The ACM clock speed is limited to a maximum of 10 MHz, more than sufficient

to handle the low-bandwidth requirements of configuring the Analog Block and the RTC (sub-block of the

Analog Block).

Table 2-54 decodes the ACM address space and maps it to the corresponding Analog Quad and

configuration byte for that quad.

Table 2-54 • ACM Address Decode Table for Analog Quad

ACMADDR [7:0] in

Decimal

Associated

Peripheral

Name

–

Description

–

0

1

2

3

4

5

Analog Quad

AQ0

AQ1

Byte 0

Byte 1

Byte 2

Byte 3

Byte 0

.

36

37

38

39

40

41

AQ8

AQ9

Byte 3

Byte 0

Analog Quad

Byte 1

Byte 2

Byte 3

Undefined

.

63

64

65

66

67

68

72

73

Undefined

RTC

COUNTER0

COUNTER1

COUNTER2

COUNTER3

COUNTER4

MATCHREG0

MATCHREG1

Counter bits 7:0

Counter bits 15:8

Counter bits 23:16

Counter bits 31:24

Counter bits 39:32

Match register bits 7:0

Match register bits 15:8

Revision 4

2-129

Device Architecture

Table 2-54 • ACM Address Decode Table for Analog Quad (continued)

ACMADDR [7:0] in

Decimal

Associated

Peripheral

Name

Description

74

75

76

80

81

82

83

84

88

MATCHREG2

MATCHREG3

MATCHREG4

MATCHBITS0

MATCHBITS1

MATCHBITS2

MATCHBITS3

MATCHBITS4

CTRL_STAT

Match register bits 23:16

Match register bits 31:24

Match register bits 39:32

Individual match bits 7:0

Individual match bits 15:8

Individual match bits 23:16

Individual match bits 31:24

Individual match bits 39:32

RTC

Control (write) / Status (read) register

bits 7:0

Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC.

1

ACM Characteristics

ACMCLK

t_SUEACM

t_HEACM

ACMWEN

ACMWDATA

t_SUDACM

t_HDACM

D0

D1

A1

t_SUAACM

t_HAACM

ACMADDRESS

A0

Figure 2-97 • ACM Write Waveform

t_MPWCLKACM

ACMCLK

ACMADDRESS

ACMRDATA

A0

A1

t_CLKQACM

RD0

RD1

Figure 2-98 • ACM Read Waveform

1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and

aq_wen signals have no impact.

2-130

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-55 • Analog Configuration Multiplexer (ACM) Timing

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_CLKQACM

t_SUDACM

t_HDACM

Description

Clock-to-Q of the ACM

–2

–1

Std.

26.42

5.88

0.00

6.33

0.00

5.27

0.00

10.00

Units

ns

19.73

4.39

0.00

4.73

0.00

3.93

0.00

22.48

5.00

0.00

5.38

0.00

4.48

0.00

10.00

Data Setup time for the ACM

Data Hold time for the ACM

Address Setup time for the ACM

Address Hold time for the ACM

Enable Setup time for the ACM

Enable Hold time for the ACM

ns

t_SUAACM

t_HAACM

t_SUEACM

t_HEACM

ns

t_MPWARACM

Asynchronous Reset Minimum Pulse Width for the 10.00

ACM

ns

t_REMARACM

t_RECARACM

t_MPWCLKACM

t_FMAXCLKACM

Asynchronous Reset Removal time for the ACM

Asynchronous Reset Recovery time for the ACM

Clock Minimum Pulse Width for the ACM

lock Maximum Frequency for the ACM

12.98

45.00

10.00

14.79

45.00

10.00

17.38

45.00

10.00

ns

MHz

Revision 4

2-131

Device Architecture

Analog Quad ACM Description

Table 2-56 maps out the ACM space associated with configuration of the Analog Quads within the

Analog Block. Table 2-56 shows the byte assignment within each quad and the function of each bit within

each byte. Subsequent tables will explain each bit setting and how it corresponds to a particular

configuration. After 3.3 V and 1.5 V are applied to Fusion, Analog Quad configuration registers are

loaded with default settings until the initialization and configuration state machine changes them to user-

defined settings.

Table 2-56 • Analog Quad ACM Byte Assignment

Byte

Bit

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Signal (Bx)

B0[0]

B0[1]

B0[2]

B0[3]

B0[4]

B0[5]

B0[6]

B0[7]

B1[0]

B1[1]

B1[2]

B1[3]

B1[4]

B1[5]

B1[6]

B1[7]

B2[0]

B2[1]

B2[2]

B2[3]

B2[4]

B2[5]

B2[6]

B2[7]

B3[0]

B3[1]

B3[2]

B3[3]

B3[4]

B3[5]

B3[6]

B3[7]

Function

Default Setting

Byte 0

(AV)

Scaling factor control – prescaler

Highest voltage range

Analog MUX select

Prescaler

Current monitor switch

Direct analog input switch

Selects V-pad polarity

Off

Positive

Prescaler op amp mode

Scaling factor control – prescaler

Power-down

Highest voltage range

Byte 1

(AC)

Analog MUX select

Prescaler

Direct analog input switch

Selects C-pad polarity

Prescaler op amp mode

Off

Positive

Power-down

Byte 2

(AG)

Internal chip temperature monitor * Off

Spare

–

Current drive control

Lowest current

Spare

–

Spare

–

Selects G-pad polarity

Selects low/high drive

Scaling factor control – prescaler

Positive

Low drive

Byte 3

(AT)

Highest voltage range

Analog MUX select

Prescaler

Direct analog input switch

Off

–

Prescaler op amp mode

Power-down

Note: *For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set.

2-132

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-57 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note

that the AT pin has a reduced number of available prescaler values.

Table 2-57 • Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

LSB for an

8-Bit

LSB for a

10-Bit

LSB for a

12-Bit

Full-Scale

Voltage in

10-Bit

Scaling

Control Lines Factor, Pad to

Conversion¹

(mV)

Conversion¹

(mV)

Conversion¹

(mV)

Bx[2:0]

000 ³

001

ADC Input

0.15625

0.3125

0.625

1.25

Mode²

Range Name

16 V

64

32

16

8

16

8

4

2

16.368 V

8.184 V

8 V

010 ³

4

1

4.092 V

4 V

011

2

0.5

2.046 V

2 V

100

2.5

4

1

0.25

0.125

0.0625

0.03125

1.023 V

1 V

101

5.0

2

0.5

0.25

0.125

0.5115 V

0.25575 V

0.127875 V

0.5 V

0.25 V

0.125 V

110

10.0

1

111

20.0

0.5

Notes:

1. LSB voltage equivalences assume VAREF = 2.56 V.

2. Full Scale voltage for n-bit mode: ((2^n) - 1) x (LSB for a n-bit Conversion)

3. These are the only valid ranges for the Temperature Monitor Block Prescaler.

Table 2-58 details the settings available to control the MUX within each of the AV, AC, and AT circuits.

This MUX determines whether the signal routed to the ADC is the direct analog input, prescaled signal,

or output of either the Current Monitor Block or the Temperature Monitor Block.

Table 2-58 • Analog Multiplexer Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[4]

Control Lines Bx[3]

ADC Connected To

0

1

0

1

0

1

Prescaler

Direct input

Current amplifier temperature monitor

Not valid

Table 2-59 details the settings available to control the Direct Analog Input switch for the AV, AC, and AT

pins.

Table 2-59 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[5]

Direct Input Switch

0

1

Off

On

Table 2-60 details the settings available to control the polarity of the signals coming to the AV, AC, and AT

pins. Note that the only valid setting for the AT pin is logic 0 to support positive voltages.

Table 2-60 • Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)*

Control Lines Bx[6]

Input Signal Polarity

Positive

0

1

Negative

Note: *The B3[6] signal for the AT pad should be kept at logic 0 to accept only positive voltages.

Revision 4

2-133

Device Architecture

Table 2-61 details the settings available to either power down or enable the prescaler associated with the

analog inputs AV, AC, and AT.

Table 2-61 • Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)

Control Lines Bx[7]

Prescaler Op Amp

Power-down

0

1

Operational

Table 2-62 details the settings available to enable the Current Monitor Block associated with the AC pin.

Table 2-62 • Current Monitor Input Switch Control Truth Table—AV (x = 0)

Control Lines B0[4]

Current Monitor Input Switch

0

1

Off

On

Table 2-63 details the settings available to configure the drive strength of the gate drive when not in high-

drive mode.

Table 2-63 • Low-Drive Gate Driver Current Truth Table (AG)

Control Lines B2[3]

Control Lines B2[2]

Current (µA)

0

1

0

1

0

1

3

10

30

Table 2-64 details the settings available to set the polarity of the gate driver (either p-channel- or

n-channel-type devices).

Table 2-64 • Gate Driver Polarity Truth Table (AG)

Control Lines B2[6]

Gate Driver Polarity

Positive

0

1

Negative

Table 2-65 details the settings available to turn on the Gate Driver and set whether high-drive mode is on

or off.

Table 2-65 • Gate Driver Control Truth Table (AG)

Control Lines B2[7]

GDON

Gate Driver

Off

0

1

0

1

0

1

Low drive on

Off

High drive on

Table 2-66 details the settings available to turn on and off the chip internal temperature monitor.

Note: For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set.

Table 2-66 • Internal Temperature Monitor Control Truth Table

Control Lines B2[0]

PDTMB

Chip Internal Temperature Monitor

0

1

0

1

Off

On

2-134

Revision 4

Fusion Family of Mixed Signal FPGAs

User I/Os

Introduction

Fusion devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,

and 3.3 V) through a bank-selectable voltage. Table 2-68, Table 2-69, Table 2-70, and Table 2-71 on

page 2-138 show the voltages and the compatible I/O standards. I/Os provide programmable slew rates,

drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V–tolerant.

See the "5 V Input Tolerance" section on page 2-147 for possible implementations of 5 V tolerance.

All I/Os are in a known state during power-up, and any power-up sequence is allowed without current

impact. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial

and Industrial)" section on page 3-5 for more information. In low power standby or sleep mode (VCC is

OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, digital inputs are tristated, digital

outputs are tristated, and digital bibufs (input/output) are tristated.

I/O Tile

The Fusion I/O tile provides a flexible, programmable structure for implementing a large number of I/O

standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to support

high-performance register inputs and outputs, with register enable if desired (Figure 2-99 on

page 2-136). The registers can also be used to support the JESD-79C DDR standard within the I/O

structure (see the "Double Data Rate (DDR) Support" section on page 2-142 for more information).

As depicted in Figure 2-100 on page 2-141, all I/O registers share one CLR port. The output register and

output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-141 for more

information.

I/O Banks and I/O Standards Compatibility

The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090 and

AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. Figure 2-113 on

page 2-161 and Figure 2-114 on page 2-162 show the bank configuration by device. The north side of

the I/O in the AFS600 and AFS1500 devices comprises two banks of Pro I/Os. The Pro I/Os support a

wide number of voltage-referenced I/O standards in addition to the multitude of single-ended and

differential I/O standards common throughout all Microsemi digital I/Os. Each I/O voltage bank has

dedicated I/O supply and ground voltages (VCCI/GNDQ for input buffers and VCCI/GND for output

buffers). Because of these dedicated supplies, only I/Os with compatible standards can be assigned to

the same I/O voltage bank. Table 2-69 and Table 2-70 on page 2-137 show the required voltage

compatibility values for each of these voltages.

For more information about I/O and global assignments to I/O banks, refer to the specific pin table of the

device in the "Package Pin Assignments" on page 4-1 and the "User I/O Naming Convention" section on

page 2-161.

Each Pro I/O bank is divided into minibanks. Any user I/O in a VREF minibank (a minibank is the region

of scope of a VREF pin) can be configured as a VREF pin (Figure 2-99 on page 2-136). Only one VREF

pin is needed to control the entire VREF minibank. The location and scope of the VREF minibanks can

be determined by the I/O name. For details, see the "User I/O Naming Convention" section on

page 2-161.

Table 2-70 on page 2-137 shows the I/O standards supported by Fusion devices and the corresponding

voltage levels.

I/O standards are compatible if the following are true:

•

Their VCCI values are identical.

If both of the standards need a VREF, their VREF values must be identical (Pro I/O only).

Revision 4

2-135

Device Architecture

CCC

Bank 0

Bank 1

Up to five VREF

minibanks within

an I/O bank

Common VREF

signal for all I/Os

VREF signal scope is

between 8 and 18 I/Os.

in VREF minibanks

If needed, the VREF for a given

minibank can be provided by

any I/O within the minibank.

I/O Pad

Figure 2-99 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)

Table 2-67 • I/O Standards Supported by Bank Type

Differential I/O

Hot-

I/O Bank

Single-Ended I/O Standards

Standards

Voltage-Referenced

Swap

Standard I/O LVTTL/LVCMOS 3.3 V, LVCMOS –

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V

–

Yes

Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL

and –

–

2.5 V / 1.8 V / 1.5 V, LVCMOS

LVDS

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-

X

Pro I/O

LVTTL/LVCMOS 3.3 V, LVCMOS LVPECL

and GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, Yes

HSTL Class I and II, SSTL2 Class I

and II, SSTL3 Class I and II

2.5 V / 1.8 V / 1.5 V, LVCMOS

LVDS

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-

X

2-136

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-68 • I/O Bank Support by Device

I/O Bank

AFS090

AFS250

AFS600

AFS1500

Standard I/O

Advanced I/O

Pro I/O

N

E, W

–

N

E, W

–

E, W

N

–

E, W

N

Analog Quad

S

Note: E = East side of the device

W = West side of the device

N = North side of the device

S = South side of the device

Table 2-69 • Fusion VCCI Voltages and Compatible Standards

VCCI (typical)

3.3 V

Compatible Standards

LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II),* GTL+ 3.3, GTL 3.3,* LVPECL

2.5 V

LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II),* GTL+ 2.5,* GTL 2.5,* LVDS, BLVDS, M-

LVDS

1.8 V

1.5 V

LVCMOS 1.8

LVCMOS 1.5, HSTL (Class I),* HSTL (Class II)*

Note: *I/O standard supported by Pro I/O banks.

Table 2-70 • Fusion VREF Voltages and Compatible Standards*

VREF (typical)

1.5 V

Compatible Standards

SSTL3 (Class I and II)

SSTL2 (Class I and II)

GTL+ 2.5, GTL+ 3.3

1.25 V

1.0 V

0.8 V

GTL 2.5, GTL 3.3

0.75 V

HSTL (Class I), HSTL (Class II)

Note: *I/O standards supported by Pro I/O banks.

Revision 4

2-137

Device Architecture

Table 2-71 • Fusion Standard and Advanced I/O Features

3.3 V

2.5 V

–

0.80 V

1.00 V

1.50 V

–

0.80 V

1.00 V

1.25 V

–

1.8 V

1.5 V

–

0.75 V

Note: White box: Allowable I/O standard combinations

Gray box: Illegal I/O standard combinations

2-138

Revision 4

Fusion Family of Mixed Signal FPGAs

Features Supported on Pro I/Os

Table 2-72 lists all features supported by transmitter/receiver for single-ended and differential I/Os.

Table 2-72 • Fusion Pro I/O Features

Feature

Description

Single-ended

referenced transmitter

features

and

voltage- • Hot insertion in every mode except PCI or 5 V input tolerant (these modes use

clamp diodes and do not allow hot insertion)

•

Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.

Weak pull-up and pull-down

Two slew rates

Skew between output buffer enable/disable time: 2 ns delay (rising edge) and

0 ns delay (falling edge); see "Selectable Skew between Output Buffer

Enable/Disable Time" on page 2-152 for more information

•

Five drive strengths

5 V–tolerant receiver ("5 V Input Tolerance" section on page 2-147)

LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output

Tolerance" section on page 2-151)

•

High performance (Table 2-76 on page 2-146)

Schmitt trigger option

Single-ended receiver features

ESD protection

Programmable delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns

with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

High performance (Table 2-76 on page 2-146)

Separate ground planes, GND/GNDQ, for input buffers only to avoid output-

induced noise in the input circuitry

Voltage-referenced differential • Programmable Delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns

receiver features

with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

High performance (Table 2-76 on page 2-146)

Separate ground planes, GND/GNDQ, for input buffers only to avoid output-

induced noise in the input circuitry

CMOS-style LVDS, BLVDS, • Two I/Os and external resistors are used to provide a CMOS-style LVDS,

M-LVDS, or LVPECL

transmitter

BLVDS, M-LVDS, or LVPECL transmitter solution.

Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.

Weak pull-up and pull-down

•

Fast slew rate

LVDS/LVPECL differential

receiver features

ESD protection

High performance (Table 2-76 on page 2-146)

Programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111' setting,

0.85-ns intermediate delay increments (at 25°C, 1.5 V)

•

Separate input buffer ground and power planes to avoid output-induced noise

in the input circuitry

Revision 4

2-139

Device Architecture

Table 2-73 • Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os;

All I/O Bank Types (maximum drive strength and high slew selected)

Specification

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI

Performance Up To

200 MHz

250 MHz

200 MHz

130 MHz

200 MHz

300 MHz

350 MHz

300 MHz

PCI-X

HSTL-I

HSTL-II

SSTL2-I

SSTL2-II

SSTL3-I

SSTL3-II

GTL+ 3.3 V

GTL+ 2.5 V

GTL 3.3 V

GTL 2.5 V

LVDS

LVPECL

2-140

Revision 4

Fusion Family of Mixed Signal FPGAs

I/O Registers

Each I/O module contains several input, output, and enable registers. Refer to Figure 2-100 for a

simplified representation of the I/O block.

The number of input registers is selected by a set of switches (not shown in Figure 2-100) between

registers to implement single or differential data transmission to and from the FPGA core. The Designer

software sets these switches for the user.

A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input

register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O

register combining must satisfy some rules.

1

Input

Reg

I/O / Q0

2

Input

Reg

Y

Pull-Up/Down

Resistor Control

CLR/PRE

To FPGA Core

3

Input

I/O / Q1

PAD

Reg

ICE

CLR/PRE

I/O / ICLK

Signal Drive Strength

and Slew-Rate Control

E = Enable Pin

A

4

I/O / D0

Output

Reg

OCE

ICE

From FPGA Core

CLR/PRE

5

I/O / D1 / ICE

Output

Reg

CLR/PRE

I/O / OCLK

I/O / OE

6

Output

Enable

Reg

OCE

CLR/PRE

I/O / CLR or I/O / PRE / OCE

Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on

page 2-142 for more information).

Figure 2-100 • I/O Block Logical Representation

Revision 4

2-141

Device Architecture

Double Data Rate (DDR) Support

Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every

transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity

requirements, making it very efficient for implementing very high-speed systems.

DDR interfaces can be implemented using HSTL, SSTL, LVDS, and LVPECL I/O standards. In addition,

high-speed DDR interfaces can be implemented using LVDS I/O.

Input Support for DDR

The basic structure to support a DDR input is shown in Figure 2-101. Three input registers are used to

capture incoming data, which is presented to the core on each rising edge of the I/O register clock.

Each I/O tile on Fusion devices supports DDR inputs.

Output Support for DDR

The basic DDR output structure is shown in Figure 2-102 on page 2-143. New data is presented to the

output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The

combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the

edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account

in the DDR macro.

Refer to the application note Using DDR for Fusion Devices for more information.

Input DDR

A

D

Out_QF

(to core)

Data

INBUF

FF1

E

B

C

Out_QR

(to core)

CLK

CLR

CLKBUF

INBUF

FF2

DDR_IN

Figure 2-101 • DDR Input Register Support in Fusion Devices

2-142

Revision 4

Fusion Family of Mixed Signal FPGAs

A

Data_F

(from core)

FF1

Out

B

C

D

0

CLK

E

CLKBUF

OUTBUF

1

Data_R

(from core)

FF2

B

C

CLR

INBUF

DDR_OUT

Figure 2-102 • DDR Output Support in Fusion Devices

Revision 4

2-143

Device Architecture

Hot-Swap Support

Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or

from) a powered-up system. The levels of hot-swap support and examples of related applications are

described in Table 2-74. The I/Os also need to be configured in hot insertion mode if hot plugging

compliance is required.

Table 2-74 • Levels of Hot-Swap Support

Device

Example of

Hot

Power

Card

Circuitry

Application with

Swapping

Level

Applied

Ground

Connected Cards that Contain Compliance of

Fusion Devices

Description to Device Bus State Connection to Bus Pins Fusion Devices

1

Cold-swap

No

–

System and card with Compliant I/Os

Microsemi FPGA chip can but do not

are powered down,

then card gets

have to be set to

hot insertion

plugged into system, mode.

then power supplies

are turned on for

system but not for

FPGA on card.

2

Hot-swap

while reset

Yes

Held in

reset state and

maintained for

Must be made –

In PCI hot plug

specification, reset

control circuitry

isolates the card

busses until the card mode.

supplies are at their

nominal operating

Compliant I/Os

can but do not

have to be set to

hot insertion

1 ms before,

during, and

after insertion/

removal

levels and stable.

3

Hot-swap

while bus

idle

Held idle

(no ongoing Level 2

I/O

Same as

Mustremain Board bus shared

glitch-free with card bus is

during

Compliant with

cards with two

"frozen," and there is levels of staging.

processes

during

insertion/re

moval)

power-up or no toggling activity on I/Os have to be

power-down bus. It is critical that set to hot

the logic states set on insertion mode.

the bus signal do not

get disturbed during

card

insertion/removal.

4

Hot-swapon

an active

bus

Yes

Bus may

have active Level 2

I/O

processes

ongoing,

but device

being

Same as

Level 3

There is activity on

Compliant with

the system bus, and it cards with two

is critical that the logic levels of staging.

states set on the bus I/Os have to be

signal do not get

disturbed during card insertion mode.

insertion/removal.

set to hot

inserted or

removed

must be

idle.

2-144

Revision 4

Fusion Family of Mixed Signal FPGAs

For Fusion devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to Fusion

I/Os need to have 10 k (or lower) output drive resistance at hot insertion, and 1 k (or lower) output

drive resistance at hot removal. This is the resistance of the transmitter sending a signal to the Fusion

I/O, and no additional resistance is needed on the board. If that cannot be assured, three levels of

staging can be used to meet Level 3 and/or Level 4 compliance. Cards with two levels of staging should

have the following sequence:

1. Grounds

2. Powers, I/Os, other pins

Cold-Sparing Support

Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically

connected to the system that is in operation. This means that all input buffers of the subsystem must

present very high input impedance with no power applied so as not to disturb the operating portion of the

system.

Pro I/O banks and standard I/O banks fully support cold-sparing.

For Pro I/O banks, standards such as PCI that require I/O clamp diodes, can also achieve cold-sparing

compliance, since clamp diodes get disconnected internally when the supplies are at 0 V.

For Advanced I/O banks, since the I/O clamp diode is always active, cold-sparing can be accomplished

either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each

advanced I/O pin to 0 V.

If Standard I/O banks are used in applications requiring cold-sparing, a discharge path from the power

supply to ground should be provided. This can be done with a discharge resistor or a switched resistor.

This is necessary because the standard I/O buffers do not have built-in I/O clamp diodes.

If a resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given

power supply on the board (this decoupling capacitor is in parallel with the resistor). The RC time

constant should ensure full discharge of supplies before cold-sparing functionality is required. The

resistor is necessary to ensure that the power pins are discharged to ground every time there is an

interruption of power to the device.

I/O cold-sparing may add additional current if the pin is configured with either a pull-up or pull down

resistor and driven in the opposite direction. A small static current is induced on each IO pin when the pin

is driven to a voltage opposite to the weak pull resistor. The current is equal to the voltage drop across

the input pin divided by the pull resistor. Please refer to Table 2-95 on page 2-172, Table 2-96 on

page 2-172, and Table 2-97 on page 2-174 for the specific pull resistor value for the corresponding I/O

standard.

For example, assuming an LVTTL 3.3 V input pin is configured with a weak Pull-up resistor, a current will

flow through the pull-up resistor if the input pin is driven low. For an LVTTL 3.3 V, pull-up resistor is ~45

k and the resulting current is equal to 3.3 V / 45 k = 73 µA for the I/O pin. This is true also when a

weak pull-down is chosen and the input pin is driven high. Avoiding this current can be done by driving

the input low when a weak pull-down resistor is used, and driving it high when a weak pull-up resistor is

used.

In Active and Static modes, this current draw can occur in the following cases:

•

Input buffers with pull-up, driven low

Input buffers with pull-down, driven high

Bidirectional buffers with pull-up, driven low

Bidirectional buffers with pull-down, driven high

Output buffers with pull-up, driven low

Output buffers with pull-down, driven high

Tristate buffers with pull-up, driven low

Tristate buffers with pull-down, driven high

Revision 4

2-145

Device Architecture

Electrostatic Discharge (ESD) Protection

Fusion devices are tested per JEDEC Standard JESD22-A114-B.

Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all

device pads against damage from ESD as well as from excessive voltage transients.

Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative

(N) side connected to VCCI. The second diode has its P side connected to GND and its N side

connected to the pad. During operation, these diodes are normally biased in the Off state, except when

transient voltage is significantly above VCCI or below GND levels.

By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-75 and

Table 2-76 on page 2-146 for more information about I/O standards and the clamp diode.

The second diode is always connected to the pad, regardless of the I/O configuration selected.

Table 2-75 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities

Clamp Diode

Hot Insertion

5 V Input Tolerance ¹

Standard Advanced Standard Advanced Standard Advanced

Input

Buffer

Output

Buffer

I/O Assignment

I/O

No

I/O

Yes

I/O

Yes

N/A

Yes

N/A

Yes

N/A

I/O

No

I/O

Yes¹

N/A

No

I/O

Yes¹

No

3.3 V LVTTL/LVCMOS

3.3 V PCI, 3.3 V PCI-X

LVCMOS 2.5 V

Enabled/Disabled

N/A

No

LVCMOS 2.5 V / 5.0 V

LVCMOS 1.8 V

N/A

No

N/A

No

Yes²

No

LVCMOS 1.5 V

No

Differential,

N/A

No

LVDS/BLVDS/M-

LVDS/ LVPECL ³

Notes:

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. Can be implemented with an external resistor and an internal clamp diode.

3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.

Table 2-76 • Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities

Clamp

Diode

Hot

5 V Input

I/O Assignment

Insertion Tolerance Input Buffer Output Buffer

3.3 V LVTTL/LVCMOS

3.3 V PCI, 3.3 V PCI-X

LVCMOS 2.5 V ³

No

Yes

No

Yes

No

Yes

No

Yes¹

No

Enabled/Disabled

Yes

No

LVCMOS 2.5 V / 5.0 V ³

Yes²

LVCMOS 1.8 V

Yes

No

LVCMOS 1.5 V

No

Voltage-Referenced Input Buffer

Differential, LVDS/BLVDS/M-LVDS/LVPECL⁴

Notes:

No

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. Can be implemented with an external resistor and an internal clamp diode.

3. In the SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide, select the

LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O

standard.

4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers.

2-146

Revision 4

Fusion Family of Mixed Signal FPGAs

5 V Input Tolerance

I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and

LVCMOS 2.5 V configurations are used (see Table 2-77 on page 2-150 for more details). There are four

recommended solutions (see Figure 2-103 to Figure 2-106 on page 2-149 for details of board and macro

setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the

voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any

voltage above 3.6 V may cause long-term gate oxide failures.

Solution 1

The board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits

provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not be

used for clamping, and the voltage must be limited by the two external resistors, as explained below.

Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

The following are some examples of possible resistor values (based on a simplified simulation model

with no line effects and 10  transmitter output resistance, where Rtx_out_high = (VCCI – VOH) / IOH,

Rtx_out_low = VOL / IOL).

Example 1 (high speed, high current):

Rtx_out_high = Rtx_out_low = 10 

R1 = 36  (±5%), P(r1)min = 0.069 

R2 = 82  (±5%), P(r2)min = 0.158 

Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 mA

t

_RISE= t_FALL= 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin)

_RISE= t_FALL= 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin)

Example 2 (low–medium speed, medium current):

Rtx_out_high = Rtx_out_low = 10 

R1 = 220  (±5%), P(r1)min = 0.018 

R2 = 390  (±5%), P(r2)min = 0.032 

Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 mA

t

_RISE= t_FALL= 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin)

t_RISE= t_FALL= 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin)

Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the

voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of

Vin_dc(rx) must be assured for any combination of transmitter supply (5 V ± 0.5 V), transmitter output

resistance, and board resistor tolerances.

Revision 4

2-147

Device Architecture

Temporary overshoots are allowed according to Table 3-4 on page 3-4.

Solution 1

Fusion I/O Input

On-Chip

Off-Chip

5.5 V

3.3 V

Rext1

Rext2

Requires two board resistors,

LVCMOS 3.3 V I/Os

Figure 2-103 • Solution 1

Solution 2

The board-level design must ensure that the reflected waveform at the pad does not exceed limits

provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used

for clamping, and the voltage must be limited by the external resistors and Zener, as shown in Figure 2-

104. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Solution 2

Fusion I/O Input

Off-Chip On-Chip

3.3 V

5.5 V

Rext1

Zener

3.3 V

Requires one board resistor, one

Zener 3.3 V diode, LVCMOS 3.3 V I/Os

Figure 2-104 • Solution 2

2-148

Revision 4

Fusion Family of Mixed Signal FPGAs

Solution 3

The board-level design must ensure that the reflected waveform at the pad does not exceed limits

provided in Table 3-4 on page 3-4. This is a long-term reliability requirement.

This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used

for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-105. Relying on the

diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Solution 3

Fusion I/O Input

Off-Chip

Bus

On-Chip

3.3 V

Switch

IDTQS32X23

5.5 V

Requires a bus switch on the board,

LVTTL/LVCMOS 3.3 V I/Os.

Figure 2-105 • Solution 3

Solution 4

Fusion I/O Input

Off-Chip

5.5 V

On-Chip

2.5 V On-Chip

2.5 V

Clamp

Diode

Rext1

Requires one board resistor.

Available for LVCMOS 2.5 V / 5.0 V.

Figure 2-106 • Solution 4

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2-149

Device Architecture

Table 2-77 • Comparison Table for 5 V–Compliant Receiver Scheme

Schem

e

1

2

3

4

Board Components

Two resistors

Speed

Current Limitations

Low to high¹Limited by transmitter's drive strength

Resistor and Zener 3.3 V

Bus switch

Medium

High

Limited by transmitter's drive strength

N/A

Minimum resistor value²

R = 47  at T_J= 70°C

R = 150  at T_J= 85°C

R = 420  at T_J= 100°C

Medium

Maximum diode current at 100% duty cycle, signal constantly

at '1'

52.7 mA at T_J=70°C / 10-year lifetime

16.5 mA at T_J= 85°C / 10-year lifetime

5.9 mA at T_J= 100°C / 10-year lifetime

For duty cycles other than 100%, the currents can be

increased by a factor = 1 / (duty cycle).

Example: 20% duty cycle at 70°C

Maximum current = (1 / 0.2) * 52.7 mA = 5 * 52.7 mA = 263.5

mA

Notes:

1. Speed and current consumption increase as the board resistance values decrease.

2. Resistor values ensure I/O diode long-term reliability.

2-150

Revision 4

Fusion Family of Mixed Signal FPGAs

5 V Output Tolerance

Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is

also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad

voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O.

When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, Fusion I/Os can directly drive signals into 5 V TTL

receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed

the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0'

will be recognized correctly by 5 V TTL receivers.

Simultaneously Switching Outputs and PCB Layout

•

Simultaneously switching outputs (SSOs) can produce signal integrity problems on adjacent

signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bond

wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals

adjacent to those busses. Additionally, SSOs can produce ground bounce noise and VCCI dip

noise. These two noise types are caused by rapidly changing currents through GND and VCCI

package pin inductances during switching activities:

•

Ground bounce noise voltage = L(GND) * di/dt

VCCI dip noise voltage = L(VCCI) * di/dt

Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The

shielding should be done both on the board and inside the package unless otherwise described.

In-package shielding can be achieved in several ways; the required shielding will vary depending on

whether pins next to SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or

GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to

be adequately shielded from mutual coupling and inductive noise that can be generated by the SSO bus.

Also, noise generated by the SSO bus needs to be reduced inside the package.

PCBs perform an important function in feeding stable supply voltages to the IC and, at the same time,

maintaining signal integrity between devices.

Key issues that need to considered are as follows:

•

Power and ground plane design and decoupling network design

Transmission line reflections and terminations

Revision 4

2-151

Device Architecture

Selectable Skew between Output Buffer Enable/Disable Time

The configurable skew block is used to delay the output buffer assertion (enable) without affecting

deassertion (disable) time.

Output Enable

ENABLE (IN)

(from FPGA core)

ENABLE (OUT)

MUX

Skew Circuit

I/O Output

Buffers

Skew Select

Figure 2-107 • Block Diagram of Output Enable Path

ENABLE (IN)

ENABLE (OUT)

Less than

0.1 ns

Less than

0.1 ns

Figure 2-108 • Timing Diagram (option1: bypasses skew circuit)

ENABLE (IN)

ENABLE (OUT)

1.2 ns

(typical)

Less than

0.1 ns

Figure 2-109 • Timing Diagram (option 2: enables skew circuit)

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Revision 4

Fusion Family of Mixed Signal FPGAs

At the system level, the skew circuit can be used in applications where transmission activities on

bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that

can prevent bus contention and subsequent data loss or transmitter overstress due to transmitter-to-

transmitter current shorts. Figure 2-110 presents an example of the skew circuit implementation in a

bidirectional communication system. Figure 2-111 shows how bus contention is created, and Figure 2-

112 on page 2-154 shows how it can be avoided with the skew circuit.

Transmitter

ENABLE/

DISABLE

Transmitter 1: Fusion I/O

Transmitter 2: Generic I/O

Routing

Skew or

Routing

EN(b1)

EN(b2)

EN(r1)

ENABLE(t2)

Bypass

Skew

Delay (t1)

Delay (t2)

ENABLE(t1)

Bidirectional Data Bus

Figure 2-110 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using

Fusion Devices

EN (b1)

EN (b2)

ENABLE (r1)

ENABLE (t1)

Transmitter 1: OFF

ENABLE (t2)

Transmitter 1: OFF

Transmitter 1: ON

Transmitter 2: ON

Transmitter 2: OFF

Bus

Contention

Figure 2-111 • Timing Diagram (bypasses skew circuit)

Revision 4

2-153

Device Architecture

EN (b1)

EN (b2)

ENABLE (t1)

Transmitter 1: OFF

ENABLE (t2)

Transmitter 1: OFF

Transmitter 1: ON

Transmitter 2: ON

Transmitter 2: OFF

Result: No Bus Contention

Figure 2-112 • Timing Diagram (with skew circuit selected)

Weak Pull-Up and Weak Pull-Down Resistors

Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the I/O is

pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is

connected to GND. Refer to Table 2-97 on page 2-174 for more information.

Slew Rate Control and Drive Strength

Fusion devices support output slew rate control: high and low. The high slew rate option is recommended

to minimize the propagation delay. This high-speed option may introduce noise into the system if

appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of

noise but adds some delays in the system. Low slew rate is recommended when bus transients are

expected. Drive strength should also be selected according to the design requirements and noise

immunity of the system.

The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V,

LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O

standards have a high output slew rate by default.

For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:

•

Fusion Standard I/O (Table 2-78 on page 2-155)

Fusion Advanced I/O (Table 2-79 on page 2-155)

Fusion Pro I/O (Table 2-80 on page 2-155)

Table 2-83 on page 2-158 lists the default values for the above selectable I/O attributes as well as those

that are preset for each I/O standard.

2-154

Revision 4

Fusion Family of Mixed Signal FPGAs

Refer to Table 2-78, Table 2-79, and Table 2-80 on page 2-155 for SLEW and OUT_DRIVE settings.

Table 2-81 on page 2-156 and Table 2-82 on page 2-157 list the I/O default attributes. Table 2-83 on

page 2-158 lists the voltages for the supported I/O standards.

Table 2-78 • Fusion Standard I/O Standards—OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

3

4

3

–

6

3

–

8

3

–

Slew

LVTTL/LVCMOS 3.3 V

High

Low

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

Table 2-79 • Fusion Advanced I/O Standards—SLEW and OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

3

4

3

6

3

–

8

3

–

12

3

16

3

Slew

High

LVTTL/LVCMOS 3.3 V

Low

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

–

High

Low

3

–

Table 2-80 • Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings

OUT_DRIVE (mA)

I/O Standards

2

3

4

3

6

3

8

3

12

3

16

3

24

3

Slew

High

LVTTL/LVCMOS 3.3 V

Low

LVCMOS 2.5 V

High

3

LVCMOS 2.5 V/5.0 V

LVCMOS 1.8 V

3

–

3

LVCMOS 1.5 V

–

3

Revision 4

2-155

Device Architecture

Table 2-81 • Fusion Pro I/O Default Attributes

SLEW

(output only)

OUT_DRIVE

(output only)

I/O Standards

LVTTL/LVCMO Refer to the following

Refer to the following

tables for more

information:

Off None 35 pF

–

Off

0

Off

S 3.3 V

tables for more

information:

LVCMOS 2.5 V

Off None 35 pF

–

Off

0

Off

Table 2-78 on page 2-155 Table 2-78 on page 2-155

Table 2-79 on page 2-155 Table 2-79 on page 2-155

Table 2-80 on page 2-155 Table 2-80 on page 2-155

LVCMOS

2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

Off None 35 pF

Off None 10 pF

Off None 20 pF

Off None 30 pF

–

Off

0

Off

PCI-X (3.3 V)

GTL+ (3.3 V)

GTL+ (2.5 V)

GTL (3.3 V)

GTL (2.5 V)

HSTL Class I

HSTL Class II

SSTL2

Class I and II

SSTL3

Class I and II

Off None 30 pF

–

Off

0

Off

LVDS, BLVDS,

M-LVDS

Off None

0 pF

LVPECL

2-156

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-82 • Advanced I/O Default Attributes

I/O Standards

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

SLEW (output only)

OUT_DRIVE (output only)

Refer to the following

tables for more

information:

Refer to the following tables Off None

for more information:

35 pF

10 pF

–

Off None

Table 2-78 on page 2-155

Off None

Table 2-78 on page 2-155

Table 2-79 on page 2-155

Table 2-80 on page 2-155

Table 2-79 on page 2-155

Off None

Table 2-80 on page 2-155

PCI-X (3.3 V)

LVDS, BLVDS, M-LVDS

LVPECL

–

Revision 4

2-157

Device Architecture

Table 2-83 • Fusion Pro I/O Supported Standards and Corresponding VREF and VTT Voltages

Input/Output Supply

Voltage (VCCI_TYP)

Input Reference Voltage

(VREF_TYP)

Board Termination Voltage

(VTT_TYP)

I/O Standard

LVTTL/LVCMOS 3.3 V

LVCMOS 2.5 V

3.30 V

2.50 V

–

LVCMOS 2.5 V / 5.0 V

Input

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI 3.3 V

1.80 V

1.50 V

3.30 V

2.50 V

3.30 V

2.50 V

1.50 V

3.30 V

2.50 V

3.30 V

–

PCI-X 3.3 V

–

GTL+ 3.3 V

1.00 V

0.80 V

0.75 V

1.50 V

1.25 V

–

1.50 V

1.20 V

0.75 V

1.50 V

1.25 V

–

GTL+ 2.5 V

GTL 3.3 V

GTL 2.5 V

HSTL Class I

HSTL Class II

SSTL3 Class I

SSTL3 Class II

SSTL2 Class I

SSTL2 Class II

LVDS, BLVDS, M-LVDS

LVPECL

–

2-158

Revision 4

Fusion Family of Mixed Signal FPGAs

I/O Software Support

In the Fusion development software, default settings have been defined for the various I/O standards

supported. Changes can be made to the default settings via the use of attributes; however, not all I/O

attributes are applicable for all I/O standards. Table 2-84 and Table 2-85 list the valid I/O attributes that

can be manipulated by the user for each I/O standard.

Single-ended I/O standards in Fusion support up to five different drive strengths.

Table 2-84 • Fusion Standard and Advanced I/O Attributes vs. I/O Standard Applications

SLEW

SKEW

(output OUT_DRIVE (all macros

OUT_LOAD

(output only) with OE)* RES_PULL (output only) COMBINE_REGISTER

I/O Standards

only)

LVTTL/LVCMOS 3.3 V

3

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

PCI-X (3.3 V)

3

LVDS, BLVDS, M-LVDS

LVPECL

Note: *This feature does not apply to the standard I/O banks, which are the north I/O banks of AFS090 and AFS250

devices

Revision 4

2-159

Device Architecture

Table 2-85 • Fusion Pro I/O Attributes vs. I/O Standard Applications

I/O Standards

LVTTL/LVCMOS 3.3 V

3

LVCMOS 2.5 V

LVCMOS 2.5/5.0 V

LVCMOS 1.8 V

LVCMOS 1.5 V

PCI (3.3 V)

PCI-X (3.3 V)

3

GTL+ (3.3 V)

3

GTL+ (2.5 V)

GTL (3.3 V)

GTL (2.5 V)

HSTL Class I

HSTL Class II

SSTL2 Class I and II

SSTL3 Class I and II

LVDS, BLVDS, M-LVDS

LVPECL

2-160

Revision 4

Fusion Family of Mixed Signal FPGAs

User I/O Naming Convention

Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to

show the details of the I/O (Figure 2-113 on page 2-161 and Figure 2-114 on page 2-162). The name

identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os.

I/O Nomenclature

= Gmn/IOuxwByVz

Gmn is only used for I/Os that also have CCC access—i.e., global pins.

G

m

= Global

= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C

(east middle), D (southeast corner), E (southwest corner), and F (west middle).

n

u

x

= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1,

or C2. Figure 2-22 on page 2-27 shows the three input pins per clock source MUX at CCC location m.

= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise

direction.

= P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support single-

ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict

the I/O differential pair from being selected as an LVPECL pair.

w

= D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded

out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are

bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.

For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal

adjacency does not meet the requirements for a true differential pair.

B

y

= Bank

= Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise

direction.

V

z

= Reference voltage

= Minibank number

Standard I/O Bank

CCC

"A"

CCC

"B"

Bank 0

Bank 3

Bank 1

AFS090

AFS250

CCC/PLL

"F"

CCC

"C"

Bank 3

Bank 1

CCC

"E"

CCC

"D"

Bank 2 (analog)

Analog Quads

Figure 2-113 • Naming Conventions of Fusion Devices with Three Digital I/O Banks

Revision 4

2-161

Device Architecture

Pro I/O Bank

CCC

"A"

CCC

"B"

Bank 0

Bank 1

Bank 4

Bank 2

AFS600

AFS1500

CCC/PLL

"F"

CCC/PLL

"C"

Bank 4

Bank 2

CCC

"E"

CCC

"D"

Bank 3 (analog)

Analog Quads

Figure 2-114 • Naming Conventions of Fusion Devices with Four I/O Banks

2-162

Revision 4

Fusion Family of Mixed Signal FPGAs

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

LVPECL (Pro IO banks)

t_PD= 0.56 ns

t_PD= 0.49 ns

t_Dp= 1.60 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

LVTTL/LVCMOS 3.3 V (Pro I/O banks)

Output drive strength = 12 mA

High slew rate

t_DP= 2.74 ns

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

LVTTL/LVCMOS 3.3 V (Pro I/O banks)

Output drive strength = 24 mA

_DP= 2.39 ns

High slew rate

t

t_PY= 1.22 ns

t_PD= 0.51 ns

LVPECL

(Pro IO Banks)

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

LVCMOS 1.5 V (Pro IO banks)

Output drive strength = 12 mA

High slew

t

_ICLKQ= 0.24 ns

t_DP= 3.30 ns

t_PD= 0.47 ns

t_ISUD= 0.26 ns

Input LVTTL/LVCMOS

3.3 V (Pro IO banks)

I/O Module

(Registered)

Register Cell

Combinational Cell

Y

t_PY= 0.90 ns

D

Q

D

Q

D

Q

I/O Module

(Non-Registered)

GTL+ 3.3 V

t_DP= 1.53 ns

t

_PD= 0.47 ns

t_CLKQ= 0.55 ns

_SUD= 0.43 ns

t

_CLKQ= 0.55 ns

_SUD= 0.43 ns

t

_OCLKQ= 0.59 ns

_OSUD= 0.31 ns

LVDS,

BLVDS,

M-LVDS (Pro IO Banks)

t

Input LVTTL/LVCMOS

3.3 V (Pro IO banks)

IInput LVTTL/LVCMOS

3.3 V (Pro IO banks)

t_PY= 1.36 ns

t_PY= 0.90 ns

Figure 2-115 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (T_J= 70°C),

Worst-Case VCC = 1.425 V

Revision 4

2-163

Device Architecture

t_PY

t_DIN

t_PYS

D

Q

PAD

DIN

Y

CLK

To Array

I/O interface

t_PY= MAX(t_PY(R), t_PY(F))

_PYs= MAX(t_PYS(R), t_PYS(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

t

VIH

V_trip

VIL

PAD

VCC

50%

t_PY

Y

GND

t_PY

(F)

(R)

t_PYS

(R)

t_PYS

(F)

VCC

50%

DIN

GND

t_DIN

(R)

t_DIN

(F)

Figure 2-116 • Input Buffer Timing Model and Delays (example)

2-164

Revision 4

Fusion Family of Mixed Signal FPGAs

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

VOH

DOUT

PAD

0 V

V_trip

VOL

t_DP

(F)

t_DP

(R)

Figure 2-117 • Output Buffer Model and Delays (example)

Revision 4

2-165

Device Architecture

t

EOUT

D Q

t

, t , t , t , t , t

CLK

ZL ZH HZ LZ ZLS ZHS

E

EOUT

D Q

CLK

PAD

(F))

DOUT

D

t

= MAX(t

(R). t

EOUT

EOUT EOUT

I/O Interface

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

VCCI

HZ

90% VCCI

V

trip

VOL

10% VCCI

VCC

D

VCC

50%

E

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

V

trip

VOL

Figure 2-118 • Tristate Output Buffer Timing Model and Delays (example)

2-166

Revision 4

Fusion Family of Mixed Signal FPGAs

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software Settings

Table 2-86 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Pro I/Os

VIL

Max.

VIH

VOL

VOH

IOL IOH

Drive

Strength Rate

Slew Min.

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard

V

mA mA

3.3 V LVTTL / 12 mA

3.3 V LVCMOS

High –0.3

0.8

2

3.6

0.4

2.4

12 12

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

High –0.3

0.7

1.7

3.6

0.7

1.7

12 12

High –0.3 0.35 * VCCI 0.65 * VCCI

0.45

VCCI – 0.45 12 12

0.25 * VCCI 0.75 * VCCI 12 12

Per PCI Specification

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Per PCI-X Specification

20 mA²High –0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

35 35

33 33

–

35 mA

33 mA

8 mA

High –0.3 VREF – 0.1 VREF + 0.1

0.6

0.4

–

VCCI – 0.4

8

HSTL (II)

15 mA²High –0.3 VREF – 0.1 VREF + 0.1

VCCI – 0.4 15 15

VCCI – 0.62 15 15

VCCI – 0.43 18 18

VCCI – 1.1 14 14

VCCI – 0.9 21 21

SSTL2 (I)

15 mA

18 mA

14 mA

21 mA

High –0.3 VREF – 0.2 VREF + 0.2

0.54

0.35

0.7

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

0.5

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output slew rate can be extracted by the IBIS models.

Table 2-87 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Advanced I/Os

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH

mA mA

Drive

Strength Rate

Slew Min.

Max.

V

Max.

V

Min.

V

I/O Standard

V

3.3 V LVTTL / 12 mA

3.3 V LVCMOS

High –0.3

0.8

2

3.6

0.4

2.4

12

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA High –0.3

0.7

1.7

2.7

0.7

1.7

12

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9

0.45

VCCI – 0.45 12

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12

Per PCI specifications

3.3 V PCI-X

Per PCI-X specifications

Note: Currents are measured at 85°C junction temperature.

Revision 4

2-167

Device Architecture

Table 2-88 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions

Applicable to Standard I/Os

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH

mA mA

Drive

Strength Rate

Slew Min.

Max.

V

Max.

V

Min.

V

I/O Standard

V

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

High –0.3

0.8

2

3.6

0.4

2.4

8

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

8 mA

4 mA

2 mA

High –0.3

0.7

1.7

3.6

0.7

1.7

8

4

2

8

4

2

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

Note: Currents are measured at 85°C junction temperature.

Table 2-89 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial

Conditions

Applicable to All I/O Bank Types

Commercial¹

Industrial²

IIL³

µA

10

IIH⁴

µA

10

IIL³

µA

15

IIH⁴

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Commercial range (0°C < T < 85°C)

J

2. Industrial range (–40°C < T < 100°C)

J

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

2-168

Revision 4

Fusion Family of Mixed Signal FPGAs

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-90 • Summary of AC Measuring Points

Applicable to All I/O Bank Types

Input Reference Voltage Board Termination Voltage

Measuring Trip Point

(Vtrip)

Standard

(VREF_TYP)

(VTT_REF)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

–

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X

–

0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Table 2-91 • I/O AC Parameter Definitions

Parameter

Definition

t_DP

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer with Schmitt trigger disabled

Data to Output Buffer delay through the I/O interface

t_DOUT

t_EOUT

t_DIN

t_PYS

t_HZ

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Pad to Data delay through the Input Buffer with Schmitt trigger enabled

Enable to Pad delay through the Output Buffer—High to Z

t_ZH

Enable to Pad delay through the Output Buffer—Z to High

t_LZ

Enable to Pad delay through the Output Buffer—Low to Z

t_ZL

Enable to Pad delay through the Output Buffer—Z to Low

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

Revision 4

2-169

Device Architecture

Table 2-92 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = I/O Standard Dependent

Applicable to Pro I/Os

I/O Standard

3.3 V LVTTL/

3.3 V LVCMOS

12 mA High 35

–

0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns

2.5 V LVCMOS 12 mA High 35

1.8 V LVCMOS 12 mA High 35

1.5 V LVCMOS 12 mA High 35

0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns

0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

–

3.3 V PCI

Per High 10 25 ²0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

PCI

spec

3.3 V PCI-X

Per High 10 25 ²0.49 2.09 0.03 0.77 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

PCI-X

spec

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA High 10 25 0.49 1.55 0.03 2.19

20 mA High 10 25 0.49 1.59 0.03 1.83

35 mA High 10 25 0.49 1.53 0.03 1.19

33 mA High 10 25 0.49 1.65 0.03 1.13

8 mA High 20 50 0.49 2.37 0.03 1.59

15 mA High 20 25 0.49 2.26 0.03 1.59

17 mA High 30 50 0.49 1.59 0.03 1.00

21 mA High 30 25 0.49 1.62 0.03 1.00

16 mA High 30 50 0.49 1.72 0.03 0.93

24 mA High 30 25 0.49 1.54 0.03 0.93

–

0.32 1.52 1.55 0.00 0.00 3.19 3.22 ns

0.32 1.61 1.59 0.00 0.00 3.28 3.26 ns

0.32 1.56 1.53 0.00 0.00 3.23 3.20 ns

0.32 1.68 1.57 0.00 0.00 3.35 3.24 ns

0.32 2.42 2.35 0.00 0.00 4.09 4.02 ns

0.32 2.30 2.03 0.00 0.00 3.97 3.70 ns

0.32 1.62 1.38 0.00 0.00 3.29 3.05 ns

0.32 1.65 1.32 0.00 0.00 3.32 2.99 ns

0.32 1.75 1.37 0.00 0.00 3.42 3.04 ns

0.32 1.57 1.25 0.00 0.00 3.24 2.92 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

24 mA High

–

0.49 1.57 0.03 1.36

0.49 1.60 0.03 1.22

–

ns

LVPECL

–

Notes:

1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-123 on page 2-200

for connectivity. This resistor is not required during normal operation.

2-170

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-93 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = I/O Standard Dependent

Applicable to Advanced I/Os

I/O Standard

3.3 V LVTTL/

12 mA High 35 pF

–

0.49 2.64 0.03 0.90 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns

3.3 V LVCMOS

2.5 V LVCMOS 12 mA High 35 pF

1.8 V LVCMOS 12 mA High 35 pF

1.5 V LVCMOS 12 mA High 35 pF

–

0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns

0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns

0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns

3.3 V PCI

Per PCI High 10 pF 25 ²0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

spec

3.3 V PCI-X

PerPCI-X High 10 pF 25 ²0.49 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

spec

LVDS

24 mA High

–

0.49 1.37 0.03 1.20 N/A N/A N/A N/A N/A N/A N/A ns

0.49 1.34 0.03 1.05 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

Notes:

1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-123 on page 2-200

for connectivity. This resistor is not required during normal operation.

Table 2-94 • Summary of I/O Timing Characteristics – Software Default Settings

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = I/O Standard Dependent

Applicable to Standard I/Os

I/O Standard

3.3 V LVTTL/

8 mA High

35 pF

–

0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01

ns

3.3 V LVCMOS

2.5 V LVCMOS 8 mA High

1.8 V LVCMOS 4 mA High

1.5 V LVCMOS 2 mA High

35pF

–

0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91

0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85

0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83

ns

Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values.

Revision 4

2-171

Device Architecture

Detailed I/O DC Characteristics

Table 2-95 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

VIN = 0, f = 1.0 MHz

8

C_INCLK

Input capacitance on the clock pin

pF

Table 2-96 • I/O Output Buffer Maximum Resistances ¹

R_PULL-DOWN

(ohms) ²

R_PULL-UP

Standard

Drive Strength

(ohms) ³

Applicable to Pro I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

8 mA

100

50

300

150

75

50

33

200

100

50

40

22

225

112

56

22

224

112

75

37

75

–

12 mA

25

16 mA

17

24 mA

11

2.5 V LVCMOS

1.8 V LVCMOS

4 mA

100

50

8 mA

12 mA

25

16 mA

20

24 mA

11

2 mA

200

100

50

4 mA

6 mA

8 mA

50

12 mA

20

16 mA

20

1.5 V LVCMOS

2 mA

200

100

67

4 mA

6 mA

8 mA

33

12 mA

33

3.3 V PCI/PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

Notes:

Per PCI/PCI-X specification

20 mA

25

11

20 mA

14

–

35 mA

12

–

33 mA

15

–

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2.

3.

R

= VOLspec / I

(PULL-DOWN-MAX) OLspec

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

2-172

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-96 • I/O Output Buffer Maximum Resistances ¹(continued)

R_PULL-DOWN

R_PULL-UP

(ohms) ³

Standard

Drive Strength

8 mA

(ohms) ²

HSTL (I)

50

25

27

13

44

18

50

25

31

15

69

32

HSTL (II)

15 mA

SSTL2 (I)

17 mA

SSTL2 (II)

21 mA

SSTL3 (I)

16 mA

SSTL3 (II)

24 mA

Applicable to Advanced I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

100

50

300

150

75

4 mA

6 mA

8 mA

50

12 mA

25

16 mA

17

50

24 mA

11

33

2.5 V LVCMOS

2 mA

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

25

16 mA

20

40

24 mA

11

22

1.8 V LVCMOS

2 mA

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

20

22

16 mA

20

22

1.5 V LVCMOS

2 mA

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

33

37

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

25

75

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2.

3.

R

= VOLspec / I

(PULL-DOWN-MAX) OLspec

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

Revision 4

2-173

Device Architecture

Table 2-96 • I/O Output Buffer Maximum Resistances ¹(continued)

R_PULL-DOWN

(ohms) ²

R_PULL-UP

(ohms) ³

Standard

Drive Strength

Applicable to Standard I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

100

50

300

150

200

100

225

112

224

50

2.5 V LVCMOS

1.8 V LVCMOS

100

50

200

100

200

1.5 V LVCMOS

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2.

R

= VOLspec / I

(PULL-DOWN-MAX) OLspec

3.

R

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

Table 2-97 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

(ohms)

R_{(WEAK PULL-DOWN)}

(ohms)

VCCI

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

Min.

10 k

11 k

18 k

19 k

Max.

45 k

55 k

70 k

90 k

Min.

10 k

12 k

17 k

19 k

Max.

45 k

74 k

110 k

140 k

1.

2.

R

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX) WEAK PULL-UP-MIN

= VOLspec / I

(WEAK PULL-DOWN-MAX)

WEAK PULL-DOWN-MIN

2-174

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-98 • I/O Short Currents IOSH/IOSL

Drive Strength

IOSH (mA)*

IOSL (mA)*

Applicable to Pro I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

8 mA

25

51

103

132

268

16

32

65

83

169

9

27

54

12 mA

16 mA

24 mA

4 mA

109

127

181

18

2.5 V LVCMOS

1.8 V LVCMOS

8 mA

37

12 mA

16 mA

24 mA

2 mA

74

87

124

11

4 mA

17

35

45

91

13

25

32

66

22

6 mA

44

8 mA

51

12 mA

16 mA

2 mA

74

1.5 V LVCMOS

16

4 mA

33

6 mA

39

8 mA

55

12 mA

55

Applicable to Advanced I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

2 mA

103

132

268

25

109

127

181

27

3.3 V LVCMOS

4 mA

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

103

132

268

109

127

181

Note: *T_J= 100°C

Revision 4

2-175

Device Architecture

Table 2-98 • I/O Short Currents IOSH/IOSL (continued)

Drive Strength

IOSH (mA)*

IOSL (mA)*

2.5 V LVCMOS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16

32

65

83

169

9

18

37

74

87

124

11

1.8 V LVCMOS

17

35

45

91

13

25

32

66

103

22

44

51

74

16

33

39

55

109

1.5 V LVCMOS

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Applicable to Standard I/O Banks

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

25

51

16

32

9

27

54

18

37

11

22

16

2.5 V LVCMOS

1.8 V LVCMOS

17

13

1.5 V LVCMOS

Note: *T_J= 100°C

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

2-176

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-99 • Short Current Event Duration before Failure

Temperature

–40°C

0°C

Time before Failure

>20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-100 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

Table 2-101 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement

10 ns*

20 years (100°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement

No requirement, but input

noise voltage cannot exceed

Schmitt hysteresis

20 years (100°C)

HSTL/SSTL/GTL

No requirement

10 ns*

10 years (100°C)

LVDS/BLVDS/M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is

low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.

Microsemi recommends signal integrity evaluation/characterization of the system to ensure there is no excessive

noise coupling into input signals.

Revision 4

2-177

Device Architecture

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is

supported as part of the 3.3 V LVTTL support.

Table 2-102 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH IIL¹IIH²

Max.

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Drive Strength

V

mA mA

mA³

µA⁴µA⁴

Applicable to Pro I/O Banks

4 mA

–0.3

0.8

2

3.6

0.4

2.4

4

8

4

8

27

54

25

51

10 10

8 mA

12 mA

16 mA

24 mA

12 12

16 16

24 24

109

127

181

103

132

268

Applicable to Advanced I/O Banks

2 mA

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

25

10 10

4 mA

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

12 12

16 16

24 24

109

127

181

103

132

268

Applicable to Standard I/O Banks

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

4

6

8

27

54

25

51

10 10

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-119 • AC Loading

Table 2-103 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

0

Input High (V)

3.3

Measuring Point* (V)

1.4

VREF (typ.) (V)

–

C_LOAD(pF)

35

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

2-178

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-104 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Pro I/Os

Spee

d

Drive

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

4 mA

Std.

–1

0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60

8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43

7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68

6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38

5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48

6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26

5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17

4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42

5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96

4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92

4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20

5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93

4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89

3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-179

Device Architecture

Table 2-105 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Pro I/Os

Drive

Speed

t_EOU

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

T

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94

6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60

5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67

5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38

4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43

3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76

3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11

3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34

2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81

3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84

2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12

2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62

3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39

2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74

2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28

ns

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-180

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-106 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 10.26 0.04

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

0.43 10.45 8.90

2.64

2.25

1.98

2.98

2.54

2.23

3.21

2.73

2.39

3.26

2.77

2.43

3.32

2.82

2.48

2.46 12.68 11.13

2.09 10.79 9.47

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.72

7.66

7.27

6.19

5.43

5.58

4.75

4.17

5.21

4.43

3.89

4.85

4.13

3.62

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.89

7.80

7.41

6.30

5.53

5.68

4.84

4.24

5.30

4.51

3.96

4.94

4.20

3.69

7.57

6.64

6.28

5.35

4.69

4.87

4.14

3.64

4.56

3.88

3.41

4.54

3.87

3.39

–2

1.83

3.04

2.59

2.27

3.42

2.91

2.55

3.51

2.99

2.62

3.88

3.30

2.90

9.47

9.65

8.20

7.20

7.92

6.74

5.91

7.54

6.41

5.63

7.18

6.10

5.36

8.31

8.52

7.25

6.36

7.11

6.05

5.31

6.80

5.79

5.08

6.78

5.77

5.06

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-181

Device Architecture

Table 2-107 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

7.66

6.51

5.72

4.91

4.17

3.66

3.53

3.00

2.64

3.33

2.83

2.49

3.08

2.62

2.30

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

1.20

1.02

0.90

7.80

6.63

5.82

5.00

4.25

3.73

3.60

3.06

2.69

3.39

2.89

2.53

3.13

2.66

2.34

6.59

5.60

4.92

4.07

3.46

3.04

2.82

2.40

2.11

2.56

2.18

1.91

2.12

1.80

1.58

2.65

2.25

1.98

2.99

2.54

2.23

3.21

2.73

2.40

3.26

2.77

2.44

3.32

2.83

2.48

2.61 10.03 8.82

ns

2.22

1.95

3.20

2.73

2.39

3.58

3.05

2.68

3.68

3.13

2.75

4.06

3.45

3.03

8.54

7.49

7.23

6.15

5.40

5.83

4.96

4.36

5.63

4.79

4.20

5.37

4.57

4.01

7.51

6.59

6.31

5.36

4.71

5.06

4.30

3.78

4.80

4.08

3.58

4.35

3.70

3.25

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-108 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Std.

–1

9.46

8.05

7.07

9.46

8.05

7.07

6.57

5.59

4.91

6.57

5.59

4.91

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

9.64

8.20

7.20

9.64

8.20

7.20

6.69

5.69

5.00

6.69

5.69

5.00

8.54

7.27

6.38

8.54

7.27

6.38

5.98

5.09

4.47

5.98

5.09

4.47

2.07

1.76

1.55

2.07

1.76

1.55

2.40

2.04

1.79

2.40

2.04

1.79

2.04

1.73

1.52

2.04

1.73

1.52

2.57

2.19

1.92

2.57

2.19

1.92

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-182

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-109 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

–2 ²

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

7.07

6.01

5.28

7.07

6.01

5.28

4.41

3.75

3.29

4.41

3.75

3.29

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

1.00

0.85

0.75

7.20

6.12

5.37

7.20

6.12

5.37

4.49

3.82

3.36

4.49

3.82

3.36

6.23

5.30

4.65

6.23

5.30

4.65

3.75

3.19

2.80

3.75

3.19

2.80

2.07

1.76

1.55

2.07

1.76

1.55

2.39

2.04

1.79

2.39

2.04

1.79

2.15

1.83

1.60

2.15

1.83

1.60

2.69

2.29

2.01

2.69

2.29

2.01

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-183

Device Architecture

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-110 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSL

Max.

mA mA

IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

mA³µA⁴µA⁴

Applicable to Pro I/O Banks

4 mA

–0.3

0.7

1.7

3.6

0.7

1.7

4

8

4

8

18

37

16

32

10 10

8 mA

12 mA

16 mA

24 mA

12 12

16 16

24 24

74

65

87

83

124

169

Applicable to Advanced I/O Banks

2 mA

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

18

16

10 10

4 mA

6 mA

37

32

8 mA

37

32

12 mA

16 mA

24 mA

12 12

16 16

24 24

74

65

87

83

124

169

Applicable to Standard I/O Banks

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

2

4

6

8

2

4

6

8

18

37

16

32

10 10

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t / t / t

R to GND for t / t / t

HZ ZH ZHS

Test Point

LZ ZL ZLS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t / t

/ t / t

ZH ZHS ZL ZLS

35 pF for t / t

HZ LZ

Figure 2-120 • AC Loading

Table 2-111 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

2.5

1.2

–

35

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

2-184

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-112 • 2.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

4 mA

Std.

–1

0.60 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85

0.51 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78

0.45 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34

0.60 8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25

0.51 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72

0.45 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65

0.66 6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34

0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10

0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23

0.66 6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96

0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77

0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95

0.66 5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94

0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75

0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93

ns

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-185

Device Architecture

Table 2-113 • 2.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

4 mA

Std.

–1

0.60 8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05

0.51 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40

0.45 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25

0.60 5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51

0.51 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38

0.45 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61

0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73

0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87

0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28

0.66 3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35

0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55

0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00

0.66 3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72

0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01

0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52

ns

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-186

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-114 • 2.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 11.40 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 11.22 11.40 2.68

2.20 13.45 13.63

1.88 11.44 11.60

1.65 10.05 10.18

2.89 10.34 10.05

ns

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.69

8.51

7.96

6.77

5.94

6.18

5.26

4.61

6.18

5.26

4.61

6.18

5.26

4.61

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

9.54

8.38

8.11

6.90

6.05

6.29

5.35

4.70

6.29

5.35

4.70

6.29

5.35

4.70

9.69

8.51

7.81

6.65

5.84

5.92

5.03

4.42

5.92

5.03

4.42

5.92

5.03

4.42

2.28

2.00

3.05

2.59

2.28

3.30

2.81

2.47

3.30

2.81

2.47

3.30

2.81

2.47

–2

8 mA

Std.

–1

2.46

2.16

3.32

2.83

2.48

3.32

2.83

2.48

3.32

2.83

2.48

8.80

7.72

8.53

7.26

6.37

8.53

7.26

6.37

8.53

7.26

6.37

8.55

7.50

8.15

6.94

6.09

8.15

6.94

6.09

8.15

6.94

6.09

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-187

Device Architecture

Table 2-115 • 2.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.66

7.37

6.47

5.17

4.39

3.86

3.56

3.03

2.66

3.35

2.85

2.50

3.56

3.03

2.66

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

7.83

6.66

5.85

5.04

4.28

3.76

3.63

3.08

2.71

3.41

2.90

2.55

3.63

3.08

2.71

8.66

7.37

6.47

5.17

4.39

3.86

3.43

2.92

2.56

3.06

2.60

2.29

3.43

2.92

2.56

2.68

2.28

2.00

3.05

2.59

2.28

3.30

2.81

2.47

3.36

2.86

2.51

3.30

2.81

2.47

2.30 10.07 10.90

ns

1.96

1.72

3.00

2.55

2.24

3.44

2.92

2.57

3.55

3.02

2.65

3.44

2.92

2.57

8.56

7.52

7.27

6.19

5.43

5.86

4.99

4.38

5.65

4.81

4.22

5.86

4.99

4.38

9.27

8.14

7.40

6.30

5.53

5.67

4.82

4.23

5.30

4.51

3.96

5.67

4.82

4.23

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-116 • 2.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

10.37

8.83

7.75

10.37

8.83

7.75

7.36

6.26

5.49

7.36

6.26

5.49

t_ZH

11.00

9.35

8.21

11.00

9.35

8.21

7.50

6.38

5.60

7.50

6.38

5.60

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

Std.

–1

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

2.03

1.73

1.52

2.03

1.73

1.52

2.39

2.03

1.78

2.39

2.03

1.78

1.83

1.56

1.37

1.83

1.56

1.37

2.46

2.10

1.84

2.46

2.10

1.84

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-188

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-117 • 2.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

4 mA

6 mA

8 mA

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

1.29

1.10

0.96

7.24

6.16

5.41

7.24

6.16

5.41

4.55

3.87

3.40

4.55

3.87

3.40

8.20

6.98

6.13

8.20

6.98

6.13

4.77

4.05

3.56

4.77

4.05

3.56

2.03

1.73

1.52

2.03

1.73

1.52

2.38

2.03

1.78

2.38

2.03

1.78

1.91

1.62

1.43

1.91

1.62

1.43

2.55

2.17

1.91

2.55

2.17

1.91

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-189

Device Architecture

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and push-pull output buffer.

Table 2-118 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

Applicable to Pro I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–0.3

0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45

2

4

6

8

2

4

6

8

11

22

44

51

74

9

10

17

35

45

91

0.35 * VCCI 0.65 * VCCI 3.6

0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

Applicable to Advanced I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

–0.3

0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45

2

4

6

8

2

4

6

8

11

22

44

51

74

9

10

17

35

45

91

0.35 * VCCI 0.65 * VCCI 1.9

0.35 * VCCI 0.65 * VCCI

1.9

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

Applicable to Standard I/O Banks

2 mA

4 mA

Notes:

–0.3

0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45

2

4

2

4

11

22

9

10

17

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t / t / t

R to GND for t / t / t

HZ ZH ZHS

Test Point

LZ ZL ZLS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t / t

/ t / t

ZH ZHS ZL ZLS

35 pF for t / t

HZ LZ

Figure 2-121 • AC Loading

Table 2-119 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Measuring Point* (V)

VREF (typ.) (V)

C

_LOAD(pF)

0

1.8

0.9

–

35

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

2-190

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-120 • 1.8 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07

0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37

0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50

0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99

0.56 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05

0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70

0.66 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33

0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79

0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72

0.66 8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82

0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35

0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33

0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80

0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33

0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32

ns

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-191

Device Architecture

Table 2-121 • 1.8 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.83 14.34

0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20

ns

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71

7.05 0.04 1.45 1.91 0.43 6.20 7.05 3.25 2.86 8.44 9.29

6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90

5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94

4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76

3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75

3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05

4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23

3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30

3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65

3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32

3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53

2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-192

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-122 • 1.8 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

0.66 15.53 0.04

0.56 13.21 0.04

0.49 11.60 0.03

0.66 10.48 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 14.11 15.53 2.78

0.36 12.01 13.21 2.36

0.32 10.54 11.60 2.07

0.43 10.41 10.48 3.23

1.60 16.35 17.77

1.36 13.91 15.11

1.19 12.21 13.27

2.73 12.65 12.71

2.33 10.76 10.81

ns

–1

–2²

Std.

–1

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.91 0.04

7.82 0.03

8.05 0.04

6.85 0.04

6.01 0.03

7.50 0.04

6.38 0.04

5.60 0.03

7.29 0.04

6.20 0.04

5.45 0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.86

7.77

8.20

6.97

6.12

7.64

6.50

5.71

7.23

6.15

5.40

8.91

7.82

7.84

6.67

5.86

7.30

6.21

5.45

7.29

6.20

5.45

2.75

2.41

3.54

3.01

2.64

3.61

3.07

2.69

3.71

3.15

2.77

–2

2.04

9.44

9.49

Std.

–1

3.27 10.43 10.08

2.78

2.44

3.41

2.90

2.55

3.95

3.36

2.95

8.88

7.79

9.88

8.40

7.38

9.47

8.06

7.07

8.57

7.53

9.53

8.11

7.12

9.53

8.11

7.12

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-193

Device Architecture

Table 2-123 • 1.8 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Advanced I/Os

Drive

Speed

Strength

Grade t_DOUT

t_DP

11.86 0.04 1.22 0.43 9.14 11.86 2.77

0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36

t_DIN

t_PYt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

16 mA

Std.

–1

0.66

1.66 11.37 14.10

ns

1.41

1.24

2.84

2.41

2.12

3.38

2.88

2.53

3.52

3.00

2.63

4.08

3.47

3.05

9.67 11.99

8.49 10.53

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.86

6.91

5.88

5.16

4.45

3.78

3.32

3.92

3.34

2.93

3.53

3.01

2.64

0.03 0.91 0.32 6.82

0.04 1.22 0.43 5.86

0.04 1.04 0.36 4.99

0.03 0.91 0.32 4.38

0.04 1.22 0.43 4.18

0.04 1.04 0.36 3.56

0.03 0.91 0.32 3.12

0.04 1.22 0.43 3.93

0.04 1.04 0.36 3.34

0.03 0.91 0.32 2.93

0.04 1.22 0.43 3.60

0.04 1.04 0.36 3.06

0.03 0.91 0.32 2.69

8.86

6.91

5.88

5.16

4.45

3.78

3.32

3.92

3.34

2.93

3.04

2.59

2.27

2.07

3.22

2.74

2.41

3.53

3.00

2.64

3.60

3.06

2.69

3.70

3.15

2.76

Std.

–1

8.10

6.89

6.05

6.42

5.46

4.79

6.16

5.24

4.60

5.84

4.96

4.36

9.15

7.78

6.83

6.68

5.69

4.99

6.16

5.24

4.60

5.28

4.49

3.94

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-124 • 1.8 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

13.15

11.19

9.82

9.55

8.13

7.13

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

Std.

–1

15.01

12.77

11.21

10.10

8.59

1.20

1.02

0.90

1.20

1.02

0.90

15.01

12.77

11.21

10.10

8.59

1.99

1.70

1.49

2.41

2.05

1.80

1.99

1.70

1.49

2.37

2.02

1.77

ns

–2

ns

4 mA

Std.

–1

ns

–2

7.54

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-194

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-125 • 1.8 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.7 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

0.66

0.56

0.49

t_DP

11.21

9.54

8.37

6.34

5.40

4.74

t_DIN

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

11.21

9.54

8.37

6.34

5.40

4.74

t_LZ

t_HZ

Units

ns

2 mA

1.20

1.02

0.90

1.20

1.02

0.90

8.53

7.26

6.37

5.38

4.58

4.02

1.99

1.69

1.49

2.41

2.05

1.80

1.21

1.03

0.90

2.48

2.11

1.85

ns

–2

ns

4 mA

Std.

–1

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-195

Device Architecture

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and push-pull output buffer.

Table 2-126 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

Applicable to Pro I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

2

4

6

8

2

4

6

8

16

33

39

55

13

25

32

66

10 10

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

Applicable to Advanced I/O Banks

2 mA

4 mA

6 mA

8 mA

12 mA

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

2

4

6

8

2

4

6

8

16

33

39

55

13

25

32

66

10 10

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI

–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12

Applicable to Pro I/O Banks

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

2

16

13

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

I

IH

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 1 k

Test Point

Data Path

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-122 • AC Loading

Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

1.5

0.75

–

35

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

2-196

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-128 • 1.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Pro I/Os

Drive

Speed

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37

0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08

0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48

0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10

ns

–2

Std.

–1

0.56

0.49

9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29

8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04

–2

Std.

–1

0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48

0.56

0.49

8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76

7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57

–2

Std.

–1

0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47

0.56

0.49

8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75

7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Table 2-129 • 1.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Pro I/Os

Drive

Speed

t_EOU

Strength Grade t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

T

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77

0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16

0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04

0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65

0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50

0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71

0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98

0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94

0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21

0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86

0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98

0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37

ns

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-197

Device Architecture

Table 2-130 • 1.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66 12.78 0.04

0.56 10.87 0.04

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

1.31

1.11

0.98

0.43 12.81 12.78 3.40

0.36 10.90 10.87 2.89

2.64 15.05 15.02

2.25 12.80 12.78

1.97 11.24 11.22

3.27 12.43 11.78

2.78 10.57 10.02

ns

–2

0.49

9.55

0.03

0.32

9.57

9.55

2.54

3.75

3.19

2.80

3.83

3.26

2.86

3.95

3.36

2.95

Std.

–1

0.66 10.01 0.04

0.43 10.19 9.55

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.51

7.47

9.33

7.94

6.97

8.91

7.58

6.65

0.04

0.03

0.04

0.03

0.04

0.03

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

8.67

7.61

9.51

8.09

7.10

9.07

7.72

6.78

8.12

7.13

8.89

7.56

6.64

8.89

7.57

6.64

–2

2.44

9.28

8.80

Std.

–1

3.43 11.74 11.13

2.92

2.56

9.99

8.77

9.47

8.31

–2

Std.

–1

4.05 11.31 11.13

3.44

3.02

9.62

8.45

9.47

8.31

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-131 • 1.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Advanced I/Os

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

0.04

0.03

0.04

0.03

0.04

0.03

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

8 mA

12 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.36

7.11

6.24

5.31

4.52

3.97

4.67

3.97

3.49

4.08

3.47

3.05

1.44

1.22

1.07

1.44

1.22

1.07

1.44

1.22

1.07

1.44

1.22

1.07

6.82

5.80

5.10

4.85

4.13

3.62

4.55

3.87

3.40

4.15

3.53

3.10

8.36

7.11

6.24

5.31

4.52

3.97

4.67

3.97

3.49

3.58

3.04

2.67

3.39

2.88

2.53

3.74

3.18

2.79

3.82

3.25

2.85

3.94

3.36

2.95

2.77

2.35

2.06

3.40

2.89

2.54

3.56

3.03

2.66

4.20

3.58

3.14

9.06 10.60

ns

7.71

6.76

7.09

6.03

5.29

6.78

5.77

5.07

6.39

5.44

4.77

9.02

7.91

7.55

6.42

5.64

6.90

5.87

5.16

5.81

4.95

4.34

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-198

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-132 • 1.5 V LVCMOS Low Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Standard I/Os

Drive

Speed

Strength

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

12.33

10.49

9.21

1.42

1.21

1.06

11.79

10.03

8.81

12.33

10.49

9.21

2.45

2.08

1.83

2.32

1.98

1.73

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-133 • 1.5 V LVCMOS High Slew

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V

Applicable to Standard I/Os

Drive

Strength

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

2 mA

Std.

–1

7.65

6.50

5.71

1.42

1.21

1.06

6.31

5.37

4.71

7.65

6.50

5.71

2.45

2.08

1.83

2.45

2.08

1.83

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-199

Device Architecture

3.3 V PCI, 3.3 V PCI-X

The Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

Table 2-134 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

VIH

VOL

VOH

IOL

mA

IOH IOSL IOSH IIL¹IIH²

Max. Max.

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Drive Strength

mA

mA³mA³µA⁴µA⁴

Per PCI

Per PCI curves

10

specification

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable

path characterization are described in Figure 2-123.

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R = 25

Test Point

Data Path

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

10 pF for t_HZ/ t_LZ

Figure 2-123 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the data path; Microsemi loading for tristate is

described in Table 2-135.

Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

–

10

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

2-200

Revision 4

Fusion Family of Mixed Signal FPGAs

Timing Characteristics

Table 2-136 • 3.3 V PCI/PCI-X

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Pro I/Os

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.09

4.33

3.80

t_ZHSUnits

Std.

–1

2.81

2.39

2.09

0.04 1.05 1.67

0.04 0.89 1.42

0.03 0.78 1.25

0.43

0.36

0.32

2.86

2.43

2.13

2.00

1.70

1.49

3.28

2.79

2.45

3.61

3.07

2.70

4.23

3.60

3.16

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Table 2-137 • 3.3 V PCI/PCI-X

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Advanced I/Os

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

t_PY

t_PYS

t_EOUT

2.73

2.32

2.04

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.19

3.56

3.13

t_ZHSUnits

2.68

2.28

2.00

0.04 0.86 0.43

0.04 0.73 0.36

0.03 0.65 0.32

1.95

1.66

1.46

3.21

2.73

2.40

3.58

3.05

2.68

4.97

4.22

3.71

0.66

0.56

0.49

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-201

Device Architecture

Voltage Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-138 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

VIL

VIH

VOL

VOH IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

181

268

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

GTL

25

Test Point

10 pF

Figure 2-124 • AC Loading

Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

10

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-140 • 3.3 V GTL

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 0.8 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.27

3.63

3.19

t_ZHSUnits

2.08

1.77

1.55

2.93

2.50

2.19

2.04

1.73

1.52

2.08

1.77

1.55

4.31

3.67

3.22

ns

–2

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-202

Revision 4

Fusion Family of Mixed Signal FPGAs

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-141 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

mA mA mA³mA³µA⁴µA⁴

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20

124

169

10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

GTL

25

Test Point

10 pF

Figure 2-125 • AC Loading

Table 2-142 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

0.8 1.2

C

_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

10

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-143 • 2.5 V GTL

Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 0.8 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.28

t_ZHS

4.36

3.71

3.26

Units

ns

2.13

1.81

1.59

2.46

2.09

1.83

2.16

1.84

1.61

2.13

1.81

1.59

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-203

Device Architecture

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-144 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

VIL

VIH

VOL

VOH IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

35 mA

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.6

–

35 35

181

268

10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

GTL+

25

Test Point

10 pF

Figure 2-126 • AC Loading

Table 2-145 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

1.0 1.5

C

_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

10

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-146 • 3.3 V GTL+

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.33

3.68

3.23

t_ZHS

4.29

3.65

3.20

Units

ns

2.06

1.75

1.53

1.59

1.35

1.19

2.09

1.78

1.56

2.06

1.75

1.53

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-204

Revision 4

Fusion Family of Mixed Signal FPGAs

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-147 • Minimum and Maximum DC Input and Output Levels

2.5 V

GTL+

VIL

Max.

VIH

VOL

VOH

IOL

IOH

IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max. Max.

Min.

V

Max.

mA³

Max.

V

mA

mA³µA⁴µA⁴

33 mA

–0.3 VREF – 0.1 VREF + 0.1 3.6

0.6

–

33

124

169

10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

GTL+

25

Test Point

10 pF

Figure 2-127 • AC Loading

Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

1.0 1.5

C

_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

10

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-149 • 2.5 V GTL+

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.0 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.48

3.81

3.35

t_ZHS

4.34

3.69

4.34

Units

ns

2.21

1.88

1.65

1.51

1.29

1.13

2.25

1.91

1.68

2.10

1.79

1.57

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-205

Device Architecture

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output

buffer.

Table 2-150 • Minimum and Maximum DC Input and Output Levels

HSTL

Class I

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max. Max.

Min.

V

Max. Max.

V

mA mA mA³mA³µA⁴µA⁴

8 mA

–0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

VCCI – 0.4

8

39

32

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

HSTL

Class I

50

Test Point

20 pF

Figure 2-128 • AC Loading

Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-152 • HSTL Class I

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.47

4.66

4.09

t_ZHS

5.38

4.58

4.02

Units

ns

3.18

2.70

2.37

2.12

1.81

1.59

3.24

2.75

2.42

3.14

2.67

2.35

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-206

Revision 4

Fusion Family of Mixed Signal FPGAs

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output

buffer.

Table 2-153 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

Drive Strength

15 mA³

mA mA mA³mA³µA⁴µA⁴

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.4

VCCI – 0.4 15 15

55

66

10 10

Note:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Output drive strength is below JEDEC specification.

VTT

HSTL

Class II

25

Test Point

20 pF

Figure 2-129 • AC Loading

Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

0.75 0.75

C

_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-155 • HSTL Class II

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.32

4.52

3.97

t_ZHS

4.95

4.21

3.70

Units

ns

3.02

2.57

2.26

2.12

1.81

1.59

3.08

2.62

2.30

2.71

2.31

2.03

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-207

Device Architecture

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-156 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

mA mA mA³mA³µA⁴µA⁴

15 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.54 VCCI – 0.62 15 15

87

83

10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

SSTL2

Class I

50

Test Point

25

30 pF

Figure 2-130 • AC Loading

Table 2-157 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

1.25 1.25

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

30

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-158 • SSTL 2 Class I

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.29

t_ZHS

4.08

3.47

3.05

Units

ns

2.13

1.81

1.59

1.33

1.14

1.00

2.17

1.84

1.62

1.85

1.57

1.38

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-208

Revision 4

Fusion Family of Mixed Signal FPGAs

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-159 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max. Max.

Min.

V

Max. Max.

Drive Strength

18 mA

V

mA mA mA³mA³µA⁴µA⁴

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.35 VCCI – 0.43 18 18 124

169

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

SSTL2

Class II

25

Test Point

25

30 pF

Figure 2-131 • AC Loading

Table 2-160 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)

1.25 1.25 1.25

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

30

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-161 • SSTL 2 Class II

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.44

3.78

3.32

t_ZHS

4.01

3.41

2.99

Units

ns

2.17

1.84

1.62

1.33

1.14

1.00

2.21

1.88

1.65

1.77

1.51

1.32

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-209

Device Architecture

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-162 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

mA mA mA³mA³µA⁴µA⁴

14 mA

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.7

VCCI – 1.1 14

14

54

51

10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

SSTL3

Class I

50

Test Point

25

30 pF

Figure 2-132 • AC Loading

Table 2-163 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

30

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-164 • SSTL3 Class I

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.59

3.90

3.42

t_ZHS

4.07

3.46

3.04

Units

ns

2.31

1.96

1.72

1.25

1.06

0.93

2.35

2.00

1.75

1.84

1.56

1.37

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-210

Revision 4

Fusion Family of Mixed Signal FPGAs

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-165 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Max. Max.

Min.

V

Max.

V

Min.

Max. Max.

Min.

V

Drive Strength

21 mA

V

mA mA mA³

mA³µA⁴µA⁴

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.5 VCCI – 0.9 21 21

109

103 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

VTT

SSTL3

Class II

25

Test Point

25

30 pF

Figure 2-133 • AC Loading

Table 2-166 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V) VTT (typ.) (V)

1.5 1.485

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

30

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-167 • SSTL3- Class II

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.34

3.69

3.24

t_ZHS

3.91

3.32

2.92

Units

ns

2.07

1.76

1.54

1.25

1.06

0.93

2.10

1.79

1.57

1.67

1.42

1.25

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-211

Device Architecture

Differential I/O Characteristics

Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with these standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires

that one data bit be carried through two signal lines, so two pins are needed. It also requires external

resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-134.

The building blocks of the LVDS transmitter–receiver are one transmitter macro, one receiver macro,

three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three

driver resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

165 

ZO = 50 

140 

ZO = 50 

INBUF_LVDS

+

–

100 

N

Figure 2-134 • LVDS Circuit Diagram and Board-Level Implementation

Table 2-168 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

VOL

Output Low Voltage

1.075

1.425

0.91

V

VOH

IOL ¹

IOH ¹

Input High Voltage

1.25

0.65

0

V

Output Low Voltage

1.16

2.925

10

mA

V

Output High Voltage

Input Voltage

VI

IIL ^2,3

IIH ^2,4

VODIFF

VOCM

VICM

Input Low Voltage

A

mV

V

Input High Voltage

10

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

VIDIFF

Notes:

mV

1. IOL/IOH defined by VODIFF/(Resistor Network)

2. Currents are measured at 85°C junction temperature.

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

2-212

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 2-169 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

Cross point

VREF (typ.) (V)

1.075

1.325

–

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-170 • LVDS

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V

Applicable to Pro I/Os

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

2.10

1.79

1.57

1.82

1.55

1.36

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

BLVDS/M-LVDS

Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations can contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by BLVDS and M-LVDS to accommodate the loading. The driver requires series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus, since the driver can be located anywhere on the bus. These configurations can be

implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-135. The input and output buffer delays are available in

the LVDS section in Table 2-171.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case industrial operating conditions at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

R

Z₀

T

Figure 2-135 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

Revision 4

2-213

Device Architecture

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-136.

The building blocks of the LVPECL transmitter–receiver are one transmitter macro, one receiver macro,

three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three

driver resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

OUTBUF_LVPECL

P

N

P

100 

ZO = 50 

187 W

ZO = 50 

INBUF_LVPECL

+

–

100 

N

Figure 2-136 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-171 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

3.0

3.3

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

V

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

VIDIFF

mV

Table 2-172 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

1.64

1.94

Cross point

–

Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.

Timing Characteristics

Table 2-173 • LVPECL

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Applicable to Pro I/Os

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

2.14

1.82

1.60

1.63

1.39

1.22

ns

–2

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-214

Revision 4

Fusion Family of Mixed Signal FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Preset

L

X

D

DOUT

X

Data_out

PRE

F

PRE

Y

Core

Array

E

X

Data

Enable

CLK

X

C

D

Q

D

Q

DFN1E1P1

G

E

X

E

X

B

EOUT

H

I

X

A

PRE

J

X

D

Q

DFN1E1P1

E

K

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive Edge Triggered

CLKBUF

INBUF

Figure 2-137 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Revision 4

2-215

Device Architecture

Table 2-174 • Parameter Definitions and Measuring Nodes

Parameter

Name

Measuring Nodes

(from, to)*

Parameter Definition

Clock-to-Q of the Output Data Register

t_OCLKQ

t_OSUD

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L,DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

Note: *See Figure 2-137 on page 2-215 for more information.

2-216

Revision 4

Fusion Family of Mixed Signal FPGAs

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

AA

DD

CLR

LL

HH

JJ

D

Q

CLR

DFN1E1C1

KK

E

CLR

Data Input I/O Register with

Active High Enable

Active High Clear

Positive Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive Edge Triggered

INBUF

CLKBUF

Figure 2-138 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Revision 4

2-217

Device Architecture

Table 2-175 • Parameter Definitions and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

GG, HH

LL, DOUT

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-138 on page 2-217 for more information.

2-218

Revision 4

Fusion Family of Mixed Signal FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

CLK

Data

t_IHD

50%

1

0

t_IREMPRE

t_IRECPRE

Enable

Preset

50%

t_IWPRE

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-139 • Input Register Timing Diagram

Timing Characteristics

Table 2-176 • Input Data Register Propagation Delays

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Description –2 –1

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

Std. Units

0.24 0.27 0.32

0.26 0.30 0.35

0.00 0.00 0.00

0.37 0.42 0.50

0.00 0.00 0.00

0.45 0.52 0.61

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

Revision 4

2-219

Device Architecture

Output Register

t_OCKMPWHt_OCKMPWL

50%

1

CLK

t_OSUDt_OHD

50%

0

Data_out

Enable

Preset

50%

t_OREMPRE

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_OWCLR

t_ORECCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-140 • Output Register Timing Diagram

Timing Characteristics

Table 2-177 • Output Data Register Propagation Delays

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

–2

–1

Std. Units

0.59

0.31

0.00

0.44

0.00

0.80

0.00

0.22

0.00

0.22

0.67 0.79

0.36 0.42

0.00 0.00

0.50 0.59

0.00 0.00

0.91 1.07

0.00 0.00

0.25 0.30

0.00 0.00

0.25 0.30

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22

Asynchronous Preset Minimum Pulse Width for the Output Data 0.22

Register

t_OCKMPWHClock Minimum Pulse Width High for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width Low for the Output Data Register

0.36

0.32

0.41 0.48

0.37 0.43

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

2-220

Revision 4

Fusion Family of Mixed Signal FPGAs

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

t_OESUDt_OEHD

50% 50%

50%

1

CLK

0

D_Enable

Enable

Preset

50%

t_OEREMPRE

50%

t_OEWPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OEPRE2Q

50%

t_OECLR2Q

50%

t_OECLKQ

EOUT

Figure 2-141 • Output Enable Register Timing Diagram

Timing Characteristics

Table 2-178 • Output Enable Register Propagation Delays

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

–2

–1

Std. Units

Clock-to-Q of the Output Enable Register

0.44 0.51 0.59

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.58

0.00 0.00 0.00

0.67 0.76 0.89

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

ns

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

t_OEHD

t_OESUE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPREAsynchronous Preset Removal Time for the Output Enable Register

t_OERECPREAsynchronous Preset Recovery Time for the Output Enable Register

t_OEWCLR

Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25 0.30

Register

t_OEWPRE

Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25 0.30

Register

ns

t_OECKMPWHClock Minimum Pulse Width High for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width Low for the Output Enable Register

0.36 0.41 0.48

0.32 0.37 0.43

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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Device Architecture

DDR Module Specifications

Input DDR Module

Input DDR

A

D

Out_QF

(to core)

Data

INBUF

FF1

E

B

C

Out_QR

(to core)

CLK

CLKBUF

FF2

CLR

INBUF

DDR_IN

Figure 2-142 • Input DDR Timing Model

Table 2-179 • Parameter Definitions

Parameter Name

Parameter Definition

Clock-to-Out Out_QR

Measuring Nodes (from, to)

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

B, D

B, E

A, B

C, D

C, E

C, B

Clock-to-Out Out_QF

Data Setup Time of DDR Input

Data Hold Time of DDR Input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

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Fusion Family of Mixed Signal FPGAs

CLK

t_DDRISUD

t_DDRIHD

8

Data

CLR

1

2

3

4

5

6

7

9

t_DDRIRECCLR

t_DDRIREMCLR

t_DDRICLKQ1

t_DDRICLR2Q1

Out_QF

Out_QR

6

2

4

t_DDRICLKQ2

t_DDRICLR2Q2

7

3

5

Figure 2-143 • Input DDR Timing Diagram

Timing Characteristics

Table 2-180 • Input DDR Propagation Delays

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR

–2

–1

Std.

0.52

0.37

0.38

0.00

0.76

0.62

0.00

0.30

0.48

0.43

1048

Units

ns

0.39

0.27

0.28

0.00

0.57

0.46

0.00

0.22

0.36

0.32

1404

0.44

0.31

0.32

0.00

0.65

0.53

0.00

0.25

0.41

0.37

1232

ns

t_DDRIHD

Data Hold for Input DDR

ns

t_DDRICLR2Q1

t_DDRICLR2Q2

Asynchronous Clear-to-Out Out_QR for Input DDR

Asynchronous Clear-to-Out Out_QF for Input DDR

ns

t_DDRIREMCLRAsynchronous Clear Removal Time for Input DDR

t_DDRIRECCLRAsynchronous Clear Recovery Time for Input DDR

ns

t_DDRIWCLR

Asynchronous Clear Minimum Pulse Width for Input DDR

ns

t_DDRICKMPWHClock Minimum Pulse Width High for Input DDR

t_DDRICKMPWLClock Minimum Pulse Width Low for Input DDR

ns

F_DDRIMAX

Maximum Frequency for Input DDR

MHz

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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Device Architecture

Output DDR

A

Data_F

(from core)

FF1

Out

B

C

D

0

1

CLK

E

CLKBUF

OUTBUF

Data_R

(from core)

FF2

B

C

CLR

INBUF

DDR_OUT

Figure 2-144 • Output DDR Timing Model

Table 2-181 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Clock-to-Out

Measuring Nodes (From, To)

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

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CLK

t

DDROHD2

DDROSUD2

4

9

5

Data_F

1

2

DDROSUD1

7

3

t

DDROHD1

Data_R 6

CLR

8

10

11

t

DDRORECCLR

t

DDROREMCLR

t

DDROCLKQ

DDROCLR2Q

Out

7

2

8

3

9

4

10

Figure 2-145 • Output DDR Timing Diagram

Timing Characteristics

Table 2-182 • Output DDR Propagation Delays

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–2

–1

Std. Units

Clock-to-Out of DDR for Output DDR

0.70

0.38

0.00

0.80

0.00

0.22

0.36

0.32

1404

0.80

0.43

0.00

0.91

0.00

0.25

0.41

0.37

1232

0.94

0.51

0.00

1.07

0.00

0.30

0.48

0.43

ns

Data_F Data Setup for Output DDR

Data_R Data Setup for Output DDR

Data_F Data Hold for Output DDR

t_DDROHD2

Data_R Data Hold for Output DDR

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

t_DDROCKMPWH

t_DDROCKMPWL

F_DDOMAX

Asynchronous Clear-to-Out for Output DDR

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

Clock Minimum Pulse Width High for the Output DDR

Clock Minimum Pulse Width Low for the Output DDR

Maximum Frequency for the Output DDR

1048 MHz

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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Device Architecture

Pin Descriptions

Supply Pins

GND

Ground

Ground supply voltage to the core, I/O outputs, and I/O logic.

GNDQ Ground (quiet)

Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise originated from the output buffer ground domain. This

minimizes the noise transfer within the package and improves input signal integrity. GNDQ needs to

always be connected on the board to GND. Note: In FG256, FG484, and FG676 packages, GNDQ and

GND pins are connected within the package and are labeled as GND pins in the respective package pin

assignment tables.

ADCGNDREF

Analog ground reference used by the ADC. This pad should be connected to a quiet analog ground.

GNDA Ground (analog)

Analog Reference Ground

Quiet ground supply voltage to the Analog Block of Fusion devices. The use of a separate analog ground

helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V

maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation.

GNDAQ

Ground (analog quiet)

Quiet ground supply voltage to the analog I/O of Fusion devices. The use of a separate analog ground

helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V

maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation.

Note: In FG256, FG484, and FG676 packages, GNDAQ and GNDA pins are connected within the

package and are labeled as GNDA pins in the respective package pin assignment tables.

GNDNVM

Ground supply used by the Fusion device's flash memory block module(s).

GNDOSC Oscillator Ground

Ground supply for both integrated RC oscillator and crystal oscillator circuit.

VCC15A Analog Power Supply (1.5 V)

1.5 V clean analog power supply input for use by the 1.5 V portion of the analog circuitry.

VCC33A Analog Power Supply (3.3 V)

3.3 V clean analog power supply input for use by the 3.3 V portion of the analog circuitry.

VCC33N Negative 3.3 V Output

Flash Memory Ground

This is the –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from this pin

to ground.

VCC33PMP

Analog Power Supply (3.3 V)

3.3 V clean analog power supply input for use by the analog charge pump. To avoid high current draw,

VCC33PMP should be powered up simultaneously with or after VCC33A.

VCCNVM

Flash Memory Block Power Supply (1.5 V)

1.5 V power supply input used by the Fusion device's flash memory block module(s). To avoid high

current draw, VCC should be powered up before or simultaneously with VCCNVM.

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VCCOSC

Oscillator Power Supply (3.3 V)

Power supply for both integrated RC oscillator and crystal oscillator circuit. The internal 100 MHz

oscillator, powered by the VCCOSC pin, is needed for device programming, operation of the VDDN33

pump, and eNVM operation. VCCOSC is off only when VCCA is off. VCCOSC must be powered

whenever the Fusion device needs to function.

VCC

Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is also required for powering the JTAG state

machine, in addition to VJTAG. Even when a Fusion device is in bypass mode in a JTAG chain of

interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass

through the Fusion device.

VCCIBx

I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are either

four (AFS090 and AFS250) or five (AFS600 and AFS1500) I/O banks on the Fusion devices plus a

dedicated VJTAG bank.

Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply.

VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their

corresponding VCCI pins tied to GND.

VCCPLA/B

PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V, where A and B refer to the PLL. AFS090 and AFS250

each have a single PLL. The AFS600 and AFS1500 devices each have two PLLs. Microsemi

recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise from PLL.

If unused, VCCPLA/B should be tied to GND.

VCOMPLA/B

Ground for West and East PLL

VCOMPLA is the ground of the west PLL (CCC location F) and VCOMPLB is the ground of the east PLL

(CCC location C).

VJTAG

JTAG Supply Voltage

Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives

greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is

neither used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND. It

should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a

Fusion device is in a JTAG chain of interconnected boards and it is desired to power down the board

containing the Fusion device, this may be done provided both VJTAG and VCC to the Fusion part remain

powered; otherwise, JTAG signals will not be able to transition the Fusion device, even in bypass mode.

VPUMP

Programming Supply Voltage

Fusion devices support single-voltage ISP programming of the configuration flash and FlashROM. For

programming, VPUMP should be in the 3.3 V +/-5% range. During normal device operation, VPUMP can

be left floating or can be tied to any voltage between 0 V and 3.6 V.

When the VPUMP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

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Device Architecture

User-Defined Supply Pins

VREF

I/O Voltage Reference

Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Microsemi

Pro I/O. These I/O banks support voltage reference standard I/O. The VREF pins are configured by the

user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage

reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and

(II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its

minibank.

VAREF

Analog Reference Voltage

The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be used by

the ADC. While using the internal reference, the reference voltage is output on the VAREF pin for use as

a system reference. If a different reference voltage is required, it can be supplied by an external source

and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When

VAREF is internally generated by the Fusion device, a bypass capacitor must be connected from this pin

to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF, which is based on the

needs of the individual designs. The choice of the capacitor value has an impact on the settling time it

takes the VAREF signal to reach the required specification of 2.56 V to initiate valid conversions by the

ADC. If the lower capacitor value is chosen, the settling time required for VAREF to achieve 2.56 V will

be shorter than when selecting the larger capacitor value. The above range of capacitor values supports

the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller

capacitor value will not obtain as much margin in the accuracy as that achieved with a larger capacitor

value. Depending on the capacitor value selected in the Analog System Builder, a tool in Libero SoC, an

automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that VAREF

has achieved the 2.56 V value. Microsemi recommends customers use 10 µF as the value of the bypass

capacitor. Designers choosing to use an external VAREF need to ensure that a stable and clean VAREF

source is supplied to the VAREF pin before initiating conversions by the ADC. Designers should also

make sure that the ADCRESET signal is deasserted before initiating valid conversions.²

If the user connects VAREF to external 3.3 V on their board, the internal VAREF driving OpAmp tries to

bring the pin down to the nominal 2.56 V until the device is programmed and up/functional. Under this

scenario, it is recommended to connect an external 3.3 V supply through a ~1 KOhm resistor to limit

current, along with placing a 10-100nF capacitor between VAREF and GNDA.

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up

resistors.

During programming, I/Os become tristated and weakly pulled up to VCCI. With the VCCI and VCC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os get instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

Input buffer is disabled (with tristate value of high impedance)

Weak pull-up is programmed

Axy

Analog Input/Output

Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad, T = Temperature

pad, V = Voltage pad) and y is the Analog Quad number (0 to 9). There is a minimum 1 M to ground on

AV, AC, and AT. This pin can be left floating when it is unused.

2. The ADC is functional with an external reference down to 1V, however to meet the performance parameters highlighted in the

datasheet refer to the VAREF specification in Table 3-2 on page 3-3.

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Fusion Family of Mixed Signal FPGAs

ATRTNx

Temperature Monitor Return

AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes

should be connected to these pins. There is one analog return pin for every two Analog Quads. The x in

the ATRTNx designator indicates the quad pairing (x = 0 for AQ1 and AQ2, x = 1 for AQ2 and AQ3, ...,

x = 4 for AQ8 and AQ9). The signals that drive these pins are called out as ATRETURNxy in the software

(where x and y refer to the quads that share the return signal). ATRTN is internally connected to ground.

It can be left floating when it is unused. The maximum capacitance allowed across the AT pins is 500 pF.

GL

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have identical

capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed

descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-23.

Refer to the "User I/O Naming Convention" section on page 2-161 for a description of naming of global

pins.

JTAG Pins

Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,

even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the Fusion

part must be supplied to allow JTAG signals to transition the Fusion device.

Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and

simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used,

the VJTAG pin together with the TRST pin could be tied to GND.

TCK

Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-

up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND or VJTAG through

a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired

state.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Refer to

Table 2-183 for more information.

Table 2-183 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG

Tie-Off Resistance^{2, 3}

VJTAG at 3.3 V

VJTAG at 2.5 V

VJTAG at 1.8 V

VJTAG at 1.5 V

Notes:

200  to 1 k

500  to 1 k

1. Equivalent parallel resistance if more than one device is on JTAG chain.

2. The TCK pin can be pulled up/down.

3. The TRST pin can only be pulled down.

TDI

Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor

on the TDI pin.

TDO

Test Data Output

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

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Device Architecture

TMS

Test Mode Select

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-

down resistor could be included to ensure the TAP is held in reset mode. The resistor values must be

chosen from Table 2-183 and must satisfy the parallel resistance value requirement. The values in

Table 2-183 correspond to the resistor recommended when a single device is used and to the equivalent

parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such

cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements.

Special Function Pins

NC

No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

DC

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.

NCAP Negative Capacitor

Don't Connect

Negative Capacitor is where the negative terminal of the charge pump capacitor is connected. A

capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.

PCAP

Positive Capacitor

Positive Capacitor is where the positive terminal of the charge pump capacitor is connected. A capacitor,

with a 2.2 µF recommended value, is required to connect between PCAP and NCAP.

PUB

Push Button

Push button is the connection for the external momentary switch used to turn on the 1.5 V voltage

regulator and can be floating if not used.

PTBASE

Pass Transistor Base

Pass Transistor Base is the control signal of the voltage regulator. This pin should be connected to the

base of the external pass transistor used with the 1.5 V internal voltage regulator and can be floating if

not used.

PTEM

Pass Transistor Emitter

Pass Transistor Emitter is the feedback input of the voltage regulator.

This pin should be connected to the emitter of the external pass transistor used with the 1.5 V internal

voltage regulator and can be floating if not used.

XTAL1

Crystal Oscillator Circuit Input

Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or

external clock input. When using an external crystal or ceramic oscillator, external capacitors are also

recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).

If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. In the

case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the

XTAL2 pin should be left floating.

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Fusion Family of Mixed Signal FPGAs

XTAL2

Crystal Oscillator Circuit Input

Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or

external clock input. When using an external crystal or ceramic oscillator, external capacitors are also

recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value).

If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. In the

case where the Crystal Oscillator block is not used, the XTAL1 pin should be connected to GND and the

XTAL2 pin should be left floating.

Security

Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates highly secure,

in-system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA

core fabric can be programmed independently from each other, allowing the FlashROM to be updated

without the need for change to the FPGA core fabric. The AES master key is stored in on-chip nonvolatile

memory (flash). The AES master key can be preloaded into parts in a security-protected programming

environment (such as the Microsemi in-house programming center), and then "blank" parts can be

shipped to an untrusted programming or manufacturing center for final personalization with an AES-

encrypted bitstream. Late stage product changes or personalization can be implemented easily and with

high level security by simply sending a STAPL file with AES-encrypted data. Highly secure remote field

updates over public networks (such as the Internet) are possible by sending and programming a STAPL

file with AES-encrypted data. For more information, refer to the Fusion Security application note.

128-Bit AES Decryption

The 128-bit AES standard (FIPS-197) block cipher is the National Institute of Standards and Technology

(NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect

sensitive government information well into the 21st century. It replaces the aging DES, which NIST

adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect

sensitive, unclassified information. The 128-bit AES standard has 3.4 × 10³⁸possible 128-bit key

variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text

using exhaustive techniques. Keys are stored (protected with security) in Fusion devices in nonvolatile

flash memory. All programming files sent to the device can be authenticated by the part prior to

programming to ensure that bad programming data is not loaded into the part that may possibly damage

it. All programming verification is performed on-chip, ensuring that the contents of Fusion devices remain

as secure as possible.

AES decryption can also be used on the 1,024-bit FlashROM to allow for remote updates of the

FlashROM contents. This allows for easy support of subscription model products and protects them with

measures designed to provide the highest level of security available. See the application note Fusion

Security for more details.

AES for Flash Memory

AES decryption can also be used on the flash memory blocks. This provides the best available security

during update of the flash memory blocks. During runtime, the encrypted data can be clocked in via the

JTAG interface. The data can be passed through the internal AES decryption engine, and the decrypted

data can then be stored in the flash memory block.

Programming

Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro

Systems) or FlashPro3 (Microsemi).

The user can generate STP programming files from the Designer software and can use these files to

program a device.

Fusion devices can be programmed in-system. During programming, VCCOSC is needed in order to

power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator that is

used to drive the charge pump for programming.

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Device Architecture

ISP

Fusion devices support IEEE 1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during

programming. In addition, programming via a microcontroller in a target system can be achieved. Refer to

the standard or the "In-System Programming (ISP) of Microsemi's Low Power Flash Devices Using

FlashPro4/3/3X" chapter of the Fusion FPGA Fabric User’s Guide for more details.

JTAG IEEE 1532

Programming with IEEE 1532

Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a

Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping

the global IO_EN signal deactivated, which also has the effect of disabling the input buffers.

Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this

unprogrammed state—different behavior from that of the ProASIC^PLUS®device family. This is done

because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input

buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a

noninvasive instruction. Refer to the standard or the "In-System Programming (ISP) of Microsemi's Low

Power Flash Devices Using FlashPro4/3/3X" chapter of the Fusion FPGA Fabric User’s Guide for more

details.

Boundary Scan

Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and

the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is

composed of the test access port (TAP) controller, test data registers, and instruction register (Figure 2-

146 on page 2-233). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-185 on page 2-233).

Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),

TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI,

and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied

to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on

page 2-229 for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state

machine (16 states) that operates as shown in Figure 2-146 on page 2-233. The 1s and 0s represent the

values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and

DR indicate that the instruction register or the data register is operating in that state.

Table 2-184 • TRST and TCK Pull-Down Recommendations

VJTAG

Tie-Off Resistance*

200  to 1 k

500  to 1 k

VJTAG at 3.3 V

VJTAG at 2.5 V

VJTAG at 1.8 V

VJTAG at 1.5 V

Note: *Equivalent parallel resistance if more than one device is on JTAG chain.

The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals

for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset

state. To guarantee a reset of the controller from any of the possible states, TMS must remain High for

five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-

Logic-Reset state.

Fusion devices support three types of test data registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other register needs to be accessed in a device. This

speeds up test data transfer to other devices in a test data path. The 32-bit device identification register

is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register

observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells,

each with a serial-in, serial-out, parallel-in, and parallel-out pin.

The serial pins are used to serially connect all the boundary scan register cells in a device into a

boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are

2-232

Revision 4

Fusion Family of Mixed Signal FPGAs

connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to

capture and load data into the register to control or observe the logic state of each I/O.

I/O

Test Data

Registers

Bypass Register

Instruction

Register

TAP

Controller

Device

Logic

I/O

Figure 2-146 • Boundary Scan Chain in Fusion

Table 2-185 • Boundary Scan Opcodes

Hex Opcode

EXTEST

00

07

0E

01

0F

05

FF

HIGHZ

USERCODE

SAMPLE/PRELOAD

IDCODE

CLAMP

BYPASS

Revision 4

2-233

IEEE 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/Os" section on

page 2-135 for more details.

Timing Characteristics

Table 2-186 • JTAG 1532

Commercial Temperature Range Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DISU

Description

Test Data Input Setup Time

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

–2

–1

Std.

0.67

1.33

0.67

1.33

8.00

26.67

19.00

0.00

0.27

TBD

Units

ns

0.50

1.00

0.50

1.00

6.00

20.00

25.00

0.00

0.20

TBD

0.57

1.13

0.57

1.13

6.80

22.67

22.00

0.00

0.23

TBD

t_DIHD

ns

t_TMSSU

ns

t_TMDHD

ns

t_TCK2Q

ns

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

ns

TCK Maximum Frequency

ResetB Removal Time

MHz

ns

ResetB Recovery Time

ResetB Minimum Pulse

ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to

Table 3-7 on page 3-9.

3 – DC and Power Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on

page 3-3.

Table 3-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

Commercial

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

Industrial

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

Units

V

VJTAG

VPUMP

VCCPLL

VCCI

JTAG DC voltage

Programming voltage

Analog power supply (PLL)

DC I/O output buffer supply voltage

I/O input voltage ¹

VI

–0.3 V to 3.6 V (when I/O hot insertion mode is

enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever

voltage is lower (when I/O hot-insertion mode is

disabled)

VCC33A

+3.3 V power supply

–0.3 to 3.75 ²

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 3.75 ²

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

VCC33PMP +3.3 V power supply

VAREF

Voltage reference for ADC

VCC15A

VCCNVM

VCCOSC

Notes:

Digital power supply for the analog system

Embedded flash power supply

Oscillator power supply

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4.

2. Analog data not valid beyond 3.65 V.

3. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

4. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits

refer to Table 3-2 on page 3-3.

Revision 4

3-1

DC and Power Characteristics

Table 3-1 • Absolute Maximum Ratings (continued)

Symbol

Parameter

ADC reset

Commercial

Industrial

Units

AV, AC

Unpowered,

unconfigured

asserted

or

–11.0 to 12.6

–11.0 to 12.0

V

Analog input (+16 V to +2 V prescaler range)

–0.4 to 12.6

–0.4 to 3.75

–0.4 to 12.0

–0.4 to 3.75

V

Analog input (+1 V to +0.125 V prescaler

range)

Analog input (–16 V to –2 V prescaler range)

–11.0 to 0.4

–3.75 to 0.4

–11.0 to 0.4

–3.75 to 0.4

V

Analog input (–1 V to –0.125 V prescaler

range)

Analog input (direct input to ADC)

Digital input

–0.4 to 3.75

–0.4 to 12.6

–11.0 to 12.6

–0.4 to 3.75

–0.4 to 12.0

–11.0 to 12.0

V

AG

Unpowered,

unconfigured

ADC

reset

asserted

or

Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)

–0.4 to 12.6

–11.0 to 0.4

–0.4 to 12.0

–11.0 to 0.4

V

Low Current Mode (–1 µA, –3 µA, –10 µA, –30

µA)

High Current Mode ³

–11.0 to 12.6

–0.4 to 16.0

–11.0 to 12.0

–0.4 to 15.0

V

AT

Unpowered,

unconfigured

ADC

reset

asserted

or

Analog input (+16 V, 4 V prescaler range)

Analog input (direct input to ADC)

Digital input

–0.4 to 16.0

–0.4 to 3.75

–0.4 to 16.0

–0.4 to 15.0

–0.4 to 3.75

–0.4 to 15.0

V

4

T_STG

Storage temperature

–65 to +150

+125

°C

4

T_J

Junction temperature

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4.

2. Analog data not valid beyond 3.65 V.

3. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

4. For flash programming and retention maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits

refer to Table 3-2 on page 3-3.

3-2

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-2 • Recommended Operating Conditions¹

Symbol

T_J

Parameter²

Commercial

0 to +85

Industrial

–40 to +100

1.425 to 1.575

1.4 to 3.6

Units

°C

V

Junction temperature

VCC

1.5 V DC core supply voltage

JTAG DC voltage

1.425 to 1.575

1.4 to 3.6

VJTAG

VPUMP

Programming voltage

Programming mode³

Operation⁴

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

VCCPLL

VCCI

Analog power supply (PLL)

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS differential I/O

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

2.3 to 2.7

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

LVPECL differential I/O

+3.3 V power supply

VCC33A

2.97 to 3.63

2.527 to 2.593

1.425 to 1.575

2.97 to 3.63

–10.5 to 12.0

–0.3 to 12.0

–0.3 to 3.6

2.97 to 3.63

2.527 to 2.593

1.425 to 1.575

2.97 to 3.63

–10.5 to 11.6

–0.3 to 11.6

–0.3 to 3.6

VCC33PMP +3.3 V power supply

VAREF

Voltage reference for ADC

VCC15A ⁵

VCCNVM

VCCOSC

AV, AC ⁶

Digital power supply for the analog system

Embedded flash power supply

Oscillator power supply

Unpowered, ADC reset asserted or unconfigured

Analog input (+16 V to +2 V prescaler range)

Analog input (+1 V to + 0.125 V prescaler range)

Analog input (–16 V to –2 V prescaler range)

Analog input (–1 V to –0.125 V prescaler range)

Analog input (direct input to ADC)

–10.5 to 0.3

–3.6 to 0.3

–10.5 to 0.3

–3.6 to 0.3

–0.3 to 3.6

Digital input

–0.3 to 12.0

–10.5 to 12.0

–0.3 to 12.0

–10.5 to 0.3

–10.5 to 12.0

–0.3 to 15.5

–0.3 to 3.6

–0.3 to 11.6

–10.5 to 11.6

–0.3 to 11.6

–10.5 to 0.3

–10.5 to 11.6

–0.3 to 14.5

–0.3 to 3.6

AG ⁶

Unpowered, ADC reset asserted or unconfigured

Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA)

Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA)

High Current Mode ⁷

AT ⁶

Unpowered, ADC reset asserted or unconfigured

Analog input (+16 V, +4 V prescaler range)

Analog input (direct input to ADC)

Digital input

–0.3 to 15.5

–0.3 to 14.5

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-85 on page 2-160.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. The programming temperature range supported is T

= 0°C to 85°C.

ambient

4. VPUMP can be left floating during normal operation (not programming mode).

5. Violating the V

programmed.

recommended voltage supply during an embedded flash program cycle can corrupt the page being

CC15A

6. The input voltage may overshoot by up to 500 mV above the Recommended Maximum (150 mV in Direct mode),

provided the duration of the overshoot is less than 50% of the operating lifetime of the device.

7. The AG pad should also conform to the limits as specified in Table 2-48 on page 2-117.

Revision 4

3-3

DC and Power Characteristics

Table 3-3 • Input Resistance of Analog Pads

Pads

Pad Configuration

Prescaler Range

–

Input Resistance to Ground

2 k (typical)

> 10 M

AV, AC

Analog Input (direct input to ADC)

–

Analog Input (positive prescaler)

Analog Input (negative prescaler)

+16 V to +2 V

+1 V to +0.125 V

–16 V to –2 V

–1 V to –0.125 V

+16 V to +2 V

–16 V to –2 V

–

1 M (typical)

> 10 M

1 M (typical)

> 10 M

Digital input

1 M (typical)

> 10 M

Current monitor

AT

Analog Input (direct input to ADC)

Analog Input (positive prescaler)

Digital input

+16 V, +4 V

Temperature monitor

Table 3-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot²

VCCI

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3.0 V

3.3 V

3.6 V

Notes:

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

10%

5%

10%

5%

1. Based on reliability requirements at a junction temperature of 85°C.

2. The duration is allowed at one cycle out of six clock cycle. If the overshoot/undershoot occurs at one out of two cycles,

the maximum overshoot/undershoot has to be reduced by 0.15 V.

3-4

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-5 • FPGA Programming, Storage, and Operating Limits

Product

Grade

Storage

Temperature

Grade Programming

Cycles

Element

Retention

20 years

10 years

5 years

Commercial

Min. T_J= 0°C

FPGA/FlashROM

Embedded Flash

500

Max. T_J= 85°C

< 1,000

< 10,000

< 15,000

500

Industrial

Min. T_J= –40°C

Max. T_J= 100°C

FPGA/FlashROM

Embedded Flash

20 years

10 years

5 years

< 1,000

< 10,000

< 15,000

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every Fusion device. These circuits

ensure easy transition from the powered off state to the powered up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1

on page 3-6.

There are five regions to consider during power-up.

Fusion I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 3-1).

2. VCCI > VCC – 0.75 V (typical).

3. Chip is in the operating mode.

V_CCITrip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

V_CCTrip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The V_CCactivation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels

(0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost.

Revision 4

3-5

DC and Power Characteristics

VCC = VCCI + VT

Where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

(except differential inputs)

but slower because VCCI is

below specification. For the

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH VOL, etc.

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

V

= 0.85 V ± 0.25 V

a

Deactivation trip point:

= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

V

d

VCCI

Activation trip point:

= 0.9 V ±0.3 V

Min VCCI datasheet specification

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

a

Deactivation trip point:

= 0.8 V ± 0.3 V

V

d

Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels

3-6

Revision 4

Fusion Family of Mixed Signal FPGAs

Thermal Characteristics

Introduction

The temperature variable in the Microsemi Designer software refers to the junction temperature, not the

ambient, case, or board temperatures. This is an important distinction because dynamic and static power

consumption will cause the chip's junction temperature to be higher than the ambient, case, or board

temperatures. EQ 1 through EQ 3 give the relationship between thermal resistance, temperature

gradient, and power.

T_J– _A

------------------

_JA

_JB

_JC

=

P

EQ 1

T_J– T_B

------------------

P

EQ 2

EQ 3

T_J– T_C

------------------

P

where

_JA= Junction-to-air thermal resistance

_JB= Junction-to-board thermal resistance

_JC= Junction-to-case thermal resistance

T_J= Junction temperature

T_A= Ambient temperature

T_B= Board temperature (measured 1.0 mm away from the

package edge)

T_C= Case temperature

P

= Total power dissipated by the device

Table 3-6 • Package Thermal Resistance

_JA

1.0 m/s

30.0

27.6

26.5

38.4

21.3

33.9

30.0

25.2

19.6

18.2

16.8

TBD

Product

Still Air

34.5

33.3

32.2

42.1

23.9

37.7

33.7

28.9

23.3

21.8

21.6

TBD

2.5 m/s

27.7

25.7

24.7

37

_JC

8.1

_JB

16.7

21.2

15.0

36.3

16.5

29.7

24.8

19.9

14.2

16.8

14.9

TBD

Units

AFS090-QN108

AFS090-QN180

AFS250-QN180

AFS250-PQ208

AFS600-PQ208

AFS090-FG256

AFS250-FG256

AFS600-FG256

AFS1500-FG256

AFS600-FG484

AFS1500-FG484

AFS1500-FG676

°C/W

9.2

5.7

20.5

6.1

20.48

32.2

28.3

23.5

18.0

16.7

15.2

TBD

11.5

9.3

6.8

4.3

7.7

5.6

TBD

Revision 4

3-7

DC and Power Characteristics

Theta-JA

Junction-to-ambient thermal resistance (_JA) is determined under standard conditions specified by

JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with

caution but is useful for comparing the thermal performance of one package to another.

A sample calculation showing the maximum power dissipation allowed for the AFS600-FG484 package

under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:

T

_J(MAX)– T_A(MAX)

---------------------------------------------

Maximum Power Allowed =

_JA

EQ 4

where

_JA= 19.00°C/W (taken from Table 3-6 on page 3-7).

T_A= 75.00°C

100.00°C – 75.00°C

----------------------------------------------------

Maximum Power Allowed =

= 1.3 W

19.00°C/W

EQ 5

The power consumption of a device can be calculated using the Microsemi power calculator. The

device's power consumption must be lower than the calculated maximum power dissipation by the

package. If the power consumption is higher than the device's maximum allowable power dissipation, a

heat sink can be attached on top of the case, or the airflow inside the system must be increased.

Theta-JB

Junction-to-board thermal resistance (_JB) measures the ability of the package to dissipate heat from the

surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance

from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a

means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a

JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.

Theta-JC

Junction-to-case thermal resistance (_JC) measures the ability of a device to dissipate heat from the

surface of the chip to the top or bottom surface of the package. It is applicable for packages used with

external heat sinks. Constant temperature is applied to the surface in consideration and acts as a

boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through

the surface in consideration.

Calculation for Heat Sink

For example, in a design implemented in an AFS600-FG484 package with 2.5 m/s airflow, the power

consumption value using the power calculator is 3.00 W. The user-dependent T_aand T_jare given as

follows:

T_J

T_A

=

100.00°C

70.00°C

From the datasheet:

_JA

_JC

=

17.00°C/W

8.28°C/W

T_J– T_A

------------------ -----------------------------------

= 1.76 W

100°C – 70°C

P =

=

_JA

17.00 W

EQ 6

3-8

Revision 4

Fusion Family of Mixed Signal FPGAs

The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the

airflow where the device is mounted should be increased. The design's total junction-to-air thermal

resistance requirement can be estimated by EQ 7:

T_J– T_A

------------------

P

100°C – 70°C

-----------------------------------

= 10.00°C/W

_ja(total)

=

3.00 W

EQ 7

EQ 8

Determining the heat sink's thermal performance proceeds as follows:

_JA(TOTAL)= _JC+ _CS+ _SA

where

_JA

=

0.37°C/W

Thermal resistance of the interface material between

the case and the heat sink, usually provided by the

thermal interface manufacturer

_SA

=

Thermal resistance of the heat sink in °C/W

_SA= _JA(TOTAL)– _JC– _CS

EQ 9

_SA= 13.33°C/W – 8.28°C/W – 0.37°C/W = 5.01°C/W

A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat

sinks is a function of airflow. The heat sink performance can be significantly improved with increased

airflow.

Carefully estimating thermal resistance is important in the long-term reliability of an Microsemi FPGA.

Design engineers should always correlate the power consumption of the device with the maximum

allowable power dissipation of the package selected for that device.

Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard

(JESD-51) and assumptions made in building the model. It may not be realized in actual application and

therefore should be used with a degree of caution. Junction-to-case thermal resistance assumes that all

power is dissipated through the case.

Temperature and Voltage Derating Factors

Table 3-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, Worst-Case VCC = 1.425 V)

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0°C

0.93

0.88

0.85

25°C

0.95

0.90

0.87

70°C

1.00

0.95

0.91

85°C

1.02

0.96

0.93

100°C

1.05

1.425

0.88

1.500

0.83

0.99

1.575

0.80

0.96

Revision 4

3-9

DC and Power Characteristics

Calculating Power Dissipation

Quiescent Supply Current

Table 3-8 • AFS1500 Quiescent Supply Current Characteristics

Parameter

Description

Conditions

Temp.

Min. Typ. Max. Unit

ICC¹

1.5 V quiescent current Operational standby⁴,

VCC = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

20

32

59

0

40

65

120

0

mA

µA

Standby mode⁵or Sleep mode⁶,

VCC = 0 V

ICC33²

3.3 V analog supplies

current

Operational standby⁴,

VCC33 = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

9.8

10.7

10.8

0.31

0.35

0.45

2.9

13

14

15

2

mA

µA

Operational standby, only Analog

Quad and –3.3 V output ON,

VCC33 = 3.63 V

2

Standby mode⁵, VCC33 = 3.63 V

3.6

4

2.9

3.3

6

Sleep mode⁶, VCC33 = 3.63 V

17

19

20

25

649

18

µA

24

µA

ICCI³

I/O quiescent current

Operational standby⁴,

417

µA

Standby mode, and Sleep Mode⁶,

VCCIx = 3.63 V

µA

Notes:

1. ICC is the 1.5 V power supplies, ICC and ICC15A.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

3-10

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-8 • AFS1500 Quiescent Supply Current Characteristics (continued)

Parameter

Description

Conditions

Operational standby⁴,

Temp.

Min. Typ. Max. Unit

IJTAG

JTAG I/O quiescent

current

T_J= 25°C

T_J= 85°C

T_J= 100°C

80

0

100

0

µA

VJTAG = 3.63 V

Standby mode⁵or Sleep mode⁶,

VJTAG = 0 V

IPP

Programming supply

current

Non-programming mode,

VPUMP = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

39

40

0

80

0

µA

Standby mode⁵or Sleep mode⁶,

VPUMP = 0 V

ICCNVM

ICCPLL

Notes:

Embedded NVM

current

Reset asserted, V_CCNVM= 1.575 V

T_J= 25°C

T_J=85°C

50

150

200

µA

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

50

1.5 V PLL quiescent

current

Operational standby

, VCCPLL = 1.575 V

130

1. ICC is the 1.5 V power supplies, ICC and ICC15A.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

Revision 4

3-11

DC and Power Characteristics

Table 3-9 • AFS600 Quiescent Supply Current Characteristics

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

ICC¹

1.5 V quiescent current

Operational standby⁴,

VCC = 1.575 V

T_J= 25°C

T_J= 85°C

T_J=100°C

13

20

25

0

25

45

75

0

mA

µA

Standby mode⁵or Sleep

mode⁶, VCC = 0 V

ICC33²

3.3 V analog supplies

current

Operational standby⁴,

VCC33 = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

9.8

13

mA

µA

10.7 14

10.8 15

Operational standby,

only Analog Quad and –3.3 V

output ON, VCC33 = 3.63 V

0.31

0.35

0.45

2.8

2.9

3.5

17

2

Standby mode⁵,

VCC33 = 3.63 V

3.6

4

6

Sleep mode⁶, V_CC33= 3.63 V

19

20

25

18

µA

24

µA

ICCI³

I/O quiescent current

Operational standby⁴,

VCCIx = 3.63 V

417 648 µA

417 649 µA

IJTAG

JTAG I/O quiescent current Operational standby⁴,

VJTAG = 3.63 V

80

0

100 µA

Standby mode⁵or Sleep

mode⁶, VJTAG = 0 V

0

µA

Notes:

1. ICC is the 1.5 V power supplies, ICC and ICC15A.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

3-12

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-9 • AFS600 Quiescent Supply Current Characteristics (continued)

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

IPP

Programming supply

current

Non-programming mode,

VPUMP = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

36

0

80

0

µA

Standby mode⁵or Sleep

mode⁶, VPUMP = 0 V

ICCNVM

ICCPLL

Notes:

Embedded NVM current

Reset asserted,

VCCNVM = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

22

24

25

80

µA

1.5 V PLL quiescent current Operational standby,

VCCPLL = 1.575 V

130 200 µA

1. ICC is the 1.5 V power supplies, ICC and ICC15A.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, ICCI2, and ICCI4.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

Revision 4

3-13

DC and Power Characteristics

Table 3-10 • AFS250 Quiescent Supply Current Characteristics

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

ICC¹

1.5 V quiescent current

Operational standby⁴,

VCC = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

4.8

8.2

15

0

10

30

50

0

mA

µA

Standby mode⁵or Sleep

mode⁶, VCC = 0 V

ICC33²

3.3 V analog supplies

current

Operational standby⁴,

VCC33 = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

9.8

13

14

mA

µA

10.8 15

Operational standby, only

Analog Quad and –3.3 V

output ON, VCC33 = 3.63 V

0.29

0.31

0.45

2.9

3.5

19

2

Standby mode⁵, VCC33 = 3.63V T_J= 25°C

3.0

3.1

6

T_J= 85°C

T_J= 100°C

Sleep mode⁶, VCC33 = 3.63 V T_J= 25°C

T_J= 85°C

18

20

25

19

µA

T_J= 100°C

24

µA

ICCI³

I/O quiescent current

Operational standby⁶,

VCCIx = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

266 437 µA

IJTAG

JTAG I/O quiescent current Operational standby⁴,

VJTAG = 3.63 V

80

0

100 µA

Standby mode⁵or Sleep

mode⁶, VJTAG = 0 V

0

µA

Notes:

1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, and ICCI2.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTA G = VPUMP = 0 V.

3-14

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-10 • AFS250 Quiescent Supply Current Characteristics (continued)

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

IPP

Programming supply

current

Non-programming mode,

VPUMP = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

37

80

0

80

µA

100 µA

Standby mode⁵or Sleep

mode⁶, VPUMP = 0 V

0

µA

ICCNVM

ICCPLL

Notes:

Embedded NVM current

Reset asserted,

VCCNVM = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

10

14

65

40

µA

1.5 V PLL quiescent current Operational standby,

VCCPLL = 1.575 V

100 µA

1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, and ICCI2.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTA G = VPUMP = 0 V.

Revision 4

3-15

DC and Power Characteristics

Table 3-11 • AFS090 Quiescent Supply Current Characteristics

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

ICC¹

1.5 V quiescent current

Operational standby⁴,

VCC = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

5

6.5

14

0

7.5

20

48

0

mA

µA

Standby mode⁵or Sleep

mode⁶, V_CC= 0 V

ICC33²

3.3 V analog supplies

current

Operational standby⁴,

VCC33 = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

9.8

12

mA

µA

10.7 15

Operational standby, only

Analog Quad and –3.3 V

output ON, VCC33 = 3.63 V

0.30

0.45

2.9

3.5

17

2

Standby mode⁵,

VCC33 = 3.63 V

2.9

3.0

6

Sleep mode⁶, VCC33 = 3.63 V T_J= 25°C

18

20

25

T_J= 85°C

18

µA

T_J= 100°C

24

µA

ICCI³

I/O quiescent current

Operational standby⁶,

VCCIx = 3.63 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

260 437 µA

IJTAG

JTAG I/O quiescent current Operational standby⁴,

VJTAG = 3.63 V

80

0

100 µA

Standby mode⁵or Sleep

mode⁶, VJTAG = 0 V

0

µA

IPP

Programming supply

current

Non-programming mode,

VPUMP = 3.63 V

T_J= 25°C

37

80

T_J= 85°C

37

80

0

T_J= 100°C

100 µA

µA

Standby mode⁵or Sleep

mode⁶, VPUMP = 0 V

0

Notes:

1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, and ICCI2.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

3-16

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-11 • AFS090 Quiescent Supply Current Characteristics (continued)

Parameter

Description

Conditions

Temp.

Min Typ Max Unit

ICCNVM

Embedded NVM current

Reset asserted,

VCCNVM = 1.575 V

T_J= 25°C

T_J= 85°C

T_J= 100°C

T_J= 25°C

T_J= 85°C

T_J= 100°C

10

14

65

40

µA

ICCPLL

1.5 V PLL quiescent current Operational standby,

VCCPLL = 1.575 V

100 µA

Notes:

1. ICC is the 1.5 V power supplies, ICC, ICCPLL, ICC15A, ICCNVM.

2. ICC33A includes ICC33A, ICC33PMP, and ICCOSC.

3. ICCI includes all ICCI0, ICCI1, and ICCI2.

4. Operational standby is when the Fusion device is powered up, all blocks are used, no I/O is toggling, Voltage Regulator is

loaded with 200 mA, VCC33PMP is ON, XTAL is ON, and ADC is ON.

5. XTAL is configured as high gain, VCC = VJTAG = VPUMP = 0 V.

6. Sleep Mode, VCC = VJTAG = VPUMP = 0 V.

Revision 4

3-17

DC and Power Characteristics

Power per I/O Pin

Table 3-12 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings

Static Power

Dynamic Power

PAC9 (µW/MHz)²

VCCI (V)

PDC7 (mW)¹

Applicable to Pro I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

17.39

25.51

5.76

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

7.16

2.72

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

3.3 V PCI

2.80

2.08

2.00

18.82

20.12

18.82

20.12

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

8.23

4.78

4.14

3.71

2.03

4.48

9.26

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

1.50

2.17

LVPECL

Notes:

1. PDC7 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCC and VCCI.

3-18

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-12 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued)

Static Power

PDC7 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

VCCI (V)

Applicable to Advanced I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

16.69

5.12

1.8 V LVCMOS

2.13

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

1.45

18.11

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

1.20

1.87

LVPECL

Applicable to Standard I/O Banks

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

3.3

2.5

1.8

1.5

–

16.79

5.19

2.18

1.52

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. PDC7 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCC and VCCI.

Revision 4

3-19

DC and Power Characteristics

Table 3-13 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings¹

Static Power

Dynamic Power

C

_LOAD(pF)

VCCI (V)

PDC8 (mW)²

PAC10 (µW/MHz)³

Applicable to Pro I/O Banks

Single-Ended

3.3 V LVTTL/LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

35

10

3.3

2.5

1.8

1.5

3.3

–

474.70

270.73

151.78

104.55

204.61

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.22

105.56

116.60

114.87

131.76

2.5 V GTL

–

3.3 V GTL+

–

2.5 V GTL+

–

HSTL (I)

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.62

LVPECL

19.42

168.02

Applicable to Advanced I/O Banks

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

35

10

3.3

2.5

1.8

1.5

3.3

–

468.67

267.48

149.46

103.12

201.02

3.3 V PCI-X

Notes:

1. Dynamic power consumption is given for standard load and software-default drive strength and output slew.

2. PDC8 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

3-20

Revision 4

Fusion Family of Mixed Signal FPGAs

Table 3-13 • Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings¹(continued)

Static Power

PDC8 (mW)²

Dynamic Power

C

_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Differential

LVDS

–

2.5

3.3

7.74

88.92

LVPECL

19.54

166.52

Applicable to Standard I/O Banks

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

35

3.3

2.5

1.8

1.5

–

431.08

247.36

128.46

89.46

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Notes:

1. Dynamic power consumption is given for standard load and software-default drive strength and output slew.

2. PDC8 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

Revision 4

3-21

DC and Power Characteristics

Dynamic Power Consumption of Various Internal Resources

Table 3-14 • Different Components Contributing to the Dynamic Power Consumption in Fusion Devices

Device-Specific

Power Supply

Dynamic Contributions

Parameter

Definition

Name Setting AFS1500 AFS600 AFS250 AFS090 Units

PAC1

Clock contribution of a Global VCC

Rib

1.5 V

14.5

2.5

12.8

1.9

11

µW/MHz

PAC2

PAC3

PAC4

PAC5

PAC6

Clock contribution of a Global VCC

Spine

1.6

0.8

Clock contribution of a VersaTile VCC

row

0.81

0.11

0.07

0.29

Clock contribution of a VersaTile VCC

used as a sequential module

First contribution of a VersaTile VCC

used as a sequential module

Second

contribution

of

a

VCC

VersaTile used as a sequential

module

PAC7

Contribution of a VersaTile used VCC

as a combinatorial module

1.5 V

0.29

0.70

µW/MHz

PAC8

Average contribution of a routing VCC

net

PAC9

Contribution of an I/O input pin VCCI

(standard dependent)

See Table 3-12 on page 3-18

PAC10

PAC11

PAC12

Contribution of an I/O output pin VCCI

(standard dependent)

See Table 3-13 on page 3-20

Average contribution of a RAM VCC

block during a read operation

1.5 V

25

30

µW/MHz

Average contribution of a RAM VCC

block during a write operation

PAC13

PAC15

Dynamic Contribution for PLL

VCC

1.5 V

2.6

µW/MHz

Contribution of NVM block during VCC

a read operation (F < 33MHz)

358

PAC16

PAC17

1st contribution of NVM block VCC

during a read operation (F > 33

MHz)

1.5 V

12.88

4.8

mW

2nd contribution of NVM block VCC

during a read operation (F > 33

MHz)

µW/MHz

PAC18

PAC19

PAC20

Crystal Oscillator contribution

RC Oscillator contribution

VCC33A 3.3 V

0.63

3.3

3

mW

Analog Block dynamic power VCC

contribution of ADC

1.5 V

3-22

Revision 4

Fusion Family of Mixed Signal FPGAs

Static Power Consumption of Various Internal Resources

Table 3-15 • Different Components Contributing to the Static Power Consumption in Fusion Devices

Device-Specific Static Contributions

Power

Parameter

Definition

Supply

AFS1500 AFS600 AFS250 AFS090 Units

PDC1

Core static power contribution in

operating mode

VCC

1.5 V

18

7.5

4.50

3.00

mW

PDC2

PDC3

Device static power contribution in VCC33A 3.3 V

standby mode

0.66

0.03

Device static power contribution in VCC33A 3.3 V

sleep mode

PDC4

PDC5

NVM static power contribution

VCC

1.5 V

1.19

8.25

mW

Analog

Block

static

power VCC33A 3.3 V

contribution of ADC

PDC6

PDC7

PDC8

PDC9

Analog Block

contribution per Quad

static

power VCC33A 3.3 V

3.3

mW

Static contribution per input pin – VCCI

standard dependent contribution

See Table 3-12 on page 3-18

See Table 3-13 on page 3-20

2.55

Static contribution per input pin – VCCI

standard dependent contribution

Static contribution for PLL

VCC

1.5 V

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

The number of NVM blocks used in the design

The number of Analog Quads used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-16 on

page 3-27.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 3-17 on

page 3-27.

Read rate and write rate to the RAM—guidelines are provided for typical applications in

Table 3-17 on page 3-27.

Read rate to the NVM blocks

The calculation should be repeated for each clock domain defined in the design.

Revision 4

3-23

DC and Power Characteristics

Methodology

Total Power Consumption—P

TOTAL

Operating Mode, Standby Mode, and Sleep Mode

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

Operating Mode

STAT

P_STAT= PDC1 + (N_NVM-BLOCKS* PDC4) + PDC5+ (N_QUADS* PDC6) + (N_INPUTS* PDC7) +

(N_OUTPUTS* PDC8) + (N_PLLS* PDC9)

N_NVM-BLOCKSis the number of NVM blocks available in the device.

N_QUADSis the number of Analog Quads used in the design.

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

N_PLLSis the number of PLLs available in the device.

Standby Mode

P_STAT= PDC2

Sleep Mode

P_STAT= PDC3

Total Dynamic Power Consumption—P

Operating Mode

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL+ P_NVM

P_XTL-OSC+ P_RC-OSC+ P_AB

+

Standby Mode

P_DYN= P_XTL-OSC

Sleep Mode

P_DYN= 0 W

Global Clock Dynamic Contribution—P

Operating Mode

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in the

"Spine Architecture" section of the Global Resources chapter in the Fusion and Extended

Temperature Fusion FPGA Fabric User's Guide.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in the "Spine

Architecture" section of the Global Resources chapter in the Fusion and Extended Temperature

Fusion FPGA Fabric User's Guide.

F_CLKis the global clock signal frequency.

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

Standby Mode and Sleep Mode

P_CLOCK= 0 W

Sequential Cells Dynamic Contribution—P

S-CELL

Operating Mode

3-24

Revision 4

Fusion Family of Mixed Signal FPGAs

P_S-CELL= N_S-CELL* (PAC5 + (₁/ 2) * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_S-CELL= 0 W

Combinatorial Cells Dynamic Contribution—P

C-CELL

Operating Mode

P_C-CELL= N_C-CELL* (₁/ 2) * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_C-CELL= 0 W

Routing Net Dynamic Contribution—P_NET

Operating Mode

P_NET= (N_S-CELL+ N_C-CELL) * (₁/ 2) * PAC8 * F_CLK

N_S-CELLis the number VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-16 on page 3-27.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_NET= 0 W

I/O Input Buffer Dynamic Contribution—P

INPUTS

Operating Mode

P_INPUTS= N_INPUTS* (₂/ 2) * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_INPUTS= 0 W

I/O Output Buffer Dynamic Contribution—P

OUTPUTS

Operating Mode

P_OUTPUTS= N_OUTPUTS* (₂/ 2) * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 3-16 on page 3-27.

₁is the I/O buffer enable rate—guidelines are provided in Table 3-17 on page 3-27.

F_CLKis the global clock signal frequency.

Standby Mode and Sleep Mode

P_OUTPUTS= 0 W

Revision 4

3-25

DC and Power Characteristics

RAM Dynamic Contribution—P

MEMORY

Operating Mode

P_MEMORY= (N_BLOCKS* PAC11 * ₂* F_READ-CLOCK) + (N_BLOCKS* PAC12 * ₃* F_WRITE-CLOCK

)

N_BLOCKSis the number of RAM blocks used in the design.

F_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations—guidelines are provided in Table 3-17 on

page 3-27.

₃the RAM enable rate for write operations—guidelines are provided in Table 3-17 on page 3-27.

F_WRITE-CLOCKis the memory write clock frequency.

Standby Mode and Sleep Mode

P_MEMORY= 0 W

PLL/CCC Dynamic Contribution—P

PLL

Operating Mode

P_PLL= PAC13 * F_CLKOUT

F_CLKINis the input clock frequency.

F_CLKOUTis the output clock frequency.¹

Standby Mode and Sleep Mode

P_PLL= 0 W

Nonvolatile Memory Dynamic Contribution—P

NVM

Operating Mode

The NVM dynamic power consumption is a piecewise linear function of frequency.

P_NVM= N_NVM-BLOCKS* ₄* PAC15 * F_READ-NVMwhen F_READ-NVM33 MHz,

P_NVM= N_NVM-BLOCKS* ₄*(PAC16 + PAC17 * F_READ-NVMwhen F_READ-NVM> 33 MHz

N_NVM-BLOCKSis the number of NVM blocks used in the design (2 inAFS600).

₄is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state).

F_READ-NVMis the NVM read clock frequency.

Standby Mode and Sleep Mode

P_NVM= 0 W

Crystal Oscillator Dynamic Contribution—P

XTL-OSC

Operating Mode

P_XTL-OSC= PAC18

Standby Mode

P_XTL-OSC= PAC18

Sleep Mode

P_XTL-OSC= 0 W

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula output clock by adding its corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL

contribution.

3-26

Revision 4

Fusion Family of Mixed Signal FPGAs

RC Oscillator Dynamic Contribution—P

RC-OSC

Operating Mode

P_RC-OSC= PAC19

Standby Mode and Sleep Mode

P_RC-OSC= 0 W

Analog System Dynamic Contribution—P

AB

Operating Mode

P_AB= PAC20

Standby Mode and Sleep Mode

P_AB= 0 W

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1 = 50%

Bit 2 = 25%

…

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 3-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 3-17 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

₄

RAM enable rate for read operations

RAM enable rate for write operations

NVM enable rate for read operations

12.5%

0%

Revision 4

3-27

DC and Power Characteristics

Example of Power Calculation

This example considers a shift register with 5,000 storage tiles, including a counter and memory that

stores analog information. The shift register is clocked at 50 MHz and stores and reads information from

a RAM.

The device used is a commercial AFS600 device operating in typical conditions.

The calculation below uses the power calculation methodology previously presented and shows how to

determine the dynamic and static power consumption of resources used in the application.

Also included in the example is the calculation of power consumption in operating, standby, and sleep

modes to illustrate the benefit of power-saving modes.

Global Clock Contribution—P

CLOCK

F_CLK= 50 MHz

Number of sequential VersaTiles: N_S-CELL= 5,000

Estimated number of Spines: N_SPINES= 5

Estimated number of Rows: N_ROW= 313

Operating Mode

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

P_CLOCK= (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50

P_CLOCK= 41.28 mW

Standby Mode and Sleep Mode

P_CLOCK= 0 W

Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—P

,

S-CELL

P

, and P

C-CELL

NET

F_CLK= 50 MHz

Number of sequential VersaTiles: N_S-CELL= 5,000

Number of combinatorial VersaTiles: N_C-CELL= 6,000

^{Estimated toggle rate of VersaTile outputs:}₁= 0.1 (10%)

Operating Mode

P_S-CELL= N_S-CELL* (P_AC5+ (₁/ 2) * PAC6) * F_CLK

P_S-CELL= 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50

P_S-CELL= 21.13 mW

P_C-CELL= N_C-CELL* (₁/ 2) * PAC7 * F_CLK

P_C-CELL= 6,000 * (0.1 / 2) * 0.00029 * 50

P_C-CELL= 4.35 mW

P_NET= (N_S-CELL+ N_C-CELL) * (₁/ 2) * PAC8 * F_CLK

P_NET= (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50

P_NET= 19.25 mW

P_LOGIC= P_S-CELL+ P_C-CELL+ P_NET

P_LOGIC= 21.13 mW + 4.35 mW + 19.25 mW

P_LOGIC= 44.73 mW

Standby Mode and Sleep Mode

3-28

Revision 4

Fusion Family of Mixed Signal FPGAs

P_S-CELL= 0 W

P_C-CELL= 0 W

P_NET= 0 W

P_LOGIC= 0 W

I/O Input and Output Buffer Contribution—P

I/O

This example uses LVTTL 3.3 V I/O cells. The output buffers are 12 mA–capable, configured with high

output slew and driving a 35 pF output load.

F_CLK= 50 MHz

Number of input pins used: N_INPUTS= 30

Number of output pins used: N_OUTPUTS= 40

^{Estimated I/O buffer toggle rate:}₂= 0.1 (10%)

^{Estimated IO buffer enable rate:}₁= 1 (100%)

Operating Mode

P_INPUTS= N_INPUTS* (₂/ 2) * PAC9 * F_CLK

P_INPUTS= 30 * (0.1 / 2) * 0.01739 * 50

P_INPUTS= 1.30 mW

P_OUTPUTS= N_OUTPUTS* (₂/ 2) * ₁* PAC10 * F_CLK

P_OUTPUTS= 40 * (0.1 / 2) * 1 * 0.4747 * 50

P_OUTPUTS= 47.47 mW

P_I/O= P_INPUTS+ P_OUTPUTS

P_I/O= 1.30 mW + 47.47 mW

P_I/O= 48.77 mW

Standby Mode and Sleep Mode

P_INPUTS= 0 W

P_OUTPUTS= 0 W

P_I/O= 0 W

RAM Contribution—P

MEMORY

Frequency of Read Clock: F_READ-CLOCK= 10 MHz

Frequency of Write Clock: F_WRITE-CLOCK= 10 MHz

Number of RAM blocks: N_BLOCKS= 20

^{Estimated RAM Read Enable Rate:}₂= 0.125 (12.5%)

^{Estimated RAM Write Enable Rate:}₃= 0.125 (12.5%)

Operating Mode

P_MEMORY= (N_BLOCKS* PAC11 * ₂* F_READ-CLOCK) + (N_BLOCKS* PAC12 * ₃* F_WRITE-CLOCK

)

P_MEMORY= (20 * 0.025 * 0.125 * 10) + (20 * 0.030 * 0.125 * 10)

P_MEMORY= 1.38 mW

Standby Mode and Sleep Mode

P_MEMORY= 0 W

Revision 4

3-29

DC and Power Characteristics

PLL/CCC Contribution—P

PLL

PLL is not used in this application.

P_PLL= 0 W

Nonvolatile Memory—P

NVM

Nonvolatile memory is not used in this application.

P_NVM= 0 W

Crystal Oscillator—P

XTL-OSC

The application utilizes standby mode. The crystal oscillator is assumed to be active.

Operating Mode

P_XTL-OSC= PAC18

P_XTL-OSC= 0.63 mW

Standby Mode

P_XTL-OSC= PAC18

P_XTL-OSC= 0.63 mW

Sleep Mode

P_XTL-OSC= 0 W

RC Oscillator—P

RC-OSC

Operating Mode

P_RC-OSC= PAC19

P_RC-OSC= 3.30 mW

Standby Mode and Sleep Mode

P_RC-OSC= 0 W

Analog System—P

AB

Number of Quads used: N_QUADS= 4

Operating Mode

P_AB= PAC20

P_AB= 3.00 mW

Standby Mode and Sleep Mode

P_AB= 0 W

Total Dynamic Power Consumption—P

DYN

Operating Mode

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL+ P_NVM

P_XTL-OSC+ P_RC-OSC+ P_AB

+

P_DYN= 41.28 mW + 21.1 mW + 4.35 mW + 19.25 mW + 1.30 mW + 47.47 mW + 1.38 mW + 0 + 0 +

0.63 mW + 3.30 mW + 3.00 mW

P_DYN= 143.06 mW

Standby Mode

P_DYN= P_XTL-OSC

P_DYN= 0.63 mW

Sleep Mode

P_DYN= 0 W

3-30

Revision 4

Fusion Family of Mixed Signal FPGAs

Total Static Power Consumption—P

STAT

Number of Quads used: N_QUADS= 4

Number of NVM blocks available (AFS600): N_NVM-BLOCKS= 2

Number of input pins used: N_INPUTS= 30

Number of output pins used: N_OUTPUTS= 40

Operating Mode

P_STAT= PDC1 + (N_NVM-BLOCKS* PDC4) + PDC5 + (N_QUADS* PDC6) + (N_INPUTS* PDC7) +

(N_OUTPUTS* PDC8)

P_STAT= 7.50 mW + (2 * 1.19 mW) + 8.25 mW + (4 * 3.30 mW) + (30 * 0.00) + (40 * 0.00)

P_STAT= 31.33 mW

Standby Mode

P_STAT= PDC2

P_STAT= 0.03 mW

Sleep Mode

P_STAT= PDC3

P_STAT= 0.03 mW

Total Power Consumption—P

TOTAL

In operating mode, the total power consumption of the device is 174.39 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 143.06 mW + 31.33 mW

P_TOTAL= 174.39 mW

In standby mode, the total power consumption of the device is limited to 0.66 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 0.03 mW + 0.63 mW

P_TOTAL= 0.66 mW

In sleep mode, the total power consumption of the device drops as low as 0.03 mW:

P_TOTAL= P_STAT+ P_DYN

P_TOTAL= 0.03 mW

Revision 4

3-31

DC and Power Characteristics

Power Consumption

Table 3-18 • Power Consumption

Parameter

Description

Condition

Min.

Typical

Max.

Units

Crystal Oscillator

ISTBXTAL

Standby Current of Crystal

Oscillator

10

µA

IDYNXTAL

Operating Current

RC

0.6

0.19

0.6

mA

0.032–0.2

0.2–2.0

2.0–20.0

0.6

RC Oscillator

IDYNRC

ACM

Operating Current

1

mA

Operating

clock)

Current

(fixed

(user

200

30

µA/MHz

µA

Operating

clock)

NVM System

NVM Array Operating Power

Idle

795

µA

Read

See

operation

Table 3-15 on

page 3-23.

Table 3-15 on

page 3-23.

Erase

Write

900

20

µA

PNVMCTRL

NVM Controller Operating

Power

µW/MHz

3-32

Revision 4

4 – Package Pin Assignments

QN108

A44

B41

A56

B52

Pin A1 Mark

A43

B40

A1

B1

B13

A14

B27

A29

B26

A28

B14

A15

Note: The die attach paddle center of the package is tied to ground (GND).

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-1

Package Pin Assignments

QN108

Pin Number AFS090 Function

A1

A2

NC

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

B1

GND

GCB1/IO35PDB1V0

GCB2/IO33PDB1V0

GBA2/IO31PDB1V0

NC

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

AC2

ATRTN1

AG3

GNDQ

A3

GAA2/IO52PDB3V0

A4

GND

AV3

A5

GFA1/IO47PDB3V0

VCC33A

VAREF

PUB

A6

GEB1/IO45PDB3V0

GBA1/IO30RSB0V0

GBB1/IO28RSB0V0

GND

A7

VCCOSC

A8

XTAL2

VCC33A

PTBASE

VCCNVM

VCC

A9

GEA1/IO44PPB3V0

VCC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

GEA0/IO44NPB3V0

GBC1/IO26RSB0V0

IO21RSB0V0

IO19RSB0V0

IO09RSB0V0

GAC0/IO04RSB0V0

VCCIB0

GEB2/IO42PDB3V0

VCCNVM

VCC15A

PCAP

TDI

TDO

VJTAG

NC

GDC0/IO38NDB1V

0

GNDA

GND

B36

B37

B38

VCCIB1

AV0

GAB0/IO02RSB0V0

GAA0/IO00RSB0V0

VCOMPLA

GCB0/IO35NDB1V0

AG0

GCC2/IO33NDB1V

0

ATRTN0

AT1

B2

VCCIB3

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

GBB2/IO31NDB1V0

VCCIB1

AC1

B3

GAB2/IO52NDB3V0

VCCIB3

AV2

B4

GNDQ

AG2

B5

GFA0/IO47NDB3V0

GEB0/IO45NDB3V0

XTAL1

GBA0/IO29RSB0V0

VCCIB0

AT2

B6

AT3

B7

GBB0/IO27RSB0V0

GBC0/IO25RSB0V0

IO20RSB0V0

IO10RSB0V0

GAC1/IO05RSB0V0

GAB1/IO03RSB0V0

VCC

AC3

B8

GNDOSC

GNDAQ

ADCGNDREF

NC

B9

GEC2/IO43PSB3V0

GEA2/IO42NDB3V0

VCC

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

GNDA

GNDNVM

PTEM

NCAP

GNDNVM

VPUMP

TCK

VCC33PMP

VCC33N

GAA1/IO01RSB0V0

VCCPLA

GNDAQ

TMS

AC0

TRST

AT0

GDB1/IO39PSB1V0

GDC1/IO38PDB1V0

AG1

AV1

4-2

Revision 4

Fusion Family of Mixed Signal FPGAs

QN180

A64

B60

A49

B46

C43

C56

Pin A1 Mark

D1

D4

A48

A1

B45

C42

B1

C1

C29

B31

C14

B15

A16

A33

D3

D2

Optional Corner

Pad (4X)

C15

B16

A17

C28

B30

A32

Note: The die attach paddle center of the package is tied to ground (GND).

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-3

Package Pin Assignments

QN180

Pin Number AFS090 Function

QN180

AFS250 Function

GNDQ

Pin Number AFS090 Function

AFS250 Function

VPUMP

TDI

A1

A2

GNDQ

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

B1

VPUMP

TDI

VCCIB3

A3

GAB2/IO52NDB3V0

GFA2/IO51NDB3V0

GFC2/IO50NDB3V0

VCCIB3

IO74NDB3V0

IO71NDB3V0

IO69NPB3V0

VCCIB3

TDO

A4

VJTAG

A5

GDB1/IO39PPB1V0 GDA1/IO54PPB1V0

GDC1/IO38PDB1V0 GDB1/IO53PDB1V0

A6

A7

GFA1/IO47PPB3V0 GFB1/IO67PPB3V0

VCC

A8

GEB0/IO45NDB3V0

XTAL1

NC

GCB0/IO35NPB1V0 GCB0/IO48NPB1V0

GCC1/IO34PDB1V0 GCC1/IO47PDB1V0

A9

XTAL1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

GNDOSC

VCCIB1

GEC2/IO43PPB3V0 GEA1/IO61PPB3V0

GBC2/IO32PPB1V0 GBB2/IO41PPB1V0

IO43NPB3V0

NC

GEA0/IO61NPB3V0

VCCIB3

GNDNVM

PCAP

VCCIB1

NC

VCCIB1

NC

GNDNVM

PCAP

VCC33PMP

NC

GBA0/IO29RSB0V0 GBB1/IO37RSB0V0

VCCIB0 VCCIB0

GBB0/IO27RSB0V0 GBC0/IO34RSB0V0

VCC33PMP

NC

GBC1/IO26RSB0V0

IO24RSB0V0

IO21RSB0V0

VCCIB0

IO33RSB0V0

IO29RSB0V0

IO26RSB0V0

VCCIB0

AV0

AG0

ATRTN0

AG1

ATRTN0

AG1

IO15RSB0V0

IO10RSB0V0

IO07RSB0V0

GAC0/IO04RSB0V0

IO21RSB0V0

IO13RSB0V0

IO10RSB0V0

IO06RSB0V0

AC1

AV2

AT2

AT3

GAB1/IO03RSB0V0 GAC1/IO05RSB0V0

VCC VCC

GAA1/IO01RSB0V0 GAB0/IO02RSB0V0

AC3

AV4

AC4

NC

AT4

VCOMPLA

NC

AG5

B2

GAA2/IO52PDB3V0 GAC2/IO74PDB3V0

GAC2/IO51PDB3V0 GFA2/IO71PDB3V0

GFB2/IO50PDB3V0 GFB2/IO70PSB3V0

NC

AV5

B3

ADCGNDREF

VCC33A

GNDA

PTBASE

VCCNVM

ADCGNDREF

VCC33A

GNDA

PTBASE

VCCNVM

B4

B5

VCC

B6

GFC0/IO49NDB3V0 GFC0/IO68NDB3V0

B7

GEB1/IO45PDB3V0

VCCOSC

NC

B8

VCCOSC

4-4

Revision 4

Fusion Family of Mixed Signal FPGAs

QN180

Pin Number AFS090 Function

AFS250 Function

Pin Number AFS090 Function

AFS250 Function

B9

XTAL2

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

C1

GBA2/IO31PDB1V0 GBA2/IO40PDB1V0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

GEA0/IO44NDB3V0 GFA0/IO66NDB3V0

GNDQ

GEB2/IO42PDB3V0

VCC

IO60NDB3V0

VCC

GBA1/IO30RSB0V0 GBA0/IO38RSB0V0

GBB1/IO28RSB0V0 GBC1/IO35RSB0V0

VCCNVM

VCC15A

NCAP

VCC33N

GNDAQ

AC0

VCCNVM

VCC15A

NCAP

VCC33N

GNDAQ

AC0

VCC

GBC0/IO25RSB0V0

IO23RSB0V0

IO20RSB0V0

VCC

IO31RSB0V0

IO28RSB0V0

IO25RSB0V0

VCC

IO11RSB0V0

IO08RSB0V0

GAC1/IO05RSB0V0

VCCIB0

IO14RSB0V0

IO11RSB0V0

IO08RSB0V0

VCCIB0

AT0

AT1

AV1

AC2

GAB0/IO02RSB0V0 GAC0/IO04RSB0V0

GAA0/IO00RSB0V0 GAA1/IO01RSB0V0

ATRTN1

AG3

ATRTN1

AG3

VCCPLA

NC

VCCPLA

NC

AV3

AG4

C2

NC

VCCIB3

ATRTN2

NC

ATRTN2

AC5

C3

GND

NC

GND

C4

GFC2/IO69PPB3V0

VCC33A

VAREF

PUB

VCC33A

VAREF

PUB

C5

GFC1/IO49PDB3V0 GFC1/IO68PDB3V0

GFA0/IO47NPB3V0 GFB0/IO67NPB3V0

C6

C7

VCCIB3

GND

NC

PTEM

GNDNVM

VCC

PTEM

GNDNVM

VCC

C8

GND

C9

GEA1/IO44PDB3V0 GFA1/IO66PDB3V0

GEA2/IO42NDB3V0 GEC2/IO60PDB3V0

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

TCK

NC

GEA2/IO58PSB3V0

TMS

NC

GND

NC

TRST

GND

NC

GDB2/IO41PSB1V0 GDA2/IO55PSB1V0

GDC0/IO38NDB1V0 GDB0/IO53NDB1V0

NC

VCCIB1

GNDA

NC

GNDA

NC

GCA1/IO36PDB1V0 GCA1/IO49PDB1V0

GCC0/IO34NDB1V0 GCC0/IO47NDB1V0

GCB2/IO33PSB1V0 GBC2/IO42PSB1V0

NC

VCC

NC

Revision 4

4-5

Package Pin Assignments

QN180

Pin Number AFS090 Function

QN180

AFS250 Function

Pin Number AFS090 Function

AFS250 Function

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

C51

C52

C53

C54

C55

C56

AG2

NC

AG2

NC

D1

D2

D3

D4

NC

AT5

GNDAQ

NC

GNDAQ

NC

GND

NC

GND

NC

GND

GDB0/IO39NPB1V0 GDA0/IO54NPB1V0

GDA1/IO37NSB1V0 GDC0/IO52NSB1V0

GCA0/IO36NDB1V0 GCA0/IO49NDB1V0

GCB1/IO35PPB1V0 GCB1/IO48PPB1V0

GND

IO41NPB1V0

IO40NDB1V0

NC

GCA2/IO32NPB1V0

GBB2/IO31NDB1V0

NC

GBA1/IO39RSB0V0

GBB0/IO36RSB0V0

GND

NC

GND

NC

IO30RSB0V0

IO27RSB0V0

GND

IO22RSB0V0

GND

IO13RSB0V0

IO09RSB0V0

IO06RSB0V0

GND

IO16RSB0V0

IO12RSB0V0

IO09RSB0V0

GND

NC

GAB1/IO03RSB0V0

GAA0/IO00RSB0V0

NC

4-6

Revision 4

Fusion Family of Mixed Signal FPGAs

PQ208

208

1

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-7

Package Pin Assignments

PQ208

Number

AFS250 Function

VCCPLA

AFS600 Function

VCCPLA

Number

AFS250 Function

IO60NDB3V0

GND

AFS600 Function

GEB0/IO62NDB4V0

GEA1/IO61PDB4V0

GEA0/IO61NDB4V0

1

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

2

VCOMPLA

GNDQ

VCOMPLA

3

GAA2/IO85PDB4V0

IO85NDB4V0

VCCIB3

4

VCCIB3

GEB2/IO59PDB3V0 GEC2/IO60PDB4V0

5

GAA2/IO76PDB3V0 GAB2/IO84PDB4V0

IO76NDB3V0 IO84NDB4V0

GAB2/IO75PDB3V0 GAC2/IO83PDB4V0

IO59NDB3V0

GEA2/IO58PDB3V0

IO58NDB3V0

VCC

IO60NDB4V0

VCCIB4

GNDQ

VCC

6

7

8

IO75NDB3V0

NC

IO83NDB4V0

IO77PDB4V0

IO77NDB4V0

IO76PDB4V0

IO76NDB4V0

VCC

9

VCC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

NC

VCCNVM

GNDNVM

GND

VCCNVM

GNDNVM

GND

VCC

GND

VCCIB3

IO72PDB3V0

IO72NDB3V0

VCC15A

PCAP

NCAP

VCC33PMP

VCC33N

GNDA

GNDAQ

NC

VCC15A

PCAP

NCAP

VCC33PMP

VCC33N

GNDA

GNDAQ

AV0

GND

VCCIB4

GFA2/IO71PDB3V0 GFA2/IO75PDB4V0

IO71NDB3V0 IO75NDB4V0

GFB2/IO70PDB3V0 GFC2/IO73PDB4V0

IO70NDB3V0

GFC2/IO69PDB3V0

IO69NDB3V0

VCC

IO73NDB4V0

VCCOSC

XTAL1

NC

AC0

XTAL2

NC

AG0

GND

GNDOSC

NC

AT0

VCCIB3

GFC1/IO72PDB4V0

NC

ATRTN0

AT1

GFC1/IO68PDB3V0 GFC0/IO72NDB4V0

GFC0/IO68NDB3V0 GFB1/IO71PDB4V0

GFB1/IO67PDB3V0 GFB0/IO71NDB4V0

GFB0/IO67NDB3V0 GFA1/IO70PDB4V0

NC

AG1

NC

AC1

NC

AV1

VCCOSC

XTAL1

GFA0/IO70NDB4V0

IO69PDB4V0

IO69NDB4V0

VCC

AV0

AV2

AC0

AC2

XTAL2

AG0

AG2

GNDOSC

AT0

AT2

GEB1/IO62PDB3V0

GEB0/IO62NDB3V0

GND

ATRTN0

AT1

ATRTN1

AT3

VCCIB4

GEA1/IO61PDB3V0 GEC1/IO63PDB4V0

GEA0/IO61NDB3V0 GEC0/IO63NDB4V0

GEC2/IO60PDB3V0 GEB1/IO62PDB4V0

AG1

AG3

AC1

AC3

AV1

AV3

4-8

Revision 4

Fusion Family of Mixed Signal FPGAs

PQ208

Number

AFS250 Function

AV2

AFS600 Function

AV4

Number

AFS250 Function

VCCNVM

AFS600 Function

VCCNVM

VCC

74

75

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

AC2

AC4

VCC

76

AG2

AG4

VCC

77

AT2

AT4

VPUMP

78

ATRTN1

AT3

ATRTN2

AT5

GNDQ

NC

79

VCCIB1

TCK

80

AG3

AG5

TCK

TDI

81

AC3

AC5

TDI

TMS

82

AV3

AV5

TMS

TDO

83

AV4

AV6

TDO

TRST

84

AC4

AC6

TRST

VJTAG

85

AG4

AG6

VJTAG

IO57NDB2V0

GDC2/IO57PDB2V0

IO56NDB2V0

GDB2/IO56PDB2V0

IO55NDB2V0

GDA2/IO55PDB2V0

GDA0/IO54NDB2V0

GDA1/IO54PDB2V0

VCCIB2

86

AT4

AT6

IO57NDB1V0

GDC2/IO57PDB1V0

IO56NDB1V0

GDB2/IO56PDB1V0

VCCIB1

87

ATRTN2

AT5

ATRTN3

AT7

88

89

AG5

AG7

90

AC5

AC7

91

AV5

AV7

GND

92

NC

AV8

IO55NDB1V0

GDA2/IO55PDB1V0

GDA0/IO54NDB1V0

GDA1/IO54PDB1V0

93

NC

AC8

94

NC

AG8

GND

95

NC

AT8

VCC

96

NC

ATRTN4

AT9

GDB0/IO53NDB1V0 GCA0/IO45NDB2V0

GDB1/IO53PDB1V0 GCA1/IO45PDB2V0

GDC0/IO52NDB1V0 GCB0/IO44NDB2V0

GDC1/IO52PDB1V0 GCB1/IO44PDB2V0

97

NC

98

NC

AG9

99

NC

AC9

100

101

102

103

104

105

106

107

108

109

110

NC

AV9

IO51NSB1V0

GCC0/IO43NDB2V

0

GNDAQ

VCC33A

ADCGNDREF

VAREF

PUB

GNDAQ

VCC33A

ADCGNDREF

VAREF

PUB

137

138

139

140

141

142

143

144

145

146

VCCIB1

GND

GCC1/IO43PDB2V0

IO42NDB2V0

IO42PDB2V0

IO41NDB2V0

GCC2/IO41PDB2V0

VCCIB2

VCC

IO50NDB1V0

IO50PDB1V0

GCA0/IO49NDB1V0

GCA1/IO49PDB1V0

GCB0/IO48NDB1V0

GCB1/IO48PDB1V0

VCC33A

GNDA

PTEM

PTBASE

GNDNVM

VCC33A

GNDA

PTEM

PTBASE

GNDNVM

GND

VCC

IO40NDB2V0

GCC0/IO47NDB1V0 GCB2/IO40PDB2V0

Revision 4

4-9

Package Pin Assignments

PQ208

Number

AFS250 Function

GCC1/IO47PDB1V0

IO42NDB1V0

AFS600 Function

IO39NDB2V0

GCA2/IO39PDB2V0

IO31NDB2V0

GBB2/IO31PDB2V0

IO30NDB2V0

GBA2/IO30PDB2V0

VCCIB2

Number

AFS250 Function

IO18RSB0V0

IO17RSB0V0

IO16RSB0V0

IO15RSB0V0

VCCIB0

AFS600 Function

IO10PPB0V1

IO09PPB0V1

IO10NPB0V1

IO09NPB0V1

IO08PPB0V1

IO07PPB0V1

IO08NPB0V1

IO07NPB0V1

IO06PPB0V0

IO05PPB0V0

IO06NPB0V0

IO04PPB0V0

IO05NPB0V0

IO04NPB0V0

GAC1/IO03PDB0V0

GAC0/IO03NDB0V0

VCCIB0

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

GBC2/IO42PDB1V0

VCCIB1

GND

VCC

GND

IO41NDB1V0

VCC

GBB2/IO41PDB1V0

IO40NDB1V0

GNDQ

IO14RSB0V0

IO13RSB0V0

IO12RSB0V0

IO11RSB0V0

IO10RSB0V0

IO09RSB0V0

IO08RSB0V0

IO07RSB0V0

IO06RSB0V0

GAC1/IO05RSB0V0

VCCIB0

VCOMPLB

GBA2/IO40PDB1V0

GBA1/IO39RSB0V0

GBA0/IO38RSB0V0

VCCPLB

VCCIB1

GNDQ

GBB1/IO37RSB0V0 GBB1/IO27PPB1V1

GBB0/IO36RSB0V0 GBA1/IO28PPB1V1

GBC1/IO35RSB0V0 GBB0/IO27NPB1V1

VCCIB0

GND

GBA0/IO28NPB1V1

VCCIB1

VCC

GND

GBC0/IO34RSB0V0

IO33RSB0V0

IO32RSB0V0

IO31RSB0V0

IO30RSB0V0

IO29RSB0V0

IO28RSB0V0

IO27RSB0V0

IO26RSB0V0

IO25RSB0V0

VCCIB0

VCC

GND

VCC

GBC1/IO26PDB1V1

GBC0/IO26NDB1V1

IO24PPB1V1

IO23PPB1V1

IO24NPB1V1

IO23NPB1V1

IO22PPB1V0

IO21PPB1V0

IO22NPB1V0

IO21NPB1V0

IO20PSB1V0

IO19PSB1V0

IO14NSB0V1

IO12PDB0V1

IO12NDB0V1

VCCIB0

VCC

GAB1/IO02PDB0V0

GAC0/IO04RSB0V0 GAB0/IO02NDB0V0

GAB1/IO03RSB0V0 GAA1/IO01PDB0V0

GAB0/IO02RSB0V0 GAA0/IO01NDB0V0

GAA1/IO01RSB0V0

GAA0/IO00RSB0V0

GNDQ

VCCIB0

GND

VCC

IO24RSB0V0

IO23RSB0V0

IO22RSB0V0

IO21RSB0V0

IO20RSB0V0

IO19RSB0V0

GND

VCC

4-10

Revision 4

Fusion Family of Mixed Signal FPGAs

FG256

A1 Ball Pad Corner

1

7

6

4

5

3

2

16 15 14 13 12 11 10 9

8

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-11

Package Pin Assignments

FG256

AFS250 Function

GND

Pin Number

A1

AFS090 Function

AFS600 Function

GND

AFS1500 Function

GND

VCCIB0

A2

VCCIB0

A3

GAB0/IO02RSB0V0

GAB1/IO03RSB0V0

GND

GAA0/IO00RSB0V0

GAA1/IO01RSB0V0

GND

GAA0/IO01NDB0V0

GAA1/IO01PDB0V0

GND

GAA0/IO01NDB0V0

GAA1/IO01PDB0V0

GND

A4

A5

A6

IO07RSB0V0

IO10RSB0V0

IO11RSB0V0

IO16RSB0V0

IO17RSB0V0

IO18RSB0V0

GND

IO11RSB0V0

IO14RSB0V0

IO15RSB0V0

IO24RSB0V0

IO25RSB0V0

IO26RSB0V0

GND

IO10PDB0V1

IO12PDB0V1

IO12NDB0V1

IO22NDB1V0

IO22PDB1V0

IO24NDB1V1

GND

IO07PDB0V1

IO13PDB0V2

IO13NDB0V2

IO24NDB1V0

IO24PDB1V0

IO29NDB1V1

GND

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

B1

GBC0/IO25RSB0V0

GBA0/IO29RSB0V0

VCCIB0

GBA0/IO38RSB0V0

IO32RSB0V0

VCCIB0

GBA0/IO28NDB1V1

IO29NDB1V1

VCCIB1

GBA0/IO42NDB1V2

IO43NDB1V2

VCCIB1

GND

VCOMPLA

VCCPLA

VCOMPLA

VCCPLA

VCOMPLA

B2

VCCPLA

B3

GAA0/IO00RSB0V0

GAA1/IO01RSB0V0

NC

IO07RSB0V0

IO06RSB0V0

GAB1/IO03RSB0V0

IO10RSB0V0

VCCIB0

IO00NDB0V0

IO00PDB0V0

GAB1/IO02PPB0V0

IO10NDB0V1

VCCIB0

IO00NDB0V0

IO00PDB0V0

GAB1/IO02PPB0V0

IO07NDB0V1

VCCIB0

B4

B5

B6

IO06RSB0V0

VCCIB0

B7

B8

IO12RSB0V0

IO13RSB0V0

VCCIB0

IO16RSB0V0

IO17RSB0V0

VCCIB0

IO18NDB1V0

IO18PDB1V0

VCCIB1

IO22NDB1V0

IO22PDB1V0

VCCIB1

B9

B10

B11

B12

B13

B14

B15

B16

C1

IO19RSB0V0

GBB0/IO27RSB0V0

GBC1/IO26RSB0V0

GBA1/IO30RSB0V0

NC

IO27RSB0V0

GBC0/IO34RSB0V0

GBA1/IO39RSB0V0

IO33RSB0V0

NC

IO24PDB1V1

GBC0/IO26NPB1V1

GBA1/IO28PDB1V1

IO29PDB1V1

VCCPLB

IO29PDB1V1

GBC0/IO40NPB1V2

GBA1/IO42PDB1V2

IO43PDB1V2

VCCPLB

NC

VCOMPLB

VCCIB3

VCCIB4

C2

GND

C3

VCCIB3

VCCIB4

C4

NC

VCCIB0

C5

VCCIB0

C6

GAC1/IO05RSB0V0

GAC1/IO03PDB0V0

4-12

Revision 4

Fusion Family of Mixed Signal FPGAs

FG256

AFS250 Function

IO12RSB0V0

IO22RSB0V0

IO23RSB0V0

IO30RSB0V0

IO31RSB0V0

VCCIB0

Pin Number

C7

AFS090 Function

IO09RSB0V0

IO14RSB0V0

IO15RSB0V0

IO22RSB0V0

IO20RSB0V0

VCCIB0

AFS600 Function

AFS1500 Function

IO09NDB0V1

IO23PDB1V0

IO23NDB1V0

IO31NDB1V1

IO31PDB1V1

VCCIB1

IO06NDB0V0

IO16PDB1V0

IO16NDB1V0

IO25NDB1V1

IO25PDB1V1

VCCIB1

C8

C9

C10

C11

C12

C13

C14

C15

C16

D1

GBB1/IO28RSB0V0

VCCIB1

GBC1/IO35RSB0V0

VCCIB1

GBC1/IO26PPB1V1

VCCIB2

GBC1/IO40PPB1V2

VCCIB2

GND

VCCIB1

VCCIB2

GFC2/IO50NPB3V0

GFA2/IO51NDB3V0

GAC2/IO51PDB3V0

GAA2/IO52PDB3V0

GAB2/IO52NDB3V0

GAC0/IO04RSB0V0

IO08RSB0V0

NC

IO75NDB3V0

GAB2/IO75PDB3V0

IO76NDB3V0

GAA2/IO76PDB3V0

GAB0/IO02RSB0V0

GAC0/IO04RSB0V0

IO13RSB0V0

IO20RSB0V0

IO21RSB0V0

IO28RSB0V0

GBB0/IO36RSB0V0

NC

IO84NDB4V0

GAB2/IO84PDB4V0

IO85NDB4V0

GAA2/IO85PDB4V0

GAB0/IO02NPB0V0

GAC0/IO03NDB0V0

IO06PDB0V0

IO14NDB0V1

IO14PDB0V1

IO23PDB1V1

GBB0/IO27NDB1V1

VCCIB1

IO124NDB4V0

GAB2/IO124PDB4V0

IO125NDB4V0

GAA2/IO125PDB4V0

GAB0/IO02NPB0V0

GAC0/IO03NDB0V0

IO09PDB0V1

IO15NDB0V2

IO15PDB0V2

IO37PDB1V2

GBB0/IO41NDB1V2

VCCIB1

D2

D3

D4

D5

D6

D7

D8

D9

NC

D10

D11

D12

D13

D14

D15

D16

E1

IO21RSB0V0

IO23RSB0V0

NC

GBA2/IO31PDB1V0

GBB2/IO31NDB1V0

GBC2/IO32PDB1V0

GCA2/IO32NDB1V0

GND

GBA2/IO40PDB1V0

IO40NDB1V0

GBB2/IO41PDB1V0

IO41NDB1V0

GND

GBA2/IO30PDB2V0

IO30NDB2V0

GBB2/IO31PDB2V0

IO31NDB2V0

GND

GBA2/IO44PDB2V0

IO44NDB2V0

GBB2/IO45PDB2V0

IO45NDB2V0

GND

E2

GFB0/IO48NPB3V0

GFB2/IO50PPB3V0

VCCIB3

IO73NDB3V0

IO73PDB3V0

VCCIB3

IO81NDB4V0

IO81PDB4V0

VCCIB4

IO118NDB4V0

IO118PDB4V0

VCCIB4

E3

E4

E5

NC

IO74NPB3V0

IO08RSB0V0

GND

IO83NPB4V0

IO04NPB0V0

GND

IO123NPB4V0

IO05NPB0V1

GND

E6

NC

E7

GND

E8

NC

IO18RSB0V0

NC

IO08PDB0V1

IO20NDB1V0

GND

IO11PDB0V1

IO27NDB1V1

GND

E9

NC

E10

E11

E12

GND

IO24RSB0V0

NC

GBB1/IO37RSB0V0

IO50PPB1V0

GBB1/IO27PDB1V1

IO33PSB2V0

GBB1/IO41PDB1V2

IO48PSB2V0

Revision 4

4-13

Package Pin Assignments

FG256

AFS250 Function

VCCIB1

Pin Number

E13

E14

E15

E16

F1

AFS090 Function

AFS600 Function

VCCIB2

AFS1500 Function

VCCIB2

VCCIB1

GCC2/IO33NDB1V0

IO42NDB1V0

GBC2/IO42PDB1V0

GND

IO32NDB2V0

GBC2/IO32PDB2V0

GND

IO46NDB2V0

GBC2/IO46PDB2V0

GND

GCB2/IO33PDB1V0

GND

NC

IO79NDB4V0

IO79PDB4V0

IO76NDB4V0

IO76PDB4V0

IO82PSB4V0

GAC2/IO83PPB4V0

IO04PPB0V0

IO08NDB0V1

IO20PDB1V0

IO23NDB1V1

IO36NDB2V0

IO36PDB2V0

IO39NDB2V0

GCA2/IO39PDB2V0

GCB2/IO40PDB2V0

IO40NDB2V0

IO74NPB4V0

VCCIB4

IO111NDB4V0

IO111PDB4V0

IO112NDB4V0

IO112PDB4V0

IO120PSB4V0

GAC2/IO123PPB4V0

IO05PPB0V1

IO11NDB0V1

IO27PDB1V1

IO37NDB1V2

IO50NDB2V0

IO50PDB2V0

IO59NDB2V0

GCA2/IO59PDB2V0

GCB2/IO60PDB2V0

IO60NDB2V0

IO109NPB4V0

VCCIB4

F2

NC

F3

GFB1/IO48PPB3V0

IO72NDB3V0

IO72PDB3V0

NC

F4

GFC0/IO49NDB3V0

F5

NC

F6

GFC1/IO49PDB3V0

GAC2/IO74PPB3V0

IO09RSB0V0

IO19RSB0V0

NC

F7

NC

F8

NC

F9

F10

F11

F12

F13

F14

F15

F16

G1

NC

IO29RSB0V0

IO43NDB1V0

IO43PDB1V0

IO44NDB1V0

GCA2/IO44PDB1V0

GCB2/IO45PDB1V0

IO45NDB1V0

IO70NPB3V0

VCCIB3

NC

GCC1/IO34PDB1V0

GCC0/IO34NDB1V0

GEC0/IO46NPB3V0

VCCIB3

G2

G3

GEC1/IO46PPB3V0

GFA1/IO47PDB3V0

GND

GFB2/IO70PPB3V0

GFA2/IO71PDB3V0

GND

GFB2/IO74PPB4V0

GFA2/IO75PDB4V0

GND

GFB2/IO109PPB4V0

GFA2/IO110PDB4V0

GND

G4

G5

G6

GFA0/IO47NDB3V0

GND

IO71NDB3V0

GND

IO75NDB4V0

GND

IO110NDB4V0

GND

G7

G8

VCC

G9

GND

G10

G11

G12

G13

G14

G15

G16

H1

VCC

GDA1/IO37NDB1V0

GND

GCC0/IO47NDB1V0

GND

GCC0/IO43NDB2V0

GND

GCC0/IO62NDB2V0

GND

IO37PDB1V0

GCB0/IO35NPB1V0

VCCIB1

GCC1/IO47PDB1V0

IO46NPB1V0

VCCIB1

GCC1/IO43PDB2V0

IO41NPB2V0

VCCIB2

GCC1/IO62PDB2V0

IO61NPB2V0

VCCIB2

GCB1/IO35PPB1V0

GEB1/IO45PDB3V0

GEB0/IO45NDB3V0

GCC2/IO46PPB1V0

GFC2/IO69PDB3V0

IO69NDB3V0

GCC2/IO41PPB2V0

GFC2/IO73PDB4V0

IO73NDB4V0

GCC2/IO61PPB2V0

GFC2/IO108PDB4V0

IO108NDB4V0

H2

4-14

Revision 4

Fusion Family of Mixed Signal FPGAs

FG256

AFS250 Function

XTAL2

Pin Number

H3

AFS090 Function

AFS600 Function

AFS1500 Function

XTAL2

XTAL1

H4

XTAL1

H5

GNDOSC

H6

VCCOSC

H7

VCC

H8

GND

H9

VCC

H10

H11

H12

H13

H14

H15

H16

J1

GND

GDC0/IO38NDB1V0

IO51NDB1V0

IO51PDB1V0

GCA1/IO49PDB1V0

GCA0/IO49NDB1V0

GCB0/IO48NDB1V0

GCB1/IO48PDB1V0

GFA0/IO66NDB3V0

GFA1/IO66PDB3V0

GFB0/IO67NDB3V0

GFB1/IO67PDB3V0

GFC0/IO68NDB3V0

GFC1/IO68PDB3V0

GND

IO47NDB2V0

IO47PDB2V0

GCA1/IO45PDB2V0

GCA0/IO45NDB2V0

GCB0/IO44NDB2V0

GCB1/IO44PDB2V0

GFA0/IO70NDB4V0

GFA1/IO70PDB4V0

GFB0/IO71NDB4V0

GFB1/IO71PDB4V0

GFC0/IO72NDB4V0

GFC1/IO72PDB4V0

GND

IO69NDB2V0

IO69PDB2V0

GCA1/IO64PDB2V0

GCA0/IO64NDB2V0

GCB0/IO63NDB2V0

GCB1/IO63PDB2V0

GFA0/IO105NDB4V0

GFA1/IO105PDB4V0

GFB0/IO106NDB4V0

GFB1/IO106PDB4V0

GFC0/IO107NDB4V0

GFC1/IO107PDB4V0

GND

GDC1/IO38PDB1V0

GDB1/IO39PDB1V0

GDB0/IO39NDB1V0

GCA0/IO36NDB1V0

GCA1/IO36PDB1V0

GEA0/IO44NDB3V0

J2

GEA1/IO44PDB3V0

J3

IO43NDB3V0

J4

GEC2/IO43PDB3V0

J5

NC

J6

NC

J7

GND

J8

VCC

J9

GND

J10

J11

J12

J13

J14

J15

J16

K1

VCC

GDC2/IO41NPB1V0

IO56NPB1V0

GDB0/IO53NPB1V0

GDA1/IO54PDB1V0

GDC1/IO52PPB1V0

IO50NPB1V0

GDC0/IO52NPB1V0

IO65NPB3V0

VCCIB3

IO56NPB2V0

GDB0/IO53NPB2V0

GDA1/IO54PDB2V0

GDC1/IO52PPB2V0

IO51NSB2V0

GDC0/IO52NPB2V0

IO67NPB4V0

VCCIB4

IO83NPB2V0

GDB0/IO80NPB2V0

GDA1/IO81PDB2V0

GDC1/IO79PPB2V0

IO77NSB2V0

GDC0/IO79NPB2V0

IO92NPB4V0

VCCIB4

NC

GDA0/IO40PDB1V0

NC

GDA2/IO40NDB1V0

NC

VCCIB3

NC

K2

K3

IO65PPB3V0

IO64PDB3V0

GND

IO67PPB4V0

IO65PDB4V0

GND

IO92PPB4V0

IO96PDB4V0

GND

K4

NC

K5

GND

NC

K6

IO64NDB3V0

VCC

IO65NDB4V0

VCC

IO96NDB4V0

VCC

K7

VCC

GND

K8

GND

Revision 4

4-15

Package Pin Assignments

FG256

AFS250 Function

VCC

Pin Number

K9

AFS090 Function

AFS600 Function

VCC

AFS1500 Function

VCC

GND

NC

K10

K11

K12

K13

K14

K15

K16

L1

GND

GDC2/IO57PPB1V0

GND

GDC2/IO57PPB2V0

GND

GDC2/IO84PPB2V0

GND

NC

GDA0/IO54NDB1V0

GDA2/IO55PPB1V0

VCCIB1

GDA0/IO54NDB2V0

GDA2/IO55PPB2V0

VCCIB2

GDA0/IO81NDB2V0

GDA2/IO82PPB2V0

VCCIB2

NC

VCCIB1

NC

GDB1/IO53PPB1V0

GEC1/IO63PDB3V0

GEC0/IO63NDB3V0

GEB1/IO62PDB3V0

GEB0/IO62NDB3V0

IO60NDB3V0

GEC2/IO60PDB3V0

GNDA

GDB1/IO53PPB2V0

GEC1/IO63PDB4V0

GEC0/IO63NDB4V0

GEB1/IO62PDB4V0

GEB0/IO62NDB4V0

IO60NDB4V0

GEC2/IO60PDB4V0

GNDA

GDB1/IO80PPB2V0

GEC1/IO90PDB4V0

GEC0/IO90NDB4V0

GEB1/IO89PDB4V0

GEB0/IO89NDB4V0

IO87NDB4V0

GEC2/IO87PDB4V0

GNDA

NC

L2

NC

L3

NC

L4

NC

L5

NC

L6

NC

L7

GNDA

AC0

L8

AC0

AC2

L9

AV2

AV4

L10

L11

L12

L13

L14

L15

L16

M1

AC3

AC5

PTEM

TDO

VJTAG

NC

PTEM

TDO

VJTAG

IO57NPB1V0

GDB2/IO56PPB1V0

IO55NPB1V0

GND

IO57NPB2V0

GDB2/IO56PPB2V0

IO55NPB2V0

GND

IO84NPB2V0

GDB2/IO83PPB2V0

IO82NPB2V0

GND

GDB2/IO41PPB1V0

NC

GND

NC

M2

GEA1/IO61PDB3V0

GEA0/IO61NDB3V0

VCCIB3

GEA1/IO61PDB4V0

GEA0/IO61NDB4V0

VCCIB4

GEA1/IO88PDB4V0

GEA0/IO88NDB4V0

VCCIB4

M3

NC

M4

VCCIB3

NC

M5

IO58NPB3V0

NC

IO58NPB4V0

AV0

IO85NPB4V0

AV0

M6

NC

M7

NC

AC1

M8

AG1

AG3

M9

AC2

AC4

M10

M11

M12

M13

M14

AC4

AC6

NC

AG5

AG7

VPUMP

VCCIB1

TMS

VPUMP

VCCIB1

VCCIB2

TMS

4-16

Revision 4

Fusion Family of Mixed Signal FPGAs

FG256

Pin Number

M15

M16

N1

AFS090 Function

AFS250 Function

AFS600 Function

AFS1500 Function

TRST

GND

TRST

GND

TRST

GND

GEB2/IO42PDB3V0

GEA2/IO42NDB3V0

NC

GEB2/IO59PDB3V0

IO59NDB3V0

GEA2/IO58PPB3V0

VCC33PMP

VCC15A

NC

GEB2/IO59PDB4V0

IO59NDB4V0

GEA2/IO58PPB4V0

VCC33PMP

VCC15A

AG0

GEB2/IO86PDB4V0

IO86NDB4V0

GEA2/IO85PPB4V0

VCC33PMP

VCC15A

AG0

N2

N3

N4

VCC33PMP

VCC15A

NC

N5

N6

N7

AC1

AC3

N8

AG3

AG5

N9

AV3

AV5

N10

N11

N12

N13

N14

N15

N16

P1

AG4

AG6

NC

AC8

GNDA

VCC33A

VCCNVM

TCK

GNDA

VCC33A

VCCNVM

TCK

GNDA

VCC33A

VCCNVM

TCK

VCC33A

VCCNVM

TCK

TDI

VCCNVM

GNDNVM

GNDA

NC

VCCNVM

GNDNVM

GNDA

NC

VCCNVM

GNDNVM

GNDA

VCCNVM

GNDNVM

GNDA

P2

P3

P4

AC0

P5

NC

AG1

P6

NC

AV1

P7

AG0

AG2

P8

AG2

AG4

P9

GNDA

NC

GNDA

AC5

GNDA

P10

P11

P12

P13

P14

P15

P16

R1

AC7

NC

AV8

NC

AG8

NC

AV9

ADCGNDREF

PTBASE

GNDNVM

VCCIB3

PCAP

ADCGNDREF

PTBASE

GNDNVM

VCCIB3

PCAP

ADCGNDREF

PTBASE

GNDNVM

VCCIB4

PCAP

ADCGNDREF

PTBASE

GNDNVM

VCCIB4

PCAP

R2

R3

NC

AT1

R4

NC

AT0

Revision 4

4-17

Package Pin Assignments

FG256

AFS250 Function

AV0

Pin Number

R5

AFS090 Function

AFS600 Function

AV2

AFS1500 Function

AV2

AV0

AT0

R6

AT0

AT2

R7

AV1

AV3

R8

AT3

AT5

R9

AV4

AV6

R10

R11

R12

R13

R14

R15

R16

T1

NC

AT5

AT7

NC

AV5

AV7

NC

AT9

NC

AG9

NC

AC9

PUB

VCCIB1

GND

NCAP

VCC33N

NC

VCCIB1

GND

VCCIB2

GND

VCCIB2

GND

T2

NCAP

VCC33N

NC

NCAP

VCC33N

ATRTN0

AT3

NCAP

VCC33N

ATRTN0

AT3

T3

T4

T5

AT1

T6

ATRTN0

AT2

ATRTN0

AT2

ATRTN1

AT4

ATRTN1

AT4

T7

T8

ATRTN1

AT4

ATRTN1

AT4

ATRTN2

AT6

ATRTN2

AT6

T9

T10

T11

T12

T13

T14

T15

T16

ATRTN2

NC

ATRTN2

NC

ATRTN3

AT8

ATRTN3

AT8

NC

ATRTN4

GNDA

VCC33A

VAREF

GND

ATRTN4

GNDA

VCC33A

VAREF

GND

GNDA

VCC33A

VAREF

GND

GNDA

VCC33A

VAREF

GND

4-18

Revision 4

Fusion Family of Mixed Signal FPGAs

FG484

A1 Ball Pad Corner

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-19

Package Pin Assignments

FG484

Number

AFS600 Function

AFS1500 Function

Number

AFS600 Function

AG7

AFS1500 Function

AG7

A1

A2

GND

VCC

GND

NC

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB1

AG8

A3

GAA1/IO01PDB0V0 GAA1/IO01PDB0V0

GAB0/IO02NDB0V0 GAB0/IO02NDB0V0

GAB1/IO02PDB0V0 GAB1/IO02PDB0V0

GNDA

AG9

GNDA

AG9

A4

A5

VAREF

VCCIB2

PTEM

GND

VAREF

VCCIB2

PTEM

GND

A6

IO07NDB0V1

IO07PDB0V1

IO10PDB0V1

IO14NDB0V1

IO14PDB0V1

IO17PDB1V0

IO18PDB1V0

IO19NDB1V0

IO19PDB1V0

IO24NDB1V1

IO24PDB1V1

IO07NDB0V1

IO07PDB0V1

IO09PDB0V1

IO13NDB0V2

IO13PDB0V2

IO24PDB1V0

IO26PDB1V0

IO27NDB1V1

IO27PDB1V1

IO35NDB1V2

IO35PDB1V2

A7

A8

A9

VCC

NC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

GND

AB2

VCC

NC

AB3

NC

IO94NSB4V0

GND

AB4

GND

AB5

VCC33N

AT0

VCC33N

AT0

AB6

AB7

ATRTN0

AT1

ATRTN0

AT1

GBC0/IO26NDB1V1 GBC0/IO40NDB1V2

GBA0/IO28NDB1V1 GBA0/IO42NDB1V2

AB8

AB9

AT2

IO29NDB1V1

IO29PDB1V1

VCC

IO43NDB1V2

IO43PDB1V2

NC

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

B1

ATRTN1

AT3

ATRTN1

AT3

AT6

GND

ATRTN3

AT7

ATRTN3

AT7

VCC

NC

GND

AT8

VCCIB4

PCAP

AG0

VCCIB4

PCAP

AG0

ATRTN4

AT9

ATRTN4

AT9

VCC33A

GND

VCC33A

GND

GNDA

AG1

GNDA

AG1

NC

IO76NPB2V0

NC

VCC

AG2

GND

GNDA

AG3

GNDA

AG3

VCC

NC

B2

GND

AG6

B3

GAA0/IO01NDB0V0 GAA0/IO01NDB0V0

GND GND

GNDA

B4

4-20

Revision 4

Fusion Family of Mixed Signal FPGAs

FG484

Number

AFS600 Function

IO05NDB0V0

IO05PDB0V0

GND

AFS1500 Function

IO04NDB0V0

IO04PDB0V0

GND

Number

AFS600 Function

AFS1500 Function

VCCIB1

B5

B6

C18

C19

C20

C21

C22

D1

VCCIB1

VCOMPLB

B7

GBA2/IO30PDB2V0 GBA2/IO44PDB2V0

NC IO48PSB2V0

GBB2/IO31PDB2V0 GBB2/IO45PDB2V0

B8

IO10NDB0V1

IO13PDB0V1

GND

IO09NDB0V1

IO11PDB0V1

GND

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

C1

IO82NDB4V0

GND

IO121NDB4V0

GND

IO17NDB1V0

IO18NDB1V0

GND

IO24NDB1V0

IO26NDB1V0

GND

D2

D3

IO83NDB4V0

IO123NDB4V0

D4

GAC2/IO83PDB4V0 GAC2/IO123PDB4V0

GAA2/IO85PDB4V0 GAA2/IO125PDB4V0

GAC0/IO03NDB0V0 GAC0/IO03NDB0V0

GAC1/IO03PDB0V0 GAC1/IO03PDB0V0

IO21NDB1V0

IO21PDB1V0

GND

IO31NDB1V1

IO31PDB1V1

GND

D5

D6

D7

GBC1/IO26PDB1V1 GBC1/IO40PDB1V2

GBA1/IO28PDB1V1 GBA1/IO42PDB1V2

D8

IO09NDB0V1

IO09PDB0V1

IO11NDB0V1

IO16NDB1V0

IO16PDB1V0

NC

IO10NDB0V1

IO10PDB0V1

IO14NDB0V2

IO23NDB1V0

IO23PDB1V0

IO32NPB1V1

IO34NDB1V1

IO34PDB1V1

IO37PDB1V2

D9

GND

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E1

VCCPLB

GND

VCC

NC

IO82PDB4V0

NC

IO121PDB4V0

IO122PSB4V0

IO00NDB0V0

IO00PDB0V0

VCCIB0

IO23NDB1V1

IO23PDB1V1

IO25PDB1V1

C2

C3

IO00NDB0V0

IO00PDB0V0

VCCIB0

C4

GBB1/IO27PDB1V1 GBB1/IO41PDB1V2

C5

VCCIB2

NC

VCCIB2

IO47PPB2V0

IO44NDB2V0

GND

C6

IO06NDB0V0

IO06PDB0V0

VCCIB0

IO05NDB0V1

IO05PDB0V1

VCCIB0

C7

IO30NDB2V0

GND

C8

C9

IO13NDB0V1

IO11PDB0V1

VCCIB0

IO11NDB0V1

IO14PDB0V2

VCCIB0

IO31NDB2V0

IO81NDB4V0

IO81PDB4V0

VCCIB4

IO45NDB2V0

IO120NDB4V0

IO120PDB4V0

VCCIB4

C10

C11

C12

C13

C14

C15

C16

C17

E2

VCCIB1

E3

IO20NDB1V0

IO20PDB1V0

VCCIB1

IO29NDB1V1

IO29PDB1V1

VCCIB1

E4

GAB2/IO84PDB4V0 GAB2/IO124PDB4V0

E5

IO85NDB4V0

GND

IO125NDB4V0

GND

E6

IO25NDB1V1

IO37NDB1V2

E7

VCCIB0

NC

VCCIB0

GBB0/IO27NDB1V1 GBB0/IO41NDB1V2

E8

IO08NDB0V1

Revision 4

4-21

Package Pin Assignments

FG484

Number

AFS600 Function

NC

AFS1500 Function

IO08PDB0V1

GND

Number

AFS600 Function

IO35PDB2V0

IO77PDB4V0

GND

AFS1500 Function

IO51PDB2V0

IO115PDB4V0

GND

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

F1

F22

G1

GND

IO15NDB1V0

IO15PDB1V0

GND

IO22NDB1V0

IO22PDB1V0

GND

G2

G3

IO78NDB4V0

IO78PDB4V0

VCCIB4

IO116NDB4V0

IO116PDB4V0

VCCIB4

G4

NC

IO32PPB1V1

IO36NPB1V2

VCCIB1

G5

NC

G6

NC

IO117PDB4V0

VCCIB4

VCCIB1

GND

G7

VCCIB4

GND

G8

GND

NC

IO47NPB2V0

IO49PDB2V0

VCCIB2

G9

IO04NDB0V0

IO04PDB0V0

IO12NDB0V1

IO12PDB0V1

NC

IO06NDB0V1

IO06PDB0V1

IO16NDB0V2

IO16PDB0V2

IO28NDB1V1

IO28PDB1V1

GND

IO33PDB2V0

VCCIB2

IO32NDB2V0

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

H1

IO46NDB2V0

GBC2/IO32PDB2V0 GBC2/IO46PDB2V0

IO80NDB4V0

IO80PDB4V0

NC

IO118NDB4V0

IO118PDB4V0

IO119NSB4V0

IO124NDB4V0

GND

NC

F2

GND

F3

NC

IO38PPB1V2

IO53PDB2V0

VCCIB2

F4

IO84NDB4V0

GND

NC

F5

VCCIB2

F6

VCOMPLA

VCCPLA

VCOMPLA

VCCPLA

IO36PDB2V0

IO36NDB2V0

GND

IO52PDB2V0

IO52NDB2V0

GND

F7

F8

VCCIB0

F9

IO08NDB0V1

IO08PDB0V1

VCCIB0

IO12NDB0V1

IO12PDB0V1

VCCIB0

IO35NDB2V0

IO77NDB4V0

IO76PDB4V0

VCCIB4

IO51NDB2V0

IO115NDB4V0

IO113PDB4V0

VCCIB4

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

H2

VCCIB1

H3

IO22NDB1V0

IO22PDB1V0

VCCIB1

IO30NDB1V1

IO30PDB1V1

VCCIB1

H4

IO79NDB4V0

IO79PDB4V0

NC

IO114NDB4V0

IO114PDB4V0

IO117NDB4V0

GND

H5

H6

NC

IO36PPB1V2

IO38NPB1V2

GND

H7

GND

NC

H8

VCC

GND

H9

VCCIB0

IO33NDB2V0

IO34PDB2V0

IO34NDB2V0

IO49NDB2V0

IO50PDB2V0

IO50NDB2V0

H10

H11

H12

GND

VCCIB0

VCCIB1

4-22

Revision 4

Fusion Family of Mixed Signal FPGAs

FG484

Number

AFS600 Function

GND

AFS1500 Function

GND

Number

AFS600 Function

AFS1500 Function

IO110NDB4V0

GND

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

J1

K4

K5

IO75NDB4V0

GND

VCCIB1

GND

VCCIB1

GND

K6

NC

IO104NDB4V0

IO111NDB4V0

GND

K7

NC

IO53NDB2V0

IO57PDB2V0

K8

GND

IO38PDB2V0

K9

VCC

GCA2/IO39PDB2V0 GCA2/IO59PDB2V0

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

L1

GND

VCCIB2

IO37NDB2V0

IO37PDB2V0

NC

VCCIB2

VCC

IO54NDB2V0

IO54PDB2V0

IO112PPB4V0

IO113NDB4V0

GND

VCC

GND

J2

IO76NDB4V0

GND

J3

GFB2/IO74PDB4V0 GFB2/IO109PDB4V0

GFA2/IO75PDB4V0 GFA2/IO110PDB4V0

IO40NDB2V0

NC

IO60NDB2V0

IO58PDB2V0

GND

J4

J5

NC

IO112NPB4V0

IO104PDB4V0

IO111PDB4V0

VCCIB4

GND

J6

NC

IO68NPB2V0

IO61NDB2V0

GND

J7

NC

IO41NDB2V0

GND

J8

VCCIB4

GND

VCC

J9

IO42NDB2V0

IO73NDB4V0

VCCOSC

VCCIB4

XTAL2

IO56NDB2V0

IO108NDB4V0

VCCOSC

VCCIB4

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

K1

VCC

GND

VCC

GND

L2

VCC

L3

GND

VCC

GND

L4

XTAL2

VCC

L5

GFC1/IO72PDB4V0 GFC1/IO107PDB4V0

VCCIB4 VCCIB4

GFB1/IO71PDB4V0 GFB1/IO106PDB4V0

VCCIB2

L6

GCB2/IO40PDB2V0 GCB2/IO60PDB2V0

L7

NC

IO58NDB2V0

IO57NDB2V0

IO59NDB2V0

L8

VCCIB4

GND

VCCIB4

GND

IO38NDB2V0

IO39NDB2V0

L9

L10

L11

L12

L13

L14

L15

L16

VCC

GCC2/IO41PDB2V0 GCC2/IO61PDB2V0

GND

NC

IO55PSB2V0

IO56PDB2V0

VCC

IO42PDB2V0

GND

GFC2/IO73PDB4V0 GFC2/IO108PDB4V0

VCC

K2

GND

VCCIB2

IO48PDB2V0

VCCIB2

IO70PDB2V0

K3

IO74NDB4V0

IO109NDB4V0

Revision 4

4-23

Package Pin Assignments

FG484

Number

AFS600 Function

VCCIB2

AFS1500 Function

VCCIB2

Number

AFS600 Function

AFS1500 Function

L17

L18

L19

L20

L21

L22

M1

N8

N9

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

IO46PDB2V0

IO69PDB2V0

GCA1/IO45PDB2V0 GCA1/IO64PDB2V0

VCCIB2 VCCIB2

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

P1

GCC0/IO43NDB2V0 GCC0/IO62NDB2V0

GCC1/IO43PDB2V0 GCC1/IO62PDB2V0

NC

IO103PDB4V0

XTAL1

M2

XTAL1

M3

VCCIB4

GNDOSC

VCCIB4

GDB2/IO56PDB2V0 GDB2/IO83PDB2V0

M4

GNDOSC

NC

IO78PDB2V0

GND

M5

GFC0/IO72NDB4V0 GFC0/IO107NDB4V0

VCCIB4 VCCIB4

GFB0/IO71NDB4V0 GFB0/IO106NDB4V0

GND

M6

IO47NDB2V0

IO47PDB2V0

GND

IO72NDB2V0

IO72PDB2V0

GND

M7

M8

VCCIB4

VCC

VCCIB4

VCC

M9

IO49PDB2V0

IO71PDB2V0

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

N1

GND

GFA1/IO70PDB4V0 GFA1/IO105PDB4V0

GFA0/IO70NDB4V0 GFA0/IO105NDB4V0

VCC

P2

GND

P3

IO68NDB4V0

IO65PDB4V0

IO65NDB4V0

NC

IO101NDB4V0

IO96PDB4V0

IO96NDB4V0

IO99NDB4V0

IO97NDB4V0

VCCIB4

VCC

P4

GND

P5

VCCIB2

IO48NDB2V0

VCCIB2

IO46NDB2V0

VCCIB2

IO70NDB2V0

VCCIB2

IO69NDB2V0

P6

P7

NC

P8

VCCIB4

VCC

P9

VCC

GCA0/IO45NDB2V0 GCA0/IO64NDB2V0

VCCIB2 VCCIB2

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

GND

VCC

GCB0/IO44NDB2V0 GCB0/IO63NDB2V0

GCB1/IO44PDB2V0 GCB1/IO63PDB2V0

GND

VCC

NC

GND

IO103NDB4V0

GND

N2

VCCIB2

IO56NDB2V0

NC

VCCIB2

N3

IO68PDB4V0

NC

IO101PDB4V0

IO100NPB4V0

GND

IO83NDB2V0

IO78NDB2V0

N4

N5

GND

GDA1/IO54PDB2V0 GDA1/IO81PDB2V0

GDB1/IO53PDB2V0 GDB1/IO80PDB2V0

N6

NC

IO99PDB4V0

IO97PDB4V0

N7

NC

IO51NDB2V0

IO73NDB2V0

4-24

Revision 4

Fusion Family of Mixed Signal FPGAs

FG484

Number

AFS600 Function

IO51PDB2V0

IO49NDB2V0

IO69PDB4V0

IO69NDB4V0

VCCIB4

AFS1500 Function

IO73PDB2V0

IO71NDB2V0

IO102PDB4V0

IO102NDB4V0

VCCIB4

Number

AFS600 Function

AFS1500 Function

AV5

P21

P22

R1

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

U1

AV5

AC5

NC

R2

GNDA

NC

GNDA

R3

IO77PPB2V0

IO74PDB2V0

VCCIB2

R4

IO64PDB4V0

IO64NDB4V0

NC

IO91PDB4V0

IO91NDB4V0

IO92PDB4V0

GND

NC

R5

VCCIB2

IO55NDB2V0

R6

IO82NDB2V0

R7

GND

GDA2/IO55PDB2V0 GDA2/IO82PDB2V0

GND GND

GDC1/IO52PDB2V0 GDC1/IO79PDB2V0

R8

GND

R9

VCC33A

GNDA

VCC33A

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

T1

GNDA

IO67PDB4V0

IO67NDB4V0

IO98PDB4V0

IO98NDB4V0

VCC33A

GNDA

VCC33A

U2

GNDA

U3

GEC1/IO63PDB4V0 GEC1/IO90PDB4V0

GEC0/IO63NDB4V0 GEC0/IO90NDB4V0

VCC33A

GNDA

VCC33A

U4

GNDA

U5

GND

VCCNVM

VCCIB4

VCC15A

GNDA

GND

VCCNVM

VCCIB4

VCC15A

GNDA

VCC

U6

GND

U7

NC

IO74NDB2V0

U8

GDA0/IO54NDB2V0 GDA0/IO81NDB2V0

GDB0/IO53NDB2V0 GDB0/IO80NDB2V0

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

V1

AC4

VCCIB2

IO50NDB2V0

IO50PDB2V0

NC

VCCIB2

IO75NDB2V0

IO75PDB2V0

IO100PPB4V0

GND

VCC33A

GNDA

VCC33A

GNDA

AG5

GNDA

T2

GND

PUB

T3

IO66PDB4V0

IO66NDB4V0

VCCIB4

NC

IO95PDB4V0

IO95NDB4V0

VCCIB4

VCCIB2

TDI

VCCIB2

TDI

T4

T5

GND

T6

IO92NDB4V0

GNDNVM

GNDA

IO57NDB2V0

IO84NDB2V0

T7

GNDNVM

GNDA

GDC2/IO57PDB2V0 GDC2/IO84PDB2V0

NC IO77NPB2V0

T8

T9

NC

GDC0/IO52NDB2V0 GDC0/IO79NDB2V0

GEB1/IO62PDB4V0 GEB1/IO89PDB4V0

GEB0/IO62NDB4V0 GEB0/IO89NDB4V0

T10

T11

AV4

NC

V2

Revision 4

4-25

Package Pin Assignments

FG484

Number

AFS600 Function

AFS1500 Function

Number

AFS600 Function

AFS1500 Function

GNDA

V3

V4

VCCIB4

W16

W17

W18

W19

W20

W21

W22

Y1

GNDA

AV9

GEA1/IO61PDB4V0 GEA1/IO88PDB4V0

GEA0/IO61NDB4V0 GEA0/IO88NDB4V0

AV9

V5

VCCIB2

NC

VCCIB2

V6

GND

VCC33PMP

NC

GND

VCC33PMP

NC

IO68PPB2V0

TCK

V7

TCK

V8

GND

NC

GND

V9

VCC33A

AG4

VCC33A

AG4

IO76PPB2V0

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

W1

GEC2/IO60PDB4V0 GEC2/IO87PDB4V0

IO60NDB4V0 IO87NDB4V0

GEA2/IO58PDB4V0 GEA2/IO85PDB4V0

AT4

Y2

ATRTN2

AT5

ATRTN2

AT5

Y3

Y4

IO58NDB4V0

NCAP

IO85NDB4V0

NCAP

VCC33A

NC

VCC33A

NC

Y5

Y6

AC0

VCC33A

GND

VCC33A

GND

Y7

VCC33A

AC1

VCC33A

AC1

Y8

TMS

Y9

AC2

VJTAG

VCCIB2

TRST

TDO

VJTAG

VCCIB2

TRST

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

VCC33A

AC3

VCC33A

AC3

AC6

TDO

VCC33A

AC7

VCC33A

AC7

NC

IO93PDB4V0

GND

W2

GND

AC8

W3

NC

IO93NDB4V0

VCC33A

AC9

VCC33A

AC9

W4

GEB2/IO59PDB4V0 GEB2/IO86PDB4V0

W5

IO59NDB4V0

AV0

IO86NDB4V0

AV0

ADCGNDREF

PTBASE

GNDNVM

VCCNVM

VPUMP

ADCGNDREF

PTBASE

GNDNVM

VCCNVM

VPUMP

W6

W7

GNDA

AV1

GNDA

AV1

W8

W9

AV2

W10

W11

W12

W13

W14

W15

GNDA

AV3

GNDA

AV3

AV6

GNDA

AV7

GNDA

AV7

AV8

4-26

Revision 4

Fusion Family of Mixed Signal FPGAs

FG676

A1 Ball Pad Corner

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7 6

5

4

3

2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/default.aspx.

Revision 4

4-27

Package Pin Assignments

FG676

Pin Number AFS1500 Function

A1

A2

NC

GND

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

AV2

GNDA

AB21

AB22

AB23

AB24

AB25

AB26

AC1

PTBASE

GNDNVM

VCCNVM

VPUMP

NC

A3

NC

AV3

A4

NC

AV6

A5

GND

GNDA

A6

NC

AV7

GND

NC

A7

NC

AV8

A8

GND

GNDA

AC2

NC

A9

IO17NDB0V2

IO17PDB0V2

GND

AV9

AC3

NC

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

VCCIB2

IO68PPB2V0

TCK

AC4

GND

VCCIB4

PCAP

AG0

AC5

IO18NDB0V2

IO18PDB0V2

IO20NDB0V2

IO20PDB0V2

GND

AC6

GND

AC7

IO76PPB2V0

VCCIB2

NC

AC8

AC9

GNDA

AG1

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

IO21PDB0V2

IO21NDB0V2

GND

AG2

AB2

NC

GNDA

AG3

AB3

GEC2/IO87PDB4V0

IO87NDB4V0

GEA2/IO85PDB4V0

IO85NDB4V0

NCAP

IO39NDB1V2

IO39PDB1V2

GND

AB4

AG6

AB5

GNDA

AG7

AB6

NC

AB7

AG8

NC

AB8

AC0

GNDA

AG9

GND

AB9

VCC33A

AC1

NC

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

VAREF

VCCIB2

PTEM

GND

NC

AC2

VCCIB4

IO93PDB4V0

GND

VCC33A

AC3

AC6

IO93NDB4V0

GEB2/IO86PDB4V0

IO86NDB4V0

AV0

VCC33A

AC7

NC

AC8

NC

VCC33A

AC9

AD2

NC

GNDA

AD3

GND

NC

AV1

ADCGNDREF

AD4

4-28

Revision 4

Fusion Family of Mixed Signal FPGAs

FG676

Pin Number AFS1500 Function

AD5

AD6

IO94NPB4V0

GND

VCC33N

AT0

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

GNDA

NC

AF25

AF26

B1

GND

NC

AD7

NC

GND

AD8

GNDA

NC

B2

GND

AD9

ATRTN0

AT1

B3

NC

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

NC

B4

NC

AT2

NC

B5

NC

ATRTN1

AT3

NC

B6

VCCIB0

NC

B7

AT6

NC

B8

NC

ATRTN3

AT7

GND

NC

B9

VCCIB0

IO15NDB0V2

IO15PDB0V2

VCCIB0

IO19NDB0V2

IO19PDB0V2

VCCIB1

IO25NDB1V0

IO25PDB1V0

VCCIB1

IO33NDB1V1

IO33PDB1V1

VCCIB1

NC

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

AT8

ATRTN4

AT9

AF2

GND

NC

AF3

VCC33A

GND

IO76NPB2V0

NC

AF4

NC

AF5

NC

AF6

NC

AF7

NC

GND

NC

AF8

NC

AF9

VCC33A

NC

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

GND

NC

AE2

VCC33A

NC

AE3

NC

AE4

NC

AE5

NC

VCC33A

NC

GND

AE6

NC

GND

AE7

NC

AE8

NC

VCC33A

NC

C2

NC

AE9

GNDA

NC

C3

GND

AE10

AE11

AE12

AE13

AE14

NC

C4

NC

C5

GAA1/IO01PDB0V0

GAB0/IO02NDB0V0

GAB1/IO02PDB0V0

IO07NDB0V1

GNDA

NC

C6

NC

C7

NC

C8

Revision 4

4-29

Package Pin Assignments

FG676

Pin Number AFS1500 Function

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

IO07PDB0V1

IO09PDB0V1

IO13NDB0V2

IO13PDB0V2

IO24PDB1V0

IO26PDB1V0

IO27NDB1V1

IO27PDB1V1

IO35NDB1V2

IO35PDB1V2

GBC0/IO40NDB1V2

GBA0/IO42NDB1V2

IO43NDB1V2

IO43PDB1V2

NC

D19

D20

D21

D22

D23

D24

D25

D26

E1

GBC1/IO40PDB1V2

GBA1/IO42PDB1V2

GND

F3

F4

IO121NDB4V0

GND

F5

IO123NDB4V0

GAC2/IO123PDB4V0

GAA2/IO125PDB4V0

GAC0/IO03NDB0V0

GAC1/IO03PDB0V0

IO10NDB0V1

IO10PDB0V1

IO14NDB0V2

IO23NDB1V0

IO23PDB1V0

IO32NPB1V1

IO34NDB1V1

IO34PDB1V1

IO37PDB1V2

GBB1/IO41PDB1V2

VCCIB2

VCCPLB

F6

GND

F7

NC

F8

NC

F9

NC

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

GND

E2

IO122NPB4V0

IO121PDB4V0

IO122PPB4V0

IO00NDB0V0

IO00PDB0V0

VCCIB0

E3

E4

E5

E6

E7

GND

E8

IO05NDB0V1

IO05PDB0V1

VCCIB0

NC

E9

NC

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

NC

IO11NDB0V1

IO14PDB0V2

VCCIB0

IO47PPB2V0

IO44NDB2V0

GND

D2

NC

D3

NC

D4

GND

VCCIB1

IO45NDB2V0

VCCIB2

D5

GAA0/IO01NDB0V0

GND

IO29NDB1V1

IO29PDB1V1

VCCIB1

D6

NC

D7

IO04NDB0V0

IO04PDB0V0

GND

NC

D8

IO37NDB1V2

GBB0/IO41NDB1V2

VCCIB1

G2

IO119PPB4V0

IO120NDB4V0

IO120PDB4V0

VCCIB4

D9

G3

D10

D11

D12

D13

D14

D15

D16

D17

D18

IO09NDB0V1

IO11PDB0V1

GND

G4

VCOMPLB

GBA2/IO44PDB2V0

IO48PPB2V0

GBB2/IO45PDB2V0

NC

G5

G6

GAB2/IO124PDB4V0

IO125NDB4V0

GND

IO24NDB1V0

IO26NDB1V0

GND

G7

G8

G9

VCCIB0

IO31NDB1V1

IO31PDB1V1

GND

G10

G11

G12

IO08NDB0V1

IO08PDB0V1

GND

NC

F2

VCCIB4

4-30

Revision 4

Fusion Family of Mixed Signal FPGAs

FG676

Pin Number AFS1500 Function

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

H1

IO22NDB1V0

IO22PDB1V0

GND

H23

H24

H25

H26

J1

IO50NDB2V0

IO51PDB2V0

NC

K7

K8

IO114PDB4V0

IO117NDB4V0

GND

K9

IO32PPB1V1

IO36NPB1V2

VCCIB1

GND

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

L1

VCC

NC

VCCIB0

J2

VCCIB4

GND

J3

IO115PDB4V0

GND

VCCIB0

IO47NPB2V0

IO49PDB2V0

VCCIB2

J4

VCCIB1

J5

IO116NDB4V0

IO116PDB4V0

VCCIB4

GND

J6

VCCIB1

IO46NDB2V0

GBC2/IO46PDB2V0

IO48NPB2V0

NC

J7

GND

J8

IO117PDB4V0

VCCIB4

GND

J9

IO53NDB2V0

IO57PDB2V0

GCA2/IO59PDB2V0

VCCIB2

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

K1

GND

IO06NDB0V1

IO06PDB0V1

IO16NDB0V2

IO16PDB0V2

IO28NDB1V1

IO28PDB1V1

GND

H2

NC

H3

IO118NDB4V0

IO118PDB4V0

IO119NPB4V0

IO124NDB4V0

GND

IO54NDB2V0

IO54PDB2V0

NC

H4

H5

H6

NC

H7

GND

H8

VCOMPLA

VCCPLA

IO38PPB1V2

IO53PDB2V0

VCCIB2

L2

NC

H9

L3

IO112PPB4V0

IO113NDB4V0

GFB2/IO109PDB4V0

GFA2/IO110PDB4V0

IO112NPB4V0

IO104PDB4V0

IO111PDB4V0

VCCIB4

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

VCCIB0

L4

IO12NDB0V1

IO12PDB0V1

VCCIB0

IO52PDB2V0

IO52NDB2V0

GND

L5

L6

L7

VCCIB1

IO51NDB2V0

VCCIB2

L8

IO30NDB1V1

IO30PDB1V1

VCCIB1

L9

NC

L10

L11

L12

L13

L14

L15

L16

NC

GND

IO36PPB1V2

IO38NPB1V2

GND

K2

NC

VCC

K3

IO115NDB4V0

IO113PDB4V0

VCCIB4

GND

K4

VCC

IO49NDB2V0

IO50PDB2V0

K5

GND

K6

IO114NDB4V0

VCC

Revision 4

4-31

Package Pin Assignments

FG676

Pin Number AFS1500 Function

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

M1

VCCIB2

GCB2/IO60PDB2V0

IO58NDB2V0

IO57NDB2V0

IO59NDB2V0

GCC2/IO61PDB2V0

IO55PPB2V0

IO56PDB2V0

IO55NPB2V0

GND

N1

N2

NC

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

R1

VCC

GND

N3

IO108NDB4V0

VCCOSC

VCC

N4

GND

N5

VCCIB4

VCC

N6

XTAL2

GND

N7

GFC1/IO107PDB4V0

VCCIB4

VCCIB2

N8

IO70NDB2V0

VCCIB2

N9

GFB1/IO106PDB4V0

VCCIB4

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

P1

IO69NDB2V0

GCA0/IO64NDB2V0

VCCIB2

NC

GND

M2

VCCIB4

VCC

M3

GFC2/IO108PDB4V0

GND

GCB0/IO63NDB2V0

GCB1/IO63PDB2V0

IO66NDB2V0

IO67PDB2V0

NC

M4

VCC

M5

IO109NDB4V0

IO110NDB4V0

GND

M6

VCC

M7

VCCIB2

M8

IO104NDB4V0

IO111NDB4V0

GND

IO70PDB2V0

VCCIB2

R2

VCCIB4

M9

R3

IO103NDB4V0

GND

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

IO69PDB2V0

GCA1/IO64PDB2V0

VCCIB2

R4

VCC

R5

IO101PDB4V0

IO100NPB4V0

GND

R6

VCC

GCC0/IO62NDB2V0

GCC1/IO62PDB2V0

IO66PDB2V0

IO65NDB2V0

NC

R7

GND

R8

IO99PDB4V0

IO97PDB4V0

GND

VCC

R9

GND

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

GND

IO60NDB2V0

IO58PDB2V0

GND

P2

NC

VCC

P3

IO103PDB4V0

XTAL1

GND

P4

VCC

IO68NPB2V0

IO61NDB2V0

GND

P5

VCCIB4

GND

P6

GNDOSC

GFC0/IO107NDB4V0

VCCIB4

VCC

P7

GND

IO56NDB2V0

VCCIB2

P8

GDB2/IO83PDB2V0

IO78PDB2V0

GND

P9

GFB0/IO106NDB4V0

VCCIB4

IO65PDB2V0

P10

4-32

Revision 4

Fusion Family of Mixed Signal FPGAs

FG676

Pin Number AFS1500 Function

R21

R22

R23

R24

R25

R26

T1

IO72NDB2V0

IO72PDB2V0

GND

U5

U6

VCCIB4

IO91PDB4V0

IO91NDB4V0

IO92PDB4V0

GND

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

W1

AC5

NC

U7

GNDA

IO71PDB2V0

VCCIB2

U8

IO77PPB2V0

IO74PDB2V0

VCCIB2

U9

IO67NDB2V0

GND

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V1

GND

VCC33A

GNDA

IO82NDB2V0

GDA2/IO82PDB2V0

GND

T2

NC

T3

GFA1/IO105PDB4V0

GFA0/IO105NDB4V0

IO101NDB4V0

IO96PDB4V0

IO96NDB4V0

IO99NDB4V0

IO97NDB4V0

VCCIB4

VCC33A

GNDA

T4

GDC1/IO79PDB2V0

VCCIB2

T5

VCC33A

GNDA

T6

NC

T7

VCC

GND

T8

GND

W2

IO94PPB4V0

IO98PDB4V0

IO98NDB4V0

GEC1/IO90PDB4V0

GEC0/IO90NDB4V0

GND

T9

IO74NDB2V0

GDA0/IO81NDB2V0

GDB0/IO80NDB2V0

VCCIB2

W3

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

U1

W4

VCC

W5

GND

W6

VCC

IO75NDB2V0

IO75PDB2V0

NC

W7

GND

W8

VCCNVM

VCCIB4

VCC

W9

GND

NC

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

VCC15A

VCCIB2

NC

GNDA

IO83NDB2V0

IO78NDB2V0

GDA1/IO81PDB2V0

GDB1/IO80PDB2V0

IO73NDB2V0

IO73PDB2V0

IO71NDB2V0

NC

V2

VCCIB4

AC4

V3

IO100PPB4V0

GND

VCC33A

V4

GNDA

V5

IO95PDB4V0

IO95NDB4V0

VCCIB4

AG5

V6

GNDA

V7

PUB

V8

IO92NDB4V0

GNDNVM

GNDA

VCCIB2

V9

TDI

GND

V10

V11

V12

V13

V14

GND

NC

IO84NDB2V0

GDC2/IO84PDB2V0

IO77NPB2V0

GDC0/IO79NDB2V0

U2

NC

AV4

U3

IO102PDB4V0

IO102NDB4V0

NC

U4

AV5

Revision 4

4-33

Package Pin Assignments

FG676

Pin Number AFS1500 Function

W25

W26

Y1

NC

GND

NC

Y2

NC

Y3

GEB1/IO89PDB4V0

Y4

GEB0/IO89NDB4V0

Y5

VCCIB4

GEA1/IO88PDB4V0

GEA0/IO88NDB4V0

GND

Y6

Y7

Y8

Y9

VCC33PMP

NC

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

VCC33A

AG4

AT4

ATRTN2

AT5

VCC33A

NC

VCC33A

GND

TMS

VJTAG

VCCIB2

TRST

TDO

NC

4-34

Revision 4

5 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each revision of the Fusion datasheet.

Revision

Changes

Page

Revision 4

(January 2013)

The "Product Ordering Codes" section has been updated to mention "Y" as "Blank"

mentioning "Device Does Not Include License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43177).

III

The note in Table 2-12 • Fusion CCC/PLL Specification referring the reader to

SmartGen was revised to refer instead to the online help associated with the core

(SAR 42563).

2-30

2-120

2-133

Table 2-49 • Analog Channel Specifications was modified to update the uncalibrated

offset values (AFS250) of the external and internal temperature monitors (SAR

43134).

In Table 2-57 • Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3),

changed the column heading from 'Full-Scale Voltage' to 'Full Scale Voltage in 10-Bit

Mode', and added and updated Notes as required (SAR 20812).

The values for the Speed Grade (-1 and Std.) for FDDRIMAX (Table 2-180 • Input 2-223,

DDR Propagation Delays) and values for the Speed Grade (-2 and Std.) for

FDDOMAX (Table 2-182 • Output DDR Propagation Delays) had been inadvertently

interchanged. This has been rectified (SAR 38514).

2-225

Added description about what happens if a user connects VAREF to an external 3.3

V on their board to the "VAREF Analog Reference Voltage" section (SAR 35188).

2-228

3-3

Added a note to Table 3-2 • Recommended Operating Conditions1 (SAR 43429):

The programming temperature range supported is T_ambient= 0°C to 85°C.

Added the Package Thermal details for AFS600-PQ208 and AFS250-PQ208 to

Table 3-6 • Package Thermal Resistance (SAR 37816). Deleted the Die Size column

from the table (SAR 43503).

3-7

Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip

(SoC) throughout the document (SAR 42495).

NA

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

Revision 3

(August 2012)

Microblade U1AFS250 and U1AFS1500 devices were added to the product tables.

I – IV

1-8

A sentence pertaining to the analog I/Os was added to the "Specifying I/O States

During Programming" section (SAR 34831).

The "RC Oscillator" section was revised to correct a sentence that did not

differentiate accuracy for commercial and industrial temperature ranges, which is

given in Table 2-9 • Electrical Characteristics of RC Oscillator (SAR 33722).

2-20

Figure 2-57 • FIFO Read and Figure 2-58 • FIFO Write are new (SAR 34840).

2-75

2-98

The first paragraph of the "Offset" section was removed; it was intended to be

replaced by the paragraph following it (SAR 22647).

IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected in Table 2-86 •

Summary of Maximum and Minimum DC Input and Output Levels Applicable to

Commercial and Industrial Conditions (SAR 39813).

2-167

Revision 4

5-1

Datasheet Information

Revision

Changes

Page

Revision 3

(continued)

The drive strength, IOL, and IOH for 3.3 V GTL and 2.5 V GTL were changed from

25 mA to 20 mA in the following tables (SAR 37373):

2-167

Table 2-86 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions,

Table 2-92 • Summary of I/O Timing Characteristics – Software Default Settings

Table 2-96 • I/O Output Buffer Maximum Resistances 1

2-170

2-172

2-202

2-203

Table 2-138 • Minimum and Maximum DC Input and Output Levels

Table 2-141 • Minimum and Maximum DC Input and Output Levels

The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34800):

"It uses a 5 V–tolerant input buffer and push-pull output buffer."

2-184

2-214

Corrected the inadvertent error in maximum values for LVPECL VIH and VIL and

revised them to "3.6" in Table 2-171 • Minimum and Maximum DC Input and Output

Levels, making these consistent with Table 3-1 • Absolute Maximum Ratings, and

Table 3-4 • Overshoot and Undershoot Limits 1 (SAR 37687).

The maximum frequency for global clock parameter was removed from Table 2-5 • 2-17 to

AFS1500 Global Resource Timing through Table 2-8 • AFS090 Global Resource

Timing because a frequency on the global is only an indication of what the global

network can do. There are other limiters such as the SRAM, I/Os, and PLL.

SmartTime software should be used to determine the design frequency (SAR

36955).

2-18

Revision 2

(March 2012)

The phrase "without debug" was removed from the "Soft ARM Cortex-M1 Fusion

Devices (M1)" section (SAR 21390).

I

The "In-System Programming (ISP) and Security" section, "Security" section, "Flash

Advantages" section, and "Security" section were revised to clarify that although no

existing security measures can give an absolute guarantee, Microsemi FPGAs

implement the best security available in the industry (SAR 34679).

I, 1-2,

2-231

The Y security option and Licensed DPA Logo was added to the "Product Ordering

Codes" section. The trademarked Licensed DPA Logo identifies that a product is

covered by a DPA counter-measures license from Cryptography Research (SAR

34721).

III

The "Specifying I/O States During Programming" section is new (SAR 34693).

The following information was added before Figure 2-17 • XTLOSC Macro:

1-8

2-21

In the case where the Crystal Oscillator block is not used, the XTAL1 pin should be

connected to GND and the XTAL2 pin should be left floating (SAR 24119).

Table 2-12 • Fusion CCC/PLL Specification was updated. A note was added

indicating that when the CCC/PLL core is generated by Microsemi core generator

software, not all delay values of the specified delay increments are available (SAR

34814).

2-30

2-33

A note was added to Figure 2-27 • Real-Time Counter System (not all the signals are

shown for the AB macro) stating that the user is only required to instantiate the

VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator

to be different from the default, or employ user logic to shut the voltage regulator off

(SAR 21773).

5-2

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

Revision 2

(continued)

VPUMP was incorrectly represented as VPP in several places. This was corrected to 2-34, 3-10

VPUMP in the "Standby and Sleep Mode Circuit Implementation" section and

Table 3-8 • AFS1500 Quiescent Supply Current Characteristics through Table 3-11 •

AFS090 Quiescent Supply Current Characteristics (21963).

Additional information was added to the Flash Memory Block "Write Operation"

section, including an explanation of the fact that a copy-page operation takes no less

than 55 cycles (SAR 26338).

2-47

The "FlashROM" section was revised to refer to Figure 2-46 • FlashROM Timing 2-56, 2-57

Diagram and Table 2-26 • FlashROM Access Time rather than stating 20 MHz as the

maximum FlashROM access clock and 10 ns as the time interval for D0 to become

valid or invalid (SAR 22105).

The following figures were deleted (SAR 29991). Reference was made to a new

application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs, which covers these cases in detail (SAR 34862).

Figure 2-55 • Write Access after Write onto Same Address

Figure 2-56 • Read Access after Write onto Same Address

Figure 2-57 • Write Access after Read onto Same Address

The port names in the SRAM "Timing Waveforms", "Timing Characteristics", SRAM

tables, Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18., and

2-66,

2-69,

the FIFO "Timing Characteristics" tables were revised to ensure consistency with the 2-68, 2-78

software names (SAR 35753).

In several places throughout the datasheet, GNDREF was corrected to

ADCGNDREF (SAR 20783):

2-80

2-81

Figure 2-64 • Analog Block Macro

Table 2-36 • Analog Block Pin Description

"ADC Operation" section

2-107

The following note was added below Figure 2-78 • Timing Diagram for the

Temperature Monitor Strobe Signal:

2-96

When the IEEE 1149.1 Boundary Scan EXTEST instruction is executed, the AG pad

drive strength ceases and becomes a 1 µA sink into the Fusion device. (SAR

24796).

The "Analog-to-Digital Converter Block" section was extensively revised,

reorganizing the information and adding the "ADC Theory of Operation" section and

"Acquisition Time or Sample Time Control" section. The "ADC Example" section was

reworked and corrected (SAR 20577).

2-99

Table 2-49 • Analog Channel Specifications was modified to include calibrated and

uncalibrated values for offset (AFS090 and AFS250) for the external and internal

temperature monitors. The "Offset" section was revised accordingly and now

references Table 2-49 • Analog Channel Specifications (SARs 22647, 27015).

2-98,

2-120

The "Intra-Conversion" section and "Injected Conversion" section had definitions 2-112,

incorrectly interchanged and have been corrected. Figure 2-92 • Intra-Conversion

Timing Diagram and Figure 2-93 • Injected Conversion Timing Diagram were also

incorrectly interchanged and have been replaced correctly. Reference in the figure

notes to EQ 10 has been corrected to EQ 23 (SAR 20547).

2-115,

2-116

The prescalar range for the 'Analog Input (direct input to ADC)" configurations was

removed as inapplicable for direct inputs. The input resistance for direct inputs is

covered in Table 2-50 • ADC Characteristics in Direct Input Mode (SAR 31201).

2-123

Revision 4

5-3

Datasheet Information

Revision

Changes

Page

Revision 2

(continued)

The "Examples" for calibrating accuracy for ADC channels were revised and

corrected to make them consistent with terminology in the associated tables (SARs

36791, 36773).

2-127

A note was added to Table 2-56 • Analog Quad ACM Byte Assignment and the 2-132,

introductory text for Table 2-66 • Internal Temperature Monitor Control Truth Table,

stating that for the internal temperature monitor to function, Bit 0 of Byte 2 for all 10

Quads must be set (SAR 34418).

2-134

t

_DOUTwas corrected to t_DINin Figure 2-116 • Input Buffer Timing Model and Delays

2-164

2-174

2-178

(example) (SAR 37115).

The formulas in the table notes for Table 2-97 • I/O Weak Pull-Up/Pull-Down

Resistances were corrected (SAR 34751).

The AC Loading figures in the "Single-Ended I/O Characteristics" section were

updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O

Software Settings" section (SAR 34877).

The following notes were removed from Table 2-168 • Minimum and Maximum DC

Input and Output Levels (SAR 34808):

2-212

±5%

Differential input voltage = ±350 mV

An incomplete, duplicate sentence was removed from the end of the "GNDAQ

Ground (analog quiet)" pin description (SAR 30185).

2-226

2-228

2-230

3-4

Information about configuration of unused I/Os was added to the "User Pins" section

(SAR 32642).

The following information was added to the pin description for "XTAL1 Crystal

Oscillator Circuit Input" and "XTAL2 Crystal Oscillator Circuit Input" (SAR 24119).

The input resistance to ground value in Table 3-3 • Input Resistance of Analog Pads

for Analog Input (direct input to ADC), was corrected from 1 M (typical) to 2 k

(typical) (SAR 34371).

The Storage Temperature column in Table 3-5 • FPGA Programming, Storage, and

Operating Limits stated Min. T_Jtwice for commercial and industrial product grades

and has been corrected to Min. T_Jand Max. T_J(SAR 29416).

3-5

The reference to guidelines for global spines and VersaTile rows, given in the

"Global Clock Dynamic Contribution—PCLOCK" section, was corrected to the

"Spine Architecture" section of the Global Resources chapter in the Fusion

FPGA Fabric User's Guide (SAR 34741).

3-24

Package names used in the "Package Pin Assignments" section were revised to

4-1

match standards given in Package Mechanical Drawings (SAR 36612).

July 2010

The versioning system for datasheets has been changed. Datasheets are assigned

a revision number that increments each time the datasheet is revised. The "Fusion

Device Status" table indicates the status for each device in the device family.

N/A

5-4

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

v2.0, Revision 1

(July 2009)

The MicroBlade and Fusion datasheets have been combined. Pigeon Point

information is new.

N/A

CoreMP7 support was removed since it is no longer offered.

–F was removed from the datasheet since it is no longer offered.

The operating temperature was changed from ambient to junction to better reflect

actual conditions of operations.

Commercial: 0°C to 85°C

Industrial: –40°C to 100°C

The version number category was changed from Preliminary to Production, which

means the datasheet contains information based on final characterization. The

version number changed from Preliminary v1.7 to v2.0.

The "Integrated Analog Blocks and Analog I/Os" section was updated to include a

reference to the "Analog System Characteristics" section in the Device Architecture

chapter of the datasheet, which includes Table 2-46 • Analog Channel Specifications

and specific voltage data.

1-4

The phrase "Commercial-Case Conditions" in timing table titles was changed to

"Commercial Temperature Range Conditions."

N/A

The "Crystal Oscillator" section was updated significantly. Please review carefully.

2-21

2-35

The "Real-Time Counter (part of AB macro)" section was updated significantly.

Please review carefully.

There was a typo in Table 2-19 • Flash Memory Block Pin Names for the

ERASEPAGE description; it was the same as DISCARDPAGE. As as a result, the

ERASEPAGE description was updated.

2-42

2-54

The t_FMAXCLKNVMparameter was updated in Table 2-25 • Flash Memory Block

Timing.

Table 2-31 • RAM4K9 and Table 2-32 • RAM512X18 were updated.

2-69

2-81

In Table 2-36 • Analog Block Pin Description, the Function description for PWRDWN

was changed from "Comparator power-down if 1"

to

"ADC comparator power-down if 1. When asserted, the ADC will stop functioning,

and the digital portion of the analog block will continue operating. This may result in

invalid status flags from the analog block. Therefore, Microsemi does not

recommend asserting the PWRDWN pin."

Figure 2-75 • Gate Driver Example was updated.

2-94

2-107

2-116

The "ADC Operation" section was updated. Please review carefully.

Figure 2-92 • Intra-Conversion Timing Diagram and Figure 2-93 • Injected

Conversion Timing Diagram are new.

The "Typical Performance Characteristics" section is new.

2-118

2-120

2-123

2-126

2-127

Table 2-49 • Analog Channel Specifications was significantly updated.

Table 2-50 • ADC Characteristics in Direct Input Mode was significantly updated.

In Table 2-52 • Calibrated Analog Channel Accuracy 1,2,3, note 2 was updated.

In Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages,

note 1 was updated.

In Table 2-54 • ACM Address Decode Table for Analog Quad, bit 89 was removed.

2-129

Revision 4

5-5

Datasheet Information

Revision

Changes

Page

v2.0, Revision 1

(continued)

The data in the 2.5 V LCMOS and LVCMOS 2.5 V / 5.0 V rows were updated in

Table 2-75 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance

Capabilities.

2-146

In Table 2-78 • Fusion Standard I/O Standards—OUT_DRIVE Settings, LVCMOS

1.5 V, for OUT_DRIVE 2, was changed from a dash to a check mark.

2-155

2-226

The "VCC15A Analog Power Supply (1.5 V)" definition was changed from "A 1.5 V

analog power supply input should be used to provide this input" to "1.5 V clean

analog power supply input for use by the 1.5 V portion of the analog circuitry."

In the "VCC33PMP Analog Power Supply (3.3 V)" pin description, the following text

was changed from "VCC33PMP should be powered up before or simultaneously

with VCC33A" to "VCC33PMP should be powered up simultaneously with or after

VCC33A."

2-226

The "VCCOSC Oscillator Power Supply (3.3 V)" section was updated to include

information about when to power the pin.

2-227

2-231

2-159

In the "128-Bit AES Decryption" section, FIPS-192 was incorrect and changed to

FIPS-197.

The note in Table 2-84 • Fusion Standard and Advanced I/O Attributes vs. I/O

Standard Applications was updated.

For 1.5 V LVCMOS, the VIL and VIH parameters, 0.30 * VCCI was changed to 0.35 * 2-167 to

VCCI and 0.70 * VCCI was changed to 0.65 * VCCI in Table 2-86 • Summary of

Maximum and Minimum DC Input and Output Levels Applicable to Commercial and

Industrial Conditions, Table 2-87 • Summary of Maximum and Minimum DC Input

and Output Levels Applicable to Commercial and Industrial Conditions, and

Table 2-88 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions.

2-168

In Table 2-87 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions, the VIH max column was

updated.

Table 2-89 • Summary of Maximum and Minimum DC Input Levels Applicable to

Commercial and Industrial Conditions was updated to include notes 3 and 4. The

temperature ranges were also updated in notes 1 and 2.

2-168

The titles in Table 2-92 • Summary of I/O Timing Characteristics – Software Default 2-170 to

Settings to Table 2-94 • Summary of I/O Timing Characteristics – Software Default

Settings were updated to "VCCI = I/O Standard Dependent."

2-171

2-175

2-177

3-1

Below Table 2-98 • I/O Short Currents IOSH/IOSL, the paragraph was updated to

change 110°C to 100°C and three months was changed to six months.

Table 2-99 • Short Current Event Duration before Failure was updated to remove

110°C data.

In Table 2-101 • I/O Input Rise Time, Fall Time, and Related I/O Reliability,

LVTTL/LVCMOS rows were changed from 110°C to 100°C.

VCC33PMP was added to Table 3-1 • Absolute Maximum Ratings. In addition,

conditions for AV, AC, AG, and AT were also updated.

VCC33PMP was added to Table 3-2 • Recommended Operating Conditions1. In

addition, conditions for AV, AC, AG, and AT were also updated.

3-3

Table 3-5 • FPGA Programming, Storage, and Operating Limits was updated to

include new data and the temperature ranges were changed. The notes were

removed from the table.

3-5

5-6

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

v2.0, Revision 1

(continued)

Table 3-6 • Package Thermal Resistance was updated to include new data.

In EQ 4 to EQ 6, the junction temperature was changed from 110°C to 100°C.

3-7

3-8 to 3-8

Table 3-8 • AFS1500 Quiescent Supply Current Characteristics through Table 3-11 • 3-10 to

AFS090 Quiescent Supply Current Characteristics are new and have replaced the

Quiescent Supply Current Characteristics (IDDQ) table.

3-16

3-22

In Table 3-14 • Different Components Contributing to the Dynamic Power

Consumption in Fusion Devices, the power supply for PAC9 and PAC10 were

changed from VMV/VCC to VCCI.

In Table 3-15 • Different Components Contributing to the Static Power Consumption

in Fusion Devices, the power supply for PDC7 and PDC8 were changed from

VMV/VCC to VCCI. PDC1 was updated from TBD to 18.

3-23

4-2

The "QN108" table was updated to remove the duplicates of pins B12 and B34.

Preliminary v1.7

(October 2008)

The version number category was changed from Advance to Preliminary, which

means the datasheet contains information based on simulation and/or initial

characterization. The information is believed to be correct, but changes are possible.

For the VIL and VIH parameters, 0.30 * VCCI was changed to 0.35 * VCCI and 0.70

* VCCI was changed to 0.65 * VCCI in Table 2-126 • Minimum and Maximum DC

Input and Output Levels.

2-196

N/A

The version number category was changed from Advance to Preliminary, which

means the datasheet contains information based on simulation and/or initial

characterization. The information is believed to be correct, but changes are possible.

The following updates were made to Table 2-141 • Minimum and Maximum DC Input

and Output Levels:

2-203

Temperature

213

Digital Output

00 1111 1101

283

01 0001 1011

358

01 0110 0110 – only the digital output was updated.

Temperature 358 remains in the temperature column.

In Advance v1.2, the "VAREF Analog Reference Voltage" pin description was

significantly updated but the change was not noted in the change table.

2-228

N/A

Advance v1.6

(August 2008)

The title of the datasheet changed from Actel Programmable System Chips to Actel

Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip

were changed to mixed signal FPGA.

The references to the Peripherals User’s Guide in the "No-Glitch MUX (NGMUX)" 2-32, 2-42

section and "Voltage Regulator Power Supply Monitor (VRPSM)" section were

changed to Fusion Handbook.

Advance v1.5

(July 2008)

The following bullet was updated from High-Voltage Input Tolerance: ±12 V to High-

Voltage Input Tolerance: 10.5 V to 12 V.

I

The following bullet was updated from Programmable 1, 3, 10, 30 µA and 25 mA

Drive Strengths to Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths.

I

Revision 4

5-7

Datasheet Information

Revision

Changes

Page

Advance v1.5

(continued)

This bullet was added to the "Integrated A/D Converter (ADC) and Analog I/O"

section: ADC Accuracy is Better than 1%

I

In the "Integrated Analog Blocks and Analog I/Os" section, ±4 LSB was changed to

0.72. The following sentence was deleted:

1-4

The input range for voltage signals is from –12 V to +12 V with full-scale output

values from 0.125 V to 16 V.

In addition, 2°C was changed to 3°C:

"One analog input in each quad can be connected to an external temperature

monitor diode and achieves detection accuracy of ±3ºC."

The following sentence was deleted:

The input range for voltage signals is from –12 V to +12 V with full-scale output

values from 0.125 V to 16 V.

The title of the datasheet changed from Actel Programmable System Chips to Actel

Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip

were changed to mixed signal FPGA.

N/A

Advance v1.4

(July 2008)

In Table 3-8 · Quiescent Supply Current Characteristics (IDDQ)1, footnote

3-11

references were updated for I_DC2and I_DC3

.

Footnote 3 and 4 were updated and footnote 5 is new.

Advance v1.3

(July 2008)

The "ADC Description" section was significantly updated. Please review carefully.

2-102

Advance v1.2

(May 2008)

Table 2-25 • Flash Memory Block Timing was significantly updated.

2-55

The "V_AREFAnalog Reference Voltage" pin description section was significantly

update. Please review it carefully.

2-226

Table 2-45 • ADC Interface Timing was significantly updated.

2-110

2-131

Table 2-56 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1),

and AT (x = 3) was significantly updated.

The following sentence was deleted from the "Voltage Monitor" section:

The Analog Quad inputs are tolerant up to 12 V + 10%.

2-86

The "180-Pin QFN" figure was updated. D1 to D4 are new and the figure was

changed to bottom view. The note below the figure is new.

3-3

Advance v1.1

(May 2008)

The following text was incorrect and therefore deleted:

2-204

VCC33A

Analog Power Filter

Analog power pin for the analog power supply low-pass filter. An external 100 pF

capacitor should be connected between this pin and ground.

There is still a description of V_CC33Aon page 2-224.

5-8

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

Advance v1.0

(January 2008)

All Timing Characteristics tables were updated. For the Differential I/O Standards,

the Standard I/O support tables are new.

N/A

Table 2-3 • Array Coordinates was updated to change the max x and y values

Table 2-12 • Fusion CCC/PLL Specification was updated.

2-9

2-31

2-37

2-42

A note was added to Table 2-16 · RTC ACM Memory Map.

A reference to the Peripheral’s User’s Guide was added to the "Voltage Regulator

Power Supply Monitor (VRPSM)" section.

In Table 2-25 • Flash Memory Block Timing, the commercial conditions were

updated.

2-55

2-58

2-82

2-86

In Table 2-26 • FlashROM Access Time, the commercial conditions were missing

and have been added below the title of the table.

In Table 2-36 • Analog Block Pin Description, the function description was updated

for the ADCRESET.

In the "Voltage Monitor" section, the following sentence originally had ± 10% and it

was changed to +10%.

The Analog Quad inputs are tolerant up to 12 V + 10%.

In addition, this statement was deleted from the datasheet:

Each I/O will draw power when connected to power (3 mA at 3 V).

The "Terminology" section is new.

2-88

2-90

The "Current Monitor" section was significantly updated. Figure 2-72 • Timing

Diagram for Current Monitor Strobe to Figure 2-74 • Negative Current Monitor and

Table 2-37 • Recommended Resistor for Different Current Range Measurement are

new.

The "ADC Description" section was updated to add the "Terminology" section.

2-93

2-94

In the "Gate Driver" section, 25 mA was changed to 20 mA and 1.5 MHz was

changed to 1.3 MHz. In addition, the following sentence was deleted:

The maximum AG pad switching frequency is 1.25 MHz.

The "Temperature Monitor" section was updated to rewrite most of the text and add

Figure 2-78, Figure 2-79, and Table 2-38 • Temperature Data Format.

2-96

2-98

In Table 2-38 • Temperature Data Format, the temperature K column was changed

for 85°C from 538 to 358.

In Table 2-45 • ADC Interface Timing, "Typical-Case" was changed to "Worst-Case."

The "ADC Interface Timing" section is new.

2-110

2-118

2-224

2-225

2-224

Table 2-46 • Analog Channel Specifications was updated.

The "V_CC15AAnalog Power Supply (1.5 V)" section was updated.

The "V_CCPLA/BPLL Supply Voltage" section is new.

In "V_CCNVMFlash Memory Block Power Supply (1.5 V)" section, supply was

changed to supply input.

The "V_CCPLA/BPLL Supply Voltage" pin description was updated to include the

following statement:

2-225

Actel recommends tying VCCPLX to VCC and using proper filtering circuits to

decouple V_CCnoise from PLL.

The "V_COMPLA/BGround for West and East PLL" section was updated.

2-225

Revision 4

5-9

Datasheet Information

Revision

Changes

Page

Advance 1.0

(continued)

In Table 2-47 • ADC Characteristics in Direct Input Mode, the commercial conditions

were updated and note 2 is new.

2-121

The V_CC33ACAPsignal name was changed to "XTAL1 Crystal Oscillator Circuit

Input".

2-228

Table 2-48 • Uncalibrated Analog Channel Accuracy* is new.

Table 2-49 • Calibrated Analog Channel Accuracy ^1,2,3is new.

2-123

2-124

2-125

Table 2-50 • Analog Channel Accuracy: Monitoring Standard Positive Voltages is

new.

In Table 2-57 • Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT

(x = 3)*, the following I/O Bank names were changed:

2-131

Hot-Swap changed to Standard

LVDS changed to Advanced

In Table 2-58 • Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1),

and AT (x = 3), the following I/O Bank names were changed:

2-132

Hot-Swap changed to Standard

LVDS changed to Advanced

In the title of Table 2-64 • I/O Standards Supported by Bank Type, LVDS I/O was

changed to Advanced I/O.

2-134

2-136

The title was changed from "Fusion Standard, LVDS, and Standard plus Hot-Swap

I/O" to Table 2-68 • Fusion Standard and Advanced I/O Features. In addition, the

table headings were all updated. The heading used to be Standard and LVDS I/O

and was changed to Advanced I/O. Standard Hot-Swap was changed to just

Standard.

This sentence was deleted from the "Slew Rate Control and Drive Strength" section:

2-152

The Standard hot-swap I/Os do not support slew rate control. In addition, these

references were changed:

• From: Fusion hot-swap I/O (Table 2-69 on page 2-122) To: Fusion Standard I/O

• From: Fusion LVDS I/O (Table 2-70 on page 2-122) To: Fusion Advanced I/O

The "Cold-Sparing Support" section was significantly updated.

2-143

2-153

In the title of Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings,

Hot-Swap was changed to Standard.

In the title of Table 2-76 • Fusion Advanced I/O Standards—SLEW and OUT_DRIVE

Settings, LVDS was changed to Advanced.

2-153

2-157

2-160

In the title of Table 2-81 • Fusion Standard and Advanced I/O Attributes vs. I/O

Standard Applications, LVDS was changed to Advanced.

In Figure 2-111 • Naming Conventions of Fusion Devices with Three Digital I/O

Banks and Figure 2-112 • Naming Conventions of Fusion Devices with Four I/O

Banks the following names were changed:

Hot-Swap changed to Standard

LVDS changed to Advanced

The Figure 2-113 • Timing Model was updated.

2-161

2-166

In the notes for Table 2-86 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions, T_Jwas changed to T_A.

5-10

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

Advance v1.0

(continued)

This change table states that in the "208-Pin PQFP" table listed under the Advance

v0.8 changes, the AFS090 device had a pin change. That is incorrect. Pin 102 was

updated for AFS250 and AFS600. The function name changed from V_CC33ACAPto

3-8

V_CC33A

.

Advance v0.9

In the

"Package

I/Os:

Single-/Double-Ended

(Analog)"

table,

the

II

(October 2007)

AFS1500/M7AFS1500 I/O counts were updated for the following devices:

FG484: 223/109

FG676: 252/126

In the "108-Pin QFN" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pin:

3-2

3-4

B25

In the "180-Pin QFN" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pins:

AFS090: B29

AFS250: B29

In the "208-Pin PQFP" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pins:

3-8

AFS090: 102

AFS250: 102

In the "256-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pins:

3-12

AFS090: T14

AFS250: T14

AFS600: T14

AFS1500: T14

Advance v0.9

(continued)

In the "484-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pins:

3-20

3-28

AFS600: AB18

AFS1500: AB18

In the "676-Pin FBGA" table, the function changed from V_CC33ACAPto V_CC33Afor the

following pins:

AFS1500: AD20

Advance v0.8

(June 2007)

Figure 2-16 • Fusion Clocking Options and the "RC Oscillator" section were updated 2-20, 2-21

to change GND_OSC and VCC_OSC to GNDOSC and VCCOSC.

Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro was updated

to change the positions of OADIVRST and OADIVHALF, and a note was added.

2-25

2-22

2-24

2-41

The "Crystal Oscillator" section was updated to include information about controlling

and enabling/disabling the crystal oscillator.

Table 2-11 · Electrical Characteristics of the Crystal Oscillator was updated to

change the typical value of I_DYNXTALfor 0.032–0.2 MHz to 0.19.

The "1.5 V Voltage Regulator" section was updated to add "or floating" in the

paragraph stating that an external pull-down is required on TRST to power down the

VR.

The "1.5 V Voltage Regulator" section was updated to include information on

powering down with the VR.

2-41

Revision 4

5-11

Datasheet Information

Revision

Changes

Page

Advance v0.8

(continued)

This sentence was updated in the "No-Glitch MUX (NGMUX)" section to delete GLA:

2-32

The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e.,

internal signal or GLC).

In Table 2-13 • NGMUX Configuration and Selection Table, 10 and 11 were deleted.

2-32

2-38

The method to enable sleep mode was updated for bit 0 in Table 2-16 • RTC

Control/Status Register.

S2 was changed to D2 in Figure 2-39 • Read Waveform (Pipe Mode, 32-bit access)

for RD[31:0] was updated.

2-51

2-52

The definitions for bits 2 and 3 were updated in Table 2-24 • Page Status Bit

Definition.

Figure 2-46 • FlashROM Timing Diagram was updated.

Table 2-26 • FlashROM Access Time is new.

2-58

Figure 2-55 • Write Access After Write onto Same Address, Figure 2-56 • Read

Access After Write onto Same Address, and Figure 2-57 • Write Access After Read

onto Same Address are new.

2-68–

2-70

Table 2-31 • RAM4K9 and Table 2-32 • RAM512X18 were updated.

2-71, 2-72

2-82

The VAREF and SAMPLE functions were updated in Table 2-36 • Analog Block Pin

Description.

The title of Figure 2-72 • Timing Diagram for Current Monitor Strobe was updated to

add the word "positive."

2-91

2-94

The "Gate Driver" section was updated to give information about the switching rate

in High Current Drive mode.

The "ADC Description" section was updated to include information about the

SAMPLE and BUSY signals and the maximum frequencies for SYSCLK and

ADCCLK. EQ 2 was updated to add parentheses around the entire expression in the

denominator.

2-102

Table 2-46 · Analog Channel Specifications and Table 2-47 · ADC Characteristics in

Direct Input Mode were updated.

2-118,

2-121

The note was removed from Table 2-55 • Analog Multiplexer Truth Table—AV (x = 0),

AC (x = 1), and AT (x = 3).

2-131

Table 2-63 • Internal Temperature Monitor Control Truth Table is new.

2-132

2-143

The "Cold-Sparing Support" section was updated to add information about cases

where current draw can occur.

Figure 2-104 • Solution 4 was updated.

2-147

2-153

2-224

Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings was updated.

The "GNDA Ground (analog)" section and "GNDAQ Ground (analog quiet)" section

were updated to add information about maximum differential voltage.

The "V_AREFAnalog Reference Voltage" section and "VPUMP Programming Supply

Voltage" section were updated.

2-226

2-225

The "V_CCPLA/BPLL Supply Voltage" section was updated to include information

about the east and west PLLs.

The V_COMPLFpin description was deleted.

N/A

The "Axy Analog Input/Output" section was updated with information about

grounding and floating the pin.

2-226

5-12

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

Advance v0.8

(continued)

The voltage range in the "VPUMP Programming Supply Voltage" section was

updated. The parenthetical reference to "pulled up" was removed from the

statement, "VPUMP can be left floating or can be tied (pulled up) to any voltage

between 0 V and 3.6 V."

2-225

The "ATRTNx Temperature Monitor Return" section was updated with information

about grounding and floating the pin.

2-226

2-225

2-228

The following text was deleted from the "VREF I/O Voltage Reference" section: (all

digital I/O).

The "NCAP Negative Capacitor" section and "PCAP Positive Capacitor" section

were updated to include information about the type of capacitor that is required to

connect the two.

1 µF was changed to 100 pF in the "XTAL1 Crystal Oscillator Circuit Input".

2-228

2-229

N/A

3-2

The "Programming" section was updated to include information about V_CCOSC

The VMV pins have now been tied internally with the V_CCIpins.

The AFS090"108-Pin QFN" table was updated.

.

The AFS090 and AFS250 devices were updated in the "108-Pin QFN" table.

The AFS250 device was updated in the "208-Pin PQFP" table.

The AFS600 device was updated in the "208-Pin PQFP" table.

3-2

3-8

The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the "256-Pin

FBGA" table.

3-12

The AFS600 and AFS1500 devices were updated in the "484-Pin FBGA" table.

The AFS600 device was updated in the "676-Pin FBGA" table.

3-20

Advance v0.7

3-28

(January 2007)

The AFS1500 digital I/O count was updated in the "Fusion Family" table.

I

The AFS1500 digital I/O count was updated in the "Package I/Os: Single-/Double-

Ended (Analog)" table.

II

Advance v0.6

(October 2006)

The second paragraph of the "PLL Macro" section was updated to include

information about POWERDOWN.

2-30

The description for bit 0 was updated in Table 2-17 · RTC Control/Status Register.

3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section.

All function descriptions in Table 2-18 · Signals for VRPSM Macro.

2-38

2-40.

2-42

2-43

In Table 2-19 • Flash Memory Block Pin Names, the RD[31:0] description was

updated.

The "RESET" section was updated.

Table 2-35 • FIFO was updated.

2-61

2-64

2-79

2-82

The VAREF function description was updated in Table 2-36 • Analog Block Pin

Description.

The "Voltage Monitor" section was updated to include information about low power

mode and sleep mode.

2-86

The text in the "Current Monitor" section was changed from 2 mV to 1 mV.

2-90

2-94

The "Gate Driver" section was updated to include information about forcing 1 V on

the drain.

Revision 4

5-13

Datasheet Information

Revision

Changes

Page

Advance v0.6

(continued)

The "Analog-to-Digital Converter Block" section was updated with the following

statement:

2-99

"All results are MSB justified in the ADC."

The information about the ADCSTART signal was updated in the "ADC Description"

section.

2-102

Table 2-46 · Analog Channel Specifications was updated.

2-118

2-121

2-127

2-130

Table 2-47 · ADC Characteristics in Direct Input Mode was updated.

Table 2-51 • ACM Address Decode Table for Analog Quad was updated.

In Table 2-53 • Analog Quad ACM Byte Assignment, the Function and Default

Setting for Bit 6 in Byte 3 was updated.

The "Introduction" section was updated to include information about digital inputs,

outputs, and bibufs.

2-133

2-137

In Table 2-69 • Fusion Pro I/O Features, the programmable delay descriptions were

updated for the following features:

Single-ended receiver

Voltage-referenced differential receiver

LVDS/LVPECL differential receiver features

The "User I/O Naming Convention" section was updated to include "V" and "z"

descriptions

2-159

2-224

2-185

The "VCC33PMP Analog Power Supply (3.3 V)" section was updated to include

information about avoiding high current draw.

The "VCCNVM Flash Memory Block Power Supply (1.5 V)" section was updated to

include information about avoiding high current draw.

The "VMVx I/O Supply Voltage (quiet)" section was updated to include this

statement: VMV and VCCI must be connected to the same power supply and V_CCI

pins within a given I/O bank.

The "PUB Push Button" section was updated to include information about leaving

the pin floating if it is not used.

2-228

3-8

The "PTBASE Pass Transistor Base" section was updated to include information

about leaving the pin floating if it is not used.

The "PTEM Pass Transistor Emitter" section was updated to include information

about leaving the pin floating if it is not used.

The heading was incorrect in the "208-Pin PQFP" table. It should be AFS250 and not

AFS090.

5-14

Revision 4

Fusion Family of Mixed Signal FPGAs

Revision

Changes

Page

Advance v0.5

(June 2006)

The low power modes of operation were updated and clarified.

N/A

The AFS1500 digital I/O count was updated in Table 1 • Fusion Family.

i

The AFS1500 digital I/O count was updated in the "Package I/Os: Single-/Double-

Ended (Analog)" table.

ii

The "Voltage Regulator Power Supply Monitor (VRPSM)" was updated.

Figure 2-45 • FlashROM Timing Diagram was updated.

The "256-Pin FBGA" table for the AFS1500 is new.

2-36

2-53

3-12

III

Advance v0.4

(April 2006)

The G was moved in the "Product Ordering Codes" section.

Advance v0.3

(April 2006)

The "Features and Benefits" section was updated.

The "Fusion Family" table was updated.

I

The "Package I/Os: Single-/Double-Ended (Analog)" table was updated.

The "Product Ordering Codes" table was updated.

The "Temperature Grade Offerings" table was updated.

The "General Description" section was updated to include ARM information.

Figure 2-46 • FlashROM Timing Diagram was updated.

The "FlashROM" section was updated.

II

III

IV

1-1

2-58

2-57

2-61

2-64

2-35

2-43

2-45

The "RESET" section was updated.

Figure 2-27 · Real-Time Counter System was updated.

Table 2-19 • Flash Memory Block Pin Names was updated.

Figure 2-33 • Flash Memory Block Diagram was updated to include AUX block

information.

Figure 2-34 • Flash Memory Block Organization was updated to include AUX block

information.

2-46

The note in the "Program Operation" section was updated.

Figure 2-76 • Gate Driver Example was updated.

2-48

2-95

The "Analog Quad ACM Description" section was updated.

2-130

2-94

Information about the maximum pad input frequency was added to the "Gate Driver"

section.

Figure 2-65 • Analog Block Macro was updated.

The "Analog Quad" section was updated.

The "Voltage Monitor" section was updated.

The "Direct Digital Input" section was updated.

The "Current Monitor" section was updated.

2-81

2-84

2-86

2-89

2-90

2-94

Information about the maximum pad input frequency was added to the "Gate Driver"

section.

Revision 4

5-15

Datasheet Information

Revision

Changes

The "Temperature Monitor" section was updated.

EQ 2 is new.

Page

2-96

Advance v0.3

(continued)

2-103

2-102

2-20

The "ADC Description" section was updated.

Figure 2-16 • Fusion Clocking Options was updated.

Table 2-46 · Analog Channel Specifications was updated.

2-118

2-144

The notes in Table 2-72 • Fusion Standard and Advanced I/O – Hot-Swap and 5 V

Input Tolerance Capabilities were updated.

The "Simultaneously Switching Outputs and PCB Layout" section is new.

2-149

2-157

LVPECL and LVDS were updated in Table 2-81 • Fusion Standard and Advanced I/O

Attributes vs. I/O Standard Applications.

LVPECL and LVDS were updated in Table 2-82 • Fusion Pro I/O Attributes vs. I/O

Standard Applications.

2-158

The "Timing Model" was updated.

2-161

N/A

All voltage-referenced Minimum and Maximum DC Input and Output Level tables

were updated.

All Timing Characteristic tables were updated

N/A

Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions was updated.

2-165

Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings

was updated.

2-134

Table 2-93 • I/O Output Buffer Maximum Resistances ¹was updated.

2-171

2-211

The "BLVDS/M-LVDS" section is new. BLVDS and M-LVDS are two new I/O

standards included in the datasheet.

The "CoreMP7 and Cortex-M1 Software Tools" section is new.

2-257

2-165

Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions was updated.

Table 2-79 • Summary of I/O Timing Characteristics – Software Default Settings

was updated.

2-134

Table 2-93 • I/O Output Buffer Maximum Resistances ¹was updated.

2-171

2-211

The "BLVDS/M-LVDS" section is new. BLVDS and M-LVDS are two new I/O

standards included in the datasheet.

The "108-Pin QFN" table for the AFS090 device is new.

The "180-Pin QFN" table for the AFS090 device is new.

The "208-Pin PQFP" table for the AFS090 device is new.

The "256-Pin FBGA" table for the AFS090 device is new.

The "256-Pin FBGA" table for the AFS250 device is new.

3-2

3-4

3-8

3-12

5-16

Revision 4

Fusion Family of Mixed Signal FPGAs

Datasheet Categories


型号：	M1AFS250M1AFS600-2FGG256I
厂家：	Microsemi
描述：	Fusion Family of Mixed Signal FPGAs Fusion系列混合信号FPGA的
文件：	总334页 (文件大小：18785K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M1AFS250M1AFS600-2FGG256I [MICROSEMI]

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