M1AGLPE3000V2-FG896YI

1 – IGLOOe Device Family Overview

General Description

The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOOe devices enables entering and exiting an ultra-low power

mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management

through I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOOe

device is completely functional in the system. This allows the IGLOOe device to control system power

management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal

power.

Nonvolatile flash technology gives IGLOOe devices the advantage of being a secure, low power, single-

chip solution that is Instant On. IGLOOe is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOOe devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock

conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOOe devices have up to 3

million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os.

M1 IGLOOe devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for

implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It

has a three-stage pipeline that offers a good balance between low power consumption and speed when

implemented in an M1 IGLOOe device. The processor runs the ARMv6-M instruction set, has a

configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-

M1 is available for free from Microsemi for use in M1 IGLOOe FPGAs.

The ARM-enabled devices have Microsemi ordering numbers that begin with M1AGLE and do not

support AES decryption.

Flash*Freeze Technology

The IGLOOe device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-

low power Flash*Freeze mode. IGLOOe devices do not need additional components to turn off I/Os or

clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is

combined with in-system programmability, which enables users to quickly and easily upgrade and update

their designs in the final stages of manufacturing or in the field. The ability of IGLOOe V2 devices to

support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus

achieving the lowest total system power.

When the IGLOOe device enters Flash*Freeze mode, the device automatically shuts off the clocks and

inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is

retained.

The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage

solution, and availability of small-footprint, high pin-count packages, make IGLOOe devices the best fit

for portable electronics.

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IGLOOe Device Family Overview

Flash Advantages

Low Power

Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them an

ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on current

surge and no high-current transition period, both of which occur on many FPGAs.

IGLOOe devices also have low dynamic power consumption to further maximize power savings; power is

even further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOOe device the lowest total system power offered by any FPGA.

Security

The nonvolatile, flash-based IGLOOe devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOOe devices incorporate FlashLock, which provides a

unique combination of reprogrammability and design security without external overhead, advantages that

only an FPGA with nonvolatile flash programming can offer.

IGLOOe devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of

protection in the FPGA industry for programmed intellectual property and configuration data. In addition,

all FlashROM data in IGLOOe devices can be encrypted prior to loading, using the industry-leading

AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of

Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOOe devices have a

built-in AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. IGLOOe devices with AES-based security

provide a high level of protection for remote field updates over public networks such as the Internet, and

are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners,

and IP thieves.

Security, built into the FPGA fabric, is an inherent component of the IGLOOe family. The flash cells are

located beneath seven metal layers, and many device design and layout techniques have been used to

make invasive attacks extremely difficult. The IGLOOe family, with FlashLock and AES security, is unique

in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with

industry-standard security, making remote ISP possible. An IGLOOe device provides the best available

security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOOe FPGAs do

not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

Instant On

Flash-based IGLOOe devices support Level 0 of the Instant On classification standard. This feature

helps in system component initialization, execution of critical tasks before the processor wakes up, setup

and configuration of memory blocks, clock generation, and bus activity management. The Instant On

feature of flash-based IGLOOe devices greatly simplifies total system design and reduces total system

cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and

brownouts in system power will not corrupt the IGLOOe device's flash configuration, and unlike SRAM-

based FPGAs, the device will not have to be reloaded when system power is restored. This enables the

reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout

detection, and clock generator devices from the PCB design. Flash-based IGLOOe devices simplify total

system design and reduce cost and design risk while increasing system reliability and improving system

initialization time.

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IGLOOe Low Power Flash FPGAs

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, Flash-based IGLOOe devices allow all functionality to be Instant On; no external boot

PROM is required. On-board security mechanisms prevent access to all the programming information

and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

reprogramming to support future design iterations and field upgrades with confidence that valuable

intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-

standard AES algorithm. The IGLOOe family device architecture mitigates the need for ASIC migration at

higher user volumes. This makes the IGLOOe family a cost-effective ASIC replacement solution,

especially for applications in the consumer, networking/communications, computing, and avionics

markets.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of IGLOOe flash-based

FPGAs. Once it is programmed, the flash cell configuration element of IGLOOe FPGAs cannot be altered

by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user

data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction

(EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOOe family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

IGLOOe family FPGAs utilize design and process techniques to minimize power consumption in all

modes of operation.

Advanced Architecture

The proprietary IGLOOe architecture provides granularity comparable to standard-cell ASICs. The

IGLOOe device consists of five distinct and programmable architectural features (Figure 1-1 on page 4):

•

Flash*Freeze technology

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the IGLOOe core tile as either a three-input lookup table (LUT)

equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the Microsemi ProASIC^®family of third-generation-architecture flash FPGAs.

VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed

throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core

utilization is possible for virtually any design.

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IGLOOe Device Family Overview

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Figure 1-1 • IGLOOe Device Architecture Overview

Flash*Freeze Technology

The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all

SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology

enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the

Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global

I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be

driven or can be toggling without impact on power consumption, and the device retains all core registers,

SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a

certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the

I/O banks, clocks, JTAG pins, or PLL in this mode.

Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power

management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide

when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if

Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power

static and dynamic capabilities of the IGLOOe device. Refer to Figure 1-2 for an illustration of

entering/exiting Flash*Freeze mode.

IGLOOe

Flash*Freeze

FPGA

Mode Control

Flash*Freeze Pin

Figure 1-2 • IGLOOe Flash*Freeze Mode

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Revision 13

IGLOOe Low Power Flash FPGAs

VersaTiles

The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The IGLOOe VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

User Nonvolatile FlashROM

IGLOOe devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be

used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard IGLOOe IEEE 1532 JTAG programming interface. The core

can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The IGLOOe development software solutions, Libero^®System-on-Chip (SoC) and Designer, have

extensive support for the FlashROM. One such feature is auto-generation of sequential programming

files for applications requiring a unique serial number in each part. Another feature allows the inclusion of

static data for system version control. Data for the FlashROM can be generated quickly and easily using

Libero SoC and Designer software tools. Comprehensive programming file support is also included to

allow for easy programming of large numbers of parts with differing FlashROM contents.

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IGLOOe Device Family Overview

SRAM and FIFO

IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-aspect-

ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2,

and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with

different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single

bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation

mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member of the

IGLOOe family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC

(center west side) has a PLL.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time is 300 µs

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}

Global Clocking

IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL

support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

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IGLOOe Low Power Flash FPGAs

Pro I/Os with Advanced I/O Standards

The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,

1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards,

including single-ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight

banks per device (two per side). The configuration of these banks determines the I/O standards

supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced

I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.

Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that

minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

IGLOOe banks support M-LVDS with 20 multi-drop points.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

IGLOOe devices support JEDEC-defined wide range I/O operation. IGLOOe devices support both the

JESD8-B specification, covering 3.0 V and 3.3 V supplies, for an effective operating range of 2.7 V to

3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States

During Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-4 on page 1-8).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

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IGLOOe Device Family Overview

Figure 1-4 • I/O States During Programming Window

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States During programming are saved to the ADB and resulting programming files after

completing programming file generation.

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Revision 13

2 – IGLOOe DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

VJTAG

VPUMP

VCCPLL

Programming voltage

Analog power supply (PLL)

VCCI and VMV³DC I/O buffer supply voltage

VI

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

2

T_STG

Storage temperature

Junction temperature

–65 to +150

+125

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

3. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

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IGLOOe DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_A

Parameter

Commercial

0 to +70

Industrial

–40 to +85

–40 to +100

Units

°C

V

Ambient Temperature

Junction Temperature²

T_J

VCC ³

0 to + 85

1.5 V DC core supply voltage⁴

1.425 to 1.575 1.425 to 1.575

1.14 to 1.575 1.14 to 1.575

1.2 V–1.5 V wide range DC

core voltage^{5, 6}

V

VJTAG

JTAG DC voltage

1.4 to 3.6

3.15 to 3.45

0 to 3.6

1.4 to 3.6

3.15 to 3.45

0 to 3.6

V

VPUMP

Programming voltage⁶

Programming Mode

Operation⁷

VCCPLL⁸Analog power supply (PLL)

1.5 V DC core supply voltage⁴1.425 to 1.575 1.425 to 1.575

1.2 V–1.5 V DC core supply 1.14 to 1.575 1.14 to 1.575

voltage⁵

VCCI and 1.2 V DC supply voltage⁵

1.14 to 1.26

V

VMV⁹

1.2 V wide range DC supply

1.14 to 1.575 1.14 to 1.575

voltage⁵

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.0 V DC supply voltage¹⁰

3.3 V DC supply voltage

LVDS differential I/O

LVPECL differential I/O

Notes:

1.425 to 1.575 1.425 to 1.575

V

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

1.7 to 1.9

2.3 to 2.7

2.7 to 3.6

3.0 to 3.6

2.375 to 2.625 2.375 to 2.625

3.0 to 3.6 3.0 to 3.6

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-21 on page 2-20. VCCI should be at the same voltage within a given I/O bank.

4. For IGLOOe V5 devices

5. For IGLOOe V2 devices only, operating at VCCI  VCC

6. All IGLOOe devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2

devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming.

7. VPUMP can be left floating during operation (not programming mode).

8. VCCPLL pins should be tied to VCC pins. See the "VCCPLA/B/C/D/E/F PLL Supply Voltage" section for further

information.

9. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section for

further information.

10. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

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IGLOOe Low Power Flash FPGAs

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature¹

Programming Program Retention

Maximum Storage

Maximum Operating Junction

Temperature T_J(°C) ²

Product Grade

Commercial

Industrial

Cycles

(biased/unbiased) Temperature T_STG(°C) ²

500

20 years

110

100

500

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

Table 2-4 • Overshoot and Undershoot Limits ^{1, 3}

Average VCCI–GND Overshoot or Undershoot Duration

as a Percentage of Clock Cycle²

Maximum Overshoot/

Undershoot²

VCCI

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at junction temperature at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOOe device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4 and Figure 2-2 on page 2-5.

There are five regions to consider during power-up.

IGLOOe I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and

Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

Revision 13

2-3

IGLOOe DC and Switching Characteristics

•

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup

behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2-

2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOOe FPGA Fabric User’s

Guide for information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential inputs)

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

V_a= 0.85 V ± 0.25 V

Deactivation trip point:

Region 1: I/O buffers are OFF

V_d= 0.75 V ± 0.25 V

VCCI

Activation trip point:

_a= 0.9 V ± 0.3 V

Deactivation trip point:

Min VCCI datasheet specification

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

V_d= 0.8 V ± 0.3 V

Figure 2-1 • V5 – I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 13

IGLOOe Low Power Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Activation trip point:

V = 0.85 V ± 0.2 V

a

Deactivation trip point:

Region 1: I/O buffers are OFF

V = 0.75 V ± 0.2 V

d

VCCI

Activation trip point:

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

V = 0.9 V ± 0.15 V

Deactivation trip point:

a

V = 0.8 V ± 0.15 V

d

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Thermal Characteristics

Introduction

The temperature variable in Microsemi Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5.

P = Power dissipation

Revision 13

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IGLOOe DC and Switching Characteristics

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The absolute maximum junction

temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for an 896-pin FBGA package at commercial temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.206 W

_ja(C/W)

13.6C/W

EQ 2

Table 2-5 • Package Thermal Resistivities

_ja

Package Type

Pin Count

_jcStill Air

200 ft./min.

22.5

500 ft./min.

20.8

Units

Plastic Quad Flat Package (PQFP)

208

8.0

3.8

26.1

16.2

C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

13.3

11.9

Fine Pitch Ball Grid Array (FBGA)

256

484

676

896

3.8

3.2

2.4

26.9

20.5

16.4

13.6

22.8

17.0

13.0

10.4

21.5

15.9

12.0

9.4

C/W

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C,VCC = 1.425 V)

For IGLOOe V2 or V5 devices, 1.5 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0.945

0.876

0.824

0°C

25°C

0.978

0.906

0.852

70°C

1.000

0.927

0.872

85°C

100°C

1.425

0.965

0.893

0.840

1.008

0.934

0.879

1.013

0.940

0.884

1.500

1.575

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, VCC = 1.14 V)

For IGLOOe V2, 1.2 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0.968

0.864

0.793

0°C

25°C

0.991

0.885

0.813

70°C

1.000

0.893

0.821

85°C

1.006

0.898

0.826

100°C

1.010

0.902

0.829

1.14

0.978

0.873

0.803

1.20

1.26

2-6

Revision 13

IGLOOe Low Power Flash FPGAs

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating

voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power

modes usage. Microsemi recommends using the PowerCalculator and SmartPower software

estimation tools to evaluate the projected static and active power based on the user design, power

mode usage, operating voltage, and temperature.

Table 2-8 • Power Supply State per Mode

Power Supply Configurations

Modes/power supplies

Flash*Freeze

VCC

On

VCCPLL

VCCI

On

VJTAG

VPUMP

On/off/floating

Off

On

Off

On

Off

On

Sleep

Off

On

Shutdown

Off

No Flash*Freeze

Note: Off: Power supply level = 0 V

On

On/off/floating

Table 2-9 • Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode*

Core Voltage

1.2 V

AGLE600

AGLE3000

Units

µA

Typical (25°C)

34

72

95

1.5 V

310

µA

Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution,

which is shown in Table 2-13 on page 2-9 and Table 2-14 on page 2-10 (PDC6 and PDC7).

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOOe Sleep Mode*

Core Voltage

AGLE600

AGLE3000

Units

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

1.8

1.9

2.2

2.5

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI/VJTAG= 3.3 V (per bank)

Typical (25°C)

Note: *IDD = N_BANKS× ICCI. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-9

and Table 2-14 on page 2-10 (PDC6 and PDC7).

Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOOe Shutdown Mode*

Core Voltage

AGLE600

AGLE3000

Units

Typical (25°C)

1.2 V / 1.5 V

0

µA

Revision 13

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IGLOOe DC and Switching Characteristics

Table 2-12 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode¹

Core Voltage

AGLE600

AGLE3000

Units

ICCA Current²

Typical (25°C)

1.2 V

1.5 V

28

82

89

µA

320

ICCI or IJTAG Current³

VCCI/VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI/VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

VCCI/VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI/VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI/VJTAG= 3.3 V (per bank)

Typical (25°C)

Notes:

1. IDD = N

× ICCI + ICCA. JTAG counts as one bank when powered.

BANKS

2. Includes VCC and VPUMP and VCCPLL currents.

3. Values do not include I/O static contribution (PDC6 and PDC7).

2-8

Revision 13

IGLOOe Low Power Flash FPGAs

Power per I/O Pin

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

VCCI

(V)

Static Power

PDC6 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

3.3 V LVCMOS Wide Range ³

3.3 V LVCMOS Wide Range – Schmitt trigger ³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.34

24.49

16.34

24.49

4.71

2.5 V LVCMOS

6.13

1.8 V LVCMOS

1.66

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

1.2 V LVCMOS ⁴

1.2 V LVCMOS – Schmitt trigger ⁴

1.2 V LVCMOS Wide Range ⁴

1.2 V LVCMOS Wide Range – Schmitt trigger ⁴

3.3 V PCI

1.78

1.01

0.97

0.60

0.53

0.60

0.53

17.76

19.10

17.76

19.10

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

7.14

3.54

2.91

2.61

0.79

.079

3.26

7.97

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

0.89

1.94

LVPECL

Notes:

1. PDC6 is the static power (where applicable) measured on VCCI.

2. PAC9 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.

4. Applicable for IGLOOe V2 devices only.

Revision 13

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IGLOOe DC and Switching Characteristics

Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

C_LOAD

(pF)

VCCI

(V)

Static Power

PDC7 (mW)²

Dynamic Power

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVCMOS Wide Range ⁴

2.5 V LVCMOS

5

3.3

2.5

1.8

1.5

1.2

–

148.00

83.23

54.58

37.05

17.94

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS (JESD8-11)

1.2 V LVCMOS (JESD8-11) – Wide

Range

3.3 V PCI

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

10

3.3

–

204.61

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.18

105.56

116.60

114.67

131.69

–

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.62

LVPECL

19.42

167.86

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.

2-10

Revision 13

IGLOOe Low Power Flash FPGAs

Power Consumption of Various Internal Resources

Table 2-15 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices

For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device-Specific Dynamic

Contributions (µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

AGLE600

19.7

AGLE3000

12.77

PAC2

Clock contribution of a Global Spine

4.16

1.85

PAC3

Clock contribution of a VersaTile row

0.88

PAC4

Clock contribution of a VersaTile used as a sequential module

First contribution of a VersaTile used as a sequential module

Second contribution of a VersaTile used as a sequential module

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.11

0.057

0.207

0.7

PAC5

PAC6

PAC7

PAC8

PAC9

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

Average contribution of a RAM block during a read operation

Average contribution of a RAM block during a write operation

Dynamic contribution for PLL

See Table 2-13 on page 2-9.

PAC10

PAC11

PAC12

PAC13

See Table 2-14 on page 2-10.

25.00

30.00

2.70

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

calculator or SmartPower in Libero SoC software.

Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Device Specific Static Power (mW)

Parameter

PDC1

Definition

AGLE600

AGLE3000

Array static power in Active mode

See Table 2-12 on page 2-8.

See Table 2-11 on page 2-7.

See Table 2-9 on page 2-7.

1.84

PDC2

Array static power in Static (Idle) mode

Array static power in Flash*Freeze mode

Static PLL contribution

PDC3

PDC4

PDC5

Bank quiescent power (VCCI-dependent)

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-12 on page 2-8.

See Table 2-13 on page 2-9.

See Table 2-14 on page 2-10.

PDC6

PDC7

Revision 13

2-11

IGLOOe DC and Switching Characteristics

Table 2-17 • Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices

For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage

Device-Specific Dynamic

Contributions (µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

AGLE600

12.61

AGLE3000

8.17

PAC2

Clock contribution of a Global Spine

2.66

1.18

PAC3

Clock contribution of a VersaTile row

0.56

PAC4

Clock contribution of a VersaTile used as a sequential module

First contribution of a VersaTile used as a sequential module

Second contribution of a VersaTile used as a sequential module

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.071

0.045

0.186

0.109

0.449

PAC5

PAC6

PAC7

PAC8

PAC9

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

See Table 2-9 on page 2-7.

PAC10

See Table 2-10 on page 2-7

and Table 2-11 on page 2-7.

PAC11

PAC12

PAC13

Average contribution of a RAM block during a read operation

Average contribution of a RAM block during a write operation

Dynamic PLL contribution

25.00

30.00

2.10

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

calculator or SmartPower in Libero SoC software.

Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO Devices

For IGLOOe V2 Devices, 1.2 V DC Core Supply Voltage

Device Specific Static Power (mW)

Parameter

PDC1

Definition

AGLE600

AGLE3000

Array static power in Active mode

See Table 2-12 on page 2-8.

See Table 2-11 on page 2-7.

See Table 2-9 on page 2-7.

0.90

PDC2

Array static power in Static (Idle) mode

Array static power in Flash*Freeze mode

Static PLL contribution

PDC3

PDC4

PDC5

Bank quiescent power (VCCI-dependent)

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-12 on page 2-8.

See Table 2-13 on page 2-9.

See Table 2-14 on page 2-10.

PDC6

PDC7

2-12

Revision 13

IGLOOe Low Power Flash FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on

page 2-15.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on

page 2-15.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-20 on page 2-15. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (PDC1 or PDC2 or PDC3) + N_BANKS* PDC5 + N_INPUTS* PDC6 + N_OUTPUTS* P_DC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the Global Resources chapter in the IGLOOe FPGA Fabric

User's Guide.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in the

"Spine Architecture" section of the Global Resources chapter in the IGLOOe FPGA Fabric

User's Guide.

F

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—P

N

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + ₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-15.

F

_CLKis the global clock signal frequency.

Revision 13

2-13

IGLOOe DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-15.

F

_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-15.

F

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-15.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-15.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-15.

F

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* ₂+ PAC12 * N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations—guidelines are provided in Table 2-20 on

page 2-15.

F

_WRITE-CLOCKis the memory write clock frequency.

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on

page 2-15.

PLL Contribution—P

PLL

P_PLL= PDC4 + PAC13 * F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

2-14

Revision 13

IGLOOe Low Power Flash FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

Revision 13

2-15

IGLOOe DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL

t_PD= 1.19 ns

t_PD= 1.04 ns

t_DP= 1.75 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

LVTTL/LVCMOS 3.3 V

Output drive strength = 12 mA

High slew rate

t_DP= 3.13 ns

t_PD= 1.77 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

LVTTL/LVCMOS 3.3 V

Output drive strength = 24 mA

High slew rate

t_DP= 2.76 ns

t

_PY= 1.45 ns

t_PD= 1.33 ns

LVPECL

D

Q

I/O Module

(Non-Registered)

Combinational Cell

Y

LVCMOS 1.5V

Output drive strength = 12 mA

High slew

t

_ICLKQ= 0.43 ns

t_DP= 3.30 ns

_ISUD= 0.47 ns

t_PD= 0.85 ns

Input LVTTL/LVCMOS 3.3 V

Clock

I/O Module

(Registered)

Register Cell

Combinational Cell

t_PY= 1.10 ns

Y

D

Q

D

Q

D

Q

GTL+ 3.3V

_DP= 1.85 ns

I/O Module

(Non-Registered)

t_PD= 0.90 ns

t

_CLKQ= 0.90 ns

t

_CLKQ= 0.90 ns

t

_OCLKQ= 1.02 ns

LVDS,

BLVDS,

M-LVDS

_SUD= 0.82 ns

t_SUD= 0.82 ns

t_OSUD= 0.52 ns

Input LVTTL/LVCMOS 3.3 V

Clock

Input LVTTL/LVCMOS 3.3 V

Clock

t_PY= 1.62 ns

t_PY= 1.10 ns

Figure 2-3 • Timing Model

Operating Conditions: Std. Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices

2-16

Revision 13

IGLOOe Low Power Flash FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t_PY= MAX(t_PY(R), t_PY(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

Vtrip

VCC

PAD

VIL

50%

Y

t_PY

(F)

GND

(R)

t_PYS

(F)

t_PYS

(R)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

Revision 13

2-17

IGLOOe DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

2-18

Revision 13

IGLOOe Low Power Flash FPGAs

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

Revision 13

2-19

IGLOOe DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions

Equivalent

Software

Default

VIL

VIH

VOL

VOH

IOL¹IOH¹

I/O

Drive

Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Standard Strength Strength²Rate

V

mA mA

3.3 V

LVTTL /

3.3 V

12 mA

High –0.3

0.8

2

3.6

0.4

2.4

12 12

LVCMOS

3.3 V

100 µA

12 mA

0.8

0.7

2

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide

Range³

2.5 V

LVCMOS

12 mA

2 mA

12 mA

2 mA

1.7

0.7

1.7

12 12

1.8 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45 12 12

1.5 V

LVCMOS

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

1.2 V

2

LVCMOS

1.2 V

100 µA

2 mA

High –0.3 0.3 * VCCI

0.7 * VCCI

3.6

0.1

VCCI – 0.1 0.1 0.1

LVCMOS

Wide

Range ⁴

3.3 V PCI

Per PCI Specification

Per PCI-X Specification

3.3VPCI-X

3.3 V GTL 20 mA⁵20 mA⁵High –0.3 VREF – 0.05 VREF + 0.05 3.6

2.5 V GTL 20 mA⁵20 mA⁵High –0.3 VREF – 0.05 VREF + 0.05 3.6

0.4

0.6

0.4

–

20 20

35 35

33 33

–

3.3 V GTL+ 35 mA

2.5 V GTL+ 33 mA

35 mA

33 mA

8 mA

High –0.3 VREF – 0.1 VREF + 0.1 3.6

–

HSTL (I)

8 mA

VCCI – 0.4

8

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Output drive strength is below JEDEC specification.

6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx.

2-20

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels (continued)

Applicable to Commercial and Industrial Conditions

Equivalent

Software

Default

VIL

VIH

VOL

VOH

IOL¹IOH¹

mA mA

I/O

Drive

Slew Min.

Max.

Min.

Max.

V

Max.

V

Min.

V

Standard Strength Strength²Rate

V

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA⁵15 mA⁵High –0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

0.54

0.35

0.7

VCCI – 0.4 15 15

VCCI – 0.62 15 15

VCCI – 0.43 18 18

VCCI – 1.1 14 14

VCCI – 0.9 21 21

15 mA

18 mA

14 mA

21 mA

15 mA

18 mA

14 mA

21 mA

High –0.3 VREF – 0.2 VREF + 0.2 3.6

0.5

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-12 specification.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Output drive strength is below JEDEC specification.

6. Output Slew Rates can be extracted from IBIS Models, http://www.microsemi.com/soc/download/ibis/default.aspx.

Revision 13

2-21

IGLOOe DC and Switching Characteristics

Table 2-22 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

IIL³

Industrial²

IIH⁴

µA

10

IIL³

µA

15

IIH⁴

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS⁵

1.2 V LVCOMS Wide Range⁵

3.3 V PCI

µA

10

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Commercial range (0°C < T < 70°C)

A

2. Industrial range (–40°C < T < 85°C)

A

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

5. Applicable to V2 devices operating at VCCI  VCC.

2-22

Revision 13

IGLOOe Low Power Flash FPGAs

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-23 • Summary of AC Measuring Points

Input Reference

Voltage (VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip

Point (Vtrip)

Standard

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

–

1.4 V

–

1.2 V

1.8 V LVCMOS

–

0.90 V

1.5 V LVCMOS

–

0.75 V

1.2 V LVCMOS*

–

0.6 V

1.2 V LVCMOS – Wide Range*

3.3 V PCI

–

0.6 V

–

0.285 * VCCI (RR)

0.615 * VCCI (FF))

0.285 * VCCI (RR)

0.615 * VCCI (FF)

VREF

–

3.3 V PCI-X

–

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Note: *Applicable to V2 devices ONLY operating in the 1.2 V core range.

Revision 13

2-23

IGLOOe DC and Switching Characteristics

Table 2-24 • I/O AC Parameter Definitions

Parameter

Definition

t_DP

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer with Schmitt trigger disabled

Data to Output Buffer delay through the I/O interface

t_DOUT

t_EOUT

t_DIN

t_PYS

t_HZ

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Pad to Data delay through the Input Buffer with Schmitt trigger enabled

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

t_ZH

t_LZ

t_ZL

Enable to Pad delay through the Output Buffer—Z to LOW

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

2-24

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

Std. Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI (per standard)

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12

12 High

5

–

0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns

0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87 ns

3.3 V LVCMOS 100 µA 12 High

Wide Range^{1, 2}

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12

12 High

5

–

.097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns

0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns

0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns

Per

PCI

–

High 10 25 ³0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns

spec

3.3 V PCI-X

Per

PCI-X

spec

–

High 10 25 ³0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20⁴

35

33

8

–

High 10 25 0.97 1.78 0.19 2.35

High 10 25 0.97 1.85 0.19 1.98

High 10 25 0.97 1.80 0.19 1.32

High 10 25 0.97 1.92 0.19 1.26

High 20 50 0.97 2.67 0.18 1.72

High 20 25 0.97 2.55 0.18 1.72

High 30 50 0.97 1.86 0.19 1.12

High 30 25 0.97 1.89 0.19 1.12

High 30 50 0.97 2.00 0.19 1.06

High 30 25 0.97 1.81 0.19 1.06

–

0.66 1.80 1.78

0.66 1.89 1.82

0.66 1.84 1.77

0.66 1.96 1.80

0.66 2.72 2.67

0.66 2.60 2.34

0.66 1.90 1.68

0.66 1.93 1.62

0.66 2.04 1.67

0.66 1.85 1.55

–

5.39 5.38 ns

5.49 5.42 ns

5.44 5.36 ns

5.56 5.40 ns

6.32 6.26 ns

6.20 5.93 ns

5.50 5.28 ns

5.53 5.22 ns

5.64 5.27 ns

5.45 5.14 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15

18

14

21

24

High

–

0.97 1.73 0.19 1.62

0.97 1.65 0.18 1.42

–

ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications. See Figure 2-12 on page 2-49 for

connectivity. This resistor is not required during normal operation.

4. Output drive strength is below JEDEC specification.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-25

IGLOOe DC and Switching Characteristics

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

Std. Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI (per standard)

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12

12 High

5

–

1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82 ns

1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46 ns

3.3 V LVCMOS 100 µA 12 High 35

Wide Range^1,2

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

12

2

12 High

5

–

1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33 8.00 ns

1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19 ns

1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93 8.49 ns

1.55 4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71 9.24 ns

2

High

1.2 V LVCMOS 100 µA

Wide Range^1,3

3.3 V PCI

PerPCI

spec

–

High 10 25⁴1.55 2.76 0.26 1.19 1.63 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns

High 10 25⁴1.55 2.76 0.25 1.22 1.58 1.10 2.79 2.16 3.29 3.97 8.58 7.94 ns

3.3 V PCI-X

Per

PCI-X

spec

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20⁵

35

33

8

–

High 10 25 1.55 2.08 0.25 2.76

High 10 25 1.55 2.17 0.25 2.35

High 10 25 1.55 2.12 0.25 1.62

High 10 25 1.55 2.25 0.25 1.55

High 20 50 1.55 3.09 0.25 1.95

High 20 25 1.55 2.94 0.25 1.95

High 30 50 1.55 2.18 0.25 1.40

High 30 25 1.55 2.21 0.25 1.40

High 30 50 1.55 2.33 0.25 1.33

High 30 25 1.55 2.13 0.25 1.33

–

1.10 2.09 2.08

1.10 2.20 2.13

1.10 2.14 2.07

1.10 2.27 2.10

1.10 3.11 3.09

1.10 2.98 2.74

1.10 2.21 2.03

1.10 2.24 1.97

1.10 2.36 2.02

1.10 2.16 1.89

–

7.88 7.87 ns

7.99 7.91 ns

7.93 7.85 ns

8.06 7.89 ns

8.90 8.88 ns

8.77 8.53 ns

7.99 7.82 ns

8.03 7.76 ns

8.15 7.81 ns

7.94 7.67 ns

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15

18

14

21

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-49 for

connectivity. This resistor is not required during normal operation.

5. Output drive strength is below JEDEC specification.

6. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-26

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings (continued)

Std. Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI (per standard)

I/O Standard

LVDS

24

–

High

–

1.55 2.26 0.25 1.95

1.55 2.17 0.25 1.70

–

ns

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-49 for

connectivity. This resistor is not required during normal operation.

5. Output drive strength is below JEDEC specification.

6. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-27

IGLOOe DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-27 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

VIN = 0, f = 1.0 MHz

8

C_INCLK

Input capacitance on the clock pin

pF

Table 2-28 • I/O Output Buffer Maximum Resistances¹

Standard

Drive Strength

4 mA

R

_PULL-DOWN()²

R_PULL-UP()³

3.3 V LVTTL / 3.3 V LVCMOS

100

50

25

17

11

300

150

75

8 mA

12 mA

16 mA

50

24 mA

33

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

4 mA

8 mA

100

50

200

100

50

12 mA

16 mA

24 mA

2 mA

25

20

40

11

22

1.8 V LVCMOS

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

16 mA

2 mA

20

22

20

22

1.5 V LVCMOS

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

2 mA

33

37

1.2 V LVCMOS⁴

158

164

1.2 V LVCMOS Wide Range⁴

100 µA

Same as regular

1.2 V LVCMOS

Same as regular

1.2 V LVCMOS

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website at

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2.

3.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY.

5. Output drive strength is below JEDEC specification.

2-28

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-28 • I/O Output Buffer Maximum Resistances¹(continued)

Standard

Drive Strength

R

_PULL-DOWN()²

R_PULL-UP()³

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

25

75

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁵

35 mA

33 mA

8 mA

11

14

12

15

50

25

27

13

44

18

–

50

25

31

15

69

32

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA

18 mA

14 mA

21 mA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website at

http://www.microsemi.com/soc/techdocs/models/ibis.html.

2.

3.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Applicable to IGLOOe V2 devices operating in the 1.2 V core range ONLY.

5. Output drive strength is below JEDEC specification.

Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R(_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCI

Minimum

Maximum

45 k

Minimum

10 k

Maximum

45 k

3.3 V

10 k

11 k

18 k

19 k

25 k

19 k

3.3 V (wide range I/Os)

45 k

10 k

45 k

2.5 V

55 k

12 k

74 k

1.8 V

70 k

17 k

110 k

140 k

150 k

1.5 V

90 k

19 k

1.2 V

110 k

25 k

1.2 V (wide range I/Os)

19 k

Notes:

1.

2.

R

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN)

= (VOLspec) / I

(WEAK PULL-DOWN-MAX)

(WEAK PULL-DOWN-MIN)

Revision 13

2-29

IGLOOe DC and Switching Characteristics

Table 2-30 • I/O Short Currents IOSH/IOSL

Drive Strength

4 mA

IOSH (mA)*

IOSL (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

25

51

27

54

8 mA

12 mA

103

132

268

109

127

181

16 mA

24 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

4 mA

8 mA

16

32

65

83

169

9

18

37

74

87

124

11

12 mA

16 mA

24 mA

2 mA

1.8 V LVCMOS

4 mA

17

35

45

91

13

25

32

66

20

22

44

51

74

16

33

39

55

26

6 mA

8 mA

12 mA

16 mA

2 mA

1.5 V LVCMOS

4 mA

6 mA

8 mA

12 mA

2 mA

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI/PCIX

100 µA

Per PCI/PCI-X

Specification

Per PCI Curves

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

25 mA

35 mA

33 mA

8 mA

268

169

268

169

32

181

124

181

124

39

HSTL (II)

15 mA

18 mA

14 mA

21 mA

66

55

SSTL2 (I)

83

87

SSTL2 (II)

SSTL3 (I)

169

51

124

54

SSTL3 (II)

Note: T_J= 100°C

103

109

2-30

Revision 13

IGLOOe Low Power Flash FPGAs

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-31 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-32 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration

Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

1.2 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

40 mV

Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*

Input Rise/Fall Time

Input Buffer

(min.)

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement

10 ns*

20 years

(100°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement

No requirement, but input noise

voltage cannot exceed Schmitt

hysteresis.

20 years

(100°C)

HSTL/SSTL/GTL

No requirement

10 ns*

10 years

(100°C)

LVDS/B-LVDS/M-LVDS/LVPECL

10 ns*

10 years

(100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

Revision 13

2-31

IGLOOe DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is

supported as part of the 3.3 V LVTTL support.

Table 2-34 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSH

IOSL

IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

Drive Strength

4 mA

V

mA mA

µA⁴µA⁴

10 10

–0.3

0.8

2

3.6

0.4

2.4

4

8

4

8

25

51

27

54

8 mA

12 mA

12 12

16 16

24 24

103

132

268

109

127

181

16 mA

24 mA

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-35 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

3.3

1.4

–

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

2-32

Revision 13

IGLOOe Low Power Flash FPGAs

Timing Characteristics

1.5 V DC Core Voltage

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed

Grade

Unit

s

Drive Strength

4 mA

t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHS

0.97 4.90 0.18 1.08 1.34 0.66 5.00 3.99 2.27 2.16 8.60 7.59

0.97 4.05 0.18 1.08 1.34 0.66 4.13 3.45 2.53 2.65 7.73 7.05

0.97 3.44 0.18 1.08 1.34 0.66 3.51 3.05 2.71 2.95 7.11 6.64

0.97 3.27 0.18 1.08 1.34 0.66 3.34 2.96 2.74 3.04 6.93 6.55

0.97 3.18 0.18 1.08 1.34 0.66 3.24 2.97 2.79 3.36 6.84 6.56

Std.

ns

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

0.97 2.85 0.18 1.08 1.34 0.66 2.92 2.27 2.27 2.27 6.51 5.87 ns

0.97 2.39 0.18 1.08 1.34 0.66 2.44 1.88 2.53 2.76 6.03 5.47 ns

0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns

0.97 2.08 0.18 1.08 1.34 0.66 2.12 1.65 2.75 3.17 5.72 5.25 ns

0.97 2.10 0.18 1.08 1.34 0.66 2.14 1.60 2.80 3.49 5.74 5.20 ns

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-33

IGLOOe DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 5.54 0.26 1.31 1.58 1.10 5.63 4.53 2.79 2.87 11.42 10.32 ns

8 mA

1.55 4.60 0.26 1.31 1.58 1.10 4.67 3.94 3.09 3.45 10.45 9.73

1.55 3.93 0.26 1.31 1.58 1.10 3.99 3.51 3.28 3.82 9.77 9.29

1.55 3.74 0.26 1.31 1.58 1.10 3.79 3.41 3.32 3.92 9.58 9.20

1.55 3.64 0.26 1.31 1.58 1.10 3.69 3.42 3.38 4.30 9.48 9.21

ns

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength Speed Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

1.55 3.26 0.26 1.31 1.58 1.10 3.33 2.67 2.79 3.01 9.12 8.46

1.55 2.77 0.26 1.31 1.58 1.10 2.80 2.24 3.09 3.59 8.59 8.03

1.55 2.47 0.26 1.31 1.58 1.10 2.51 2.04 3.28 3.97 8.29 7.82

1.55 2.42 0.26 1.31 1.58 1.10 2.46 2.00 3.33 4.08 8.24 7.79

1.55 2.45 0.26 1.31 1.58 1.10 2.48 1.95 3.38 4.46 8.26 7.73

ns

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-34

Revision 13

IGLOOe Low Power Flash FPGAs

3.3 V LVCMOS Wide Range

Table 2-40 • Minimum and Maximum DC Input and Output Levels

3.3 V LVCMOS Wide Range

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Equivalent

Software Default

Drive

Strength

Drive Strength Min. Max. Min. Max

Max.

(V)

Min.

(V)

Max.

Option³

(V)

3.6

µA µA (mA)⁴(mA)⁴µA⁵µA⁵

100 µA

Notes:

2 mA

–0.3 0.8

2

0.2

VDD – 0.2 100 100

25

27

10 10

4 mA

2

6 mA

2

51

54

8 mA

2

51

54

12 mA

16 mA

24 mA

2

103

132

268

109

127

181

2

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is

larger when operating outside recommended ranges.

3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

4. Currents are measured at 85°C junction temperature.

5. All LVCMOS 3.3 V software macros supports LVCMOS 3.3 V wide range as specified in the JDEC8a specification.

6. Software default selection highlighted in gray.

Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

3.3

1.4

–

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Revision 13

2-35

IGLOOe DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-42 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Strength Speed

Option¹

4 mA

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

Std.

0.97 7.26 0.18 1.42 1.84 0.66 7.28 5.78 3.18 2.93 10.88 9.38

0.97 5.94 0.18 1.42 1.84 0.66 5.96 4.96 3.59 3.69 9.56 8.56

0.97 5.00 0.18 1.42 1.84 0.66 5.02 4.34 3.86 4.16 8.62 7.94

0.97 4.73 0.18 1.42 1.84 0.66 4.75 4.21 3.92 4.29 8.35 7.81

0.97 4.59 0.18 1.42 1.84 0.66 4.61 4.23 3.99 4.78 8.21 7.82

ns

8 mA

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-43 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Strength Speed

Option¹Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std.

0.97 4.10 0.18 1.42 1.84 0.66 4.12 3.17 3.18 3.11 7.71 6.77

0.97 3.37 0.18 1.42 1.84 0.66 3.39 2.57 3.59 3.87 6.99 6.16

0.97 2.96 0.18 1.42 1.84 0.66 2.98 2.28 3.86 4.36 6.58 5.87

0.97 2.90 0.18 1.42 1.84 0.66 2.92 2.22 3.93 4.49 6.51 5.82

0.97 2.92 0.18 1.42 1.84 0.66 2.94 2.15 4.00 4.99 6.54 5.75

ns

12 mA

16 mA

24 mA

1. The minimum drive strength for any or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3. Software default selection highlighted in gray.

2-36

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-44 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Strength Option¹

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std.

1.55 8.14 0.26 1.66 2.14 1.10 8.14 6.46 3.80 3.79 13.93 12.25 ns

1.55 6.68 0.26 1.66 2.14 1.10 6.68 5.57 4.25 4.69 12.47 11.36 ns

1.55 5.65 0.26 1.66 2.14 1.10 5.65 4.91 4.55 5.25 11.44 10.69 ns

1.55 5.36 0.26 1.66 2.14 1.10 5.36 4.76 4.61 5.41 11.14 10.55 ns

1.55 5.20 0.26 1.66 2.14 1.10 5.20 4.78 4.69 6.00 10.99 10.56 ns

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-45 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Strength Option¹

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std.

1.55 4.65 0.26 1.66 2.14 110 4.65 3.64 3.80 4.00 10.44 9.43

1.55 3.85 0.26 1.66 2.14 1.10 3.85 2.99 4.25 4.91 9.64 8.77

1.55 3.40 0.26 1.66 2.14 1.10 3.40 2.68 4.55 5.49 9.19 8.46

1.55 3.33 0.26 1.66 2.14 1.10 3.33 2.62 4.62 5.65 9.11 8.41

1.55 3.36 0.26 1.66 2.14 1.10 3.36 2.54 4.71 6.24 9.15 8.32

ns

12 mA

16 mA

24 mA

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

3. Software default selection highlighted in gray.

Revision 13

2-37

IGLOOe DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

Max.

mA³

mA mA

µA⁴µA⁴

10 10

4 mA

–0.3

0.7

1.7

3.6

0.7

1.7

4

8

4

8

16

32

18

37

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

65

74

83

87

169

124

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

2.5

1.2

–

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

2-38

Revision 13

IGLOOe Low Power Flash FPGAs

Timing Characteristics

1.5 V DC Core Voltage

Table 2-48 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed

Grade

Unit

s

Drive Strength

4 mA

t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHS

0.97 5.55 0.18 1.31 1.41 0.66 5.66 4.75 2.28 1.96 9.26 8.34

0.97 4.58 0.18 1.31 1.41 0.66 4.67 4.07 2.58 2.53 8.27 7.66

0.97 3.89 0.18 1.31 1.41 0.66 3.97 3.58 2.78 2.91 7.56 7.17

0.97 3.68 0.18 1.31 1.41 0.66 3.75 3.47 2.82 3.01 7.35 7.06

0.97 3.59 0.18 1.31 1.41 0.66 3.66 3.48 2.88 3.37 7.26 7.08

Std.

ns

8 mA

12 mA

16 mA

24 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-49 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed

Grade

Unit

s

Drive Strength

4 mA

t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHS

0.97 2.94 0.18 1.31 1.41 0.66 3.00 2.68 2.28 2.03 6.60 6.27

0.97 2.45 0.18 1.31 1.41 0.66 2.50 2.12 2.58 2.62 6.10 5.72

0.97 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45

0.97 2.10 0.18 1.31 1.41 0.66 2.15 1.80 2.82 3.08 5.75 5.40

0.97 2.11 0.18 1.31 1.41 0.66 2.16 1.74 2.88 3.47 5.75 5.33

Std.

ns

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-39

IGLOOe DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-50 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

1.55 6.25 0.26 1.55 1.77 1.10 6.36 5.34 2.81 2.63 12.14 11.13

1.55 5.18 0.26 1.55 1.77 1.10 5.26 4.61 3.13 3.32 11.05 10.39 ns

t_LZt_HZt_ZLSt_ZHSUnits

4 mA

Std.

ns

8 mA

12 mA

16 mA

24 mA

1.55 4.42 0.26 1.55 1.77 1.10 4.49 4.08 3.36 3.76 10.28 9.86

1.55 4.19 0.26 1.55 1.77 1.10 4.25 3.96 3.40 3.89 10.04 9.75

1.55 4.09 0.26 1.55 1.76 1.10 4.15 3.97 3.47 4.32 9.94 9.76

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

1.55 3.38 0.26 1.55 1.77 1.10 3.42 3.11 2.81 2.72 9.21

1.55 2.83 0.26 1.55 1.77 1.10 2.87 2.51 3.13 3.42 8.66

1.55 2.51 0.26 1.55 1.77 1.10 2.54 2.22 3.36 3.85 8.33

1.55 2.45 0.26 1.55 1.77 1.10 2.48 2.16 3.40 3.97 8.27

1.55 2.46 0.26 1.55 1.77 1.10 2.49 2.09 3.47 4.44 8.28

8.89

8.30

8.00

7.95

7.88

ns

8 mA

12 mA

16 mA

24 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-40

Revision 13

IGLOOe Low Power Flash FPGAs

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-52 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max. Max.

Min.

V

Max.

mA³

V

mA mA mA³

µA⁴µA⁴

10 10

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45 VCCI – 0.45

2

4

6

8

2

4

6

8

9

11

22

44

51

74

4 mA

17

35

45

91

6 mA

8 mA

12 mA

16 mA

Notes:

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-53 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

1.8

0.9

–

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Revision 13

2-41

IGLOOe DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-54 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

0.97 7.33 0.18 1.27 1.59 0.66 7.47 6.18 2.34 1.18 11.07 9.77

0.97 6.07 0.18 1.27 1.59 0.66 6.20 5.25 2.69 2.42 9.79 8.84

0.97 5.18 0.18 1.27 1.59 0.66 5.29 4.61 2.93 2.88 8.88 8.21

0.97 4.88 0.18 1.27 1.59 0.66 4.98 4.48 2.99 3.01 8.58 8.08

0.97 4.80 0.18 1.27 1.59 0.66 4.89 4.49 3.07 3.47 8.49 8.09

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-55 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

0.97 3.43 0.18 1.27 1.59 0.66 3.51 3.39 2.33 1.19 7.10

0.97 2.83 0.18 1.27 1.59 0.66 2.89 2.59 2.69 2.49 6.48

0.97 2.45 0.18 1.27 1.59 0.66 2.51 2.19 2.93 2.95 6.10

0.97 2.38 0.18 1.27 1.59 0.66 2.43 2.12 2.98 3.08 6.03

0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02

6.98

6.18

5.79

5.71

5.62

ns

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-42

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-56 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

1.55 8.21 0.26 1.53 1.96 1.10 8.35 6.88 2.87 1.70 14.14 12.67 ns

1.55 6.83 0.26 1.53 1.96 1.10 6.94 5.88 3.27 3.18 12.73 11.67 ns

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

1.55 5.85 0.26 1.53 1.96 1.10 5.94 5.19 3.53 3.37 11.73 10.98 ns

1.55 5.52 0.26 1.53 1.96 1.10 5.61 5.06 3.59 3.88 11.39 10.84 ns

1.55 5.42 0.26 1.53 1.96 1.10 5.51 5.06 3.68 4.44 11.30 10.85 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-57 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Speed

Drive Strength Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

Std.

1.55 3.82 0.26 1.53 1.96 1.10 3.98 3.87 2.86 1.72 9.76 9.66

1.55 3.25 0.26 1.53 1.96 1.10 3.30 3.01 3.26 3.26 9.08 8.79

1.55 2.84 0.26 1.53 1.96 1.10 2.88 2.58 3.53 3.81 8.66 8.37

1.55 2.76 0.26 1.53 1.96 1.10 2.80 2.50 3.58 3.97 8.58 8.29

1.55 2.75 0.26 1.53 1.96 1.10 2.78 2.40 3.68 4.56 8.57 8.19

ns

4 mA

6 mA

8 mA

12 mA

16 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-43

IGLOOe DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-58 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH IOSL IIL¹IIH²

Max. Max.

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.25 * VCCI 0.75 * VCCI

2

4

6

8

2

4

6

8

13

25

32

66

16

33

39

55

10 10

0.25 * VCCI 0.75 * VCCI 12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

1.5

0.75

–

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

2-44

Revision 13

IGLOOe Low Power Flash FPGAs

Timing Characteristics

1.5 V DC Core Voltage

Table 2-60 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

0.97 7.61 0.18 1.47 1.77 0.66 7.76 6.33 2.81 2.34 11.36 9.92

0.97 6.54 0.18 1.47 1.77 0.66 6.67 5.56 3.09 2.88 10.26 9.16

0.97 6.15 0.18 1.47 1.77 0.66 6.27 5.42 3.15 3.02 9.87 9.02

0.97 6.07 0.18 1.47 1.77 0.66 6.20 5.42 2.64 3.56 9.79 9.02

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-61 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

0.97 3.25 0.18 1.47 1.77 0.66 3.32 3.00 2.80 2.43 6.92 6.59

0.97 2.81 0.18 1.47 1.77 0.66 2.87 2.51 3.08 2.97 6.46 6.10

0.97 2.72 0.18 1.47 1.77 0.66 2.78 2.41 3.14 3.12 6.37 6.01

0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 13

2-45

IGLOOe DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-62 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

1.55 8.53 0.26 1.72 2.16 1.10 8.67 7.05 3.39 3.09 14.46 12.83 ns

1.55 7.34 0.26 1.72 2.16 1.10 7.46 6.22 3.70 3.73 13.25 12.01 ns

1.55 6.91 0.26 1.72 2.16 1.10 7.03 6.07 3.77 3.90 12.82 11.85

1.55 6.83 0.26 1.72 2.16 1.10 6.94 6.07 2.91 4.54 12.73 11.86

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-63 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

1.55 3.72 0.26 1.72 2.16 1.10 3.78 3.45 3.38 3.19 9.56

1.55 3.23 0.26 1.72 2.16 1.10 3.27 2.92 3.69 3.83 9.06

1.55 3.13 0.26 1.72 2.16 1.10 3.18 2.82 3.76 4.01 8.96

1.55 3.10 0.26 1.72 2.16 1.10 3.15 2.70 3.86 4.68 8.93

9.24

8.71

8.61

8.49

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-46

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V

applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-64 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

1.2 V

LVCMOS¹

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSH

Max.

IOSL IIL²IIH³

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA

mA⁴

mA⁴µA⁵µA⁵

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

2

20

26

10 10

Notes:

1. Applicable to V2 devices ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

0

1.2

0.6

–

5

Note: *Measuring point = Vtrip_.See Table 2-23 on page 2-23 for a complete table of trip points.

Revision 13

2-47

IGLOOe DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-66 • 1.2 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

ns

2 mA

Std. 1.55

9.92 0.26 2.09 2.95 1.10 9.53 7.48 4.02 3.67 15.31 13.26

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Table 2-67 • 1.2 LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Speed

Drive Strength Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

9.24 ns

2 mA

Std. 1.55

4.06 0.26 2.09 2.95 1.10 3.92 3.46 4.01 3.79 9.71

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

1.2 V LVCMOS Wide Range

Table 2-68 • Minimum and Maximum DC Input and Output Levels

1.2 V LVCMOS

Wide Range¹

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL²IIH³

Equivalent

Software

Default

Drive

Strength Min.

Max.

(V)

Min.

(V)

Max

(V)

Max.

(V)

Min.

(V)

Max. Max.

Strength Option⁴(V)

µA µA (mA)⁵(mA)⁵µA⁶µA⁶

100 µA

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 20

26

10 10

Notes:

1. Applicable to V2 devices ONLY.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI . Input current is

larger when operating outside recommended ranges.

4. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

5. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

6. Currents are measured at 85°C junction temperature.

7. Software default selection highlighted in gray.

Timing Characteristics

Refer to LVCMOS 1.2 V (normal range) "Timing Characteristics" on page 2-48 for worst-case timing.

2-48

Revision 13

IGLOOe Low Power Flash FPGAs

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

VIH

VOL

VOH IOL IOH

IOSH

IOSL

IIL¹IIH²

Min.

V

Max. Min., Max. Max.

Min.

V

Max.

mA³

Max.

mA³

Drive Strength

V

mA mA

µA⁴µA⁴

Per PCI

Per PCI curves

10 10

specification

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable

path characterization are described in Figure 2-12.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

10 pF for t_HZ/ t_LZ

Figure 2-12 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-70.

Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C

_LOAD(pF)

0

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

–

10

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Revision 13

2-49

IGLOOe DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-71 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_PYSt_EOUT

0.66

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

ns

Std.

0.97

2.38 0.18 0.96 1.42

2.43 1.80 2.72 3.08 6.03 5.39

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-72 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_PYSt_EOUT

1.10

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

ns

Std.

1.55

2.76 0.26 1.19 1.63

2.79 2.16 3.29 3.97 8.58 7.94

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-50

Revision 13

IGLOOe Low Power Flash FPGAs

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-73 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

VIL

Max.

VIH

VOL

VOH IOL IOH IOSL

IOSH IIL¹IIH²

Max.

Drive

Strength

Min.

V

Min.

V

Max.

V

Max

V

Min.

V

Max.

mA³

V

mA mA

mA³

µA⁴µA⁴

20 mA⁵

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

268

181

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Output drive strength is below JEDEC specification.

VTT

GTL

25

Test Point

10 pF

Figure 2-13 • AC Loading

Table 2-74 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V) Measuring Point* (V) VREF (typ.) (V)

VREF + 0.05 0.8 0.8

VTT (typ.) (V)

C

_LOAD(pF)

VREF – 0.05

1.2

10

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Revision 13

2-51

IGLOOe DC and Switching Characteristics

Timing Characteristics

1.5 V DC Core Voltage

Table 2-75 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

0.98

1.83

0.19

2.41

0.67

1.84

1.83

5.47

5.46

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-76 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.09

0.26

2.75

1.10

2.10

2.09

7.91

7.89

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-52

Revision 13

IGLOOe Low Power Flash FPGAs

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-77 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

VIL

VIH

VOL VOH IOL IOH

IOSH

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max. Max.

Min.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

20 mA⁵

–0.3 VREF – 0.05 VREF + 0.05 3.6

0.4

–

20 20

169

124

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Output drive strength is below JEDEC specification.

VTT

GTL

25

Test Point

10 pF

Figure 2-14 • AC Loading

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)

0.8 0.8 1.2

C

_LOAD(pF)

VREF – 0.05

VREF + 0.05

10

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-79 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

0.98

1.90

0.19

2.04

0.67

1.94

1.87

5.57

5.50

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-80 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.16

0.26

2.35

1.10

2.20

2.13

8.01

7.94

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-53

IGLOOe DC and Switching Characteristics

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V

Table 2-81 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

VIL

VIH

VOL

VOH IOL IOH IOSH

IOSL IIL¹IIH²

Max.

Drive

Strength

Min.

V

Max.

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

V

mA mA

mA³

µA⁴µA⁴

35 mA

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.6

–

35 35

268

181

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-15 • AC Loading

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V)

1.0 1.0 1.5

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

10

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-83 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

0.98

1.85

0.19

1.35

0.67

1.88

1.81

5.51

5.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-84 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.11

0.26

1.61

1.10

2.15

2.07

7.95

7.88

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-54

Revision 13

IGLOOe Low Power Flash FPGAs

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-85 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+

VIL

VIH

VOL

VOH IOL IOH

IOSH

IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

Max.

mA mA

mA³µA⁴µA⁴

33 mA

–0.3

VREF – 0.1 VREF + 0.1

3.6

0.6

–

33 33

169

124

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-16 • AC Loading

Table 2-86 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

10

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-87 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

5.47

Units

Std.

0.98

1.97

0.19

1.29

0.67

2.00

1.84

5.63

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-88 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.23

0.26

1.55

1.10

2.28

2.11

8.08

7.91

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-55

IGLOOe DC and Switching Characteristics

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output

buffer.

Table 2-89 • Minimum and Maximum DC Input and Output Levels

HSTLClass

I

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

V

mA mA

mA³

µA⁴µA⁴

8 mA

–0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

VCCI – 0.4

8

32

39

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V_TT

HSTL

Class I

50

Test Point

20 pF

Figure 2-17 • AC Loading

Table 2-90 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-91 • HSTL Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

0.98

2.74

0.19

1.77

0.67

2.79

2.73

6.42

6.36

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-92 • HSTL Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

3.10

0.26

1.94

1.10

3.12

3.10

8.93

8.91

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-56

Revision 13

IGLOOe Low Power Flash FPGAs

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output

buffer.

Table 2-93 • Minimum and Maximum DC Input and Output Levels

HSTL

Class II

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

mA mA

IOSL

IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max. Max.

Min.

V

Max.

mA³

V

mA³

µA⁴µA⁴

15 mA⁵

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.4

VCCI – 0.4 15 15

66

55

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Output drive strength is below JEDEC specification.

V_TT

HSTL

Class II

25

Test Point

20 pF

Figure 2-18 • AC Loading

Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-95 • HSTL Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

6.03

Units

Std.

0.98

2.62

0.19

1.77

0.67

2.66

2.40

6.29

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-96 • HSTL Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 1.4 V VREF = 0.75 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.93

0.26

1.94

1.10

2.98

2.75

8.79

8.55

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-57

IGLOOe DC and Switching Characteristics

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-97 • Minimum and Maximum DC Input and Output Levels

SSTL2

Class I

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

IOSL IIL¹IIH²

Drive

Strength

Min.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA

mA³

mA³µA⁴µA⁴

15 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.54 VCCI – 0.62 15 15

83

87

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V

TT

SSTL2

Class I

50

Test Point

25

30 pF

Figure 2-19 • AC Loading

Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

30

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-99 • SSTL 2 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

ns

Std.

0.98

1.91

0.19

1.15

0.67

1.94

1.72

5.57

5.35

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-100 • SSTL 2 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.17

0.26

1.39

1.10

2.21

2.04

8.02

7.84

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-58

Revision 13

IGLOOe Low Power Flash FPGAs

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-101 • Minimum and Maximum DC Input and Output Levels

SSTL2

Class II

VIL

Max.

VIH

VOL

VOH

IOL IOH IOSH

Max.

IOSL IIL¹IIH²

Max.

Drive

Strength

Min.

V

Min.

V

Max. Max.

Min.

V

mA mA

mA³

µA⁴µA⁴

18 mA

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.35 VCCI – 0.43 18 18

169

124

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V

TT

SSTL2

Class II

25

Test Point

25

30 pF

Figure 2-20 • AC Loading

Table 2-102 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input HIGH (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

30

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-103 • SSTL 2 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

5.29

Units

Std.

0.98

1.94

0.19

1.15

0.67

1.97

1.66

5.60

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-104 • SSTL 2 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V VREF = 1.25 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.20

0.26

1.39

1.10

2.24

1.97

8.05

7.78

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-59

IGLOOe DC and Switching Characteristics

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class

I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-105 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSH

IOSL IIL¹IIH²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA mA mA³

mA³µA⁴µA⁴

14 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.7 VCCI – 1.1 14 14

51

54

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V

TT

SSTL3

Class I

50

Test Point

25

30 pF

Figure 2-21 • AC Loading

Table 2-106 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

30

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-107 • SSTL 3 Class I – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

0.98

2.05

0.19

1.09

0.67

2.09

1.71

5.72

5.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-108 • SSTL 3 Class I – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.32

0.26

1.32

1.10

2.37

2.02

8.17

7.83

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

2-60

Revision 13

IGLOOe Low Power Flash FPGAs

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class

II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-109 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSH

IOSL IIL¹IIH²

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Max.

Drive Strength

21 mA

mA mA mA³

mA³µA⁴µA⁴

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.5

VCCI – 0.9 21 21

103

109

10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

V

TT

SSTL3

Class II

25

Test Point

25

30 pF

Figure 2-22 • AC Loading

Table 2-110 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

30

Note: Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-111 • SSTL 3 Class II – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

ns

Std.

0.98

1.86

0.19

1.09

0.67

1.89

1.58

5.52

5.21

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-112 • SSTL 3 Class II – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V VREF = 1.5 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

t_ZL

t_ZH

t_LZt_HZ

t_ZLS

t_ZHS

Units

Std.

1.55

2.12

0.26

1.32

1.10

2.16

1.89

7.97

7.70

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-61

IGLOOe DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer software

when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional

I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

+

–

100 

N

Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation

2-62

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-113 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

Supply Voltage

VOL

Output Low Voltage

1.075

1.425

0.91

V

VOH

IOL¹

IOH¹

Output High Voltage

1.25

0.65

0

V

Output Lower Current

Output High Current

1.16

2.925

10

mA

V

VI

IIH^2,3

IIL^2,4

Input Voltage

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

µA

mV

V

10

VODIFF

VOCM

VICM

VIDIFF

Notes:

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

mV

1. IOL/IOH is defined by VODIFF/(resistor network).

2. Currents are measured at 85°C junction temperature.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

4. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL.

Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

1.075

1.325

Cross point

–

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-115 • LVDS – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

0.98

1.77

0.19

1.62

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-116 • LVDS – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.19

0.26

1.88

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-63

IGLOOe DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in

the LVDS section in Table 2-115 on page 2-63 and Table 2-116 on page 2-63.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

N

OUTBUF_LVPECL

100 

Z = 50 

0

INBUF_LVPECL

+

–

187 W

Z = 50 

100 

0

N

Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation

2-64

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-117 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max. Units

3.0

3.3

3.6

V

VOL

Output Low Voltage

0.96

1.8

0

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

V

0.625 0.97 0.625 0.97 0.625 0.97

1.762 1.98 1.762 1.98 1.762 1.98

V

1.01

300

2.57

1.01

300

2.57

1.01

300

2.57

V

VIDIFF

mV

Table 2-118 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

VREF (typ.) (V)

1.64

1.94

Cross point

–

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-23 for a complete table of trip points.

Timing Characteristics

1.5 V DC Core Voltage

Table 2-119 • LVPECL – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

0.98

1.75

0.19

1.45

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

1.2 V DC Core Voltage

Table 2-120 • LVPECL – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

t_DP

t_DIN

t_PY

Units

Std.

1.55

2.16

0.26

1.70

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-65

IGLOOe DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

DFN1E1P1

G

E

EOUT

B

A

H

I

PRE

J

D

Q

DFN1E1P1

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

CLKBUF

INBUF

Postive-Edge Triggered

Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-66

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-121 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

t_OHD

F, H

t_OSUE

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

I, EOUT

I, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

B, A

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

Note: See Figure 2-26 on page 2-66 for more information.

Revision 13

2-67

IGLOOe DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

AA

DD

CLR

LL

HH

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-68

Revision 13

IGLOOe Low Power Flash FPGAs

Table 2-122 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

t_OHD

FF, HH

t_OSUE

GG, HH

LL, DOUT

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-27 on page 2-68 for more information.

Revision 13

2-69

IGLOOe DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

1

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-28 • Input Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-123 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

Std. Units

Clock-to-Q of the Input Data Register

0.42

0.47

0.00

0.67

0.00

0.79

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-70

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-124 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_ICLKQ

Description

Std. Units

Clock-to-Q of the Input Data Register

0.68

0.97

0.00

1.02

0.00

1.19

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-71

IGLOOe DC and Switching Characteristics

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-29 • Output Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-125 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

Std. Units

Clock-to-Q of the Output Data Register

1.00

0.51

0.00

0.70

0.00

1.34

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-72

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-126 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OCLKQ

Description

Std. Units

Clock-to-Q of the Output Data Register

1.52

1.15

0.00

1.11

0.00

1.96

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.

Revision 13

2-73

IGLOOe DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_{OESUD OEHD}

t

50% 50%

1

0

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

EOUT

Figure 2-30 • Output Enable Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-127 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

Std. Units

Clock-to-Q of the Output Enable Register

0.75

0.51

0.00

0.73

0.00

1.13

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OESUE

Enable Setup Time for the Output Enable Register

t_OEHE

Enable Hold Time for the Output Enable Register

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

t_OEWPRE

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register

t_OECKMPWHClock Minimum Pulse Width HIGH for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width LOW for the Output Enable Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-74

Revision 13

IGLOOe Low Power Flash FPGAs

1.2 V DC Core Voltage

Table 2-128 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OECLKQ

t_OESUD

Description

Std. Units

Clock-to-Q of the Output Enable Register

1.10

1.15

0.00

1.22

0.00

1.65