M2S025T-VFG256I [MICROSEMI]
Field Programmable Gate Array, 27696-Cell, CMOS, PBGA256, VFBGA-256;
| 型号： | M2S025T-VFG256I |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 27696-Cell, CMOS, PBGA256, VFBGA-256 栅 可编程逻辑 |
| 文件： | 总141页 (文件大小：1153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS0128
Datasheet
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Fax: +1 (949) 215-4996
Email: sales.support@microsemi.com
www.microsemi.com
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and
scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
51700128. 11.0 10/16
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
Revision 11.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 IGLOO2 FPGA and SmartFusion2 SoC FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Average Fabric Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Element Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
FPGA Fabric SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Programming Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.10 Math Block Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.3.11 Embedded NVM (eNVM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.3.12 SRAM PUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.3.13 Non-Deterministic Random Bit Generator (NRBG) Characteristics . . . . . . . . . . . . . . . . . . . . 106
2.3.14 Cryptographic Block Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.3.15 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.3.16 On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.3.17 Clock Conditioning Circuits (CCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.3.18 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.3.19 System Controller SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.3.20 Power-up to Functional Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.3.21 DEVRST_N Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.3.22 DEVRST_N to Functional Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.3.23 Flash*Freeze Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.3.24 DDR Memory Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.3.25 SFP Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.3.26 SerDes Electrical and Timing AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.3.27 SmartFusion2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.3.28 CAN Controller Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2.3.29 USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2.3.30 MMUART Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2.3.31 IGLOO2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
DS0128 Datasheet Revision 11.0
iii
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
High Temperature Data Retention (HTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Tristate Buffer for Enable Path Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing Model for Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O Register Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timing Model for Output/Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
I/O Register Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Output DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LUT-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Sequential Module Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Power-up to Functional Timing Diagram for SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Power-up to Functional Timing Diagram for IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DEVRST_N to Functional Timing Diagram for SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DEVRST_N to Functional Timing Diagram for IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I2C Timing Parameter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . . . . . 128
SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . . . . . 131
DS0128 Datasheet Revision 11.0
iv
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
IGLOO2 and SmartFusion2 Design Security Densities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
IGLOO2 and SmartFusion2 Data Security Densities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FPGA Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Embedded Operating Flash Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Storage Temperature and Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
High Temperature Data Retention (HTR) Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . 10
Quiescent Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.2 V) – Typical Process . . . . . . . 12
Currents During Program Cycle, 0 °C < = TJ <= 85 °C – Typical Process . . . . . . . . . . . . . . . . . . . 13
Currents During Verify Cycle, 0 °C <= TJ <= 85 °C – Typical Process . . . . . . . . . . . . . . . . . . . . . . 13
SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.26 V) – Worst-Case Process . . 13
Average Junction Temperature and Voltage Derating Factors for Fabric Timing Delays . . . . . . . . 14
Inrush Currents at Power up, –40 °C <= TJ <= 100 °C – Typical Process . . . . . . . . . . . . . . . . . . . 14
Timing Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum Data Rate Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions . 19
Maximum Data Rate Summary Table for Voltage-Referenced I/O in Worst-Case
Industrial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Maximum Data Rate Summary Table for Differential I/O in Worst-Case Industrial Conditions . . . 20
Maximum Frequency Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions . 20
Maximum Frequency Summary Table for Voltage-Referenced I/O in Worst-Case Industrial
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum Frequency Summary Table for Differential I/O in Worst-Case Industrial Conditions . . . 21
Input Capacitance, Leakage Current, and Ramp Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Weak Pull-up/Pull-down Resistances for DDRIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I/O Weak Pull-up/Pull-down Resistances for MSIOD I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Schmitt Trigger Input Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions (Applicable to MSIO I/O
Bank Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LVTTL/LVCMOS 3.3 V Input Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . 24
LVCMOS 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . . . 24
LVTTL 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) . . . . . . . . . . . 24
LVTTL/LVCMOS 3.3 V AC Maximum Switching Speed (Applicable to MSIO I/O Bank Only) . . . . 24
LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . 25
LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO I/O Bank Only) . . 25
LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications for MSIO I/O Bank . . . . . . . . . . 25
LVCMOS 2.5 V DC Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V AC Minimum and Maximum Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V AC Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LVCMOS 2.5 V Receiver Characteristics (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers) . . . . . 27
LVCMOS 2.5 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Drive Strength Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LVCMOS 2.5 V Transmitter Characteristics for MSIO Bank (Output and Tristate Buffers) . . . . . . 28
LVCMOS 1.8 V DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LVCMOS 1.8 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LVCMOS 1.8 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
DS0128 Datasheet Revision 11.0
v
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
LVCMOS 1.8 V Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LVCMOS 2.5 V Transmitter Characteristics for MSIOD Bank (Output and Tristate Buffers) . . . . . 29
LVCMOS 1.8 V Receiver Characteristics (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVCMOS 1.8 V AC Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVCMOS 1.8 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVCMOS 1.8 V Transmitter Drive Strength Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LVCMOS 1.8 V Transmitter Characteristics for DDRIO I/O Bank with Fixed Code (Output and
Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVCMOS 1.5 V DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS 1.5 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS 1.8 V Transmitter Characteristics for MSIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS 1.8 V Transmitter Characteristics for MSIOD I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS 1.5 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS 1.5 V AC Minimum and Maximum Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS 1.5 V AC Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS 1.5 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS 1.5 V Transmitter Drive Strength Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LVCMOS 1.5 V Receiver Characteristics for DDRIO I/O Bank with Fixed Codes (Input Buffers) . 34
LVCMOS 1.5 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . 34
LVCMOS 1.5 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . 34
LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . 34
LVCMOS 1.5 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . 35
LVCMOS 1.2 V DC Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVCMOS 1.2 V DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVCMOS 1.2 V DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVCMOS 1.2 V Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVCMOS 1.5 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) . . 36
LVCMOS 1.2 V Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers) . . 37
LVCMOS 1.2 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . 37
LVCMOS 1.2 V AC Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LVCMOS 1.2 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LVCMOS 1.2 V Transmitter Drive Strength Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LVCMOS 1.2 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . 38
LVCMOS 1.2 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . 38
LVCMOS 1.2 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . 38
PCI/PCI-X DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCI/PCI-X DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCI/PCI-X DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCI/PCI-X Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCI/PCI-X AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LVCMOS 1.2 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) . . 39
PCI/PCIX AC Switching Characteristics for Receiver for MSIO I/O Bank (Input Buffers) . . . . . . . . 40
PCI/PCIX AC switching Characteristics for Transmitter for MSIO I/O Bank (Output and
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HSTL Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HSTL DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HSTL DC Output Voltage Specification Applicable to DDRIO I/O Bank Only . . . . . . . . . . . . . . . . . 41
HSTL DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HSTL AC Differential Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HSTL Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HSTL Impedance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HSTL Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers) . . . . . . . . . . 42
HSTL Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . . . . . . . . . 42
HSTL AC Test Parameter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DDR1/SSTL2 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR1/SSTL2 DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR1/SSTL2 DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR1/SSTL2 DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SSTL2 Receiver Characteristics for DDRIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . 44
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
DS0128 Datasheet Revision 11.0
vi
Table 108
Table 109
Table 110
Table 111
Table 112
Table 113
Table 114
Table 115
SSTL2 AC Differential Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SSTL2 Minimum and Maximum AC Switching Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SSTL2 AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DDR1/SSTL2 AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SSTL2 Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . 45
DDR1/SSTL2 Receiver Characteristics for MSIOD I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . 45
SSTL2 Class I Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . . 45
DDR1/SSTL2 Class I Transmitter Characteristics for MSIO I/O Bank (Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DDR1/SSTL2 Class I Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DDR1/SSTL2 Class II Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SSTL18 DC Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SSTL18 DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SSTL18 DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DDR1/SSTL2 Class II Transmitter Characteristics for MSIO I/O Bank (Output and Tristate
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DDR2/SSTL18 Receiver Characteristics for DDRIO I/O Bank with Fixed Code . . . . . . . . . . . . . . . 47
SSTL18 DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SSTL18 AC Differential Voltage Specifications (Applicable to DDRIO Bank Only) . . . . . . . . . . . . 47
SSTL18 Minimum and Maximum AC Switching Speed (Applicable to DDRIO Bank Only) . . . . . . 47
SSTL18 AC Impedance Specifications (Applicable to DDRIO Bank Only) . . . . . . . . . . . . . . . . . . . 47
SSTL18 AC Test Parameter Specifications (Applicable to DDRIO Bank Only) . . . . . . . . . . . . . . . 47
SSTL15 DC Recommended DC Operating Conditions (for DDRIO I/O Bank Only) . . . . . . . . . . . . 48
SSTL15 DC Input Voltage Specification (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . . . 48
DDR2/SSTL18 Transmitter Characteristics (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . 48
SSTL15 AC SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only) . 49
SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only) . . . . . . . . . . . 49
SSTL15 AC Calibrated Impedance Option (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . 49
SSTL15 DC Output Voltage Specification (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . . 49
SSTL15 DC Differential Voltage Specification (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . 49
DDR3/SSTL15 Receiver Characteristics for DDRIO I/O Bank – with Calibration Only . . . . . . . . . 50
DDR3/SSTL15 Transmitter Characteristics (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . 50
SSTL15 AC Test Parameter Specifications (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . 50
LPDDR DC Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LPDDR DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LPDDR DC Output Voltage Specification Reduced Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 122
Table 123
Table 124
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
Table 138
Table 139
Table 140
Table 141
Table 142
Table 143
Table 144
Table 145
Table 146
Table 147
Table 148
Table 149
Table 150
Table 151
Table 152
Table 153
Table 154
Table 155
Table 156
Table 157
Table 158
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LPDDR DC Output Voltage Specification Full Drive
LPDDR DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LPDDR Receiver Characteristics for DDRIO I/O Bank with Fixed Codes . . . . . . . . . . . . . . . . . . . 52
LPDDR Reduced Drive for DDRIO I/O Bank (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . 52
LPDDR AC Differential Voltage Specifications (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . 52
LPDDR AC Specifications (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LPDDR AC Calibrated Impedance Option (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . 52
LPDDR AC Test Parameter Specifications (for DDRIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . 52
LPDDR-LVCMOS 1.8 V Mode Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . 53
LPDDR-LVCMOS 1.8 V Mode DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LPDDR-LVCMOS 1.8 V Minimum and Maximum AC Switching Speeds . . . . . . . . . . . . . . . . . . . . 53
LPDDR-LVCMOS 1.8 V Calibrated Impedance Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LPDDR Full Drive for DDRIO I/O Bank (Output and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . 53
LPDDR-LVCMOS 1.8 V AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification for DDRIO Bank . . . . . . 54
LPDDR-LVCMOS 1.8V AC Switching Characteristics for Receiver (for DDRIO I/O Bank with Fixed
Code - Input Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output
and Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LVDS Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 159
Table 160
DS0128 Datasheet Revision 11.0
vii
Table 161
Table 162
Table 163
Table 164
Table 165
Table 166
Table 167
Table 168
Table 169
Table 170
Table 171
Table 172
Table 173
Table 174
Table 175
Table 176
Table 177
Table 178
Table 179
Table 180
Table 181
Table 182
LVDS DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LVDS25 Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . 56
LVDS DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LVDS DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LVDS Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LVDS AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LVDS AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LVDS33 Receiver Characteristics for MSIO I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . . . . . . 57
LVDS33 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . . . . . . . 57
LVDS25 Receiver Characteristics for MSIOD I/O Bank (Input Buffers) . . . . . . . . . . . . . . . . . . . . . 57
LVDS25 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . . . . . . . 57
LVDS25 Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) . . . . . . . . 57
B-LVDS Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only) . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B-LVDS AC Switching Characteristics for Receiver for MSIO I/O Bank (Input Buffers) . . . . . . . . . 59
B-LVDS AC Switching Characteristics for Receiver for MSIOD I/O Bank (Input Buffers) . . . . . . . . 59
B-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and
Tristate Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
M-LVDS Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
M-LVDS DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
M-LVDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) . . . . . . . 60
M-LVDS DC Voltage Specification Output Voltage Specification (for MSIO I/O Bank Only) . . . . . 60
M-LVDS Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M-LVDS Minimum and Maximum AC Switching Speed for MSIO I/O Bank . . . . . . . . . . . . . . . . . . 60
M-LVDS AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M-LVDS AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Mini-LVDS Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mini-LVDS DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mini-LVDS DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mini-LVDS DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mini-LVDS Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
M-LVDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank - Input Buffers) . . . . . . 61
M-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mini-LVDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) . . . . . . 62
Mini-LVDS AC Switching Characteristics for Transmitter for MSIO I/O Bank (Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mini-LVDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mini-LVDS AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mini-LVDS AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
RSDS Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS DC Output Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS Minimum and Maximum AC Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS AC Impedance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS AC Test Parameter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RSDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) . . . . . . . . . 64
RSDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank - Input Buffers) . . . . . . . . 64
RSDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RSDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate
Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 183
Table 184
Table 185
Table 186
Table 187
Table 188
Table 189
Table 190
Table 191
Table 192
Table 193
Table 194
Table 195
Table 196
Table 197
Table 198
Table 199
Table 200
Table 201
Table 202
Table 203
Table 204
Table 205
Table 206
Table 207
Table 208
Table 209
Table 210
Table 211
Table 212
Table 213
DS0128 Datasheet Revision 11.0
viii
Table 214
Table 215
Table 216
Table 217
Table 218
Table 219
Table 220
Table 221
Table 222
Table 223
Table 224
Table 225
Table 226
Table 227
Table 228
Table 229
Table 230
Table 231
Table 232
Table 233
Table 234
Table 235
Table 236
Table 237
Table 238
Table 239
Table 240
Table 241
Table 242
Table 243
Table 244
Table 245
Table 246
Table 247
Table 248
Table 249
Table 250
Table 251
Table 252
Table 253
Table 254
Table 255
Table 256
Table 257
Table 258
Table 259
Table 260
Table 261
Table 262
Table 263
Table 264
Table 265
Table 266
Table 267
Table 268
Table 269
Table 270
Table 271
Table 272
LVPECL Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LVPECL Receiver Characteristics for MSIO I/O Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LVPECL DC Input Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LVPECL DC Differential Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LVPECL Minimum and Maximum AC Switching Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input Data Register Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Output/Enable Data Register Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Input DDR Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output DDR Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Combinatorial Cell Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Register Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
150 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
090 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
050 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
025 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
010 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
005 Device Global Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18 . . . . . . . . . . . . . . . . . . . . . 79
RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9 . . . . . . . . . . . . . . . . . . . . . . 80
RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4 . . . . . . . . . . . . . . . . . . . . . . 81
RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8K × 2 . . . . . . . . . . . . . . . . . . . . . . 83
RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16K × 1 . . . . . . . . . . . . . . . . . . . . . 84
RAM1K18 – Two-Port Mode for Depth × Width Configuration 512 × 36 . . . . . . . . . . . . . . . . . . . . 85
µSRAM (RAM64x18) in 64 × 18 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
µSRAM (RAM64x16) in 64 × 16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
µSRAM (RAM128x9) in 128 × 9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
µSRAM (RAM128x8) in 128 × 8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
µSRAM (RAM256x4) in 256 × 4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
µSRAM (RAM512x2) in 512 × 2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
µSRAM (RAM1024x1) in 1024 × 1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
JTAG Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
JTAG Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
JTAG Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2 Step IAP Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2 Step IAP Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2 Step IAP Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SmartFusion2 Cortex-M3 ISP Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (Fabric Only) . . . . . 97
Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (eNVM Only) . . . . . 97
Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (Fabric and eNVM) . 98
JTAG Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
JTAG Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
JTAG Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2 Step IAP Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2 Step IAP Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2 Step IAP Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SmartFusion2 Cortex-M3 ISP Programming (Fabric Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . 101
Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric Only) . . . . 102
Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (eNVM Only) . . . . 102
Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric and eNVM) 102
Math Blocks with all Registers Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Math Block with Input Bypassed and Output Registers Used . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Math Block with Input Register Used and Output in Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . 104
Math Block with Input and Output in Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
eNVM Read Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
DS0128 Datasheet Revision 11.0
ix
Table 273
Table 274
Table 275
Table 276
Table 277
Table 278
Table 279
Table 280
Table 281
Table 282
Table 283
Table 284
Table 285
Table 286
Table 287
Table 288
Table 289
Table 290
Table 291
Table 292
Table 293
Table 294
Table 295
Table 296
Table 297
Table 298
Table 299
Table 300
Table 301
Table 302
Table 303
Table 304
Table 305
Table 306
Table 307
Table 308
Table 309
Table 310
eNVM Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SRAM PUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Non-Deterministic Random Bit Generator (NRBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Cryptographic Block Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) . . . . . . . . . . . . . . 107
Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz) . . . . . . . . . . . . 108
Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz) . . . . . . . . . . . . . . . 108
Electrical Characteristics of the 50 MHz RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Electrical Characteristics of the 1 MHz RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Specification . . . . . . . . . . . . . . . . . . . . . . . . 110
IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter Specifications . . . . . . . . . . . . . . . . . . . 111
JTAG 1532 for 005, 010, 025, and 050 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JTAG 1532 for 060, 090, and 150 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
System Controller SPI Characteristics for All Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Supported I/O Configurations for System Controller SPI (for MSIO Bank Only) . . . . . . . . . . . . . 113
Power-up to Functional Times for SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Power-up to Functional Times for IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DEVRST_N Characteristics for All Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DEVRST_N to Functional Times for SmartFusion2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DEVRST_N to Functional Times for IGLOO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Flash*Freeze Entry and Exit Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
DDR Memory Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SFP Transceiver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Transmitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Receiver Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SerDes Protocol Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SerDes Reference Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
HCSL Minimum and Maximum DC Input Levels (Applicable to SerDes REFCLK Only) . . . . . . . 123
HCSL Minimum and Maximum AC Switching Speeds (Applicable to SerDes REFCLK Only) . . . 123
Maximum Frequency for MSS Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
I2C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I2C Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Characteristics for All Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CAN Controller Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MMUART Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Maximum Frequency for HPMS Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SPI Characteristics for All Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
DS0128 Datasheet Revision 11.0
x
Revision History
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
Revision 11.0
The following is a summary of the changes in revision 11.0 of this document.
•
•
Updated Table 24, page 22 with minimum and maximum values for input current low and high (SAR
73114 and 80314).
Added Non-Deterministic Random Bit Generator (NRBG) Characteristics, page 106 (SAR 73114
and 79517).
•
•
•
•
•
•
•
Added 060 device in Table 282, page 110 (SAR 79860).
Added DEVRST_N to Functional Times, page 116 (SAR 73114).
Added Cryptographic Block Characteristics, page 106 (SAR 73114 and 79516).
Update Table 296, page 121 with VTX-AMP details (SAR 81756).
Update note in Table 297, page 122 (SAR 74570 and 80677).
Update Table 298, page 122 with generic EPCS details (SAR 75307).
Added Table 308, page 129 (SAR 50424).
1.2
Revision 10.0
The following is a summary of the changes in revision 10.0 of this document.
•
The Surge Current on VDD during DEVRST_B Assertion and Surge Current on VDD during Digest
Check using System Services tables were deleted and added reference to AC393: Board Design
Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note. (SAR 76865 and 76623).
Added 060 device in Table 4, page 6 (SAR 76383).
Updated Table 24, page 22 for ramp time input (SAR 72103).
Added 060 device details in Table 284, page 112 (SAR 74927).
•
•
•
•
•
•
Updated Table 290, page 116 for name change (SAR 74925).
Updated Table 283, page 111 for 060 FG676 Package details (SAR 78849).
Updated Table 305, page 126 for SmartFusion2 and Table 310, page 129 for IGLOO2 for SPI timing
and Fmax (SAR 56645, 75331).
•
•
•
•
•
•
Updated Table 293, page 119 for Flash*Freeze entry and exit times (SAR 75329, 75330).
Updated Table 297, page 122 for RX-CID information (SAR 78271).
Added Table 8, page 8 and Figure 1, page 9 (SAR 78932).
Updated Table 223, page 76 for timing characteristics and Table 224, page 77(SAR 75998).
Added SRAM PUF, page 105 (SAR 64406).
Added a footnote on digest cycle in Table 5, page 7 (SAR 79812).
1.3
Revision 9.0
The following is a summary of the changes in revision 9.0 of this document.
•
•
•
•
Added a note in Table 5, page 7 (SAR 71506).
Added a note in Table 6, page 8 (SAR 74616).
Added a note in Figure 3, page 17 (SAR 71506).
Updated Quiescent Supply Current for 060 in Table 11, page 12 and Table 12, page 13 (SAR
74483).
•
Updated programming currents for 060 in Table 13, page 13, Table 14, page 13, and Table 15,
page 14.
•
•
•
•
•
Added DEVRST_B assertion tables (SAR 74708).
Updated I/O speeds for LVDS 3.3 V in Table 18, page 19 and Table 21, page 20 (SAR 69829).
Updated Table 24, page 22 (SAR 69418).
Updated Table 25, page 22, Table 26, page 23, Table 27, page 23 (SAR 74570).
Updated all AC/DC table to link to the Input Capacitance, Leakage Current, and Ramp Time,
page 22 for reference (SAR 69418).
DS0128 Datasheet Revision 11.0
1
Revision History
•
•
•
•
•
•
Added Table 244, page 94 and Table 256, page 99 (SAR 73971).
Updated the SerDes Electrical and Timing AC and DC Characteristics, page 121 (SAR 71171).
Added the DEVRST_N Characteristics, page 116 (SAR 64100, 72103).
Added Table 298, page 122 (SAR 71897).
Updated Table 25, page 22, Table 26, page 23, and Table 27, page 23 (SAR 74570).
Added 060 devices in Table 277, page 107, Table 278, page 108, and Table 279, page 108 (SAR
57898).
•
Updated duty cycle parameter of crystal in Table 280, page 109 and Table 281, page 109 (SAR
57898).
•
•
•
Added 32 KHz mode PLL acquisition time in Table 282, page 110 (SAR 68281).
Updated Table 293, page 119 for 060 devices (SAR 57828).
Updated Table 297, page 122 for CID value (SAR 70878).
1.4
Revision 8.0
The following is a summary of the changes in revision 8.0 of this document.
•
•
•
Updated Table 11, page 12 (SAR 69218).
Updated Table 12, page 13 (SAR 69218).
Updated Table 283, page 111 (SAR 69000).
1.5
1.6
Revision 7.0
The following is a summary of the changes in revision 7.0 of this document.
•
Updated Table 1, page 4(SAR 68620).
Revision 6.0
The following is a summary of the changes in revision 6.0 of this document.
•
•
•
•
•
•
•
•
•
Updated Table 5, page 7 (SAR 65949).
Updated Table 9, page 10 (SAR 62995).
Updated Table 123, page 47 and Table 133, page 49 (SAR 67210).
Added Embedded NVM (eNVM) Characteristics, page 104 (SAR 52509).
Updated Table 277, page 107 (SAR 64855).
Updated Table 282, page 110 (SAR 65958 and SAR 56666).
Added DDR Memory Interface Characteristics, page 120 (SAR 66223).
Added SFP Transceiver Characteristics, page 120 (SAR 63105).
Updated Table 302, page 123 and Table 309, page 129 (SAR 66314).
1.7
1.8
Revision 5.0
The following is a summary of the changes in revision 5.0 of this document.
•
•
•
•
•
•
•
Updated Table 1, page 4.
Updated Table 4, page 6 for TJ symbol information.
Updated Table 5, page 7 (SAR 63109).
Updated Table 9, page 10.
Updated Table 282, page 110 (SAR 62012).
Added Table 290, page 116 (SAR 64100).
Added Table 306, page 128, Table 307, page 128 (SAR 50424).
Revision 4.0
The following is a summary of the changes in revision 4.0 of this document.
•
•
•
Updated Table 1, page 4. Changed the Status of 090 devices to "Production" (SAR 62750).
Updated Figure 10, page 70. Removed inverter bubble from DDR_IN latch (SAR 61418).
Updated SerDes Electrical and Timing AC and DC Characteristics, page 121 (SAR 62836).
DS0128 Datasheet Revision 11.0
2
Revision History
1.9
Revision 3.0
In revision 3.0 of this document, the Theta B/C columns and FCS325 package was updated. For more
information, see Table 9, page 10 (SAR 62002).
1.10 Revision 2.0
The following is a summary of the changes in revision 2.0 of this document.
•
•
•
Table 1, page 4 was updated (SAR 59056).
Table 7, page 8 temperature and data retention information was updated SAR (61363).
Storage Operating Table was updated and split into three tables – Table 5, page 7, Table 7, page 8
(SAR 58725).
•
•
•
•
•
•
Updated Theta B/C columns and FCS325 package in Table 9, page 10 (SAR 62002).
Added 090-FCS325 thermal resistance to Table 9, page 10 (SAR 59384).
TQ144 package was added to Table 9, page 10 (SAR 57708).
Added PLL jitter data for the VF400 package (SAR 53162).
Added Additional Worst Case IDD to Table 11, page 12 and Table 12, page 13 (SAR 59077).
Table 13, page 13, Table 14, page 13, and Table 15, page 14 were added to verify Inrush currents
(SAR 56348).
•
•
•
Table 18, page 19 and Table 21, page 20 – I/O speeds were replaced.
Max speed was changed in Table 41, page 26 (SAR 57221) and in Table 52, page 29 (SAR 57113).
Minimum and Maximum DC/AC Input and Output Levels Specification, page 29 and
Table 49, page 29–Table 57, page 31 were added.
•
•
Added Cload to Table 89, page 39 (SAR 56238).
Removed "Rs" information in DDR Timing Measurement Table 123, page 47, Table 133, page 49,
and Table 144, page 52.
•
•
•
•
Updated drive programming for M/B-LVDS outputs (SAR 58154).
Added an inverter bubble to DDR_IN latch in Figure 10, page 70 (SAR 61418).
QF waveform in Figure 11, page 71 was updated (SAR 59816).
uSRAM Write Clock minimum values were updated in Table 237, page 86–Table 243, page 93 (SAR
55236).
•
•
Fixed typo in the 32 kHz Crystal (XTAL) oscillator accuracy data section (SAR 59669).
The "On-Chip Oscillator" section was split, and the Embedded NVM (eNVM) Characteristics,
page 104 was added. Table 277, page 107–Table 281, page 109 were revised.(SARs 57898 and
59669).
•
•
•
•
•
•
•
PLL VCP Frequency and conditions were added to Table 282, page 110 (SAR 57416).
Fixed typo for PLL jitter data in the 100-400 MHz range (SAR 60727).
Updated FCCC information in Table 282, page 110 and Table 283, page 111 (SAR 60799).
Device 025 specifications were added to Table 283, page 111 (SAR 51625).
JTAG Table 284, page 112 was replaced (SAR 51188).
Flash*Freeze Table 293, page 119 was replaced (SAR 57828).
Added support for HCSL I/O Standard for SERDES reference clocks in Table 300, page 123 and
Table 301, page 123 (SAR 50748).
•
•
•
Tir and Tif parameters were added to Table 303, page 124 (SAR 52203).
Speed grade consistency was fixed in tables throughout the datasheet (SAR 50722).
Added jitter attenuation information (SAR 59405).
1.11
Revision 1.0
The following is a summary of the changes in revision 1.0 of this document.
•
The IGLOO2 v2 and the SmartFusion2 v5 datasheets are combined into this single product family
datasheet.
DS0128 Datasheet Revision 11.0
3
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Microsemi’s mainstream SmartFusion®2 SoC and IGLOO®2 FPGA families integrate an industry
standard 4-input lookup table-based (LUT) FPGA fabric with integrated math blocks, multiple embedded
memory blocks, and high-performance SerDes communication interfaces on a single chip. Both families
benefit from low-power flash technology and are the most secure and reliable FPGAs in the industry.
These next generation devices offer up to 150K Logic Elements, up to 5 MBs of embedded RAM, up to
16 SerDes lanes, and up to four PCI Express Gen 2 endpoints, as well as integrated hard DDR3 memory
controllers with error correction.
SmartFusion2 devices integrate an entire low-power, real-time microcontroller subsystem (MSS) with a
rich set of industry-standard peripherals including Ethernet, USB, and CAN, while IGLOO2 devices
integrate a high-performance memory subsystem with on-chip flash, 32 Kbyte embedded SRAM, and
multiple DMA controllers.
2.1
Device Status
The following table shows the design security densities and development status of the IGLOO2 FPGA
and SmartFusion2 SoC FPGA devices.
Table 1 •
IGLOO2 and SmartFusion2 Design Security Densities
Design Security Device Densities
Status
005
Production
Production
Production
Production
Production
Production
Production
010, 010T
025, 025T
050, 050T
060, 060T
090, 090T
150, 150T
The following table shows the data security densities and development status of the IGLOO2 FPGA and
SmartFusion2 SoC FPGA devices.
Table 2 •
IGLOO2 and SmartFusion2 Data Security Densities
Data Security Device Densities
Status
005S
Production
Production
Production
Production
Production
Production
Production
010TS
025TS
050TS
060TS
090TS
150TS
DS0128 Datasheet Revision 11.0
4
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.2
References
The following documents are recommended references:
•
•
•
•
PB0121: IGLOO2 Product Brief
DS0124: IGLOO2 Pin Descriptions
PB0115: SmartFusion2 SoC FPGA Product Brief
DS0115: SmartFusion2 Pin Descriptions
All product documentation for IGLOO2 and SmartFusion2 is available at:
http://www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#overview
2.3
Electrical Specifications
2.3.1
Operating Conditions
The following table lists the stress limits. Stress applied above the specified limit may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the recommended operating conditions specified in the
following table are not implied.
Table 3 •
Absolute Maximum Ratings
Parameter
Symbol
VDD
Min
–0.3
–0.3
Max Unit
DC core supply voltage. Must always power this pin.
1.32
3.63
V
V
Power supply for charge pumps (for normal operation
and programming). Must always power this pin.
VPP
Analog power pad for MDDR PLL
Analog power pad for MDDR PLL
Analog power pad for FDDR PLL
Analog power pad for MDDR PLL
Analog power pad for MDDR PLL
Analog power pad for PLL0–5
MSS_MDDR_PLL_VDDA
HPMS_MDDR_PLL_VDDA
FDDR_PLL_VDDA
–0.3
–0.3
–0.3
–0.3
3.63
3.63
3.63
3.63
3.63
3.63
3.63
2.75
V
V
V
V
V
V
V
V
PLL0_PLL1_MSS_MDDR_VDDA
PLL0_PLL1_HPMS_MDDR_VDDA –0.3
CCC_XX[01]_PLL_VDDA
SERDES_[01]_PLL_VDDA
–0.3
–0.3
High supply voltage for PLL SerDes[01]
Analog power for SerDes[01] PLL lane0 to lane3.
This is a 2.5 V SerDes internal PLL supply.
SERDES_[01]_L[0123]_VDDAPLL –0.3
TX/RX analog I/O voltage. Low voltage power for the
lanes of SerDesIF0. This is a 1.2 V SerDes PMA supply.
SERDES_[01]_L[0123]_VDDAIO
–0.3
1.32
V
PCIe/PCS power supply
SERDES_[01]_VDD
–0.3
–0.3
–0.3
1.32
3.63
2.75
V
V
V
DC FPGA I/O buffer supply voltage for MSIO I/O bank
VDDIx
VDDIx
DC FPGA I/O buffer supply voltage for MSIOD/DDRIO
I/O banks
I/O Input voltage for MSIO I/O bank
VI
–0.3
–0.3
–0.3
3.63
2.75
3.63
V
V
V
I/O Input voltage for MSIOD/DDRIO I/O bank
VI
Analog sense circuit supply of embedded nonvolatile
VPPNVM
memory (eNVM). Must be shorted to VPP
.
Storage temperature1
TSTG
TJ
–65
–55
150
135
°C
°C
Junction temperature
DS0128 Datasheet Revision 11.0
5
IGLOO2 FPGA and SmartFusion2 SoC FPGA
1. For flash programming and retention maximum limits, see Table 5, page 7. For recommended operating conditions, see Table 4,
page 6.
Table 4 •
Recommended Operating Conditions
Symbol
Parameter
Min
0
Typ
25
Max
85
Unit
°C
°C
°C
°C
V
Conditions
Commercial
Industrial
Operating junction temperature
TJ
–40
0
25
100
85
Programming junction temperatures1 TJ
25
Commercial
Industrial
–40
1.14
25
100
1.26
DC core supply voltage.
Must always power this pin.
VDD
VPP
1.2
Power supply for charge pumps
(for normal operation and
programming) for the 005, 010,
025, 050, 060 devices
2.375 2.5
2.625
3.45
V
V
2.5 V range
3.3 V range
3.15
3.3
Power supply for charge pumps (for VPP
normal operation and programming)
for the 090 and 150 devices
3.15
3.3
3.45
V
3.3 V range
Analog power pad for MDDR PLL
MSS_MDDR_PLL_VDDA
2.375 2.5
3.15 3.3
HPMS_MDDR_PLL_VDDA 2.375 2.5
3.15 3.3
2.375 2.5
3.15 3.3
2.625
3.45
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.5 V range
3.3 V range
2.5 V range
3.3 V range
2.5 V range
3.3 V range
2.5 V range
3.3 V range
2.5 V range
3.3 V range
2.5 V range
3.3 V range
2.5 V range
3.3 V range
Analog power pad for MDDR PLL
2.625
3.45
Analog power pad for FDDR PLL
FDDR_PLL_VDDA
2.625
3.45
Analog power pad for MDDR PLL
PLL0_PLL1_MSS_MDDR_V 2.375 2.5
DDA
2.625
3.45
3.15
3.3
Analog power pad for MDDR PLL
PLL0_PLL1_HPMS_MDDR_ 2.375 2.5
VDDA
2.625
3.45
3.15
3.3
Analog power pad for PLL0 to PLL5 CCC_XX[01]_PLL_VDDA
2.375 2.5
3.15 3.3
SERDES_[01]_PLL_VDDA 2.375 2.5
3.15 3.3
2.625
3.45
High supply voltage for PLL
SerDes[01]
2.625
3.45
Analog power for SerDes[01] PLL
Lane 0 to Lane 3. This is a 2.5 V
SerDes internal PLL supply.
SERDES_[01]_L[0123]_VD 2.375 2.5
DAPLL
2.625
TX/RX analog I/O voltage. Low
voltage power for the lanes of
SerDesIF0. This is a 1.2 V SerDes
PMA supply.
SERDES_[01]_L[0123]_VD 1.14
DAIO
1.2
1.26
V
PCIe/PCS power supply
1.2 V DC supply voltage
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
SERDES_[01]_VDD
1.14
1.14
1.2
1.2
1.26
V
V
V
V
V
VDDIx
VDDIx
VDDIx
VDDIx
1.26
1.425 1.5
1.71 1.8
2.375 2.5
1.575
1.89
2.625
DS0128 Datasheet Revision 11.0
6
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 4 •
Recommended Operating Conditions (continued)
Parameter
Symbol
VDDIx
Min
Typ
Max
3.45
3.45
2.625
Unit
V
Conditions
3.3 V DC supply voltage
LVDS differential I/O
3.15
3.3
VDDIx
2.375 2.5
2.375 2.5
V
B-LVDS, M-LVDS, Mini-LVDS,
RSDS differential I/O
VDDIx
V
LVPECL differential I/O
VDDIx
3.15
3.3
3.45
V
Reference voltage supply for FDDR VREFx
(Bank0) and MDDR (Bank5)
0.49 × 0.5 × 0.51 × V
VDDIx VDDIx VDDIx
Analog sense circuit supply of
embedded nonvolatile memory
(eNVM). Must be shorted to VPP.
VPPNVM
2.375 2.5
3.15 3.3
2.625
3.45
V
V
2.5 V range
3.3 V range
1. Programming at Industrial temperature range is available only with VPP = 3.3 V.
Note: Power supply ramps must all be strictly monotonic, without plateaus.
Table 5 •
FPGA Operating Limits
Retention
Product
Grade
Programming
Element Temperature
Operating
Temperature
Programming Digest
Digest (Biased/
Cycles Unbiased)
Cycles
Temperature
Commercial FPGA
Min TJ = 0 °C
Max TJ = 85 °C Max TJ = 85 °C
Min TJ = 0 °C
500
Min TJ = 0 °C
Max TJ = 85 °C
2000
20 years
20 years
Industrial1
FPGA
Min TJ = –40 °C Min TJ = –40 °C 500
Max TJ = 100 °C Max TJ = 100 °C
Min TJ = –40 °C 2000
Max TJ = 100 °C
1. Programming at Industrial temperature range is available only with VPP = 3.3 V.
Note: The retention specification is defined as the total number of programing and digest cycles. For example,
20 years of retention after 500 programming cycles.
Note: The digest cycle specification is 2000 digest cycles for every program cycle with a maximum of 500
programming cycles.
Note: If your product qualification requires accelerated programming cycles, see Microsemi SoC Products
Quality and Reliability Report about recommended methodologies.
DS0128 Datasheet Revision 11.0
7
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the embedded operating flash limits.
Embedded Operating Flash Limits
Table 6 •
Maximum
Product
Grade
Programming
Temperature
Operating
Temperature
Programming
Cycles
Retention
(Biased/Unbiased)
Element
Commercial Embedded flash Min TJ = 0 °C
Max TJ = 85 °C
Min TJ = 0 °C
Max TJ = 85 °C up to two million cycles
per eNVM array
< 1000 cycles per page, 20 years
Min TJ = 0 °C
< 10000 cycles per page, 10 years
Max TJ = 85 °C up to 20 million cycles per
eNVM array
Industrial
Embedded flash Min TJ = –40 °C Min TJ = –40 °C < 1000 cycles per page, 20 years
Max TJ = 100 °C Max TJ = 100 °C up to two million cycles
per eNVM array
Min TJ = –40 °C < 10000 cycles per page, 10 years
Max TJ = 100 °C up to 20 million cycles per
eNVM array
Note: If your product qualification requires accelerated programming cycles, see Microsemi SoC Products
Quality and Reliability Report about recommended methodologies.
Table 7 •
Device Storage Temperature and Retention
Product Grade
Storage Temperature (Tstg)
Retention
Commercial
Min TJ = 0 °C
20 years
Max TJ = 85 °C
Industrial
Min TJ = –40 °C
Max TJ = 100 °C
20 years
Table 8 •
High Temperature Data Retention (HTR) Lifetime
TJ (C)
90
HTR Lifetime1 (yrs)
20.5
20.5
20.5
17.0
15.0
13.0
11.5
10.0
8.0
95
100
105
110
115
120
125
130
135
140
145
150
6.0
4.5
3.0
1.5
1. HTR Lifetime is the period during which a verify failure is not expected due
to flash leakage.
DS0128 Datasheet Revision 11.0
8
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 1 • High Temperature Data Retention (HTR)
2.3.1.1
Overshoot/Undershoot Limits
For AC signals, the input signal may undershoot during transitions to –1.0 V for no longer than 10% of
the period. The current during the transition must not exceed 100 mA.
For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10%
of the period. The current during the transition must not exceed 100 mA.
Note: The above specifications do not apply to the PCI standard. The IGLOO2 and SmartFusion2 PCI I/Os are
compliant with the PCI standard including the PCI overshoot/undershoot specifications.
2.3.1.2
Thermal Characteristics
The temperature variable in the Microsemi SoC Products Group Designer software refers to the junction
temperature, not the ambient, case, or board temperatures. This is an important distinction because
dynamic and static power consumption causes the chip's junction temperature to be higher than the
ambient, case, or board temperatures.
EQ1 through EQ3 give the relationship between thermal resistance, temperature gradient, and power.
TJ – TA
------------------
P
JA
=
EQ 1
TJ – TB
------------------
P
JB
=
=
EQ 2
EQ 3
TJ – TC
------------------
P
JC
DS0128 Datasheet Revision 11.0
9
IGLOO2 FPGA and SmartFusion2 SoC FPGA
where
=
JA
JB
JC
TJ
Junction-to-air thermal resistance
=
=
=
=
=
=
=
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Junction temperature
TA
TB
TC
P
Ambient temperature
Board temperature (measured 1.0 mm away from the package edge)
Case temperature
Total power dissipated by the device
Table 9 •
Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices
Still Air
1.0 m/s
2.5 m/s
Device
005
JA
JB
JC
Unit
FG484
VF256
VF400
TQ144
010
19.36
41.30
20.19
42.80
15.81
38.16
16.94
36.80
14.63
35.30
15.41
34.50
9.74
5.27
3.94
4.95
10.80
°C/W
°C/W
°C/W
°C/W
28.41
8.86
37.20
FG484
VF256
VF400
TQ144
025
18.22
37.36
19.40
38.60
14.83
34.26
15.75
32.60
13.62
31.45
14.22
30.30
8.83
4.92
7.89
4.22
8.60
°C/W
°C/W
°C/W
°C/W
24.84
8.11
31.80
FG484
VF256
VF400
FCS325
050
17.03
33.85
18.36
29.17
13.66
30.59
14.89
24.87
12.45
27.85
13.36
23.12
7.66
4.18
6.13
3.41
2.31
°C/W
°C/W
°C/W
°C/W
21.63
7.12
14.44
FG484
FG896
VF400
FCS325
060
15.29
14.70
17.53
27.38
12.19
12.50
14.17
23.18
10.99
10.90
12.63
21.41
6.27
7.20
6.32
12.47
3.24
4.90
2.81
1.59
°C/W
°C/W
°C/W
°C/W
FG484
FG676
VF400
FCS325
090
15.40
15.49
17.45
27.03
12.06
12.21
14.01
22.91
10.85
11.06
12.47
21.25
6.14
7.07
6.22
12.33
3.15
3.87
2.69
1.54
°C/W
°C/W
°C/W
°C/W
FG484
FG676
FCS325
14.64
14.52
26.63
11.37
11.19
22.26
10.16
10.37
20.13
5.43
6.17
14.24
2.77
3.24
2.50
°C/W
°C/W
°C/W
DS0128 Datasheet Revision 11.0
10
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 9 •
Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices (continued)
Still Air
1.0 m/s
2.5 m/s
Device
150
JA
JB
JC
Unit
FC1152
FCS536
FCV484
9.08
6.81
5.87
2.56
3.69
6.73
0.38
1.55
0.10
°C/W
°C/W
°C/W
15.01
16.21
12.06
13.11
10.76
11.84
2.3.1.2.1 Theta-JA
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by
JEDEC (JESD-51), but it has little relevance in the actual performance of the product. It must be used
with caution, but it is useful for comparing the thermal performance of one package with another.
The maximum power dissipation allowed is calculated using EQ4.
T
J(MAX) – TA(MAX)
---------------------------------------------
Maximum power allowed =
JA
EQ 4
The absolute maximum junction temperature is 100 °C. EQ5 shows a sample calculation of the absolute
maximum power dissipation allowed for the M2GL050T-FG896 package at commercial temperature and
in still air, where:
JA = 14.7 °C/W (taken from Table 9, page 10).
TA
= 85 °C
100 °C – 85 °C
14.7 °C/W
---------------------------------------
Maximum power allowed =
= 1.088 W
EQ 5
The power consumption of a device can be calculated using the Microsemi SoC Products Group power
calculator. The device's power consumption must be lower than the calculated maximum power
dissipation by the package.
If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink
may be attached to the top of the case, or the airflow inside the system must be increased.
2.3.1.2.2 Theta-JB
Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the
surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance
from the junction to the board uses an isothermal ring cold plate zone concept. The ring cold plate is
simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is
mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.
2.3.1.2.3 Theta-JC
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the
surface of the chip to the top or bottom surface of the package. It is applicable to packages used with
external heat sinks. Constant temperature is applied to the surface, which acts as a boundary condition.
This only applies to situations where all or nearly all of the heat is dissipated through the surface in
consideration.
2.3.1.3
ESD Performance
See RT0001: Microsemi Corporation - SoC Products Reliability Report for information about ESD.
DS0128 Datasheet Revision 11.0
11
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.2
Power Consumption
The following sections describe the power consumptions of the devices.
2.3.2.1
Quiescent Supply Current
Table 10 • Quiescent Supply Current Characteristics
Modes and Configurations
Power Supplies/Blocks
FPGA Core
Non-Flash*Freeze
Flash*Freeze
On
On
On
0 V
Off
On
On
0 V
VDD/SERDES_[01]_VDD1
VPP/VPPNVM
HPMS_MDDR_PLL_VDDA/FDDR_PLL_VDDA/
CCC_XX[01]_PLL_VDDA/PLL0_PLL1_HPMS_MDDR_VDD
A
SERDES_[01]_PLL_VDDA2
0 V
0 V
SERDES_[01]_L[0123]_VDDAPLL/VDD_2V52
SERDES_[01]_L[0123]_VDDAIIO2
On
On
On
On
3, 4
VDDIx
On
On
VREFx
On
On
MSSDDR CLK
32 kHz
On
32 kHz
Sleep state
50 MHz
Disabled
Disabled
Disabled
RAM
System controller
50 MHz
Enable
Disabled
Disabled
50 MHz oscillator (enable/disable)
1 MHz oscillator (enable/disable)
Crystal oscillator (enable/disable)
1. SERDES_[01]_VDD Power Supply is shorted to VDD
2. SerDes and DDR blocks to be unused.
.
3. VDDIx has been set to ON for test conditions as described. Banks on the east side should always be powered with
the appropriate VDDI bank supplies. For details on bank power supplies, see “Recommendation for Unused Bank
Supplies” table in the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.
4. No Differential (that is to say, LVDS) I/Os or ODT attributes to be used.
Table 11 • SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.2 V) – Typical Process
Symbol
Modes
005
010
025
050
060
090
150
Unit
Conditions
IDC1
Non-
6.2
6.9
8.9
13.1
15.3
15.4
27.5
mA
Typical
Flash*Freeze
(TJ = 25 °C)
24.0
35.2
28.4
41.9
40.6
60.5
67.8
80.6
81.4
144.7 mA
Commercial
(TJ = 85 °C)
102.1 121.4
122.6 219.1 mA
Industrial
(TJ = 100 °C)
DS0128 Datasheet Revision 11.0
12
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 11 • SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.2 V) – Typical Process
Symbol
Modes
005
010
025
050
060
090
150
Unit
Conditions
IDC2
Flash*Freeze
1.4
2.6
3.7
5.1
5.0
5.1
8.9
mA
Typical
(TJ = 25 °C)
12.0
18.5
20.0
30.8
26.6
41.0
35.3
54.5
35.4
54.5
35.7
55.0
57.8
89.0
mA
mA
Commercial
(TJ = 85 °C)
Industrial
(TJ = 100 °C)
Table 12 • SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.26 V) – Worst-Case Process
Symbol
Modes
005
010
025
050
060
090
150
Unit Conditions
IDC1
Non-
Flash*Freeze
43.8
57.0
84.6
132.3
161.4
163.0
242.5
mA Commercial
(TJ= 85 °C)
65.3
85.7
45.6
70.3
127.8
51.7
79.7
200.9
62.7
96.5
245.4
69.3
247.8
70.0
369.0
84.8
mA Industrial
(TJ = 100 °C)
IDC2
Flash*Freeze 29.1
44.9
mA Commercial
(TJ = 85 °C)
106.8
107.8
130.6
mA Industrial
(TJ = 100 °C)
2.3.2.2
Programming Currents
The following tables represent programming, verify and Inrush currents for SmartFusion2 SoC and
IGLOO2 FPGA devices.
Table 13 • Currents During Program Cycle, 0 °C < = TJ <= 85 °C – Typical Process
Power Supplies
Voltage (V) 005
010
53
11
2
025
55
6
050
58
10
3
060
30
9
090
42
12
3
1501
52
Unit
mA
mA
mA
mA
mA
VDD
1.26
3.46
3.46
2.62
3.46
46
8
VPP
12
VPPNVM
VDDI
1
2
3
31
62
7
16
31
8
17
36
8
1
12
12
10
12
17
9
81
84
19
1
Number of banks
10
1. VPP and VPPNVM are internally shorted.
Table 14 • Currents During Verify Cycle, 0 °C <= TJ <= 85 °C – Typical Process
Power Supplies
Voltage (V)
1.26
005
44
6
010
53
5
025
55
3
050
58
15
1
060
33
8
090
1501
51
Unit
mA
mA
mA
mA
mA
VDD
41
11
1
VPP
3.46
12
VPPNVM
VDDI
3.46
1
0
0
1
2.62
31
61
7
16
32
8
17
36
8
1
12
12
10
11
17
9
81
84
19
3.46
1
Number of banks
10
1. VPP and VPPNVM are internally shorted.
DS0128 Datasheet Revision 11.0
13
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 15 • Inrush Currents at Power up, –40 °C <= TJ <= 100 °C – Typical Process
Power Supplies Voltage (V)
005
25
33
134
7
010
32
49
141
8
025
38
36
161
8
050
48
060
45
13
93
10
090
77
150
109
51
Unit
mA
mA
mA
VDD
1.26
3.46
2.62
VPP
180
187
10
36
VDDI
272
9
388
19
Number of banks
2.3.3
Average Fabric Temperature and Voltage Derating Factors
The following table lists the average temperature and voltage derating factors for fabric timing delays
normalized to TJ = 85 °C, in worst-case VDD = 1.14 V.
Table 16 • Average Junction Temperature and Voltage Derating Factors for Fabric Timing Delays
Array Voltage VDD (V) –40 °C
0 °C
0.89
0.80
0.73
25 °C
0.92
0.83
0.76
70 °C
0.98
0.89
0.81
85 °C
1.00
0.91
0.83
100 °C
1.02
1.14
1.2
0.83
0.75
0.69
0.93
1.26
0.85
DS0128 Datasheet Revision 11.0
14
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.4
Timing Model
This section describes timing model and timing parameters.
Figure 2 • Timing Model
The following table lists the timing model parameters in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 17 • Timing Model Parameters
Index Symbol
Description
–1
Unit
ns
For More Information
See Table 137, page 50
See Table 221, page 71
See Table 221, page 71
See Table 227, page 78
See Table 227, page 78
See Table 167, page 56
A
B
TPY
Propagation delay of DDR3 receiver
Clock-to-Q of the input data register
Setup time of the input data register
Input high delay for global clock
Input low delay for global clock
1.605
0.16
TICLKQ
TISUD
TRCKH
TRCKL
TPY
ns
0.357
1.53
ns
C
ns
0.897
2.774
ns
D
E
Input propagation delay of LVDS
receiver
ns
TDP
Propagation delay of a three-input AND 0.198
gate
ns
See Table 223, page 76
DS0128 Datasheet Revision 11.0
15
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 17 • Timing Model Parameters (continued)
Index Symbol
Description
–1
Unit
ns
For More Information
See Table 223, page 76
See Table 169, page 57
F
TDP
TDP
Propagation delay of an OR gate
0.179
2.136
G
Propagation delay of an LVDS
transmitter
ns
H
I
TDP
TDP
Propagation delay of a three-input XOR 0.241
Gate
ns
ns
See Table 223, page 76
See Table 46, page 27
Propagation delay of LVCMOS 2.5 V
transmitter, drive strength of 16 mA on
the MSIO bank
2.412
J
TDP
TDP
Propagation delay of a two-input NAND 0.179
gate
ns
ns
See Table 223, page 76
See Table 46, page 27
K
Propagation delay of LVCMOS 2.5 V
transmitter, drive strength of 8 mA on
the MSIO bank
2.309
L
TCLKQ
TSUD
TDP
Clock-to-Q of the data register
Setup time of the data register
0.108
0.254
ns
ns
ns
See Table 224, page 77
See Table 224, page 77
See Table 223, page 76
M
N
Propagation delay of a two-input AND 0.179
gate
TOCLKQ
TOSUD
TDP
Clock-to-Q of the output data register
Setup time of the output data register
0.263
0.19
ns
ns
ns
See Table 220, page 69
See Table 220, page 69
See Table 114, page 45
O
P
Propagation delay of SSTL2, Class I
transmitter on the MSIO bank
2.055
TDP
Propagation delay of LVCMOS 1.5 V
transmitter, drive strength of 12 mA,
fast slew on the DDRIO bank
3.316
ns
See Table 70, page 34
DS0128 Datasheet Revision 11.0
16
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5
User I/O Characteristics
There are three types of I/Os supported in the IGLOO2 FPGA and SmartFusion2 SoC FPGA families:
MSIO, MSIOD, and DDRIO I/O banks. The I/O standards supported by the different I/O banks is
described in the I/Os section of the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User
Guide.
2.3.5.1
Input Buffer and AC Loading
The following figure shows the input buffer and AC loading.
Figure 3 • Input Buffer AC Loading
TPY
TPYS
Note: TPYS
= Schmitt Trigger Input
PAD
Y
IN
TPY = MAX(TPY(R), TPY(F))
TPYS = MAX(TPYS(R), TPYS(F))
VIH
VTRIP
VCCA
VTRIP
VIL
IN
50%
50%
Y
GND
TPY
(R)
TPYS
(R)
TPY
(F)
TPYS
(F)
DS0128 Datasheet Revision 11.0
17
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5.2
Output Buffer and AC Loading
The following figure shows the output buffer and AC loading.
Figure 4 • Output Buffer AC Loading
Single-Ended I/O Test Setup
TDP
HSTL/PCI Test Setup
TDP
VTT/VDDI
PAD
PAD
Rtt_test
CLOAD
D
OUT
D
OUT
CLOAD
TDP = MAX(TDP(R), TDP(F))
TDP = MAX(TDP(R), TDP(F))
Voltage-Referenced, Singled-Ended I/O Test Setup
TDP
VTT
Rtt_test
CLOAD
PAD
OUT
D
TDP = MAX(TDP(R), TDP(F))
Differential I/O Test Setup
TDP
TPY
PAD_P
OUT
PAD_P
D
IN
PAD_N
PAD_N
TPY = MAX(TPY(R), TPY(F))
TDP = MAX(TDP(R), TDP(F))
TPYS = MAX(TPYS(R), TPYS(F))
DS0128 Datasheet Revision 11.0
18
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5.3
Tristate Buffer and AC Loading
The tristate path for enable path loadings is described in the respective specifications. The following
figure shows the methodology of characterization illustrated by the enable path test point.
Figure 5 • Tristate Buffer for Enable Path Test Point
T
, T , T , T
ZL ZH HZ LZ
E
R
C
to V
DDI
for T , T
ZL LZ
ent
PAD
OUT
D
T
, T , T , T
ent ZL LZ ZH HZ
R
to GND for T , T
ent
ZH HZ
Data
(D)
50%
50%
ZL
Enable
(E)
50%
50%
T
T
LZ
T
T
HZ
ZH
PAD
90% V
DDI
90% V
DDI
10% V
DDI
10% V
DDI
2.3.5.4
I/O Speeds
This section describes the maximum data rate summary of I/O in worst-case industrial conditions. See
the individual I/O standards for operating conditions.
Table 18 • Maximum Data Rate Summary Table for Single-Ended I/O in Worst-Case
Industrial Conditions
I/O
MSIO
630
600
600
410
295
160
120
MSIOD
DDRIO
Unit
PCI 3.3 V
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
LVTTL 3.3 V
LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
LVCMOS 1.2 V
LPDDR-LVCMOS 1.8 V mode
420
400
220
160
400
400
235
200
400
DS0128 Datasheet Revision 11.0
19
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 19 • Maximum Data Rate Summary Table for Voltage-Referenced I/O in Worst-Case
Industrial Conditions
I/O
MSIO
MSIOD
DDRIO
400
Unit
LPDDR
Mbps
Mbps
Mbps
Mbps
Mbps
HSTL1.5 V
SSTL 2.5 V
SSTL 1.8 V
SSTL 1.5 V
400
510
700
400
667
667
Table 20 • Maximum Data Rate Summary Table for Differential I/O in Worst-Case
Industrial Conditions
I/O
MSIO
900
535
535
520
500
500
520
MSIOD
Unit
LVPECL (input only)
LVDS 3.3 V
LVDS 2.5 V
RSDS
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
700
700
BLVDS
MLVDS
Mini-LVDS
700
Table 21 • Maximum Frequency Summary Table for Single-Ended I/O in Worst-Case
Industrial Conditions
I/O
MSIO
315
300
300
205
147.5
80
MSIOD
DDRIO Unit
MHz
PCI 3.3 V
LVTTL 3.3 V
MHz
LVCMOS 3.3 V
LVCMOS 2.5 V
LVCMOS 1.8 V
LVCMOS 1.5 V
LVCMOS 1.2 V
LPDDR– LVCMOS 1.8 V mode
MHz
210
200
110
80
200
200
118
100
200
MHz
MHz
MHz
MHz
MHz
60
DS0128 Datasheet Revision 11.0
20
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 22 • Maximum Frequency Summary Table for Voltage-Referenced I/O in Worst-
Case Industrial Conditions
I/O
MSIO
MSIOD
DDRIO Unit
LPDDR
200
200
200
334
334
MHz
MHz
MHz
MHz
MHz
HSTL1.5 V
SSTL 2.5 V
SSTL 1.8 V
SSTL 1.5 V
255
350
Table 23 • Maximum Frequency Summary Table for Differential I/O in Worst-Case
Industrial Conditions
I/O
MSIO
450
MSIOD
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVPECL (input only)
LVDS 3.3 V
LVDS 2.5 V
RSDS
267.5
267.5
260
350
350
BLVDS
250
MLVDS
250
Mini-LVDS
260
350
DS0128 Datasheet Revision 11.0
21
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5.5
Detailed I/O Characteristics
Table 24 • Input Capacitance, Leakage Current, and Ramp Time
Symbol Description
Maximum Unit
Conditions
CIN
Input capacitance
10
pF
µA
µA
µA
µA
IIL (dc)
Input current low
(Applicable to HSTL/SSTL inputs only)
400
500
600
10
VDDI = 2.5 V
VDDI = 1.8 V
V
DDI = 1.5 V1
Input current low
(Applicable to all other digital inputs)
IIH (dc)
Input current high
(Applicable to HSTL/SSTL inputs only)
400
500
600
10
µA
µA
µA
µA
VDDI = 2.5 V
VDDI = 1.8 V
V
DDI = 1.5 V1
Input current high
(Applicable to all other digital inputs)
2
TRAMPIN Input ramp time
(Applicable to all digital inputs)
50
ns
1. Applicable when I/O pair is programmed with an HSTL/SSTL I/O type on IOP and an un-
terminated I/O type (LVCMOS, for example) on ION pad.
2. Voltage ramp must be monotonic.
The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of
DDRIO I/O bank at VOH/VOL Level.
Table 25 • I/O Weak Pull-up/Pull-down Resistances for DDRIO I/O Bank
R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL (
VDDI Domain Min
Max
Min
Max
2.5 V1, 2
1.8 V1, 2
1.5 V1, 2
1.2 V1, 2
10K
17.8K
19.1K
20.2K
22.7K
9.98K
10.3K
10.6K
11.2K
18K
10.3K
10.6K
11.1K
19.5K
21.1K
24.6K
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).
2. R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).
DS0128 Datasheet Revision 11.0
22
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of
MSIO I/O bank at VOH/VOL Level.
Table 26 • I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank
R(WEAK PULL-UP) at VOH ( R(WEAK PULL-DOWN) at VOL (
VDDI Domain Min
Max
Min
Max
3.3 V
9.9K
17.1K
17.6K
19.1K
20.4K
23.2K
9.98K
10.1K
10.4K
10.8K
11.5K
17.5K
18.4K
20.4K
22.2K
26.7K
2.5 V1, 2
1.8 V1, 2
1.5 V1, 2
1.2 V1, 2
10K
10.4K
10.7K
11.3K
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).
2. R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).
The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of
MSIOD I/O bank at VOH/VOL Level.
Table 27 • I/O Weak Pull-up/Pull-down Resistances for MSIOD I/O Bank
R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at VOL ()
VDDI Domain Min
Max
Min
Max
2.5 V1, 2
1.8 V1, 2
1.5 V1, 2
1.2 V1, 2
9.6K
9.7K
9.9K
10.3K
16.6K
17.3K
18K
9.5K
9.7K
9.8K
10K
16.4K
17.1K
17.6K
19.1K
19.6K
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX).
2. R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN).
The following table lists the hysteresis voltage value for schmitt trigger mode input buffers.
Table 28 • Schmitt Trigger Input Hysteresis
Input Buffer Configuration
Hysteresis Value (Typical, unless otherwise noted)
3.3 V LVTTL/LVCMOS/
PCI/PCI-X
0.05 × VDDI (worst-case)
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
0.05 × VDDI (worst-case)
0.1 × VDDI (worst-case)
60 mV
20 mV
DS0128 Datasheet Revision 11.0
23
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5.6
Single-Ended I/O Standards
2.3.5.6.1 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined
by JEDEC (JESD 8-5). The LVCMOS standards supported in IGLOO2 FPGAs and SmartFusion2 SoC
FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33.
2.3.5.6.2 3.3 V LVCMOS/LVTTL
LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V
applications.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 29 • LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions
(Applicable to MSIO I/O Bank Only)
Parameter
Symbol
Min
Typ Max
Unit
Supply voltage
VDDI
3.15
3.3 3.45
V
Table 30 • LVTTL/LVCMOS 3.3 V Input Voltage Specification (Applicable to MSIO I/O
Bank Only)
Parameter
Symbol
Min
2.0
Max
3.45
0.8
Unit
V
DC input logic high
DC input logic low
Input current high1
Input current low1
VIH (DC)
V
IL (DC)
–0.3
V
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
Table 31 • LVCMOS 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank
Only)
Parameter
Symbol
VOH
Min
Max
Unit
V
DC output logic high1
DC output logic low1
VDDI – 0.4
VOL
0.4
V
1. The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B
requirements.
Table 32 • LVTTL 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only)
Parameter
Symbol
VOH
Min
Max
Unit
V
DC output logic high
DC output logic low
2.4
VOL
0.4
V
Table 33 • LVTTL/LVCMOS 3.3 V AC Maximum Switching Speed (Applicable to MSIO I/O Bank
Only)
Parameter
Symbol
Max Unit
Conditions
Maximum data rate
(for MSIO I/O bank)
DMAX
600 Mbps AC loading: 17 pF load, maximum
drive/slew
DS0128 Datasheet Revision 11.0
24
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 34 • LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO I/O
Bank Only)
Parameter
Symbol
VTRIP
RENT
Typ Unit
Measuring/trip point for data path
1.4
2K
5
V
Resistance for enable path (TZH, TZL, THZ, TLZ
)
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
pF
Capacitive loading for data path (TDP
)
CLOAD
5
Table 35 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications for MSIO I/O Bank
VOH
Output Drive Selection (V)
VOL
(V)
IOH (at VOH
mA
)
IOL (at VOL
mA
)
2 mA
VDDI – 0.4 0.4
VDDI – 0.4 0.4
2
2
4 mA
4
4
8 mA
VDDI – 0.4
0.4
8
8
12 mA
16 mA
20 mA
V
DDI – 0.4 0.4
12
16
20
12
16
20
VDDI – 0.4 0.4
VDDI – 0.4 0.4
Note: For a detailed I/V curve, use the corresponding IBIS models:
www.microsemi.com/soc/download/ibis/default.aspx.
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 3.0 V
Table 36 • LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Bank (Input
Buffers)
TPY
–Std
2.663
TPYS
–Std
2.695
On-Die Termination
(ODT)
–1
–1
Unit
None
2.262
2.289
ns
Table 37 • LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection
TDP
–Std
TZL
TZH
–Std
THZ
TLZ
Slew
Control
–1
3.192 3.755 3.47
2.331 2.742 2.673 3.145 2.526 2.973 3.034 3.569 4.451 5.236 ns
2.135 2.511 2.33 2.741 2.297 2.703 4.532 5.331 4.825 5.676 ns
2.052 2.414 2.107 2.479 2.162 2.544 5.75 6.764 5.445 6.406 ns
2.062 2.425 2.072 2.438 2.145 2.525 5.993 7.05 5.625 6.618 ns
2.148 2.527 1.999 2.353 2.088 2.458 6.262 7.367 5.876 6.913 ns
–1
–Std
–1
–1
–Std
–1
–Std
Unit
2 mA
Slow
Slow
Slow
Slow
Slow
Slow
4.083 2.969 3.494 1.856 2.183 3.337 3.926 ns
4 mA
8 mA
12 mA
16 mA
20 mA
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
DS0128 Datasheet Revision 11.0
25
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.5.7 2.5 V LVCMOS
LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in IGLOO2 FPGA and
SmartFusion2 SoC FPGAs that are in compliance with the JEDEC specification JESD8-5A.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 38 • LVCMOS 2.5 V DC Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
2.375
2.5
2.625
V
Table 39 • LVCMOS 2.5 V DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
DC input logic high (for MSIOD
and DDRIO I/O banks)
VIH (DC)
1.7
2.625
V
DC input logic high (for MSIO I/O VIH (DC)
bank)
1.7
3.45
0.7
V
V
DC input logic low
Input current high1
Input current low1
VIL (DC)
IIH (DC)
IIL (DC)
–0.3
1. See Table 24, page 22.
Table 40 • LVCMOS 2.5 V DC Output Voltage Specification
Parameter
Symbol
Min
Max
Unit
V
1
DC output logic high
DC output logic low
VOH
VDDI – 0.4
–
2
VOL
0.4
V
1. The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.
Table 41 • LVCMOS 2.5 V AC Minimum and Maximum Switching Speed
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate (for DDRIO I/O bank)
DMAX
400
Mbps
AC loading: 17 pF load,
maximum drive/slew
Maximum data rate (for MSIO I/O bank)
Maximum data rate (for MSIOD I/O bank)
DMAX
DMAX
410
420
Mbps
Mbps
AC loading: 17 pF load,
maximum drive/slew
AC loading: 17 pF load,
maximum drive/slew
Table 42 • LVCMOS 2.5 V AC Calibrated Impedance Option
Parameter
Symbol
Typ
Unit
Supported output driver calibrated impedance (for
DDRIO I/O bank)
Rodt_cal
75, 60, 50, 33,
25, 20
DS0128 Datasheet Revision 11.0
26
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 43 • LVCMOS 2.5 V AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
1.2
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Capacitive loading for data path (TDP
)
pF
pF
)
CENT
)
CLOAD
5
Table 44 • LVCMOS 2.5 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
VOL (V) IOH (at VOH) mA IOL (at VOL) mA
DDRIO I/O Bank
MSIO I/O MSIOD I/O (With Software Default
Bank
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Bank
2 mA
4 mA
6 mA
8 mA
12 mA
Fixed Code)
Min
Max
2 mA
VDDI – 0.4
VDDI – 0.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
4 mA
4
4
6 mA
VDDI – 0.4
6
6
8 mA
VDDI – 0.4
VDDI – 0.4
8
8
12 mA
16 mA
12
16
12
16
VDDI – 0.4
Note: For board design considerations, output slew rates extraction, detailed output buffer resistances, and I/V
Curve, use the corresponding IBIS models located at:
www.microsemi.com/soc/download/ibis/default.aspx.
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V
Table 45 • LVCMOS 2.5 V Receiver Characteristics (Input Buffers)
TPY
–Std
TPYS
–Std
On-Die Termination
(ODT)
–1
–1
Unit
ns
LVCMOS 2.5 V (for DDRIO I/O bank)
LVCMOS 2.5 V (for MSIO I/O bank)
LVCMOS 2.5 V (for MSIOD I/O bank)
None
None
None
1.823
2.486
2.29
2.145
2.925
2.694
1.932
2.495
2.305
2.274
2.935
2.712
ns
ns
Table 46 • LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
THZ
TLZ
Slew
–1
3.657 4.302 3.393 3.991 3.675
3.374 3.97 3.139 3.693 3.396
–1
–1
–Std
–1
–Std
–1
–Std
Unit
ns
2 mA
Slow
4.323 3.894 4.582 3.552 4.18
Medium
3.995 3.635 4.277 3.253 3.828 ns
3.836 3.519 4.141 3.128 3.681 ns
Medium fast 3.239 3.811 3.036 3.572 3.261
Fast 3.224 3.793 3.029 3.563 3.246
3.818 3.512 4.132 3.119 3.67
ns
DS0128 Datasheet Revision 11.0
27
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 46 • LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers)
(continued)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
–1
–1
–1
–Std
–1
–Std
Unit
4 mA
6 mA
8 mA
12 mA
16 mA
Slow
3.095 3.641 2.705 3.182 3.088
2.825 3.324 2.488 2.927 2.823
3.633 4.738 5.575 4.348 5.116 ns
3.321 4.492 5.285 4.063 4.781 ns
3.173 4.364 5.135 3.945 4.642 ns
Medium
Medium fast 2.701 3.178 2.384 2.804 2.698
Fast
2.69
2.919 3.434 2.491 2.93
2.65 3.118 2.279 2.681 2.642
2.521
2.168 2.551 2.508
3.165 2.377 2.796 2.687
3.161 4.359 5.129 3.94
4.636 ns
ns
Slow
2.902
3.414 5.085 5.983 4.674 5.5
Medium
3.108 4.845 5.701 4.375 5.148 ns
2.965 4.724 5.558 4.259 5.011 ns
Medium fast 2.529 2.975 2.176 2.56
Fast
2.516 2.96
2.95
4.717 5.55
4.251 5.002 ns
Slow
2.863 3.368 2.427 2.855 2.844
2.599 3.058 2.217 2.608 2.59
3.346 5.196 6.114 4.769 5.612 ns
3.047 4.952 5.827 4.471 5.261 ns
Medium
Medium fast 2.483 2.921 2.114 2.487 2.473
2.91
2.89
4.832 5.685 4.364 5.134 ns
4.826 5.678 4.348 5.116 ns
Fast
2.467 2.902 2.106 2.478 2.457
2.747 3.232 2.296 2.701 2.724
2.493 2.934 2.102 2.473 2.483
Slow
3.204 5.39
6.342 4.938 5.81
ns
Medium
2.921 5.166 6.078 4.65
5.471 ns
Medium fast 2.382 2.803 2.006 2.36
2.371
2.789 5.067 5.962 4.546 5.349 ns
2.773 5.063 5.958 4.538 5.339 ns
Fast
2.369 2.787 1.999 2.352 2.357
2.677 3.149 2.213 2.604 2.649
2.432 2.862 2.028 2.386 2.421
Slow
3.116 5.575 6.56
5.08
4.801 5.649 ns
5.531 ns
2.706 5.296 6.231 4.699 5.529 ns
5.977 ns
Medium
2.848 5.372 6.32
Medium fast 2.324 2.734 1.937 2.278 2.311
Fast 2.313 2.721 1.929 2.269 2.3
2.718 5.297 6.233 4.7
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
Table 47 • LVCMOS 2.5 V Transmitter Characteristics for MSIO Bank (Output and Tristate Buffers)
1
1
Output
Drive
TDP
TZL
TZH
THZ
TLZ
Slew
Selection Control
–1
–Std
–1
–Std
–1
–Std
4.453 2.12
3.691 4.143 4.874 4.687 5.513 ns
3.317 4.909 5.775 5.083 5.98 ns
3.223 5.812 6.837 5.523 6.497 ns
3.089 6.131 7.213 5.712 6.72 ns
2.979 6.54 7.694 6.007 7.067 ns
–1
–Std
–1
–Std
Unit
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Slow
Slow
Slow
Slow
Slow
Slow
3.48
4.095 3.855 4.534 3.785
2.494 3.45
4.059 ns
2.583 3.039 3.042 3.579 3.138
2.392 2.815 2.669 3.139 2.82
2.309 2.717 2.565 3.017 2.74
2.333 2.745 2.437 2.867 2.626
2.412 2.838 2.335 2.747 2.533
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
DS0128 Datasheet Revision 11.0
28
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 48 • LVCMOS 2.5 V Transmitter Characteristics for MSIOD Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
TZL
TZH
–Std
THZ
TLZ
Slew
–1
–Std
–1
–Std
–1
–1
–Std
–1
–Std
Unit
2 mA
4 mA
6 mA
8 mA
12 mA
Slow
Slow
Slow
Slow
Slow
2.206 2.596 2.678 3.15
2.64
3.106 4.935 5.805 4.74
2.654 5.413 6.368 5.15
5.576 ns
6.059 ns
1.835 2.159 2.242 2.637 2.256
1.709 2.01 2.132 2.508 2.167
1.63 1.918 1.958 2.303 2.012
1.648 1.939 1.86 2.187 1.921
2.549 5.813 6.838 5.499 6.469 ns
2.367 6.226 7.324 5.816 6.842 ns
2.259 6.519 7.669 6.027 7.09
ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
2.3.5.8 1.8 V LVCMOS
LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in IGLOO2 FPGAs and
SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-7A.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 49 • LVCMOS 1.8 V DC Recommended Operating Conditions
Parameter
Symbol Min
LVCMOS 1.8 V DC Recommended Operating Conditions
Supply voltage VDDI 1.710 1.8 1.89
Typ Max
Unit
V
Table 50 • LVCMOS 1.8 V DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
DC input logic high (for MSIOD
and DDRIO I/O banks)
V
V
V
IH (DC)
IH (DC)
IL (DC)
0.65 × VDDI
1.89
V
DC input logic high (for MSIO
I/O bank)
0.65 × VDDI
–0.3
3.45
V
DC input logic low
Input current high1
Input current low1
0.35 × VDDI
V
–
–
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
Table 51 • LVCMOS 1.8 V DC Output Voltage Specification
Parameter
Symbol
VOH
Min
Max
Unit
DC output logic high
DC output logic low
VDDI – 0.45
V
V
VOL
0.45
Table 52 • LVCMOS 1.8 V Minimum and Maximum AC Switching Speed
Parameter
Symbol Max Unit Conditions
Maximum data rate (for DDRIO I/O bank)1 DMAX
400
295
400
Mbps AC loading: 17 pF load, maximum drive/slew
Mbps AC loading: 17 pF load, maximum drive/slew
Mbps AC loading: 17 pF load, maximum drive/slew
Maximum data rate (for MSIO I/O bank)
DMAX
Maximum data rate (for MSIOD I/O bank)1 DMAX
1. Maximum Data Rate applies for Drive Strength 8 mA and above, All Slews.
DS0128 Datasheet Revision 11.0
29
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 53 • LVCMOS 1.8 V AC Calibrated Impedance Option
Parameter
Symbol
Typ
Unit
Supported output driver calibrated
impedance (for DDRIO I/O bank)
Rodt_cal
75, 60, 50,
33, 25, 20
Table 54 • LVCMOS 1.8 V AC Test Parameter Specifications
Parameter
Symbol
VTRIP
Typ
0.9
2k
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, CENT
TLZ
5
pF
)
Capacitive loading for data path (TDP
)
CLOAD
5
pF
Table 55 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
DDRIO I/O Bank Min
VOL (V)
IOH (at VOH
mA
)
IOL (at VOL
mA
)
MSIO I/O Bank MSIOD I/O Bank
Max
0.45
0.45
0.45
0.45
0.45
0.45
0.45
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
10 mA
2 mA
VDDI – 0.45
2
2
4 mA
V
V
DDI – 0.45
DDI – 0.45
4
4
6 mA
6
6
8 mA
VDDI – 0.45
8
8
10 mA
12 mA
16 mA1
V
V
DDI – 0.45
DDI – 0.45
10
12
16
10
12
16
VDDI – 0.45
1. 16 mA drive strengths, all slews, meets LPDDR JEDEC electrical compliance.
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.71 V
Table 56 • LVCMOS 1.8 V Receiver Characteristics (Input Buffers)
TPY
–Std
TPYS
On-Die Termination
(ODT)
–1
–1
–Std
Unit
LVCMOS 1.8 V
None
1.968
2.315
2.099
2.47
ns
(for DDRIO I/O bank
with Fixed Codes)
None
50
2.898
3.05
3.411
3.59
2.883
3.044
2.987
2.933
2.598
2.775
2.712
2.655
3.393
3.583
3.516
3.452
3.057
3.265
3.19
ns
ns
ns
ns
ns
ns
ns
ns
75
2.999
2.947
2.611
2.775
2.72
3.53
LVCMOS 1.8 V
(for MSIO I/O bank)
150
None
50
3.469
3.071
3.264
3.2
75
LVCMOS 1.8 V
(for MSIOD I/O bank)
150
2.666
3.137
3.123
DS0128 Datasheet Revision 11.0
30
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 57 • LVCMOS 1.8 V Transmitter Characteristics for DDRIO I/O Bank with Fixed Code (Output and
Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std –1
TZL
–Std
TZH
THZ
TLZ
Slew
–1
4.234 4.981 3.646 4.29
3.824 4.498 3.282 3.861 3.834 4.511 4.625 5.441 4.116 4.843 ns
3.637 4.279 4.481 5.272 3.984 4.687 ns
3.605 4.241 3.097 3.644 3.615 4.253 4.472 5.262 3.973 4.674 ns
3.923 4.615 3.314 3.9 3.918 4.61 5.403 6.356 4.894 5.757 ns
3.518 4.138 2.961 3.484 3.515 4.135 5.121 6.025 4.561 5.366 ns
–1
–Std
–1
–Std
–1
–Std
Unit
2 mA
Slow
4.245 4.995 4.908 5.774 4.434 5.216 ns
Medium
Medium fast 3.627 4.267 3.111 3.66
Fast
4 mA
Slow
Medium
Medium fast 3.321 3.907 2.783 3.275 3.317 3.903 4.966 5.843 4.426 5.206 ns
Fast
3.301 3.883 2.77
3.259 3.296 3.878 4.957 5.831 4.417 5.196 ns
4.364 3.104 3.652 3.702 4.355 5.62 6.612 5.08 5.977 ns
3.325 3.913 5.346 6.289 4.777 5.62 ns
6 mA
Slow
3.71
Medium
3.333 3.921 2.779 3.27
Medium fast 3.155 3.712 2.62
3.083 3.146 3.702 5.21
6.13
4.657 5.479 ns
4.648 5.468 ns
Fast
3.134 3.688 2.608 3.068 3.125 3.677 5.202 6.12
8 mA
Slow
3.619 4.258 3.007 3.538 3.607 4.244 5.815 6.841 5.249 6.175 ns
3.246 3.819 2.686 3.16 3.236 3.807 5.542 6.52 4.936 5.807 ns
ns
3.046 3.584 2.513 2.957 3.034 3.57 5.401 6.353 4.803 5.651 ns
Medium
Medium fast 3.066 3.607 2.525 2.971 3.054 3.593 5.405 6.359 4.811 5.66
Fast
10 mA
12 mA
16 mA
Slow
3.498 4.115 2.878 3.386 3.481 4.096 6.046 7.113 5.444 6.404 ns
3.138 3.692 2.569 3.023 3.126 3.678 5.782 6.803 5.129 6.034 ns
Medium
Medium fast 2.966 3.489 2.414 2.841 2.951 3.472 5.666 6.665 5.013 5.897 ns
Fast
2.945 3.464 2.401 2.826 2.93
3.417 4.02 2.807 3.303 3.401 4.002 6.083 7.156 5.464 6.428 ns
3.076 3.618 2.519 2.964 3.063 3.604 5.828 6.856 5.176 6.089 ns
5.725 6.736 5.072 5.966 ns
2.879 3.388 5.715 6.724 5.064 5.957 ns
3.448 5.659 6.658 5.003 5.886 ns
Slow
Medium
Medium fast 2.913 3.427 2.376 2.795 2.898 3.41
Fast
2.894 3.405 2.362 2.78
3.366 3.96 2.751 3.237 3.348 3.939 6.226 7.324 5.576 6.56
3.03 3.565 2.47
Slow
ns
Medium
2.906 3.017 3.55
5.981 7.036 5.282 6.214 ns
Medium fast 2.87
3.377 2.328 2.739 2.854 3.358 5.895 6.935 5.18
6.094 ns
ns
Fast 2.853 3.357 2.314 2.723 2.837 3.338 5.889 6.929 5.177 6.09
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
DS0128 Datasheet Revision 11.0
31
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 58 • LVCMOS 1.8 V Transmitter Characteristics for MSIO I/O Bank
1
1
TDP
–Std –1
3.441 4.047 4.165 4.9
3.218 3.786 3.642 4.284 3.941 4.636 5.665 6.665 5.568 6.551 ns
3.141 3.694 3.501 4.118 3.823 4.498 6.587 7.75 6.032 7.096 ns
3.165 3.723 3.319 3.904 3.654 4.298 6.898 8.115 6.216 7.313 ns
3.202 3.767 3.278 3.857 3.616 4.254 7.25 8.529 6.435 7.571 ns
3.277 3.855 3.175 3.736 3.519 4.139 7.392 8.697 6.538 7.692 ns
TZL
TZH
–Std
4.413 5.192 4.891 5.755 5.138 6.044 ns
THZ
TLZ
Output Drive Slew
Selection
Control
–1
–Std
–1
–1
–Std
–1
–Std
Unit
2 mA
Slow
Slow
Slow
Slow
Slow
Slow
4 mA
6 mA
8 mA
10 mA
12 mA
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
Table 59 • LVCMOS 1.8 V Transmitter Characteristics for MSIOD I/O Bank
1
1
TDP
–Std –1
2.725 3.206 3.316 3.901 3.484 4.099 5.204 6.123 4.997 5.88
2.242 2.638 2.777 3.267 2.947 3.466 5.729 6.74 5.448 6.41
TZL
TZH
THZ
TLZ
Output Drive Slew
Selection
Control
–1
–Std
–1
–Std
–1
–Std
–1
–Std
Unit
ns
2 mA
Slow
Slow
Slow
Slow
Slow
4 mA
ns
6 mA
1.995 2.347 2.466 2.901 2.63
2.001 2.354 2.44 2.87 2.6
2.025 2.382 2.312 2.719 2.47
3.094 6.372 7.496 5.987 7.043 ns
3.058 6.633 7.804 6.193 7.286 ns
8 mA
10 mA
2.906 6.94
8.165 6.412 7.544 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
2.3.5.9 1.5 V LVCMOS
LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in IGLOO2 FPGAs and
SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-11A.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 60 • LVCMOS 1.5 V DC Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
1.425
1.5
1.575
V
Table 61 • LVCMOS 1.5 V DC Input Voltage Specification
Parameter Symbol Min
Max
Unit
DC input logic high for (MSIOD and DDRIO VIH (DC)
I/O banks)
0.65 × VDDI 1.575
V
DC input logic high (for MSIO I/O bank)
DC input logic low
VIH (DC)
IL (DC)
0.65 × VDDI 3.45
V
V
–
V
–0.3
0.35 × VDDI
Input current high1
IIH (DC)
IIL (DC
Input current low1
–
1. See Table 24, page 22.
DS0128 Datasheet Revision 11.0
32
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 62 • LVCMOS 1.5 V DC Output Voltage Specification
Parameter
DC output logic high VOH
DC output logic low VOL
Symbol Min
Max
Unit
V
VDDI × 0.75
VDDI × 0.25
V
Table 63 • LVCMOS 1.5 V AC Minimum and Maximum Switching Speed
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate (for DDRIO I/O bank)
DMAX
235
Mbps
AC loading: 17 pF load, maximum
drive/slew
Maximum data rate (for MSIO I/O bank)
Maximum data rate (for MSIOD I/O bank)
DMAX
DMAX
160
220
Mbps
Mbps
AC loading: 17 pF load, maximum
drive/slew
AC loading: 17 pF load, maximum
drive/slew
Table 64 • LVCMOS 1.5 V AC Calibrated Impedance Option
Parameter
Symbol
RODT_CA 75, 60,
50, 40
Typ
Unit
Supported output driver calibrated
impedance (for DDRIO I/O bank)
L
Table 65 • LVCMOS 1.5 V AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
0.75
2K
5
Unit
V
Measuring/trip point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
pF
Capacitive loading for data path (TDP
)
CLOAD
5
Table 66 • LVCMOS 1.5 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
VOL (V)
IOH (at VOH
mA
)
IOL (at VOL
mA
)
MSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank Min
Max
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
VDDI × 0.75
DDI × 0.75
VDDI × 0.25
VDDI × 0.25
VDDI × 0.25
VDDI × 0.25
VDDI × 0.25
VDDI × 0.25
2
2
V
4
4
VDDI × 0.75
VDDI × 0.75
6
6
8
8
VDDI × 0.75
10
12
10
12
VDDI × 0.75
Note: For a detailed I/V curve, use the corresponding IBIS models:
www.microsemi.com/soc/download/ibis/default.aspx.
DS0128 Datasheet Revision 11.0
33
IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.425 V
Table 67 • LVCMOS 1.5 V Receiver Characteristics for DDRIO I/O Bank with Fixed
Codes (Input Buffers)
TPY
–Std
2.051 2.413 2.086 2.455 ns
TPYS
On-Die Termination
(ODT)
–1
–1
–Std
Unit
None
Table 68 • LVCMOS 1.5 V Receiver Characteristics for MSIO I/O Bank (Input
Buffers)
TPY
–Std
TPYS
–Std
On-Die Termination
(ODT)
–1
–1
Unit
ns
None
50
3.311
3.654
3.533
3.415
3.896
4.299
4.156
4.018
3.285
3.623
3.501
3.388
3.865
4.263
4.119
3.986
ns
75
ns
150
ns
Table 69 • LVCMOS 1.5 V Receiver Characteristics for MSIOD I/O Bank (Input
Buffers)
TPY
–Std
2.959 3.481 2.93
3.298 3.88 3.268 3.845 ns
3.162 3.719 3.128 3.68 ns
3.053 3.592 3.021 3.554 ns
TPYS
–Std
3.447 ns
On-Die Termination
(ODT)
–1
–1
Unit
None
50
75
150
Table 70 • LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
–1
–1
–1
–Std –1
–Std Unit
2 mA
Slow
5.122
4.58
4.323
6.026 4.31
5.389 3.86
5.07
4.54
5.145
4.6
6.052
5.411
5.107
5.258 6.186 4.672 5.496 ns
4.977 5.855 4.357 5.126 ns
4.804 5.652 4.228 4.974 ns
Medium
Medium
fast
5.086 3.629 4.269 4.341
Fast
4.296
4.449
3.961
3.729
5.054 3.609 4.245 4.314
5.235 3.707 4.361 4.443
5.075
5.227
4.651
4.376
4.791 5.636 4.219 4.963 ns
6.058 7.127 5.458 6.421 ns
5.778 6.797 5.116 6.018 ns
4 mA
Slow
Medium
4.66
3.264 3.839 3.954
Medium
fast
4.387 3.043 3.579 3.72
5.63
6.624 4.981 5.86
ns
Fast
3.704
4.358 3.027 3.56
3.695
4.347
5.624 6.617 4.973 5.851 ns
DS0128 Datasheet Revision 11.0
34
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 70 • LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)
(continued)
1
1
Output
Drive
Selection Control
TDP
TZL
TZH
–Std
THZ
TLZ
Slew
–1
–Std
–1
–Std
–1
–1
–Std –1
–Std Unit
6 mA
Slow
4.244
3.774
3.544
4.993 3.465 4.076 4.233
4.979
4.426
4.152
6.39
7.518 5.736 6.748 ns
Medium
4.44
4.17
3.05
3.587 3.762
6.114 7.193 5.397 6.35
5.978 7.033 5.27 6.2
ns
ns
Medium
fast
2.839 3.339 3.529
Fast
3.519
4.099
3.656
3.437
4.14
2.82
3.317 3.504
4.122
4.807
4.284
4.023
5.965 7.017 5.259 6.187 ns
6.584 7.746 5.854 6.888 ns
6.311 7.425 5.553 6.533 ns
6.182 7.273 5.435 6.394 ns
8 mA
Slow
4.823 3.311 3.894 4.087
4.301 2.927 3.443 3.642
4.044 2.731 3.213 3.42
Medium
Medium
fast
Fast
3.41
4.012 2.715 3.193 3.393
3.991
4.723
4.218
3.958
6.178 7.269 5.425 6.383 ns
6.732 7.921 5.965 7.018 ns
6.473 7.615 5.669 6.669 ns
10 mA
12 mA
Slow
4.029
3.601
3.384
4.74
3.238 3.809 4.015
Medium
4.237 2.867 3.372 3.586
3.981 2.672 3.143 3.365
Medium
fast
6.351 7.471 5.55
6.529 ns
Fast
3.357
3.974
3.55
3.949 2.655 3.123 3.338
4.675 3.196 3.759 3.958
4.176 2.827 3.326 3.534
3.935 2.638 3.103 3.325
3.927
4.656
4.157
3.911
6.345 7.464 5.54
6.518 ns
Slow
6.842 8.049 6.068 7.139 ns
6.584 7.746 5.751 6.766 ns
6.488 7.633 5.641 6.637 ns
Medium
Medium
fast
3.345
Fast
3.316
3.902 2.621 3.083 3.297
3.878
6.486 7.63
5.626 6.619 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
Table 71 • LVCMOS 1.5 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
TZL
TZH
–Std
THZ
TLZ
Slew
–1
–Std
–1
–Std
–1
–1
–Std –1
–Std Unit
2 mA
4 mA
6 mA
8 mA
Slow
Slow
Slow
Slow
4.423
4.05
4.081
4.234
5.203 5.397 6.35
5.686
6.69
5.609 6.599 5.561 6.542 ns
7.358 8.657 6.525 7.677 ns
7.659 9.011 6.709 7.893 ns
4.765 4.503 5.298 4.92
4.801 4.259 5.012 4.699
5.788
5.528
5.319
4.98
4.068 4.786 4.521
8.218 9.668 7.05
8.294 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
DS0128 Datasheet Revision 11.0
35
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 72 • LVCMOS 1.5 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
–1
–1
–1
–Std –1
–Std Unit
2 mA
4 mA
6 mA
Slow
Slow
Slow
2.735
2.426
2.433
3.218 3.371 3.966 3.618
2.854 2.992 3.521 3.221
4.257
3.79
6.03
7.095 5.705 6.712 ns
6.738 7.927 6.298 7.41
7.123 8.38 6.596 7.76
ns
ns
2.862 2.81
3.306 3.031
3.566
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
2.3.5.10 1.2 V LVCMOS
LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in IGLOO2 FPGAs and
SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-12A.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 73 • LVCMOS 1.2 V DC Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
1.140
1.2
1.26
V
Table 74 • LVCMOS 1.2 V DC Input Voltage Specification
Parameter
Symbol Min
Max
Unit
DC input logic high (for
MSIOD and DDRIO I/O
banks)
VIH (DC) 0.65 × VDDI 1.26
V
DC input logic high (for
MSIO I/O bank)
VIH (DC) 0.65 × VDDI 3.45
V
V
DC input logic low
Input current high1
Input current low1
VIL (DC) –0.3
IIH (DC)
0.35 × VDDI
IIL (DC)
1. See Table 24, page 22.
Table 75 • LVCMOS 1.2 V DC Output Voltage Specification
Parameter
Symbol Min
Max
Unit
V
DC output logic high
DC output logic low
VOH
VOL
VDDI × 0.75
VDDI × 0.25
V
Table 76 • LVCMOS 1.2 V Minimum and Maximum AC Switching Speed
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate (for DDRIO I/O bank) DMAX
200
Mbps
AC loading: 17 pF load, maximum
drive/slew
Maximum data rate (for MSIO I/O bank)
DMAX
120
160
Mbps
Mbps
AC loading: 17 pF load, maximum
drive/slew
Maximum data rate (for MSIOD I/O bank) DMAX
AC loading: 17 pF load, maximum
drive/slew
DS0128 Datasheet Revision 11.0
36
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 77 • LVCMOS 1.2 V AC Calibrated Impedance Option
Parameter
Symbol
Typ
Unit
Supported output driver calibrated
impedance (for DDRIO I/O bank)
RODT_CAL
75, 60, 50, 40
Table 78 • LVCMOS 1.2 V AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
0.6
2K
5
Unit
V
Measuring/trip point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Capacitive loading for data path (TDP
)
CENT
pF
pF
)
CLOAD
5
Table 79 • LVCMOS 1.2 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
VOL (V)
Max
IOH (at VOH
mA
)
IOL (at VOL
mA
)
MSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank Min
2 mA
4 mA
2 mA
4 mA
2 mA
4 mA
6 mA
VDDI × 0.75 VDDI × 0.25
VDDI × 0.75 VDDI × 0.25
2
4
6
2
4
6
V
DDI × 0.75 VDDI × 0.25
Note: For a detailed I/V curve, use the corresponding IBIS models:
www.microsemi.com/soc/download/ibis/default.aspx.
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.14 V
Table 80 • LVCMOS 1.2 V Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input
Buffers)
TPY
–Std
2.88
TPYS
–Std
2.901
On-Die Termination (ODT)
–1
–1
Unit
None
2.448
2.466
ns
Table 81 • LVCMOS 1.2 V Receiver Characteristics for MSIO I/O Bank (Input Buffers)
TPY
–Std
TPYS
–Std
On-Die Termination ODT)
–1
–1
Unit
ns
None
50
4.714
6.668
5.832
5.162
5.545
7.845
6.862
6.073
4.675
6.579
5.76
5.111
5.5
7.74
6.777
6.014
ns
75
ns
150
ns
DS0128 Datasheet Revision 11.0
37
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 82 • LVCMOS 1.2 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers)
TPY
–Std
TPYS
–Std
On-Die Termination (ODT) –1
–1
Unit
ns
None
50
4.154
4.887
8.139
6.603
5.549
4.114
6.806
5.533
4.657
4.84
6.918
5.613
4.716
8.008
6.509
5.479
ns
75
ns
150
ns
Table 83 • LVCMOS 1.2 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
–1
–1
–1
–Std
–1
–Std
Unit
2 mA
4 mA
6 mA
Slow
6.713 7.897 5.362 6.308 6.723 7.909 7.233 8.51
6.375
7.499 ns
7.069 ns
6.865 ns
Medium
5.912 6.955 4.616 5.43
5.915 6.959 6.887 8.102 6.009
6.469 4.231 4.978 5.5 6.471 6.672 7.849 5.835
Medium
fast
5.5
Fast
5.462 6.426 4.194 4.935 5.463 6.427 6.646 7.819 5.828
6.109 7.186 4.708 5.539 6.098 7.174 8.005 9.418 7.033
6.857 ns
8.274 ns
7.849 ns
7.646 ns
Slow
Medium
5.355 6.299 4.034 4.746 5.338 6.28
7.637 8.985 6.672
8.752 6.499
Medium
fast
4.953 5.826 3.685 4.336 4.932 5.802 7.44
Fast
4.911 5.777 3.658 4.303 4.89
5.754 7.427 8.737 6.488
7.632 ns
8.605 ns
8.168 ns
Slow
5.89 6.929 4.506 5.301 5.874 6.911 8.337 9.808 7.315
Medium
5.176 6.089 3.862 4.543 5.155 6.065 7.986 9.394 6.943
4.792 5.637 3.523 4.145 4.765 5.606 7.808 9.186 6.775
Medium
fast
7.97
ns
Fast
4.754 5.593 3.486 4.101 4.728 5.563 7.777 9.149 6.769
7.963 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
Table 84 • LVCMOS 1.2 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
6.746 7.937 7.458 8.774 8.172 9.614 9.867 11.608 8.393
7.068 8.315 6.678 7.857 7.474 8.793 10.986 12.924 9.043 10.638 ns
–1
–1
–1
–Std
–1
–Std
Unit
2 mA
4 mA
Slow
Slow
9.874 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
DS0128 Datasheet Revision 11.0
38
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 85 • LVCMOS 1.2 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers)
1
1
Output
Drive
Selection Control
TDP
–Std
TZL
–Std
TZH
–Std
THZ
TLZ
Slew
–1
3.883 4.568 4.868 5.726 5.329 6.269 7.994 9.404
3.774 4.44 4.188 4.926 4.613 5.426 8.972 10.555 8.315
–1
–1
–1
–Std
–1
–Std
Unit
2 mA
4 mA
Slow
Slow
7.527
8.855 ns
9.782 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management.
2.3.5.11 3.3 V PCI/PCIX
Peripheral Component Interface (PCI) for 3.3 V standards specify support for 33 MHz and 66 MHz PCI
bus applications.
Minimum and Maximum DC/AC Input and Output Levels Specification (Applicable to MSIO Bank
Only)
Table 86 • PCI/PCI-X DC Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
3.15
3.3
3.45
V
Table 87 • PCI/PCI-X DC Input Voltage Specification
Parameter
Symbol
VI
Min
Max
Unit
DC input voltage
Input current high1
Input current low1
0
3.45
V
IIH(DC)
IIL(DC)
1. See Table 24, page 22.
Table 88 • PCI/PCI-X DC Output Voltage Specification
Parameter
Symbol Min
Typ
Max
Unit
V
DC output logic high
DC output logic low
VOH
VOL
Per PCI specification
Per PCI specification
V
Table 89 • PCI/PCI-X Minimum and Maximum AC Switching Speed
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate (MSIO I/O bank)
DMAX
630
Mbps AC Loading: per JEDEC specifications
Table 90 • PCI/PCI-X AC Test Parameter Specifications
Parameter
Symbol
Typ
Unit
V
Measuring/trip point for data path (falling edge)
Measuring/trip point for data path (rising edge)
Resistance for data test path
VTRIP
VTRIP
0.615 × VDDI
0.285 × VDDI
V
RTT_TEST 25
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
CENT
CLOAD
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
pF
pF
Capacitive loading for data path (TDP
)
10
DS0128 Datasheet Revision 11.0
39
IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 3.0 V
Table 91 • PCI/PCIX AC Switching Characteristics for Receiver for MSIO I/O Bank
(Input Buffers)
TPY
–Std
2.229 2.623 2.238 2.633 ns
TPYS
On-Die Termination (ODT) –1
None
–1
–Std
Unit
Table 92 • PCI/PCIX AC switching Characteristics for Transmitter for MSIO I/O Bank (Output
and Tristate Buffers)
TDP
–Std –1
TZL
–Std –1
TZH
–Std –1
THZ
–Std –1
TLZ
–Std Unit
–1
2.146 2.525 2.043 2.404 2.084 2.452 6.095 7.171 5.558 6.539 ns
2.3.6 Memory Interface and Voltage Referenced I/O Standards
This section describes High-Speed Transceiver Logic (HSTL) memory interface and voltage reference
I/O standards.
2.3.6.1 High-Speed Transceiver Logic (HSTL)
The HSTL standard is a general purpose high-speed bus standard sponsored by IBM (EIA/JESD8-6).
IGLOO2 FPGA and SmartFusion2 SoC FPGA devices support two classes of the 1.5 V HSTL. These
differential versions of the standard require a differential amplifier input buffer and a push-pull output
buffer.
Minimum and Maximum DC/AC Input and Output Levels Specification (Applicable to DDRIO Bank
Only)
Table 93 • HSTL Recommended DC Operating Conditions
Parameter
Symbol
VDDI
Min
Typ
Max
Unit
V
Supply voltage
1.425
0.698
0.698
1.5
1.575
0.803
0.803
Termination voltage
Input reference voltage
VTT
0.750
0.750
V
VREF
V
Table 94 • HSTL DC Input Voltage Specification
Parameter
Symbol
VIH (DC)
VIL (DC)
IIH (DC)
IIL (DC)
Min
Max
Unit
V
DC input logic high
DC input logic low
Input current high1
Input current low1
VREF + 0.1
–0.3
1.575
VREF – 0.1
V
1. See Table 24, page 22.
DS0128 Datasheet Revision 11.0
40
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 95 • HSTL DC Output Voltage Specification Applicable to DDRIO I/O Bank Only
Parameter
Symbol
HSTL Class I
VOH
Min
Max
Unit
DC output logic high
DC output logic low
VDDI – 0.4
V
VOL
0.4
V
Output minimum source DC
current (MSIO and DDRIO I/O
banks)
IOH at VOH –8.0
mA
Output minimum sink current IOL at VOL
(MSIO and DDRIO I/O banks)
8.0
mA
HSTL Class II
VOH
VOL
IOH at VOH –16.0
DC output logic high
DC output logic low
VDDI – 0.4
V
0.4
V
Output minimum source DC
current
mA
Output minimum sink current IOL at VOL
16.0
mA
Table 96 • HSTL DC Differential Voltage Specification
Parameter
Symbol
Min
Unit
DC input differential voltage
VID (DC)
0.2
V
Table 97 • HSTL AC Differential Voltage Specifications
Parameter
Symbol
VDIFF
Vx
Min
0.4
Max Unit
AC input differential voltage
AC differential cross point voltage
V
0.68
0.9
V
Table 98 • HSTL Minimum and Maximum AC Switching Speed
Parameter
Symbol
Max Unit Conditions
Maximum data rate
DMAX
400
Mbps AC loading: per JEDEC
specifications
Table 99 • HSTL Impedance Specification
Parameter
Symbol
RREF
Typ
Unit Conditions
Supported output driver calibrated
impedance (for DDRIO I/O bank)
25.5, 47.8
Reference resistance =
191
Effective impedance value (ODT for
DDRIO I/O bank only)
RTT
47.8
Reference resistance =
191
DS0128 Datasheet Revision 11.0
41
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 100 • HSTL AC Test Parameter Specification
Parameter
Symbol
VTRIP
Typ
0.75
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
Reference resistance for data test path for HSTL15
RTT_TEST
50
Class I (TDP
Reference resistance for data test path for HSTL15
Class II (TDP
)
RTT_TEST
CLOAD
25
5
)
Capacitive loading for data path (TDP
)
pF
AC Switching Characteristics
Worst-case commercial conditions: TJ = 85 °C, VDD = 1.14 V, worst-case VDDI
.
Table 101 • HSTL Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
Pseudo differential
True differential
None
47.8
1.605
1.614
1.622
1.628
1.888
1.898
1.909
1.916
ns
None
47.8
ns
ns
Table 102 • HSTL Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
TZL
–Std
TZH
–Std
THZ
–Std
TLZ
–Std
–1
–1
–1
–1
–1
Unit
HSTL Class I
2.514 2.958
2.647 3.113
HSTL Class II
Single-ended 2.6
3.059 2.514
3.083 2.648
2.958
3.115
2.431
2.925
2.86
2.431 2.86
2.923 3.44
ns
ns
Differential
2.621
3.442
Single-ended 2.511
2.954 2.488
2.974 2.552
2.927
3.003
2.49
2.93
2.409
2.897
2.833
3.409
2.411 2.836
2.896 3.408
ns
ns
Differential
2.528
2.551 3.001
2.3.6.2 Stub-Series Terminated Logic
Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is
supported in IGLOO2 and SmartFusion2 SoC FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B
and SSTL18 is defined by JEDEC standard JESD8-15. IGLOO2 SSTL I/O configurations are designed to
meet double data rate standards DDR/2/3 for general purpose memory buses. Double data rate
standards are designed to meet their JEDEC specifications as defined by JEDEC standard JESD79F for
DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3, and JEDEC
standard JESD209A for LPDDR.
DS0128 Datasheet Revision 11.0
42
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.6.3 Stub-Series Terminated Logic 2.5 V (SSTL2)
SSTL2 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs and also comply
with reduced and full drive of double data rate (DDR) standards. IGLOO2 and SmartFusion2 SoC FPGA
I/Os supports both standards for single-ended signaling and differential signaling for SSTL2. This
standard requires a differential amplifier input buffer and a push-pull output buffer.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 103 • DDR1/SSTL2 DC Recommended Operating Conditions
Parameter
Symbol
VDDI
Min
Typ
Max
Unit
V
Supply voltage
2.375
1.164
1.164
2.5
2.625
Termination voltage
Input reference voltage
VTT
1.250 1.339
1.250 1.339
V
VREF
V
Table 104 • DDR1/SSTL2 DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
V
DC input logic high
DC input logic low
Input current high1
Input current low1
VIH (DC) VREF + 0.15
2.625
VIL (DC)
IIH (DC)
IIL (DC)
–0.3
VREF – 0.15
V
1. See Table 24, page 22.
Table 105 • DDR1/SSTL2 DC Output Voltage Specification
Parameter
Symbol
Min
Max
Unit
SSTL2 Class I (DDR Reduced Drive)
DC output logic high
VOH
VOL
VTT + 0.608
V
DC output logic low
VTT – 0.608
V
Output minimum source DC current
Output minimum sink current
I
OH at VOH
8.1
mA
mA
IOL at VOL
–8.1
SSTL2 Class II (DDR Full Drive) – Applicable to MSIO and DDRIO I/O Bank Only
DC output logic high
VOH
VOL
VTT + 0.81
V
DC output logic low
VTT – 0.81
V
Output minimum source DC current
Output minimum sink current
I
OH at VOH
16.2
mA
mA
IOL at VOL
–16.2
Table 106 • DDR1/SSTL2 DC Differential Voltage Specification
Parameter
Symbol
Min
0.3
Unit
DC input differential voltage
VID (DC)
V
DS0128 Datasheet Revision 11.0
43
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 107 • SSTL2 AC Differential Voltage Specifications
Parameter
Symbol
VDIFF (AC)
Vx (AC)
Min
Max
Unit
V
AC input differential voltage
0.7
AC differential cross point
voltage
0.5 × VDDI – 0.2 0.5 × VDDI + 0.2
V
Table 108 • SSTL2 Minimum and Maximum AC Switching Speeds
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate (for
DDRIO I/O bank)
DMAX
400
Mbps
AC loading: per JEDEC
specifications
Maximum data rate (for
MSIO I/O bank)
DMAX
DMAX
575
700
510
Mbps
Mbps
Mbps
AC loading: 17pF load
Maximum data rate (for
MSIOD I/O bank)
AC loading: 3 pF / 50
load
AC loading: 17pF load
Table 109 • SSTL2 AC Impedance Specifications
Parameter
Typ
Unit
Conditions
Reference resistor = 150
Supported output driver calibrated 20, 42
impedance (for DDRIO I/O bank)
Table 110 • DDR1/SSTL2 AC Test Parameter Specifications
Parameter
Symbol
Typ
1.25
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
VTRIP
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Reference resistance for data test path for SSTL2 Class I
(TDP
Reference resistance for data test path for SSTL2 Class II RTT_TEST
(TDP
)
CENT
pF
RTT_TEST
50
)
25
5
)
Capacitive loading for data path (TDP
)
CLOAD
pF
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V
Table 111 • SSTL2 Receiver Characteristics for DDRIO I/O Bank (Input Buffers)
TPY
On-Die
Termination (ODT) –1
Pseudo differential None 1.549
True differential None 1.589
–Std
1.821
1.87
Unit
ns
ns
DS0128 Datasheet Revision 11.0
44
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 112 • SSTL2 Receiver Characteristics for MSIO I/O Bank (Input Buffers)
TPY
–Std
On-Die
Termination (ODT) –1
Unit
ns
Pseudo differential None
True differential None
2.798
2.733
3.293
3.215
ns
Table 113 • DDR1/SSTL2 Receiver Characteristics for MSIOD I/O Bank (Input Buffers)
TPY
On-Die
Termination (ODT) –1
Pseudo differential None 2.476
True differential None 2.475
–Std
Unit
ns
2.913
2.911
ns
Table 114 • SSTL2 Class I Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
2.66
TZL
–Std –1
2.341 1.985
TZH
–Std
2.335 2.135 2.512 2.13
2.589 2.393 2.815 2.392 2.814
THZ
TLZ
–Std
2.505
–1
–1
–1
–Std
–1
Unit
ns
Single-ended
Differential
2.26
2.26
1.99
2.658 2.202 2.591 2.201
ns
Table 115 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
2.417 2.037 2.396 2.03
2.58 2.434 2.864 2.425
TZL
TZH
–Std
THZ
–Std
TLZ
–Std
–1
–1
–Std –1
–1
–1
Unit
ns
Single-ended
Differential
2.055
2.192
2.388 2.068 2.433 2.061 2.425
2.852 2.164 2.545 2.156 2.536
ns
Table 116 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate
Buffers)
TDP
–Std
1.779 1.462 1.72
1.971 1.774 2.087 1.766
TZL
–Std –1
1.462
TZH
–Std
1.72
2.077 1.854 2.181 1.845 2.171
THZ
–Std
1.676 1.972 1.676 1.971
TLZ
–1
–1
–1
–1
–Std
Unit
ns
Single-ended
Differential
1.512
1.676
ns
Table 117 • DDR1/SSTL2 Class II Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate
Buffers)
TDP
–Std
TZL
–Std –1
TZH
–Std
2.237 2.061 2.424 2.056 2.418
2.403 2.363 2.78 2.365 2.781
THZ
TLZ
–1
–1
–1
–Std
–1
–Std
Unit
ns
Single-ended
Differential
2.122
2.127
2.497 1.906 2.243 1.902
2.501 2.042 2.402 2.043
ns
DS0128 Datasheet Revision 11.0
45
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 118 • DDR1/SSTL2 Class II Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
TZL
–Std –1
TZH
–Std
2.326 1.989 2.34
2.702 2.131 2.506 2.124 2.499
THZ
TLZ
–Std
1.979 2.328
–1
–1
–1
–Std
–1
Unit
ns
Single-ended
Differential
2.29
2.418
2.693 1.988 2.338 1.978
2.846 2.304 2.711 2.297
ns
2.3.6.4 Stub-Series Terminated Logic 1.8 V (SSTL18)
SSTL18 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs, and also comply
with the reduced and full drive double date rate (DDR2) standard. IGLOO2 and SmartFusion2 SoC
FPGA I/Os support both standards for single-ended signaling and differential signaling for SSTL18. This
standard requires a differential amplifier input buffer and a push-pull output buffer.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 119 • SSTL18 DC Recommended DC Operating Conditions
Parameter
Symbol
VDDI
Min
Typ
Max
Unit
V
Supply voltage
Termination voltage
1.71
1.8
1.89
VTT
0.838
0.838
0.900 0.964
0.900 0.964
V
Input reference voltage VREF
V
Table 120 • SSTL18 DC Input Voltage Specification
Parameter
Symbol
Min
VREF + 0.125 1.89
–0.3 VREF – 0.125
Max
Unit
DC input logic high
DC input logic low
Input current high1
Input current low1
VIH (DC)
V
V
V
IL (DC)
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
Table 121 • SSTL18 DC Output Voltage Specification
Parameter
Symbol
Min
Max
Unit
SSTL18 Class I (DDR2 Reduced Drive)
DC output logic high
DC output logic low
VOH
VOL
VTT + 0.603
V
VTT– 0.603
V
Output minimum source DC current (DDRIO I/O bank IOH at VOH 6.5
only)
mA
Output minimum sink current (DDRIO I/O bank only)
IOL at VOL
–6.5
mA
SSTL18 Class II (DDR2 Full Drive)1
DC output logic high
DC output logic low
VOH
VOL
VTT + 0.603
V
VTT– 0.603
V
Output minimum source DC current (DDRIO I/O bank IOH at VOH 13.4
only)
mA
Output minimum sink current (DDRIO I/O bank only)
IOL at VOL
–13.4
mA
1. To meet JEDEC Electrical Compliance, use DDR2 Full Drive Transmitter.
DS0128 Datasheet Revision 11.0
46
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 122 • SSTL18 DC Differential Voltage Specification
Parameter
Symbol
Min
Unit
DC input differential voltage
VID (DC)
0.3
V
Table 123 • SSTL18 AC Differential Voltage Specifications (Applicable to DDRIO Bank Only)
Parameter
Symbol
Min
Max
Unit
AC input differential
voltage
VDIFF (AC) 0.5
V
AC differential cross
point voltage
Vx (AC)
0.5 × VDDI – 0.175 0.5 × VDDI + 0.175
V
Table 124 • SSTL18 Minimum and Maximum AC Switching Speed (Applicable to DDRIO Bank
Only)
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate
DMAX
667
Mbps
AC loading: per JEDEC specification
(for DDRIO I/O bank)
Table 125 • SSTL18 AC Impedance Specifications (Applicable to DDRIO Bank Only)
Parameter
Symbol
Typ
Unit Conditions
Supported output driver calibrated
impedance (for DDRIO I/O bank)
RREF
20, 42
Reference resistor = 150
Effective impedance value (ODT)
RTT
50, 75, 150
Reference resistor = 150
Table 126 • SSTL18 AC Test Parameter Specifications (Applicable to DDRIO Bank Only)
Parameter
Symbol
VTRIP
Typ
0.9
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Reference resistance for data test path for SSTL18 Class I (TDP
Reference resistance for data test path for SSTL18 Class II (TDP
)
CENT
pF
)
RTT_TEST
RTT_TEST
CLOAD
50
25
5
)
Capacitive loading for data path (TDP
)
pF
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.71 V
Table 127 • DDR2/SSTL18 Receiver Characteristics for DDRIO I/O Bank with Fixed Code
TPY
On-Die Termination (ODT)
Pseudo differential None
True differential None
–1
–Std
Unit
1.567 1.844 ns
1.588 1.869 ns
DS0128 Datasheet Revision 11.0
47
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 128 • DDR2/SSTL18 Transmitter Characteristics (Output and Tristate Buffers)
TDP
–Std
TZL
–Std –1
SSTL18 Class I (for DDRIO I/O Bank)
TZH
THZ
–Std
TLZ
–Std
–1
–1
–Std
–1
–1
Unit
Single-ended
Differential
2.383
2.413
2.804 2.23
2.84 2.797
2.623 2.229
3.29 2.797
2.622
3.29
2.202 2.591 2.201
2.282 2.685 2.282
2.59
ns
ns
2.685
SSTL18 Class II (for DDRIO I/O Bank)
Single-ended
Differential
2.281
2.315
2.683 2.196
2.724 2.698
2.584 2.195
3.173 2.698
2.583
3.173
2.171 2.555 2.17
2.242 2.639 2.242
2.554
2.639
ns
ns
2.3.6.5 Stub-Series Terminated Logic 1.5 V (SSTL15)
SSTL15 Class I and Class II are supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs, and also
comply with the reduced and full drive double data rate (DDR3) standard. IGLOO2 FPGA and
SmartFusion2 SoC FPGA I/Os supports both standards for single-ended signaling and differential
signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output
buffer.
Minimum and Maximum DC/AC Input and Output Levels Specification
The following table lists the SSTL15 DC voltage specifications for DDRIO bank.
Table 129 • SSTL15 DC Recommended DC Operating Conditions (for DDRIO I/O Bank Only)
Parameter
Symbol
VDDI
Min
Typ
Max
Unit
V
Supply voltage
1.425
0.698
0.698
1.5
1.575
0.803
0.803
Termination voltage
Input reference voltage
VTT
0.750
0.750
V
VREF
V
Table 130 • SSTL15 DC Input Voltage Specification (for DDRIO I/O Bank Only)
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Unit
V
DC input logic high
DC input logic low
Input current high1
Input current low1
VREF + 0.1
–0.3
1.575
VREF – 0.1
V
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
DS0128 Datasheet Revision 11.0
48
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 131 • SSTL15 DC Output Voltage Specification (for DDRIO I/O Bank Only)
Parameter
Symbol
Min
Max
Unit
DDR3/SSTL15 Class I (DDR3 Reduced Drive)
DC output logic high
DC output logic low
VOH
VOL
0.8 × VDDI
V
0.2 × VDDI
V
Output minimum source DC
current
IOH at VOH 6.5
mA
Output minimum sink current IOL at VOL
–6.5
mA
DDR3/SSTL15 Class II (DDR3 Full Drive)
DC output logic high
DC output logic low
VOH
VOL
0.8 × VDDI
V
0.2 × VDDI
V
Output minimum source DC
current
IOH at VOH 7.6
mA
Output minimum sink current IOL at VOL
–7.6
mA
Table 132 • SSTL15 DC Differential Voltage Specification (for DDRIO I/O Bank Only)
Parameter
Symbol
Min
Unit
DC input differential voltage
VID
0.2
V
Note: To meet JEDEC electrical compliance, use DDR3 full drive transmitter.
Table 133 • SSTL15 AC SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only)
Parameter
Symbol
VDIFF (AC)
Vx (AC)
Min
Max
Unit
V
AC input differential voltage
AC differential cross point voltage
0.3
0.5 × VDDI – 0.150
0.5 × VDDI + 0.150
V
Table 134 • SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only)
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate
DMAX
667
Mbps
AC loading: per JEDEC specifications
Table 135 • SSTL15 AC Calibrated Impedance Option (for DDRIO I/O Bank Only)
Parameter
Symbol
RREF
RTT
Typ
Unit Conditions
Reference resistor = 240
Reference resistor = 240
Supported output driver calibrated impedance
Effective impedance value (ODT)
34, 40
20, 30, 40, 60, 120
DS0128 Datasheet Revision 11.0
49
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 136 • SSTL15 AC Test Parameter Specifications (for DDRIO I/O Bank Only)
Parameter
Symbol
VTRIP
Typ
0.75
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Reference resistance for data test path for SSTL15 Class I (TDP
Reference resistance for data test path for SSTL15 Class II (TDP
)
CENT
pF
)
RTT_TEST
RTT_TEST
CLOAD
50
25
5
)
Capacitive loading for data path (TDP
)
pF
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.425 V
Table 137 • DDR3/SSTL15 Receiver Characteristics for DDRIO I/O Bank – with Calibration
Only
TPY
On-Die Termination (ODT) –1
Pseudo differential None 1.605
–Std
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.888
1.901
1.897
1.895
1.893
1.89
20
1.616
1.613
1.611
1.609
1.607
1.623
1.637
1.63
30
40
60
120
None
20
True differential
1.91
1.926
1.918
1.914
1.91
30
40
1.626
1.622
1.619
60
120
1.905
Table 138 • DDR3/SSTL15 Transmitter Characteristics (Output and Tristate Buffers)
TDP TZL TZH THZ
TLZ
–1
–Std
–1
–Std
–1
–Std
–1
–Std
–1
–Std Unit
DDR3 Reduced Drive/SSTL15 Class I (for DDRIO I/O Bank)
Single-ended
Differential
2.533 2.98
2.522 2.967 2.523
2.968
3.615
2.427 2.855 2.428
2.416 2.843 2.416
2.856 ns
2.843 ns
2.555 3.005 3.073 3.615 3.073
DDR3 Full Drive/SSTL15 Class II (for DDRIO I/O Bank)
Single-ended
Differential
2.53
2.977 2.514 2.958 2.516
2.96
2.422 2.849 2.425
2.882 3.391 2.881
2.852 ns
2.552 3.002 2.591 3.048 2.59
3.047
3.39
ns
DS0128 Datasheet Revision 11.0
50
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.6.6 Low Power Double Data Rate (LPDDR)
LPDDR reduced and full drive low power double data rate standards are supported in IGLOO2 FPGA
and SmartFusion2 SoC FPGA I/Os. This standard requires a differential amplifier input buffer and a
push-pull output buffer.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 139 • LPDDR DC Recommended DC Operating Conditions
Parameter
Symbol
VDDI
Min
Typ
Max
Supply voltage
1.71
1.8
1.89
Termination voltage
Input reference voltage
VTT
0.838
0.838
0.900
0.900
0.964
0.964
VREF
Table 140 • LPDDR DC Input Voltage Specification
Parameter
Symbol
Min
Max
1.89
0.3 × VDDI
DC input logic high
DC input logic low
Input current high1
Input current low1
VIH (DC)
0.7 × VDDI
–0.3
VIL (DC)
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
Table 141 • LPDDR DC Output Voltage Specification Reduced Drive
Parameter
Symbol
VOH
Min
Max
DC output logic high
DC output logic low
0.9 × VDDI
VOL
0.1 × VDDI
Output minimum source DC
current
IOH at VOH 0.1
Output minimum sink current IOL at VOL –0.1
Table 142 • LPDDR DC Output Voltage Specification Full Drive1
Parameter
Symbol
VOH
Min
Max
DC output logic high
0.9 × VDDI
DC output logic low
VOL
0.1 × VDDI
Output minimum source DC current
Output minimum sink current
IOH at VOH
0.1
I
OL at VOL
–0.1
1. To meet JEDEC Electrical Compliance, use LPDDR Full Drive Transmitter.
Table 143 • LPDDR DC Differential Voltage Specification
Parameter
Symbol
Min
DC input differential voltage
VID (DC)
0.4 × VDDI
DS0128 Datasheet Revision 11.0
51
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 144 • LPDDR AC Differential Voltage Specifications (for DDRIO I/O Bank Only)
Parameter
Symbol
VDIFF
Vx
Min
Max
Unit
V
AC input differential voltage
0.6 × VDDI
AC differential cross point
voltage
0.4 × VDDI 0.6 × VDDI
V
Table 145 • LPDDR AC Specifications (for DDRIO I/O Bank Only)
Parameter
Symbol
Max
Unit
Conditions
Maximum data rate
DMAX
400
Mbps AC loading: per JEDEC specifications
Table 146 • LPDDR AC Calibrated Impedance Option (for DDRIO I/O Bank Only)
Parameter
Symbol
RREF
RTT
Typ
Unit
Conditions
Supported output driver calibrated impedance
Effective impedance value (ODT)
20, 42
Reference resistor = 150
Reference resistor = 150
50, 70, 150
Table 147 • LPDDR AC Test Parameter Specifications (for DDRIO I/O Bank Only)
Parameter
Symbol
VTRIP
Typ
0.9
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
RENT
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
Reference resistance for data test path for LPDDR (TDP
)
RTT_TEST
CLOAD
50
5
Capacitive loading for data path (TDP
)
AC Switching Characteristics
Worst-case commercial conditions: TJ = 85 °C, VDD = 1.14 V, worst-case VDDI
.
Table 148 • LPDDR Receiver Characteristics for DDRIO I/O Bank with Fixed Codes
TPY
On-Die Termination (ODT) –1
Pseudo differential None
True differential None
–Std
Unit
1.568 1.845 ns
1.588 1.869 ns
Table 149 • LPDDR Reduced Drive for DDRIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
TENZL
–Std
2.623
TENZH
–Std –1
TENHZ
–Std
TENLZ
–Std
–1
–1
–1
–1
Unit
ns
Single-ended 2.383
2.804
2.819
2.23
2.229 2.622 2.202
2.764 3.252 2.255
2.591
2.653
2.201
2.255
2.59
Differential
2.396
2.764 3.252
2.653
ns
DS0128 Datasheet Revision 11.0
52
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 150 • LPDDR Full Drive for DDRIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
TENZL
–Std
TENZH
–Std –1
TENHZ
–Std
TENLZ
–Std
–1
–1
–1
–1
Unit
ns
Single-ended 2.281
2.683
2.703
2.196 2.584
2.288 2.692
2.195 2.583 2.171
2.288 2.692 2.593
2.555
3.051
2.17
2.593
2.554
3.051
Differential
2.298
ns
Minimum and Maximum DC/AC Input and Output Levels Specification using LPDDR-LVCMOS 1.8
V Mode
Table 151 • LPDDR-LVCMOS 1.8 V Mode Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
1.710
1.8
1.89
V
Table 152 • LPDDR-LVCMOS 1.8 V Mode DC Input Voltage Specification
Parameter Symbol Min Max
Unit
DC input logic high (for MSIOD and DDRIO VIH (DC)
I/O banks)
0.65 × VDDI 1.89
V
DC input logic high (for MSIO I/O bank)
DC input logic low
VIH (DC)
IL (DC)
0.65 × VDDI 3.45
V
V
V
–0.3
0.35 × VDDI
Input current high1
IIH (DC)
IIL (DC)
Input current low1
1. See Table 24, page 22.
Table 153 • LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification
Parameter
Symbol
VOH
Min
Max
Unit
DC output logic high
DC output logic low
VDDI – 0.45
V
V
VOL
0.45
Table 154 • LPDDR-LVCMOS 1.8 V Minimum and Maximum AC Switching Speeds
Parameter
Symbol Max Unit Conditions
Maximum data rate (for DDRIO I/O bank) DMAX
400 Mbps AC loading: 17pf load, 8 ma
drive and above/all slew
Table 155 • LPDDR-LVCMOS 1.8 V Calibrated Impedance Option
Parameter
Symbol
Typ
Unit
Supported output driver calibrated
impedance (for DDRIO I/O bank)
RODT_CAL
75, 60, 50, 33, 25, 20
DS0128 Datasheet Revision 11.0
53
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 156 • LPDDR-LVCMOS 1.8 V AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
0.9
2K
5
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
)
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
Capacitive loading for data path (TDP)
)
CENT
pF
pF
CLOAD
5
Table 157 • LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification for DDRIO Bank
VOH (V)
Min
VOL (V)
Max
Output Drive Selection
IOH (at VOH) mA
IOL (at VOL) mA
2 mA
VDDI – 0.45
VDDI – 0.45
0.45
0.45
0.45
0.45
0.45
0.45
0.45
2
2
4 mA
4
4
6 mA
V
DDI – 0.45
DDI – 0.45
6
6
8 mA
V
8
8
10 mA
12 mA
16 mA1
VDDI – 0.45
DDI – 0.45
VDDI – 0.45
10
12
16
10
12
16
V
1. 16 mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance.
Table 158 • LPDDR-LVCMOS 1.8V AC Switching Characteristics for Receiver (for DDRIO
I/O Bank with Fixed Code - Input Buffers)
ODT (On Die
Termination)
–1
–Std
–1
–Std
Unit
None
1.968
2.315
2.099
2.47
ns
Table 159 • LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output
and Tristate Buffers)
1
1
TDP
–Std –1
TZL
–Std –1
TZH
–Std –1
THZ
–Std –1
TLZ
Output Drive Slew
Selection
Control
–1
–Std Unit
2 mA
slow
4.234 4.981 3.646
3.824 4.498 3.282
4.29 4.245 4.995 4.908 5.774 4.434 5.216 ns
3.861 3.834 4.511 4.625 5.441 4.116 4.843 ns
3.66 3.637 4.279 4.481 5.272 3.984 4.687 ns
3.644 3.615 4.253 4.472 5.262 3.973 4.674 ns
medium
medium_fast 3.627 4.267 3.111
fast
3.605 4.241 3.097
3.923 4.615 3.314
3.518 4.138 2.961
4 mA
6 mA
8 mA
slow
3.9
3.918 4.61 5.403 6.356 4.894 5.757 ns
medium
3.484 3.515 4.135 5.121 6.025 4.561 5.366 ns
3.275 3.317 3.903 4.966 5.843 4.426 5.206 ns
3.259 3.296 3.878 4.957 5.831 4.417 5.196 ns
medium_fast 3.321 3.907 2.783
fast
3.301 3.883 2.77
3.71 4.364 3.104
3.333 3.921 2.779
slow
3.652 3.702 4.355 5.62
3.27 3.325 3.913 5.346 6.289 4.777 5.62 ns
3.083 3.146 3.702 5.21 6.13 4.657 5.479 ns
6.612 5.08
5.977 ns
medium
medium_fast 3.155 3.712 2.62
fast
3.134 3.688 2.608
3.619 4.258 3.007
3.068 3.125 3.677 5.202 6.12 4.648 5.468 ns
3.538 3.607 4.244 5.815 6.841 5.249 6.175 ns
slow
DS0128 Datasheet Revision 11.0
54
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 159 • LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output
and Tristate Buffers) (continued)
medium
3.246 3.819 2.686
3.16 3.236 3.807 5.542 6.52 4.936 5.807 ns
2.971 3.054 3.593 5.405 6.359 4.811 5.66 ns
2.957 3.034 3.57 5.401 6.353 4.803 5.651 ns
3.386 3.481 4.096 6.046 7.113 5.444 6.404 ns
3.023 3.126 3.678 5.782 6.803 5.129 6.034 ns
2.841 2.951 3.472 5.666 6.665 5.013 5.897 ns
medium_fast 3.066 3.607 2.525
fast
3.046 3.584 2.513
3.498 4.115 2.878
3.138 3.692 2.569
10 mA
12 mA
16 mA
slow
medium
medium_fast 2.966 3.489 2.414
fast
2.945 3.464 2.401
3.417 4.02 2.807
3.076 3.618 2.519
2.826 2.93
3.448 5.659 6.658 5.003 5.886 ns
slow
3.303 3.401 4.002 6.083 7.156 5.464 6.428 ns
2.964 3.063 3.604 5.828 6.856 5.176 6.089 ns
2.795 2.898 3.41 5.725 6.736 5.072 5.966 ns
2.78 2.879 3.388 5.715 6.724 5.064 5.957 ns
3.237 3.348 3.939 6.226 7.324 5.576 6.56 ns
2.906 3.017 3.55 5.981 7.036 5.282 6.214 ns
medium
medium_fast 2.913 3.427 2.376
fast
2.894 3.405 2.362
3.366 3.96 2.751
slow
medium
3.03
3.565 2.47
medium_fast 2.87
fast
3.377 2.328
2.739 2.854 3.358 5.895 6.935 5.18
6.094 ns
2.853 3.357 2.314
2.723 2.837 3.338 5.889 6.929 5.177 6.09 ns
1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO)
management).
2.3.7 Differential I/O Standards
Configuration of the I/O modules as a differential pair is handled by Microsemi SoC Products Group
Libero software when the user instantiates a differential I/O macro in the design. Differential I/Os can also
be used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable
register (EnReg), and Double Data Rate registers (DDR).
2.3.7.1 LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard.
Minimum and Maximum Input and Output Levels
Table 160 • LVDS Recommended DC Operating Conditions
Parameter
Symbol
VDDI
Min
2.375 2.5
3.15 3.3
Typ
Max
2.625
3.45
Unit Conditions
Supply voltage
Supply voltage
V
V
2.5 V range
3.3 V range
VDDI
Table 161 • LVDS DC Input Voltage Specification
Parameter
Symbol
VI
Min
0
Max
2.925
3.45
Unit Conditions
DC Input voltage
DC input voltage
Input current high1
Input current low1
V
V
2.5 V range
3.3 V range
VI
0
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
DS0128 Datasheet Revision 11.0
55
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 162 • LVDS DC Output Voltage Specification
Parameter
Symbol
VOH
Min
1.25
0.9
Typ
Max
Unit
V
DC output logic high
DC output logic low
1.425 1.6
VOL
1.075 1.25
V
Table 163 • LVDS DC Differential Voltage Specification
Parameter
Symbol Min
Typ
Max
450
Unit
Differential output voltage swing
Output common mode voltage
Input common mode voltage
Input differential voltage
VOD
VOCM
VICM
VID
250
350
mV
V
1.125 1.25
1.375
2.35
600
0.05
100
1.25
350
V
mV
Table 164 • LVDS Minimum and Maximum AC Switching Speed
Parameter
Symbol
Max Unit
Conditions
Maximum data rate (for MSIO I/O bank)
DMAX
535
620
700
Mbps AC loading: 12 pF / 100 differential load
Mbps AC loading: 10 pF / 100 differential load
Mbps AC loading: 2 pF / 100 differential load
Maximum data rate (for MSIOD I/O bank) no DMAX
pre-emphasis
Table 165 • LVDS AC Impedance Specifications
Parameter
Symbol
Typ
Max
Unit
Termination resistance
RT
100
Table 166 • LVDS AC Test Parameter Specifications
Parameter
Symbol Typ
Unit
V
Measuring/trip point for data path
VTRIP
RENT
CENT
Cross point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
pF
LVDS25 AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V
Table 167 • LVDS25 Receiver Characteristics for MSIO I/O Bank (Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.774
2.775
3.263
3.264
ns
DS0128 Datasheet Revision 11.0
56
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 168 • LVDS25 Receiver Characteristics for MSIOD I/O Bank (Input Buffers)
TPY
–Std
On-Die Termination (ODT)
–1
Unit
ns
None
100
2.554
2.549
3.004
2.999
ns
Table 169 • LVDS25 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
TDP
–Std
2.136 2.513 2.416 2.842 2.402 2.825 2.423 2.85
TZL
TZH
THZ
–Std –1
2.409 2.833 ns
TLZ
–1
–1
–Std –1
–Std –1
–Std Unit
Table 170 • LVDS25 Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers)
TDP
–Std –1
1.893 1.749 2.058 1.735 2.041 1.897 2.231 1.866 2.195 ns
TZL
TZH
THZ
TLZ
–1
–Std –1
–Std –1
–Std –1
–Std Unit
No pre-emphasis
Min pre-emphasis
Med pre-emphasis
1.61
1.527 1.796 1.757 2.067 1.744 2.052 1.905 2.241 1.876 2.207 ns
1.496 1.76 1.765 2.077 1.751 2.06 1.914 2.252 1.884 2.216 ns
LVDS33 AC Switching Characteristics
Table 171 • LVDS33 Receiver Characteristics for MSIO I/O Bank (Input Buffers)
TPY
–Std
On Die Termination (ODT) –1
Unit
ns
None
100
2.572
2.569
3.025
3.023
ns
Table 172 • LVDS33 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate
Buffers)
TDP
–Std –1
1.942 2.284 1.98
TZL
–Std –1
2.33 1.97
TZH
–Std –1
2.318 1.953 2.298 1.96
THZ
TLZ
–Std Unit
2.307 ns
–1
–Std –1
DS0128 Datasheet Revision 11.0
57
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.7.2 B-LVDS
Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint
bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers,
receivers, and transceivers.
Minimum and Maximum DC/AC Input and Output Levels Specification
Table 173 • B-LVDS Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
2.375 2.5
2.625
V
Table 174 • B-LVDS DC Input Voltage Specification
Parameter
Symbol
VI
Min
Max
Unit
DC input voltage
Input current high1
Input current low1
0
2.925
V
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
Table 175 • B-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only)
Parameter
Symbol
VOH
Min
1.25
0.9
Typ
Max
1.6
Unit
V
DC output logic high
DC output logic low
1.425
1.075
VOL
1.25
V
Table 176 • B-LVDS DC Differential Voltage Specification
Parameter
Symbol
Min
Max
Unit
mV
V
Differential output voltage swing (for MSIO I/O bank only) VOD
65
460
1.5
Output common mode voltage (for MSIO I/O bank only)
Input common mode voltage
VOCM
1.1
0.05
0.1
VICM
VID
2.4
V
Input differential voltage
VDDI
V
Table 177 • B-LVDS Minimum and Maximum AC Switching Speed
Parameter
Symbol
Max
Unit Conditions
Mbps AC loading: 2 pF / 100 differential load
Maximum data rate (for MSIO I/O bank) DMAX
500
Table 178 • B-LVDS AC Impedance Specifications
Parameter
Symbol
Typ
Unit
Termination resistance
RT
27
Table 179 • B-LVDS AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
Unit
V
Measuring/trip point for data path
Cross point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
DS0128 Datasheet Revision 11.0
58
IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.
Table 180 • B-LVDS AC Switching Characteristics for Receiver for MSIO I/O
Bank (Input Buffers)
TPY
On-Die Termination (ODT) –1
–Std
Unit
ns
None
100
2.738
2.735
3.221
3.218
ns
Table 181 • B-LVDS AC Switching Characteristics for Receiver for MSIOD I/O
Bank (Input Buffers)
TPY
On-Die Termination (ODT) –1
–Std
Unit
ns
None
100
2.495
2.495
2.934
2.935
ns
Table 182 • B-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and
Tristate Buffers)
TDP
–Std
2.258 2.656 2.343 2.756 2.329 2.74
TZL
TZH
THZ
–Std
2.494 2.123 2.497 ns
TLZ
–1
–1
–Std
–1
–Std
–1
–1
–Std
Unit
2.12
2.3.7.3 M-LVDS
M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus
applications. Multidrop and multipoint bus configurations may contain any combination of drivers,
receivers, and transceivers.
Minimum and Maximum Input and Output Levels
Table 183 • M-LVDS Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage1
VDDI
2.375
2.5
2.625
V
1. Only M-LVDS TYPE I is supported.
Table 184 • M-LVDS DC Input Voltage Specification
Parameter
Symbol
VI
Min
Max
Unit
DC input voltage
Input current high1
Input current low2
0
2.925
V
IIH (DC)
IIL (DC)
1. See Table 24, page 22.
DS0128 Datasheet Revision 11.0
59
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 185 • M-LVDS DC Voltage Specification Output Voltage Specification (for MSIO
I/O Bank Only)
Parameter
Symbol Min
Typ
Max
1.6
Unit
V
DC output logic high
DC output logic low
VOH
VOL
1.25
0.9
1.425
1.075
1.25
V
Table 186 • M-LVDS Differential Voltage Specification
Parameter
Symbol
Min
Max
650
2.1
Unit
mV
V
Differential output voltage swing (for MSIO I/O bank only)
Output common mode voltage (for MSIO I/O bank only)
Input common mode voltage
VOD
VOCM
VICM
VID
300
0.3
0.3
50
1.2
V
Input differential voltage
2400
mV
Table 187 • M-LVDS Minimum and Maximum AC Switching Speed for MSIO I/O Bank
Parameter
Symbol
Max
Unit Conditions
Mbps AC loading: 2 pF / 100 differential load
Maximum data rate
DMAX
500
Table 188 • M-LVDS AC Impedance Specifications
Parameter
Symbol
Typ
Unit
Termination resistance
RT
50
Table 189 • M-LVDS AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
Unit
V
Measuring/trip point for data path
Cross point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V
Table 190 • M-LVDS AC Switching Characteristics for Receiver (for MSIO I/O Bank -
Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.738
2.735
3.221
3.218
ns
DS0128 Datasheet Revision 11.0
60
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 191 • M-LVDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank -
Input Buffers)
TPY
–Std
On-Die Termination (ODT)
–1
Unit
ns
None
100
2.495
2.495
2.934
2.935
ns
Table 192 • M-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and
Tristate Buffers)
TDP
–Std –1
2.656 2.348
TZL
–Std –1
2.762 2.334
TZH
–Std –1
2.746 2.123
THZ
–Std –1
2.497 2.125
TLZ
–1
–Std Unit
2.5 ns
2.258
2.3.7.4 Mini-LVDS
Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed
to the Texas Instruments Standard SLDA007A.
Mini-LVDS Minimum and Maximum Input and Output Levels
Table 193 • Mini-LVDS Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
2.375
2.5
2.625
V
Table 194 • Mini-LVDS DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
DC Input voltage
VI
0
2.925
V
Table 195 • Mini-LVDS DC Output Voltage Specification
Parameter
Symbol Min
Typ
Max
1.6
Unit
V
DC output logic high
DC output logic low
VOH
VOL
1.25
0.9
1.425
1.075
1.25
V
Table 196 • Mini-LVDS DC Differential Voltage Specification
Parameter
Symbol Min
Max
600
1.4
Unit
mV
V
Differential output voltage swing VOD
300
1
Output common mode voltage
Input common mode voltage
Input differential voltage
VOCM
VICM
VID
0.3
100
1.2
V
600
mV
Table 197 • Mini-LVDS Minimum and Maximum AC Switching Speed
Parameter
Symbol
DMAX
Max
520
700
Unit
Conditions
Maximum data rate (for MSIO I/O bank)
Maximum data rate (for MSIOD I/O bank)
Mbps AC loading: 2 pF / 100 differential load
Mbps AC loading: 2 pF / 100 differential load
DMAX
DS0128 Datasheet Revision 11.0
61
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 198 • Mini-LVDS AC Impedance Specifications
Parameter
Symbol
Typ
Unit
Termination resistance
RT
100
Table 199 • Mini-LVDS AC Test Parameter Specifications
Parameter
Symbol
Typ
Unit
V
Measuring/trip point for data path
Resistance for enable path (TZH, TZL, THZ, TLZ
VTRIP
RENT
CENT
Cross point
)
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
pF
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.
Table 200 • Mini-LVDS AC Switching Characteristics for Receiver (for MSIO I/O
Bank - Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.855
2.85
2.602
2.597
3.359
3.353
3.061
3.055
ns
None
100
ns
ns
Table 201 • Mini-LVDS AC Switching Characteristics for Transmitter for MSIO I/O Bank (Output
and Tristate Buffers)
TDP
–Std –1
2.467 2.308
TZL
–Std –1
2.715 2.296
TZH
–Std –1
2.701 1.964
THZ
–Std –1
2.31 1.949
TLZ
–Std
2.293 ns
Unit
–1
2.097
Table 202 • Mini-LVDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and
Tristate Buffers)
TDP
–Std –1
TZL
–Std –1
TZH
–Std –1
THZ
–Std –1
TLZ
–Std
Unit
–1
No pre-emphasis
Min pre-emphasis
Med pre-emphasis
Max pre-emphasis
1.614
1.604
1.521
1.492
1.899 1.562
1.887 1.745
1.79 1.753
1.754 1.762
1.837 1.553
2.053 1.731
2.062 1.737
2.073 1.745
1.826 1.593
2.036 1.892
2.043 1.9
1.874 1.578
2.225 1.861
2.235 1.868
2.247 1.876
1.856 ns
2.189 ns
2.197 ns
2.206 ns
2.052 1.91
DS0128 Datasheet Revision 11.0
62
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.7.5 RSDS
Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using
differential signaling. RSDS has a similar implementation to LVDS devices and is only intended for
point-to-point applications.
Minimum and Maximum Input and Output Levels
Table 203 • RSDS Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
2.375
2.5
2.625
V
Table 204 • RSDS DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
DC input voltage
VI
0
2.925
V
Table 205 • RSDS DC Output Voltage Specification
Parameter
Symbol Min
Typ
Max
1.6
Unit
V
DC output logic high
DC output logic low
VOH
VOL
1.25
0.9
1.425
1.075
1.25
V
Table 206 • RSDS Differential Voltage Specification
Parameter
Symbol Min
Max Unit
Differential output voltage swing VOD
100
0.5
0.3
100
600
1.5
mV
V
Output common mode voltage
Input common mode voltage
Input differential voltage
VOCM
VICM
VID
1.5
V
600
mV
Table 207 • RSDS Minimum and Maximum AC Switching Speed
Parameter
Symbol Max
Unit
Conditions
Maximum data rate (for MSIO I/O bank)
DMAX
520
700
Mbps AC loading: 2 pF / 100 differential load
Mbps AC loading: 2 pF / 100 differential load
Maximum data rate (for MSIOD I/O bank) DMAX
Table 208 • RSDS AC Impedance Specifications
Parameter
Symbol
Typ
Unit
Termination resistance
RT
100
Table 209 • RSDS AC Test Parameter Specifications
Parameter
Symbol
VTRIP
RENT
Typ
Unit
V
Measuring/trip point for data path
Cross point
Resistance for enable path (TZH, TZL, THZ, TLZ
)
2K
5
Capacitive loading for enable path (TZH, TZL, THZ, TLZ
)
CENT
pF
DS0128 Datasheet Revision 11.0
63
IGLOO2 FPGA and SmartFusion2 SoC FPGA
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.
Table 210 • RSDS AC Switching Characteristics for Receiver (for MSIO I/O Bank -
Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.855
2.85
3.359
3.353
ns
Table 211 • RSDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank -
Input Buffers)
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.602
2.597
3.061
3.055
ns
Table 212 • RSDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and
Tristate Buffers)
TDP
–Std –1
2.467 2.303 2.709 2.291 2.695 1.961
TZL
TZH
THZ
–Std –1
2.307 1.947 2.29 ns
TLZ
–1
–Std –1
–Std –1
–Std Unit
2.097
Table 213 • RSDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate
Buffers)
TDP
TZL
–Std –1
1.834 1.55
2.05 1.728 2.032 1.889 2.222 1.858
TZH
–Std
1.823 1.59
THZ
–Std –1
1.87 1.575
TLZ
–Std Unit
–1
–Std –1
–1
No pre-emphasis
Min pre-emphasis
Med pre-emphasis
Max pre-emphasis
1.614
1.604
1.521
1.492
1.899 1.559
1.887 1.742
1.79 1.753
1.754 1.762
1.852 ns
2.185 ns
2.197 ns
2.206 ns
2.062 1.737 2.043 1.9
2.073 1.745 2.052 1.91
2.235 1.868
2.247 1.876
2.3.7.6 LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Similar to LVDS, two pins are needed. It also
requires external resistor termination. IGLOO2 and SmartFusion2 SoC FPGAs support only LVPECL
receivers and do not support LVPECL transmitters.
Minimum and Maximum Input and Output Levels (Applicable to MSIO I/O Bank Only)
Table 214 • LVPECL Recommended DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDDI
3.15
3.3
3.45
V
DS0128 Datasheet Revision 11.0
64
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 215 • LVPECL DC Input Voltage Specification
Parameter
Symbol
Min
Max
Unit
DC input voltage
VI
0
3.45
V
Table 216 • LVPECL DC Differential Voltage Specification
Parameter
Symbol
VICM
Min
0.3
Typ
Max
2.8
Unit
V
Input common mode voltage
Input differential voltage
VIDIFF
100
300
1,000
mV
Table 217 • LVPECL Minimum and Maximum AC Switching Speeds
Parameter
Symbol Max
DMAX 900
Unit
Maximum data rate
Mbps
AC Switching Characteristics
Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.
Table 218 • LVPECL Receiver Characteristics for MSIO I/O Bank
TPY
On-Die Termination (ODT)
–1
–Std
Unit
ns
None
100
2.572
2.569
3.025
3.023
ns
2.3.8 I/O Register Specifications
This section describes input and output register specifications.
2.3.8.1 Input Register
Figure 6 • Timing Model for Input Register
F
G
D
A
B
C
D
Q
Q
EN
EN
Input I/O Buffer
ALn
ALn
ADn
SLn
SD
ADn
SLn
SD
SLE
D
E
LAT
LAT
CLK
CLK
DS0128 Datasheet Revision 11.0
65
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 7 • I/O Register Input Timing Diagram
W,&.03:/
W,&.03:+
&/.
W,68'
W,+'
'
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀꢉ
ꢀꢀ
$'Q
6'
W,686/Q
W,+6/Q
6/Q
$/Q
(1
W,5(0$/Q
W,:$/Q
W,5(&$/Q
W,+(
W,68(
W,$/Qꢁ4
W,&/.4
4
ꢀ
ꢂ
ꢆ
ꢄ
DS0128 Datasheet Revision 11.0
66
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the input data register propagation delays in worst commercial-case conditions
when TJ = 85 °C, VDD = 1.14 V.
Table 219 • Input Data Register Propagation Delays
Measuring
Nodes
Parameter
Symbol
TIBYP
TICLKQ
TISUD
TIHD
(from, to)1 –1
–Std Unit
Bypass delay of the input register
F, G
E, G
A, E
A, E
B, E
B, E
D, E
D, E
C, G
C, G
C, E
C, E
C, C
E, E
E, E
0.353 0.415 ns
0.16 0.188 ns
0.357 0.421 ns
Clock-to-Q of the input register
Data setup time for the input register
Data hold time for the input register
0
0
ns
0.542 ns
ns
0.542 ns
ns
Enable setup time for the input register
TISUE
TIHE
TISUSL
TIHSL
0.46
0
Enable hold time for the input register
0
Synchronous load setup time for the input register
Synchronous load hold time for the input register
Asynchronous clear-to-Q of the input register (ADn=1)
Asynchronous preset-to-Q of the input register (ADn=0)
Asynchronous load removal time for the input register
Asynchronous load recovery time for the input register
Asynchronous load minimum pulse width for the input register
Clock minimum pulse width high for the input register
Clock minimum pulse width low for the input register
0.46
0
0
TIALN2Q
0.625 0.735 ns
0.587 0.69
ns
ns
TIREMALN
TIRECALN
TIWALN
0
0
0.074 0.087 ns
0.304 0.357 ns
0.075 0.088 ns
0.159 0.187 ns
TICKMPWH
TICKMPWL
1. For the derating values at specific junction temperature and voltage supply levels, see Table 16, page 14 for derating values.
DS0128 Datasheet Revision 11.0
67
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.8.2 Output/Enable Register
Figure 8 • Timing Model for Output/Enable Register
A
F
D
G
D
B
C
EN
EN
Q
ALn
ADn
SLn
SD
ALn
ADn
SLE
D
E
SLn
SD
LAT
CLK
LAT
CLK
H
I
J
D2
D
Q
EN
Output I/O Buffer
with Enable Control
ALn
ADn
SLn
SD
SLE
LAT
CLK
Output/Enable Registers
DS0128 Datasheet Revision 11.0
68
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 9 • I/O Register Output Timing Diagram
W2&.03:+
W2&.03:/
W2+'(
&ON
'
W268(
W2+'
W268'
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
$'Q
6'
W2686/Q
W2+'6/Q
6/Q
(1
W25(0$/Q
W25(&$/Q
$/Q
2XW
C
W2&/.4
W2$/Qꢁ4
ꢁ
ꢃ
ꢀ
The following table lists the output/enable propagation delays in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 220 • Output/Enable Data Register Propagation Delays
Measuring
Nodes
Parameter
Symbol
TOBYP
TOCLKQ
TOSUD
TOHD
(from, to)1 –1
–Std
Unit
Bypass delay of the output/enable register
Clock-to-Q of the output/enable register
F, G or H, I 0.353 0.415 ns
E, G or E, I 0.263 0.309 ns
Data setup time for the output/enable register
Data hold time for the output/enable register
Enable setup time for the output/enable register
Enable hold time for the output/enable register
Synchronous load setup time for the output/enable register
Synchronous load hold time for the output/enable register
A, E or J, E 0.19
A, E or J, E 0
0.223 ns
ns
0
TOSUE
TOHE
TOSUSL
TOHSL
B, E
B, E
D, E
D, E
0.419 0.493 ns
ns
0.196 0.231 ns
ns
0
0
0
0
Asynchronous clear-to-q of the output/enable register (ADn = 1) TOALN2Q
Asynchronous preset-to-q of the output/enable register (ADn = 0)
C, G or C, I 0.505 0.594 ns
C, G or C, I 0.528 0.621 ns
Asynchronous load removal time for the output/enable register
Asynchronous load recovery time for the output/enable register
TOREMALN
TORECALN
TOWALN
C, E
C, E
C, C
0
0
ns
ns
0.034 0.04
0.304 0.357
Asynchronous load minimum pulse width for the output/enable
register
ns
Clock minimum pulse width high for the output/enable register
Clock minimum pulse width low for the output/enable register
TOCKMPWH E, E
TOCKMPWL E, E
0.075 0.088
0.159 0.187
ns
ns
1. For the derating values at specific junction temperature and voltage supply levels, see Table 16, page 14 for derating values.
DS0128 Datasheet Revision 11.0
69
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.9 DDR Module Specification
This section describes input and output DDR module and timing specifications.
2.3.9.1 Input DDR Module
Figure 10 • Input DDR Module
A
C
D
D
E
QR
Q
EN
EN
F
ALn
ADn
SLn
SD
ALn
ADn
G
SLE
SLn
SD
LAT
CLK
LAT
B
CLK
D
Q
D
D
Q
QF
ALn
ADn
EN
Latch
ALn
ADn
SLn
SD
SLE
CLK
LAT
CLK
DDR_IN
DS0128 Datasheet Revision 11.0
70
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.9.2 Input DDR Timing Diagram
Figure 11 • Input DDR Timing Diagram
W''5,&.03:/
W''5,&.03:+
&/.
W''5,68'
W''5,+'
'
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀꢉ
ꢀꢀ
$'Q
6'
W''5,686/Q
W''5,+6/Q
6/Q
$/Q
(1
W''5,:$/
W''5,5(0$/
W''5,5(&$/
W''5,+(
W''5,68(
W''5,$/ꢁ4ꢀ
W''5,&/.4ꢀ
45
4)
ꢀ
ꢂ
ꢆ
ꢄ
W''5,$/ꢁ4ꢁ
W''5,&/.4ꢁ
ꢅ
ꢁ
ꢃ
2.3.9.3 Timing Characteristics
The following table lists the input DDR propagation delays in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 221 • Input DDR Propagation Delays
Measuring Nodes
(from, to)
Symbol
Description
–1
–Std
Unit
TDDRICLKQ1
TDDRICLKQ2
TDDRISUD
TDDRIHD
Clock-to-Out Out_QR for input DDR
Clock-to-Out Out_QF for input DDR
Data setup for input DDR
B, C
B, D
A, B
A, B
E, B
E, B
G, B
G, B
F, C
F, D
F, B
F, B
0.16
0.188 ns
0.166 0.195 ns
0.357 0.421 ns
Data hold for input DDR
0
0
ns
0.542 ns
ns
0.542 ns
TDDRISUE
Enable setup for input DDR
0.46
0
TDDRIHE
Enable hold for input DDR
0
TDDRISUSLN
TDDRIHSLN
TDDRIAL2Q1
TDDRIAL2Q2
TDDRIREMAL
TDDRIRECAL
Synchronous load setup for input DDR
Synchronous load hold for input DDR
Asynchronous load-to-out QR for input DDR
Asynchronous load-to-out QF for input DDR
Asynchronous load removal time for input DDR
Asynchronous load recovery time for input DDR
0.46
0
0
ns
ns
0.587 0.69
0.541 0.636 ns
ns
0.074 0.087 ns
0
0
DS0128 Datasheet Revision 11.0
71
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 221 • Input DDR Propagation Delays (continued)
Measuring Nodes
(from, to)
Symbol
Description
–1
–Std
Unit
TDDRIWAL
Asynchronous load minimum pulse width for input
DDR
F, F
0.304 0.357 ns
TDDRICKMPWH Clock minimum pulse width high for input DDR
TDDRICKMPWL Clock minimum pulse width low for input DDR
B, B
B, B
0.075 0.088 ns
0.159 0.187 ns
DS0128 Datasheet Revision 11.0
72
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.9.4 Output DDR Module
Figure 12 • Output DDR Module
A
D
DR
B
QR
Q
EN
EN
C
ALn
ALn
ADn
SLn
SD
ADn
SLE
D
SLn
SD
1
G
LAT
CLK
Q
LAT
E
CLK
F
DF
D
QF
Q
EN
ALn
ADn
SLn
SD
SLE
LAT
CLK
0
DDR _ OUT
DS0128 Datasheet Revision 11.0
73
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 13 • Output DDR Timing Diagram
W''5268(
W''52&.03:+
W''52&.03:/
&ON
W''52+'(
W''52+'5
W''5268'5
'5
')
ꢀ
ꢁ
ꢆ
ꢂ
ꢃ
ꢄ
W''5268')
W''52+')
ꢅ
ꢇ
ꢈ
ꢀꢉ
ꢀꢀ
$'Q
6'
W''52686/Q
W''52+'6/Q
6/Q
(1
W''52:$/
W''525(0$
W''525(&$/
$/Q
2XW
C
W''52&/.4
W''52$/ꢁ4
ꢃ
ꢈ
ꢀ
ꢅ
ꢁ
ꢆ
2.3.9.5 Timing Characteristics
The following table lists the output DDR propagation delays in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 222 • Output DDR Propagation Delays
Measuring Nodes
(from, to)
Symbol
Description
–1
–Std
Unit
TDDROCLKQ
TDDROSUDF
TDDROSUDR
TDDROHDF
TDDROHDR
TDDROSUE
TDDROHE
Clock-to-out of DDR for output DDR
Data_F data setup for output DDR
Data_R data setup for output DDR
Data_F data hold for output DDR
Data_R data hold for output DDR
Enable setup for input DDR
E, G
F, E
0.263
0.143
0.19
0
0.309 ns
0.168 ns
0.223 ns
A, E
F, E
0
0
ns
ns
A, E
B, E
B, E
D, E
D, E
C, G
C, E
C, E
0
0.419
0
0.493 ns
ns
0.231 ns
ns
0.621 ns
Enable hold for input DDR
0
TDDROSUSLN
TDDROHSLN
TDDROAL2Q
TDDROREMAL
TDDRORECAL
Synchronous load setup for input DDR
Synchronous load hold for input DDR
Asynchronous load-to-out for output DDR
Asynchronous load removal time for output DDR
Asynchronous load recovery time for output DDR
0.196
0
0
0.528
0
0
ns
ns
0.034
0.04
DS0128 Datasheet Revision 11.0
74
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 222 • Output DDR Propagation Delays (continued)
Measuring Nodes
(from, to)
Symbol
Description
–1
–Std
Unit
TDDROWAL
Asynchronous load minimum pulse width for output C, C
DDR
0.304
0.357 ns
TDDROCKMPWH Clock minimum pulse width high for the output DDR E, E
TDDROCKMPWL Clock minimum pulse width low for the output DDR E, E
0.075
0.159
0.088 ns
0.187 ns
2.3.10 Logic Element Specifications
2.3.10.1 4-input LUT (LUT-4)
The IGLOO2 and SmartFusion2 SoC FPGAs offer a fully permutable 4-input LUT. In this section, timing
characteristics are presented for a sample of the library. For more details, see SmartFusion2 and
IGLOO2 Macro Library Guide.
Figure 14 • LUT-4
T
PD
A
B
PAD
PAD
PAD
AND4 OR
Any
Combinational
Logic
Y
PAD
C
D/S (where
applicable)
PAD
V
DD
T
= Max(t (RR), T (RF), T (FF), T (FR))
PD PD PD PD
PD
where edges are applicable for the particular
combinatorial cell
A, B, C, D, S
50%
50%
GND
50%
V
DD
50%
OUT
T
GND
T
PD
PD
(FF)
(RR)
V
DD
T
OUT
PD
(FR)
50%
50%
T
PD
GND
(RF)
DS0128 Datasheet Revision 11.0
75
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.10.2 Timing Characteristics
The following table lists the combinatorial cell propagation delays in worst commercial-case conditions
when TJ = 85 °C, VDD = 1.14 V.
Table 223 • Combinatorial Cell Propagation Delays
Combinatorial Cell
INV
Equation
Symbol
TPD
–1
–Std
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Y = !A
0.1
0.118
0.193
0.173
0.193
0.173
0.193
0.265
0.246
0.338
AND2
Y = A · B
TPD
0.164
0.147
0.164
0.147
0.164
0.225
0.209
0.287
NAND2
OR2
Y = !(A · B)
Y = A + B
TPD
TPD
NOR2
Y = !(A + B)
Y = A B
Y = A B C
Y = A · B · C
Y = A · B · C · D
TPD
XOR2
TPD
XOR3
TPD
AND3
TPD
AND4
TPD
2.3.10.3 Sequential Module
IGLOO2 and SmartFusion2 SoC FPGAs offer a separate flip-flop which can be used independently from
the LUT. The flip-flop can be configured as a register or a latch and has a data input and optional enable,
synchronous load (clear or preset), and asynchronous load (clear or preset).
Figure 15 • Sequential Module
D
Q
EN
ALn
ADn
SLn
SD
SLE
LAT
CLK
DS0128 Datasheet Revision 11.0
76
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following figure shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous
clear) for a flip-flop (LAT = 0).
Figure 16 • Sequential Module Timing Diagram
W&.03:+
W&.03:/
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
&/.
W68'
W+'
ꢄꢉꢊ
'
ꢀ
ꢉ
ꢀ
ꢀ
ꢉ
ꢄꢉꢊ
6'
$'Q
ꢄꢉꢊ
(
W686/
W+6/
W+(
W68(
6/
ꢄꢉꢊ
ꢄꢉꢊ
W5(0$/Q
W:$/Q
ꢄꢉꢊ
ꢄꢉꢊ
ꢄꢉꢊ
$/Q
4
ꢄꢉꢊ
W5(&$/Q
W$/Qꢁ4
ꢄꢉꢊ
ꢄꢉꢊ
W&/.4
2.3.10.3.1 Timing Characteristics
The following table lists the register delays in worst commercial-case conditions when TJ = 85 °C,
VDD = 1.14 V.
Table 224 • Register Delays
Parameter
Symbol
TCLKQ
TSUD
THD
–1
–Std
0.127
0.298
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock-to-Q of the core register
0.108
0.254
0
Data setup time for the core register
Data hold time for the core register
Enable setup time for the core register
TSUE
THE
0.335
0
0.394
0
Enable hold time for the core register
Synchronous load setup time for the core register
Synchronous load hold time for the core register
Asynchronous Clear-to-Q of the core register (ADn = 1)
Asynchronous preset-to-Q of the core register (ADn = 0)
Asynchronous load removal time for the core register
Asynchronous load recovery time for the core register
Asynchronous load minimum pulse width for the core register
Clock minimum pulse width high for the core register
Clock minimum pulse width low for the core register
TSUSL
THSL
0.335
0
0.394
0
0.473
0.451
0
0.556
0.531
0
TALN2Q
TREMALN
TRECALN
TWALN
0.353
0.266
0.065
0.139
0.415
0.313
0.077
0.164
TCKMPWH
TCKMPWL
DS0128 Datasheet Revision 11.0
77
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.11 Global Resource Characteristics
The IGLOO2 and SmartFusion2 SoC FPGA devices offer a powerful, low skew global routing network
which provides an effective clock distribution throughout the FPGA fabric. See UG0445: IGLOO2 FPGA
and SmartFusion2 SoC FPGA Fabric User Guide for the positions of various global routing resources.
The following table lists the 150 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 225 • 150 Device Global Resource
–1
Max
–Std
Max
Parameter
Symbol
TRCKL
Min
Min
Unit
ns
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
0.83
1.457
0.911
1.588
0.131
0.831
1.715
0.913
1.869
0.154
TRCKH
ns
TRCKSW
ns
The following table lists the 090 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 226 • 090 Device Global Resource
–1
Max
–Std
Max
Parameter
Symbol
TRCKL
Min
Min
Unit
ns
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
0.835
1.405
0.888
1.489
0.084
0.833
1.654
0.886
1.752
0.098
TRCKH
ns
TRCKSW
ns
The following table lists the 050 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 227 • 050 Device Global Resource
–1
Max
0.827 0.897 0.826 0.896 ns
–Std
Parameter
Symbol
TRCKL
Min
Min
Max
Unit
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
TRCKH
1.419 1.53
0.111
1.671 1.8
ns
TRCKSW
0.129 ns
The following table lists the 025 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 228 • 025 Device Global Resource
–1
Max
–Std
Max
Parameter
Symbol
TRCKL
Min
Min
Unit
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
0.747 0.799 0.745 0.797 ns
1.294 1.378 1.522 1.621 ns
TRCKH
TRCKSW
0.084
0.099 ns
DS0128 Datasheet Revision 11.0
78
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the 010 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 229 • 010 Device Global Resource
–1
Max
–Std
Max
Parameter
Symbol
TRCKL
Min
Min
Unit
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
0.626 0.669 0.627 0.668 ns
1.112 1.182 1.308 1.393 ns
TRCKH
TRCKSW
0.07
0.085 ns
The following table lists the 005 device global resources in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 230 • 005 Device Global Resource
–1
Max
0.625 0.66
–Std
Max
0.628 0.66
Parameter
Symbol
TRCKL
Min
Min
Unit
Input low delay for global clock
Input high delay for global clock
Maximum skew for global clock
ns
TRCKH
1.126 1.187 1.325 1.397 ns
0.061 0.072 ns
TRCKSW
2.3.12 FPGA Fabric SRAM
See UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information.
2.3.12.1 FPGA Fabric Large SRAM (LSRAM)
The following table lists the RAM1K18 – dual-port mode for depth × width configuration 1K × 18 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 231 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
Min
Unit
ns
Clock period
2.5
2.941
1.323
1.323
2.941
1.323
1.323
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.125
1.125
2.5
ns
ns
ns
Pipelined clock minimum pulse width high
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Access time with feed-through write timing
Address setup time
TPLCLKMPWH 1.125
TPLCLKMPWL 1.125
ns
ns
0.334
2.273
1.529
0.393 ns
TCLK2Q
2.674 ns
1.799 ns
TADDRSU
TADDRHD
TDSU
0.441
0.274
0.341
0.107
0.207
0.519
0.322
0.401
0.126
0.244
ns
ns
ns
ns
ns
Address hold time
Data setup time
Data hold time
TDHD
Block select setup time
TBLKSU
DS0128 Datasheet Revision 11.0
79
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 231 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18 (continued)
–1
–Std
Max
Parameter
Symbol
Min
Max
Min
Unit
Block select hold time
TBLKHD
0.216
0.254
ns
Block select to out disable time (when pipelined register is TBLK2Q
disabled)
1.529
1.799 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
0.186
0.449
0.167
0.248
0.219
0.528
0.197
0.291
ns
ns
ns
ns
Read enable hold time
TRDEHD
Pipelined read enable setup time (A_DOUT_EN,
B_DOUT_EN)
TRDPLESU
Pipelined read enable hold time (A_DOUT_EN,
B_DOUT_EN)
TRDPLEHD
0.102
0.12
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
–
1.506
–
1.772 ns
TRSTREM
TRSTREC
TRSTMPW
TPLRSTREM
TPLRSTREC
TPLRSTMPW
0.506
0.004
0.301
–0.279
0.327
0.282
0.595
0.005
0.354
–0.328
0.385
0.332
ns
ns
ns
ns
ns
ns
Asynchronous reset recovery time
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time
Pipelined register asynchronous reset recovery time
Pipelined register asynchronous reset minimum pulse
width
Synchronous reset setup time
Synchronous reset hold time
Write enable setup time
Write enable hold time
TSRSTSU
TSRSTHD
TWESU
TWEHD
FMAX
0.226
0.036
0.39
0.265
0.043
0.458
0.285
ns
ns
ns
ns
0.242
Maximum frequency
400
340
MHz
The following table lists the RAM1K18 – dual-port mode for depth × width configuration 2K × 9 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 232 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9
–1
–Std
Max Unit
Parameter
Symbol
TCY
Min
Max Min
2.941
Clock period
2.5
ns
ns
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.125
1.125
2.5
1.323
1.323
2.941
1.323
1.323
ns
ns
Pipelined clock minimum pulse width high
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Access time with feed-through write timing
TPLCLKMPWH 1.125
TPLCLKMPWL 1.125
ns
ns
0.334
2.273
1.529
0.393 ns
2.674 ns
1.799 ns
TCLK2Q
DS0128 Datasheet Revision 11.0
80
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 232 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9 (continued)
–1
–Std
Max Unit
Parameter
Symbol
TADDRSU
TADDRHD
TDSU
Min
Max Min
0.559
Address setup time
Address hold time
Data setup time
0.475
0.274
0.336
0.082
0.207
0.216
ns
0.322
0.395
0.096
0.244
0.254
ns
ns
Data hold time
TDHD
ns
ns
Block select setup time
Block select hold time
TBLKSU
TBLKHD
TBLK2Q
ns
Block select to out disable time (when pipelined register is
disabled)
1.529
1.799 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
0.186
0.485
0.071
0.248
0.219
0.57
ns
ns
ns
ns
Read enable hold time
TRDEHD
0.083
0.291
Pipelined read enable setup time (A_DOUT_EN,
B_DOUT_EN)
TRDPLESU
Pipelined read enable hold time (A_DOUT_EN,
B_DOUT_EN)
TRDPLEHD
0.102
0.12
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
1.514
1.781 ns
TRSTREM
TRSTREC
TRSTMPW
TPLRSTREM
TPLRSTREC
0.506
0.004
0.301
–0.279
0.327
0.282
0.226
0.036
0.415
0.048
0.595
0.005
0.354
–0.328
0.385
0.332
0.265
0.043
0.488
0.057
ns
Asynchronous reset recovery time
ns
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time
Pipelined register asynchronous reset recovery time
ns
ns
ns
Pipelined register asynchronous reset minimum pulse width TPLRSTMPW
ns
Synchronous reset setup time
Synchronous reset hold time
Write enable setup time
Write enable hold time
TSRSTSU
TSRSTHD
TWESU
TWEHD
FMAX
ns
ns
ns
ns
Maximum frequency
400
340 MHz
The following table lists the RAM1K18 – dual-port mode for depth × width configuration 4K × 4 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 233 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4
–1
–Std
Max
Parameter
Symbol
TCY
Min
Max
Min
Unit
ns
Clock period
2.5
2.941
1.323
1.323
2.941
1.323
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.125
1.125
2.5
ns
ns
ns
Pipelined clock minimum pulse width high
TPLCLKMPWH 1.125
ns
DS0128 Datasheet Revision 11.0
81
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 233 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4 (continued)
–1
–Std
Parameter
Symbol
Min
Max
Min
Max
Unit
ns
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Access time with feed-through write timing
Address setup time
TPLCLKMPWL
1.125
1.323
0.323
2.273
1.511
0.38
ns
TCLK2Q
2.673 ns
1.778 ns
TADDRSU
TADDRHD
TDSU
0.543
0.274
0.334
0.082
0.207
0.216
0.638
0.322
0.393
0.096
0.244
0.254
ns
Address hold time
ns
Data setup time
ns
Data hold time
TDHD
ns
ns
Block select setup time
TBLKSU
TBLKHD
TBLK2Q
Block select hold time
ns
Block select to out disable time (when pipelined
register is disabled)
1.511
1.778 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
0.186
0.516
0.071
0.248
0.219
0.607
0.083
0.291
ns
ns
ns
ns
Read enable hold time
TRDEHD
Pipelined read enable setup time (A_DOUT_EN,
B_DOUT_EN)
TRDPLESU
Pipelined read enable hold time (A_DOUT_EN,
B_DOUT_EN)
TRDPLEHD
0.102
0.12
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
1.507
1.773 ns
TRSTREM
TRSTREC
TRSTMPW
0.506
0.004
0.301
–0.279
0.327
0.282
0.595
0.005
0.354
–0.328
0.385
0.332
ns
ns
ns
ns
ns
ns
Asynchronous reset recovery time
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time TPLRSTREM
Pipelined register asynchronous reset recovery time TPLRSTREC
Pipelined register asynchronous reset minimum pulse TPLRSTMPW
width
Synchronous reset setup time
Synchronous reset hold time
Write enable setup time
Write enable hold time
TSRSTSU
TSRSTHD
TWESU
TWEHD
FMAX
0.226
0.036
0.458
0.048
0.265
0.043
0.539
0.057
ns
ns
ns
ns
Maximum frequency
400
340
MHz
DS0128 Datasheet Revision 11.0
82
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the RAM1K18 – dual-port mode for depth × width configuration 8K × 2 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 234 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8K × 2
–1
–Std
Max Unit
Parameter
Symbol
Min
Max Min
2.941
Clock period
TCY
2.5
ns
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.125
1.125
2.5
1.323
1.323
2.941
1.323
1.323
ns
ns
ns
Pipelined clock minimum pulse width high
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Access time with feed-through write timing
Address setup time
TPLCLKMPWH
TPLCLKMPWL
1.125
1.125
ns
ns
0.377 ns
2.673 ns
1.778 ns
ns
0.32
TCLK2Q
2.272
1.511
TADDRSU
TADDRHD
TDSU
0.612
0.274
0.33
0.72
Address hold time
0.322
0.388
0.096
0.244
0.254
ns
Data setup time
ns
Data hold time
TDHD
0.082
0.207
0.216
ns
Block select setup time
TBLKSU
TBLKHD
TBLK2Q
ns
Block select hold time
ns
Block select to out disable time (when pipelined register is
disabled)
1.511
1.778 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
0.186
0.529
0.071
0.248
0.219
0.622
0.083
0.291
ns
ns
ns
ns
Read enable hold time
TRDEHD
Pipelined read enable setup time (A_DOUT_EN,
B_DOUT_EN)
TRDPLESU
Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD
0.102
0.12
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
1.528
1.797 ns
TRSTREM
TRSTREC
TRSTMPW
TPLRSTREM
TPLRSTREC
TPLRSTMPW
TSRSTSU
TSRSTHD
TWESU
0.506
0.004
0.301
0.595
0.005
0.354
–0.328
0.385
0.332
0.265
0.043
0.574
0.057
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous reset recovery time
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time
Pipelined register asynchronous reset recovery time
Pipelined register asynchronous reset minimum pulse width
Synchronous reset setup time
–0.279
0.327
0.282
0.226
0.036
0.488
0.048
Synchronous reset hold time
Write enable setup time
Write enable hold time
TWEHD
Maximum frequency
FMAX
400
340
MHz
DS0128 Datasheet Revision 11.0
83
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the RAM1K18 – dual-port mode for depth × width configuration 16K × 1 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 235 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16K × 1
–1
–Std
Max Unit
Parameter
Symbol
Min
Max Min
2.941
Clock period
TCY
2.5
ns
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH 1.125
1.323
1.323
2.941
1.323
1.323
ns
TCLKMPWL
TPLCY
1.125
2.5
ns
ns
Pipelined clock minimum pulse width high
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Access time with feed-through write timing
Address setup time
TPLCLKMPWH 1.125
TPLCLKMPWL 1.125
ns
ns
0.377 ns
2.669 ns
1.777 ns
ns
0.32
2.269
1.51
TCLK2Q
TADDRSU
TADDRHD
TDSU
0.626
0.274
0.322
0.082
0.207
0.216
0.737
0.322
0.378
0.096
0.244
0.254
Address hold time
ns
Data setup time
ns
Data hold time
TDHD
ns
Block select setup time
TBLKSU
TBLKHD
TBLK2Q
ns
Block select hold time
ns
Block select to out disable time (when pipelined register is
disabled)
1.51
1.777 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
TRDEHD
0.186
0.53
0.219
0.624
0.083
0.291
0.12
ns
ns
Read enable hold time
0.071
0.248
0.102
ns
Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU
Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD
ns
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
1.547
1.82 ns
TRSTREM
TRSTREC
TRSTMPW
0.506
0.004
0.301
0.595
0.005
0.354
–0.328
0.385
0.332
0.265
0.043
0.534
0.057
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous reset recovery time
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time
Pipelined register asynchronous reset recovery time
Pipelined register asynchronous reset minimum pulse width
Synchronous reset setup time
TPLRSTREM –0.279
TPLRSTREC 0.327
TPLRSTMPW 0.282
TSRSTSU
TSRSTHD
TWESU
TWEHD
FMAX
0.226
0.036
0.454
0.048
Synchronous reset hold time
Write enable setup time
Write enable hold time
Maximum frequency
400
340
MHz
DS0128 Datasheet Revision 11.0
84
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the RAM1K18 – two-port mode for depth × width configuration 512 × 36 in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 236 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512 × 36
–1
–Std
Max Unit
Parameter
Symbol
Min
Max Min
2.941
Clock period
TCY
2.5
ns
Clock minimum pulse width high
Clock minimum pulse width low
Pipelined clock period
TCLKMPWH 1.125
1.323
1.323
2.941
1.323
1.323
ns
TCLKMPWL
TPLCY
1.125
2.5
ns
ns
Pipelined clock minimum pulse width high
Pipelined clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Address setup time
TPLCLKMPWH 1.125
TPLCLKMPWL 1.125
ns
ns
0.334
2.25
0.393 ns
TCLK2Q
2.647 ns
TADDRSU
TADDRHD
TDSU
0.313
0.274
0.337
0.111
0.207
0.201
0.368
0.322
0.396
0.13
ns
Address hold time
ns
Data setup time
ns
Data hold time
TDHD
ns
ns
Block select setup time
TBLKSU
TBLKHD
TBLK2Q
0.244
0.237
Block select hold time
ns
Block select to out disable time (when pipelined register is
disabled)
2.25
2.647 ns
Block select minimum pulse width
Read enable setup time
TBLKMPW
TRDESU
TRDEHD
0.186
0.449
0.167
0.248
0.102
0.219
0.528
0.197
0.291
0.12
ns
ns
Read enable hold time
ns
Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU
Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD
ns
ns
Asynchronous reset to output propagation delay
Asynchronous reset removal time
TR2Q
1.506
1.772 ns
TRSTREM
TRSTREC
TRSTMPW
0.506
0.004
0.301
0.595
0.005
0.354
–0.328
0.385
0.332
0.265
0.043
0.458
0.285
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Asynchronous reset recovery time
Asynchronous reset minimum pulse width
Pipelined register asynchronous reset removal time
Pipelined register asynchronous reset recovery time
Pipelined register asynchronous reset minimum pulse width
Synchronous reset setup time
TPLRSTREM –0.279
TPLRSTREC 0.327
TPLRSTMPW 0.282
TSRSTSU
TSRSTHD
TWESU
TWEHD
FMAX
0.226
0.036
0.39
Synchronous reset hold time
Write enable setup time
Write enable hold time
0.242
Maximum frequency
400
340
MHz
DS0128 Datasheet Revision 11.0
85
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.12.2 FPGA Fabric Micro SRAM (µSRAM)
The following table lists the µSRAM in 64 × 18 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 237 • µSRAM (RAM64x18) in 64 × 18 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
ns
ns
ns
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
ns
ns
0.266
1.677
0.313 ns
TCLK2Q
1.973 ns
0.301
0.354
2.184
0.107
–0.915
0.327
0.067
2.163
–0.765
ns
TADDRSU
1.856
0.091
–0.778
0.278
0.057
1.839
–0.65
ns
ns
TADDRHD
ns
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
ns
Read enable hold time
ns
ns
Read block select setup time
Read block select hold time
ns
Read block select to out disable time (when pipelined
register is disabled)
2.036
2.396 ns
Read asynchronous reset removal time (pipelined clock)
–0.023
0.046
–0.027
0.054
ns
ns
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay
(with pipelined register enabled)
TR2Q
0.839
0.987 ns
Read synchronous reset setup time
Read synchronous reset hold time
Write clock period
TSRSTSU
TSRSTHD
TCCY
0.271
0.061
4
0.319
0.071
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
1.8
1.8
1.8
1.8
0.404
0.007
0.115
0.15
0.476
0.008
0.135
0.177
Write block hold time
Write input data setup time
Write input data hold time
DS0128 Datasheet Revision 11.0
86
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 237 • µSRAM (RAM64x18) in 64 × 18 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
Min
Min
Unit
ns
Write address setup time
Write address hold time
Write enable setup time
Write enable hold time
Maximum frequency
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
0.088
0.128
0.397
–0.026
0.104
0.15
ns
0.467
–0.03
ns
ns
250
250
MHz
The following table lists the µSRAM in 64 × 16 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 238 • µSRAM (RAM64x16) in 64 × 16 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
ns
ns
ns
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
ns
ns
0.266
1.677
0.313 ns
TCLK2Q
1.973 ns
0.301
0.354
2.184
0.107
–0.915
0.327
0.067
2.163
–0.765
ns
TADDRSU
1.856
0.091
–0.778
0.278
0.057
1.839
–0.65
ns
ns
TADDRHD
ns
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
ns
Read enable hold time
ns
ns
Read block select setup time
Read block select hold time
ns
Read block select to out disable time (when pipelined
register is disabled)
2.036
2.396 ns
Read asynchronous reset removal time (pipelined clock)
–0.023
0.046
–0.027
0.054
ns
ns
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay (with TR2Q
pipelined register enabled)
0.835
0.983 ns
ns
Read synchronous reset setup time
TSRSTSU
0.271
0.319
DS0128 Datasheet Revision 11.0
87
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 238 • µSRAM (RAM64x16) in 64 × 16 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
TSRSTHD
TCCY
Min
Min
Unit
ns
Read synchronous reset hold time
Write clock period
0.061
4
0.071
4
ns
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
1.8
1.8
ns
1.8
1.8
ns
0.404
0.007
0.115
0.15
0.088
0.128
0.397
–0.026
0.476
0.008
0.135
0.177
0.104
0.15
0.467
–0.03
ns
Write block hold time
ns
Write input data setup time
Write input data hold time
Write address setup time
Write address hold time
Write enable setup time
Write enable hold time
ns
ns
ns
ns
ns
ns
Maximum frequency
250
250
MHz
The following table lists the µSRAM in 128 × 9 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 239 • µSRAM (RAM128x9) in 128 × 9 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
ns
ns
ns
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
ns
ns
0.266
1.677
0.313 ns
TCLK2Q
1.973 ns
0.301
0.354
2.184
0.107
–0.915
0.327
0.067
2.163
–0.765
ns
TADDRSU
1.856
0.091
–0.778
0.278
0.057
1.839
–0.65
ns
ns
TADDRHD
ns
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
ns
Read enable hold time
ns
ns
Read block select setup time
Read block select hold time
ns
Read block select to out disable time (when pipelined
register is disabled)
2.036
2.396 ns
DS0128 Datasheet Revision 11.0
88
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 239 • µSRAM (RAM128x9) in 128 × 9 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
Min
Min
Unit
ns
Read asynchronous reset removal time (pipelined clock)
–0.023
0.046
–0.027
0.054
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
ns
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay (with TR2Q
pipelined register enabled)
0.835
0.982 ns
Read synchronous reset setup time
Read synchronous reset hold time
Write clock period
TSRSTSU
TSRSTHD
TCCY
0.271
0.061
4
0.319
0.071
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
1.8
1.8
1.8
1.8
0.404
0.007
0.115
0.15
0.476
0.008
0.135
0.177
0.104
0.15
Write block hold time
Write input data setup time
Write input data hold time
Write address setup time
Write address hold time
0.088
0.128
0.397
–0.026
Write enable setup time
0.467
–0.03
Write enable hold time
Maximum frequency
250
250
MHz
The following table lists the µSRAM in 128 × 8 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 240 • µSRAM (RAM128x8) in 128 × 8 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
ns
ns
ns
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
ns
ns
0.266
1.677
0.313 ns
1.973 ns
ns
TCLK2Q
0.301
1.856
0.354
2.184
TADDRSU
ns
DS0128 Datasheet Revision 11.0
89
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 240 • µSRAM (RAM128x8) in 128 × 8 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
Min
Min
Unit
ns
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
0.091
–0.778
0.278
0.057
1.839
–0.65
0.107
TADDRHD
–0.915
0.327
0.067
2.163
–0.765
ns
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
ns
Read enable hold time
ns
Read block select setup time
Read block select hold time
ns
ns
Read block select to out disable time (when pipelined
register is disabled)
2.036
2.396 ns
Read asynchronous reset removal time (pipelined clock)
–0.023
0.046
–0.027
0.054
ns
ns
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay (with TR2Q
pipelined register enabled)
0.835
0.982 ns
Read synchronous reset setup time
Read synchronous reset hold time
Write clock period
TSRSTSU
TSRSTHD
TCCY
0.271
0.061
4
0.319
0.071
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH 1.8
1.8
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
1.8
1.8
0.404
0.007
0.115
0.15
0.476
0.008
0.135
0.177
0.104
0.15
0.467
–0.03
Write block hold time
Write input data setup time
Write input data hold time
Write address setup time
Write address hold time
0.088
0.128
0.397
–0.026
Write enable setup time
Write enable hold time
Maximum frequency
250
250
MHz
DS0128 Datasheet Revision 11.0
90
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the µSRAM in 256 × 4 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 241 • µSRAM (RAM256x4) in 256 × 4 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
0.27
1.75
0.31
2.06
TCLK2Q
0.301
0.354
2.272
0.142
–0.76
0.327
0.067
2.163
–0.77
TADDRSU
1.931
0.121
–0.65
0.278
0.057
1.839
–0.65
TADDRHD
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
Read enable hold time
Read block select setup time
Read block select hold time
Read block select to out disable time (when pipelined
register is disabled)
2.09
2.46
Read asynchronous reset removal time (pipelined clock)
–0.02
0.046
–0.03
0.054
ns
ns
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay
(with pipelined register enabled)
TR2Q
0.83
0.98
ns
Read synchronous reset setup time
Read synchronous reset hold time
Write clock period
TSRSTSU
TSRSTHD
TCCY
0.271
0.061
4
0.319
0.071
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
1.8
1.8
1.8
1.8
0.404
0.007
0.101
0.137
0.088
0.476
0.008
0.118
0.161
0.104
Write block hold time
Write input data setup time
Write input data hold time
Write address setup time
DS0128 Datasheet Revision 11.0
91
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 241 • µSRAM (RAM256x4) in 256 × 4 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
Min
Min
Unit
ns
Write address hold time
Write enable setup time
Write enable hold time
Maximum frequency
TADDRCHD
TWECSU
TWECHD
FMAX
0.245
0.397
–0.03
0.288
0.467
–0.03
ns
ns
250
250
MHz
The following table lists the µSRAM in 512 × 2 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 242 • µSRAM (RAM512x2) in 512 × 2 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
0.27
1.76
0.31
2.08
TCLK2Q
0.301
0.354
2.306
0.161
–0.68
0.327
0.067
2.163
–0.77
TADDRSU
1.96
0.137
–0.58
0.278
0.057
1.839
–0.65
TADDRHD
TRDENSU
TRDENHD
TBLKSU
TBLKHD
TBLK2Q
Read enable hold time
Read block select setup time
Read block select hold time
Read block select to out disable time (when pipelined
register is disabled)
2.14
2.52
Read asynchronous reset removal time (pipelined clock)
–0.02
0.046
–0.03
0.054
ns
ns
TRSTREM
Read asynchronous reset removal time (non-pipelined
clock)
Read asynchronous reset recovery time (pipelined clock)
0.507
0.236
0.597
0.278
ns
ns
TRSTREC
Read asynchronous reset recovery time (non-pipelined
clock)
Read asynchronous reset to output propagation delay (with TR2Q
pipelined register enabled)
0.83
0.98
ns
Read synchronous reset setup time
Read synchronous reset hold time
TSRSTSU
0.271
0.061
0.319
0.071
ns
ns
TSRSTHD
DS0128 Datasheet Revision 11.0
92
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 242 • µSRAM (RAM512x2) in 512 × 2 Mode (continued)
–1
Max
–Std
Max
Parameter
Symbol
Min
Min
Unit
ns
Write clock period
TCCY
4
4
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
Write block hold time
TCCLKMPWH
TCCLKMPWL
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
1.8
1.8
ns
1.8
1.8
ns
0.404
0.007
0.101
0.137
0.088
0.247
0.397
–0.03
0.476
0.008
0.118
0.161
0.104
0.29
0.467
–0.03
ns
ns
Write input data setup time
Write input data hold time
Write address setup time
Write address hold time
Write enable setup time
Write enable hold time
Maximum frequency
ns
ns
ns
ns
ns
ns
250
250
MHz
The following table lists the µSRAM in 1024 × 1 mode in worst commercial-case conditions when
TJ = 85 °C, VDD = 1.14 V.
Table 243 • µSRAM (RAM1024x1) in 1024 × 1 Mode
–1
Max
–Std
Max
Parameter
Symbol
TCY
Min
4
Min
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read clock period
Read clock minimum pulse width high
Read clock minimum pulse width low
Read pipeline clock period
TCLKMPWH
TCLKMPWL
TPLCY
1.8
1.8
4
1.8
1.8
4
Read pipeline clock minimum pulse width high
Read pipeline clock minimum pulse width low
Read access time with pipeline register
Read access time without pipeline register
Read address setup time in synchronous mode
Read address setup time in asynchronous mode
Read address hold time in synchronous mode
Read address hold time in asynchronous mode
Read enable setup time
TPLCLKMPWH 1.8
TPLCLKMPWL 1.8
1.8
1.8
0.27
1.78
0.31
2.1
TCLK2Q
0.301
0.354
2.327
0.161
–0.71
0.327
0.067
2.163
–0.77
TADDRSU
1.978
0.137
–0.6
TADDRHD
TRDENSU
TRDENHD
TBLKSU
0.278
0.057
1.839
–0.65
Read enable hold time
Read block select setup time
Read block select hold time
TBLKHD
Read block select to out disable time (when pipelined register TBLK2Q
is disabled)
2.16
2.54
Read asynchronous reset removal time (pipelined clock)
TRSTREM
–0.02
0.046
–0.03
0.054
ns
ns
Read asynchronous reset removal time (non-pipelined clock)
DS0128 Datasheet Revision 11.0
93
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 243 • µSRAM (RAM1024x1) in 1024 × 1 Mode (continued)
–1
Max
–Std
Parameter
Symbol
Min
Min
Max
Unit
ns
Read asynchronous reset recovery time (pipelined clock)
Read asynchronous reset recovery time (non-pipelined clock)
0.507
0.236
0.597
0.278
TRSTREC
ns
Read asynchronous reset to output propagation delay (with TR2Q
pipelined register enabled)
0.83
0.98
ns
Read synchronous reset setup time
Read synchronous reset hold time
Write clock period
TSRSTSU
TSRSTHD
TCCY
0.271
0.061
4
0.319
0.071
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Write clock minimum pulse width high
Write clock minimum pulse width low
Write block setup time
TCCLKMPWH 1.8
TCCLKMPWL 1.8
1.8
1.8
TBLKCSU
TBLKCHD
TDINCSU
TDINCHD
TADDRCSU
TADDRCHD
TWECSU
TWECHD
FMAX
0.404
0.476
0.008
0.004
0.161
0.104
0.29
0.467
–0.03
Write block hold time
0.007
0.003
0.137
0.088
0.247
0.397
–0.03
Write input data setup time
Write input data hold time
Write address setup time
Write address hold time
Write enable setup time
Write enable hold time
Maximum frequency
250
250
2.3.13 Programming Times
The following tables list the programming times in typical conditions when TJ = 25 °C, VDD = 1.2 V.
External SPI flash part# AT25DF641-s3H is used during this measurement.
Table 244 • JTAG Programming (Fabric Only)
M2S/M2GL
Device
Image size Bytes
302672
Program
22
Verify
10
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
568784
28
18
025
1223504
2424832
2418896
3645968
6139184
51
26
050
66
54
060
77
54
090
113
155
126
193
150
DS0128 Datasheet Revision 11.0
94
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 245 • JTAG Programming (eNVM Only)
M2S/M2GL
Device
Image size Bytes Program
Verify
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
137536
274816
274816
278528
268480
544496
544496
39
4
78
9
78
9
84
8
76
8
154
155
15
15
Table 246 • JTAG Programming (Fabric and eNVM)
M2S/M2GL
Device
Image size Bytes Program Verify
Unit
005
439296
59
11
Sec
Sec
Sec
Sec
Sec
Sec
Sec
010
842688
107
120
162
158
266
316
20
025
1497408
2695168
2686464
4190208
6682768
35
050
59
060
70
090
147
231
150
Table 247 • 2 Step IAP Programming (Fabric Only)
M2S/M2GL
Device
Image size Bytes Authenticate Program Verify Unit
005
302672
4
17
23
33
52
61
84
132
6
Sec
Sec
Sec
Sec
Sec
Sec
Sec
010
568784
7
12
23
40
50
73
120
025
1223504
2424832
2418896
3645968
6139184
14
29
39
60
100
050
060
090
150
DS0128 Datasheet Revision 11.0
95
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 248 • 2 Step IAP Programming (eNVM Only)
M2S/M2GL
Device
Image size Bytes Authenticate Program Verify Unit
005
010
025
050
060
090
150
137536
274816
274816
278528
268480
544496
544496
2
37
5
Sec
Sec
Sec
Sec
Sec
Sec
Sec
4
76
11
10
9
4
78
3
85
5
76
22
43
44
10
10
152
153
Table 249 • 2 Step IAP Programming (Fabric and eNVM)
M2S/M2GL
Device
Image size Bytes
439296
Authenticate Program Verify Unit
005
6
56
11
Sec
Sec
Sec
Sec
Sec
Sec
Sec
010
842688
11
19
32
43
68
109
100
113
136
137
236
286
21
025
1497408
2695168
2686464
4190208
6682768
32
050
48
060
70
090
115
162
150
Table 250 • SmartFusion2 Cortex-M3 ISP Programming (Fabric Only)
M2S/M2GL
Device
Image size
Bytes
Authenticate
Program
19
Verify
8
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
302672
6
568784
10
21
39
44
66
108
26
14
1223504
2424832
2418896
3645968
6139184
39
29
60
50
65
54
90
79
140
128
Table 251 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program
Verify
Unit
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
137536
274816
274816
278528
268480
544496
3
42
82
82
80
80
157
4
4
7
4
8
4
8
6
8
10
15
DS0128 Datasheet Revision 11.0
96
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 251 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) (continued)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program
10 158
Verify
Unit
150
544496
15
Sec
Table 252 • SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program
Verify
11
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
439296
9
61
842688
15
26
43
48
75
117
107
121
141
143
244
296
21
1497408
2695168
2686464
4190208
6682768
35
55
60
91
141
Table 253 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates
(Fabric Only)
Auto
Programming
Programming
Auto Update Recovery
M2S/M2GL
Device
100 kHz
47
25 MHz
27
12.5 MHz
Unit
Sec
Sec
Sec
005
010
025
050
060
090
150
28
35
41
77
35
150
331
42
Not Supported Not Supported Sec
291
427
708
83
82
Sec
Sec
Sec
109
157
108
160
1. Auto Programming in 050 device is done through SC_SPI, and SPI CLK is set
to 6.25 MHz.
Table 254 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates
(eNVM Only)
Auto
Programming
Programming
Auto Update Recovery
M2S/M2GL
Device
100 kHz
41
25 MHz
48
12.5 MHz
Unit
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
49
87
86
86
87
87
85
85
Not Supported Not Supported
78
86
86
154
162
162
DS0128 Datasheet Revision 11.0
97
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 254 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates
(eNVM Only) (continued)
Auto
Programming
Programming
100 kHz
161
Auto Update Recovery
M2S/M2GL
Device
25 MHz
12.5 MHz
Unit
150
161
161
Sec
Table 255 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates
(Fabric and eNVM)
Auto
Programming
Programming
Recovery
Auto Update
M2S/M2GL
Device
100 kHz
47
25 MHz
12.5 MHz
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
005
010
025
050
060
090
150
005
010
025
050
060
090
150
27
28
77
35
35
150
331
291
427
708
41
42
41
Not Supported
Not Supported
83
82
109
108
157
160
48
49
86
87
87
87
85
86
85
Not Supported
Not Supported
78
86
86
154
161
87
162
162
161
161
67
66
161
229
112
368
582
867
113
113
120
121
Not Supported
Not Supported
161
261
309
158
260
310
1. Auto Programming in 050 device is done through SC_SPI, and SPI CLK is set to 6.25
MHz.
DS0128 Datasheet Revision 11.0
98
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the programming times in worst-case conditions when TJ = 100 °C, VDD = 1.14 V.
External SPI flash part# AT25DF641-s3H is used during this measurement.
Table 256 • JTAG Programming (Fabric Only)
Image size
M2S/M2GL Device
Bytes
Program
Verify
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
302672
568784
1223504
2424832
2418896
3645968
6139184
44
10
50
18
73
26
88
54
99
54
135
177
126
193
Table 257 • JTAG Programming (eNVM Only)
Image size
M2S/M2GL Device
Bytes
Program
61
Verify
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
137536
274816
274816
2,78,528
268480
544496
544496
4
100
9
100
9
106
98
8
8
176
177
15
15
Table 258 • JTAG Programming (Fabric and eNVM)
Image size
M2S/M2GL Device
Bytes
Program
71
Verify
11
Unit
005
010
025
050
060
090
150
439296
842688
1497408
2695168
2686464
4190208
6682768
Sec
Sec
Sec
Sec
Sec
Sec
Sec
129
20
142
35
184
59
180
70
288
147
231
338
DS0128 Datasheet Revision 11.0
99
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 259 • 2 Step IAP Programming (Fabric Only)
Image size
M2S/M2GL Device Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
302672
4
39
6
Sec
Sec
Sec
Sec
Sec
Sec
Sec
568784
7
45
12
23
40
50
73
120
1223504
2424832
2418896
3645968
6139184
14
29
39
60
100
55
74
83
106
154
Table 260 • 2 Step IAP Programming (eNVM Only)
Image size
M2S/M2GL Device Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
137536
274816
274816
2,78,528
268480
544496
544496
2
59
5
Sec
Sec
Sec
Sec
Sec
Sec
Sec
4
98
11
10
9
4
100
107
98
3
5
22
43
44
10
10
174
175
Table 261 • 2 Step IAP Programming (Fabric and eNVM)
Image size
M2S/M2GL Device Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
439296
6
78
11
Sec
Sec
Sec
Sec
Sec
Sec
Sec
842688
11
19
32
43
68
109
122
135
158
159
258
308
21
1497408
2695168
2686464
4190208
6682768
32
48
70
115
162
DS0128 Datasheet Revision 11.0
100
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 262 • SmartFusion2 Cortex-M3 ISP Programming (Fabric Only)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
302672
6
41
8
Sec
Sec
Sec
Sec
Sec
Sec
Sec
568784
10
21
39
44
66
108
48
14
29
50
54
79
128
1223504
2424832
2418896
3645968
6139184
61
82
87
112
162
Table 263 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
137536
274816
274816
2,78,528
268480
544496
544496
3
64
4
Sec
Sec
Sec
Sec
Sec
Sec
Sec
4
104
104
102
102
179
180
7
4
8
4
8
6
8
10
10
15
15
Table 264 • SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM)
M2S/M2GL
Device
Image size
Bytes
Authenticate Program Verify Unit
005
010
025
050
060
090
150
439296
9
83
11
Sec
Sec
Sec
Sec
Sec
Sec
Sec
842688
15
26
43
48
75
117
129
143
163
165
266
318
21
35
55
60
91
141
1497408
2695168
2686464
4190208
6682768
DS0128 Datasheet Revision 11.0
101
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 265 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric
Only)
Auto Programming Auto Update Programming Recovery
M2S/M2GL Device 100 kHz
25 MHz
49
12.5 MHz
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
69
50
57
63
99
57
150
551
313
449
730
64
Not Supported Not Supported
105
131
179
104
130
183
1. Auto programming in 050 device is done through SC_SPI, and SPI CLK is set to 6.25 MHz.
Table 266 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (eNVM
Only)
Auto Programming Auto Update Programming Recovery
M2S/M2GL Device 100 kHz
25 MHz
70
12.5 MHz
71
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
63
108
109
107
100
176
183
109
109
107
108
Not Supported Not Supported
108
184
183
108
184
183
Table 267 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric and
eNVM)
Auto Programming Auto Update Programming Recovery
M2S/M2GL Device 100 kHz
25 MHz
89
12.5 MHz
88
Unit
Sec
Sec
Sec
Sec
Sec
Sec
Sec
005
010
025
050
060
090
150
109
183
251
134
390
604
889
135
135
142
143
Not Supported Not Supported
183
283
331
180
282
332
DS0128 Datasheet Revision 11.0
102
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.14 Math Block Timing Characteristics
The fundamental building block in any digital signal processing algorithm is the multiply-accumulate
function. Each IGLOO2 and SmartFusion2 SoC math block supports 18×18 signed multiplication, dot
product, and built-in addition, subtraction, and accumulation units to combine multiplication results
efficiently. The following table lists the math blocks with all registers used in worst commercial-case
conditions when TJ = 85 °C, VDD = 1.14 V.
Table 268 • Math Blocks with all Registers Used
–1
–Std
Max
Parameter
Symbol
TMISU
Min
Max
Min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Input, control register setup time
Input, control register hold time
CDIN input setup time
CDIN input hold time
0.149
1.68
0.176
1.976
0.218
0.094
TMIHD
TMOCDINSU 0.185
TMOCDINHD 0.08
Synchronous reset/enable setup time TMSRSTENSU –0.419
Synchronous reset/enable hold time TMSRSTENHD 0.011
–0.493
0.013
0
Asynchronous reset removal time
Asynchronous reset recovery time
Output register clock to out delay
CLK minimum period
TMARSTREM
TMARSTREC 0.088
TMOCQ
TMCLKMP
0
0.104
0.232
0.273 ns
ns
2.245
2.641
The following table lists the math blocks with input bypassed and output registers used in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 269 • Math Block with Input Bypassed and Output Registers Used
–1
Max Min
2.699
–Std
Parameter
Symbol
TMOSU
TMOHD
Min
Max Unit
Output register setup time
Output register hold time
CDIN input setup time
CDIN input hold time
2.294
1.68
ns
1.976
0.136
–0.522
–0.493
0.013
0
ns
TMOCDINSU 0.115
TMOCDINHD –0.444
ns
ns
Synchronous reset/enable setup time TMSRSTENSU –0.419
Synchronous reset/enable hold time TMSRSTENHD 0.011
ns
ns
Asynchronous reset removal time
Asynchronous reset recovery time
Output register clock to out delay
CLK minimum period
TMARSTREM
TMARSTREC 0.014
TMOCQ
TMCLKMP
0
ns
ns
0.017
0.232
0.273 ns
ns
2.179
2.563
DS0128 Datasheet Revision 11.0
103
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the math blocks with input register used and output in bypass mode in worst
commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.
Table 270 • Math Block with Input Register Used and Output in Bypass Mode
–1
Max
–Std
Max
Parameter
Symbol
TMISU
Min
Min
Unit
ns
Input register setup time
Input register hold time
0.149
0.185
0.176
0.218
0.094
TMIHD
ns
Synchronous reset/enable setup time TMSRSTENSU 0.08
Synchronous reset/enable hold time TMSRSTENHD –0.012
ns
–0.014
–0.005
0.104
ns
Asynchronous reset removal time
Asynchronous reset recovery time
Input register clock to output delay
CDIN to output delay
TMARSTREM –0.005
TMARSTREC 0.088
TMICQ
ns
ns
2.52
2.964 ns
2.295 ns
TMCDIN2Q
1.951
The following table lists the math blocks with input and output in bypass mode in worst commercial-case
conditions when TJ = 85 °C, VDD = 1.14 V.
Table 271 • Math Block with Input and Output in Bypass Mode
–1
–Std
Max
Parameter
Symbol
TMIQ
Max
2.568
1.951
Unit
ns
Input to output delay
CDIN to output delay
3.022
2.295
TMCDIN2Q
ns
2.3.15 Embedded NVM (eNVM) Characteristics
The following table lists the eNVM read performance in worst-case conditions when VDD = 1.14 V,
VPPNVM = VPP = 2.375 V.
Table 272 • eNVM Read Performance
Operating Temperature Range
–Std –1 –Std –1
–55 °C to 125 °C –40 °C to 100 °C 0 °C to 85 °C
25 25 25 25 25 25
Symbol
TJ
Description
–1
–Std Unit
Junction temperature range
°C
FMAXREAD
eNVM maximum read
frequency
MHz
The following table lists the eNVM page programming in worst-case conditions when VDD = 1.14 V,
VPPNVM = VPP = 2.375 V.
Table 273 • eNVM Page Programming
Operating Temperature Range
–Std –1 –Std –1
–55 °C to 125 °C –40 °C to 100 °C
40 40 40 40
Symbol
TJ
Description
–1
–Std Unit
Junction temperature range
eNVM page programming time
0 °C to 85 °C
40
°C
TPAGEPGM
40 ms
DS0128 Datasheet Revision 11.0
104
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.16 SRAM PUF
For more details on static random-access memory (SRAM) physical unclonable functions (PUF)
services, see AC434: Using SRAM PUF System Service in SmartFusion2 Application Note.
The following table lists the SRAM PUF in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 274 • SRAM PUF
PUF Off
Max
PUF On
Max
Service
Typ
Typ
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Create activation code
Delete activation code
Create intrinsic keycode
Create extrinsic keycode
Get number of keys
Export (Kc0, Kc1)
Export 2 keycodes
Export 4 keycodes
Export 8 keycodes
Export 16 keycodes
Import (Kc0, Kc1)
Import 2 keycodes
Import 4 keycodes
Import 8 keycodes
Import 16 keycodes
Delete keycode
709.1
746.4
754.4
762.5
1329.3
656.6
656.6
1.3
1399.3
691.1
691.1
1.4
1414.1
698.5
698.5
1.4
1429.3
706.0
706.0
1.4
998.0
2020.2
3065.7
5101.0
9212.1
39.7
1050.5
2126.5
3227.0
5369.5
9697.0
41.8
1061.7
2149.2
3261.3
5426.6
9800.1
42.2
1073.1
2172.3
3296.4
5485.0
9905.5
42.7
50.1
52.7
53.3
53.9
60.6
63.8
64.5
65.2
80.9
85.1
86.1
87.0
123.8
552.5
31.4
130.4
581.6
33.0
131.7
587.8
33.4
133.2
594.1
33.7
Fetch key
Fetch ecc key
20.0
21.1
21.3
21.5
Get seed
2.0
2.1
2.2
2.2
DS0128 Datasheet Revision 11.0
105
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.17 Non-Deterministic Random Bit Generator (NRBG)
Characteristics
For more information about NRBG, see AC407: Using NRBG Services in SmartFusion2 and IGLOO2
Devices Application Note. The following table lists the NRBG in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 275 • Non-Deterministic Random Bit Generator (NRBG)
Conditions
Prediction Additional
Service
Timing
Unit
Resistance Input
Instantiate
85
ms
OFF
OFF
OFF
OFF
ON
X
Generate
4.5 ms + (6.25 us/byte x No. of Bytes)
6.0 ms + (6.25 us/byte x No. of Bytes)
7.0 ms + (6.25 us/byte x No. of Bytes)
47
0
(after Instantiate)1
64
128
X
Generate
ms
(after Instantiate)
Generate
0.5 ms + (6.25 us/byte x No. of Bytes)
2.0 ms + (6.25 us/byte x No. of Bytes)
3.0 ms + (6.25 us/byte x No. of Bytes)
43
OFF
OFF
OFF
ON
0
(subsequent)1
64
128
X
Generate
ms
(subsequent)
Reseed
40
ms
ms
ms
ms
ms
Uninstantiate
Reset
0.16
0.10
20
Self test
First time after power-up
Subsequent
6
1. If PUF_OFF, generate will incur additional PUF delay time for consecutive service calls.
2.3.18 Cryptographic Block Characteristics
For more information about cryptographic block and associated services, see AC410: Using AES System
Services in SmartFusion2 and IGLOO2 Devices Application Note and AC432: Using SHA-256 System
Services in SmartFusion2 and IGLOO2 Devices Application Note.
The following table lists the cryptographic block characteristics in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 276 • Cryptographic Block Characteristics
Service
Conditions
Timing Unit
Any service
First certificate check penalty at boot 11.5
ms
AES128/256
100 blocks up to 64k blocks
700
kbps
(encoding / decoding)1
DS0128 Datasheet Revision 11.0
106
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 276 • Cryptographic Block Characteristics (continued)
Service
Conditions
Timing Unit
SHA256
512 bits
540
780
950
1140
820
890
930
980
1.8
25
kbps
kbps
kbps
kbps
kbps
kbps
kbps
kbps
ms
1024 bits
2048 bits
24 kbits
HMAC
512 bytes
1024 bytes
2048 bytes
24 kbytes
KeyTree
Challenge-response
PUF = OFF
PUF = ON
ms
7
ms
ECC point multiplication
ECC point addition
590
8
ms
ms
1. Using cypher block chaining (CBC) mode.
2.3.19 Crystal Oscillator
The following table describes the electrical characteristics of the crystal oscillator in the IGLOO2 FPGA
and SmartFusion2 SoC FPGAs.
Table 277 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz)
Parameter
Symbol
FXTAL
Min
Typ
Max
Unit
MHz
%
Condition
Operating frequency
Accuracy
20
ACCXTAL
0.0047
0.0058
005, 010, 025, 050, 060,
and 090 devices
%
150 devices
Output duty cycle
CYCXTAL
49–51 47–53
%
Output period jitter (peak to
peak)
JITPERXTAL
200
300
ps
Output cycle to cycle jitter (peak JITCYCXTAL
to peak)
200
300
ps
010, 025, 050, and 060
devices
250
250
1.5
410
550
ps
150 devices
ps
005 and 090 devices
Operating current
IDYNXTAL
mA
010, 050, and 060
devices
1.65
mA
005, 025, 090, and 150
devices
Input logic level high
Input logic level low
VIHXTAL
VILXTAL
0.9 VPP
V
V
0.1 VPP
DS0128 Datasheet Revision 11.0
107
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 277 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Startup time (with regard to
stable oscillator output)
SUXTAL
0.8
ms
005, 010, 025, and 050
devices
1.0
ms
090 and 150 devices
Table 278 • Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz)
Parameter
Symbol
FXTAL
Min
Typ
Max
Unit
MHz
%
Condition
Operating frequency
Accuracy
2
ACCXTAL
0.00105
0.003
050 devices
%
005, 010, 025, 090, and
150 devices
0.004
%
%
ns
060 devices
Output duty cycle
CYCXTAL
49–51 47–53
Output period jitter (peak to
peak)
JITPERXTAL
1
5
Output cycle to cycle jitter (peak JITCYCXTAL
to peak)
1
5
ns
Operating current
Input logic level high
Input logic level low
IDYNXTAL
VIHXTAL
VILXTAL
SUXTAL
0.3
mA
V
0.9 VPP
0.1 VPP
V
Startup time (with regard to
stable oscillator output)
4.5
5
ms
ms
ms
010 and 050 devices
005 and 025 devices
090 and 150 devices
7
Table 279 • Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz)
Parameter
Symbol
FXTAL
Min
Typ
Max
Unit
kHz
%
Condition
Operating frequency
Accuracy
32
ACCXTAL
0.004
0.005
005, 010, 025, 050, 060,
and 090 devices
%
%
ns
ns
150 devices
Output duty cycle
CYCXTAL
49–51 47–53
Output period jitter (peak to peak) JITPERXTAL
150
150
300
300
Output cycle to cycle jitter (peak to JITCYCXTAL
peak)
Operating current
IDYNXTAL
0.044
0.060
mA
mA
010 and 050 devices
005, 025, 060, 090, and
150 devices
Input logic level high
Input logic level low
VIHXTAL
VILXTAL
0.9 VPP
V
V
0.1 VPP
115
Startup time (with regard to stable SUXTAL
oscillator output)
ms
005, 025, 050, 090, and
150 devices
126
ms
010 devices
DS0128 Datasheet Revision 11.0
108
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.20 On-Chip Oscillator
The following tables describe the electrical characteristics of the available on-chip oscillators in the
IGLOO2 FPGAs and SmartFusion2 SoC FPGAs.
Table 280 • Electrical Characteristics of the 50 MHz RC Oscillator
Parameter
Symbol
F50RC
Typ
Max
Unit
MHz
%
Condition
Operating frequency
Accuracy
50
ACC50RC
1
4
050 devices
1
5
%
005, 025, and 060 devices
090 devices
1
6.3
%
1
7.1
%
010 and 150 devices
Output duty cycle
CYC50RC
JIT50RC
49–51
46.5–53.5
%
Output jitter (peak to peak)
Period Jitter
200
200
300
300
400
500
ps
ps
ps
005, 010, 050, and 060 devices
150 devices
025 and 090 devices
Cycle-to-Cycle Jitter
005 and 050 devices
010, 060, and 150 devices
025 and 090 devices
200
320
320
6.5
300
420
850
ps
ps
ps
Operating current
IDYN50RC
mA
Table 281 • Electrical Characteristics of the 1 MHz RC Oscillator
Parameter
Symbol
F1RC
Typ
1
Max
Unit
MHz
%
Condition
Operating frequency
Accuracy
ACC1RC
1
3
005, 010, 025, and 050 devices
060, and 150 devices
090 devices
1
4.5
5.6
%
1
%
Output duty cycle
CYC1RC
49–51 46.5–53.5
49-51 46.0-54.0
%
005, 010, 025, 050, 090 and 150 devices
060 devices
%
Output jitter (peak to peak) JIT1RC
Period Jitter
10
10
20
28
ns
ns
005, 010, 025, and 050 devices
060, 090 and 150 devices
Cycle-to-Cycle Jitter
10
10
10
0.1
20
35
45
ns
ns
ns
mA
µs
µs
005, 010, and 050 devices
025, 060, and 150 devices
090 devices
Operating current
Startup time
IDYN1RC
SU1RC
17
18
050, 090, and 150 devices
005, 010, and 025 devices
DS0128 Datasheet Revision 11.0
109
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.21 Clock Conditioning Circuits (CCC)
The following table lists the CCC/PLL specifications in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 282 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Specification
Parameter
Min
1
Typ
Max
200
200
400
Unit
Conditions
Clock conditioning circuitry input
frequency FIN_CCC
MHz All CCC
MHz 32 kHz capable CCC
MHz
0.032
0.078
Clock conditioning circuitry output
frequency FOUT_CCC
1
PLL VCO frequency2
500
1000
100
MHz
ps
Delay increments in programmable
delay blocks
75
Number of programmable values in
each programmable delay block
64
Acquisition time
70
1
100
16
µs
FIN >= 1 MHz
ms
FIN = 32 kHz
Input duty cycle (reference clock)
Internal Feedback
10
25
35
45
90
75
65
55
%
%
%
%
1 MHz ≤ FIN_CCC ≤ 25 MHz
25 MHz ≤ FIN_CCC≤ 100 MHz
100 MHz ≤ FIN_CCC ≤ 150 MHz
150 MHz ≤ FIN_CCC ≤ 200 MHz
External Feedback (CCC, FPGA,
Off-chip)
25
35
45
48
48
75
65
55
52
52
%
%
%
%
%
1 MHz ≤ FIN_CCC ≤ 25 MHz
25 MHz ≤ FIN_CCC ≤ 35 MHz
35 MHz ≤ FIN_CCC ≤ 50 MHz
050 devices FOUT ≤ 400 MHz
Output duty cycle
005, 010, and 025 devices
FOUT < 350 MHz
46
48
44
48
45
54
52
52
52
52
%
%
%
%
%
005, 010, and 025 devices
350 MHz ≤ Fout ≤ 400 MHz
060 and 090 devices
FOUT ≤ 100 MHz
060 and 090 devices
100 MHz ≤ FOUT ≤ 400 MHz
150 devices
FOUT ≤ 120 MHz
150 devices
120 MHz ≤ FOUT ≤ 400 MHz
Spread Spectrum Characteristics
Modulation frequency range
Modulation depth range
25
0
35
50
k
1.5
%
%
Modulation depth control
0.5
DS0128 Datasheet Revision 11.0
110
IGLOO2 FPGA and SmartFusion2 SoC FPGA
1. The minimum output clock frequency is limited by the PLL. For more information, see UG0449: SmartFusion2 and IGLOO2
Clocking Resources User Guide.
2. The PLL is used in conjunction with the Clock Conditioning Circuitry. Performance is limited by the CCC output frequency.
The following table lists the CCC/PLL jitter specifications in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 283 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter Specifications
CCC Output Maximum Peak-to-Peak Period Jitter FOUT_CCC
Parameter
Conditions/Package Combinations
Unit
10 FG484, 050
SSO = 0
0 < SSO <= 2
SSO <= 4 SSO <= 8 SSO <= 16
FG896/FG484/FCS325
Packages1
20 MHz to 100 MHz
100 MHz to 400 MHz
Max(110, ± 1% x
(1/FOUT_CCC))
Max(150, ± 1% x (1/FOUT_CCC))
Max(150, ± 1% x (1/FOUT_CCC))
ps
ps
Max(120, ± 1% x
(1/FOUT_CCC))
Max(170, ± 1% x
(1/FOUT_CCC))
025 FG484/FCS325
Package1
0 < SSO <=16
20 MHz to 74 MHz
74 MHz to 400 MHz
± 1% x (1/FOUT_CCC))
210
ps
ps
005 FG484 Package1 0 < SSO <=16
20 MHz to 53 MHz
53 MHz to 400 MHz
± 1% x (1/FOUT_CCC))
270
ps
ps
090 FG676 and FC325 0 < SSO <=16
Package1
20 MHz to 100 MHz
100 MHz to 400 MHz
± 1% x (1/FOUT_CCC))
150
ps
ps
060 FG676 Package1 0 < SSO <=16
20 MHz to 100 MHz
± 1% x (1/FOUT_CCC
150
)
ps
100 MHz to 400 MHz
150 FC1152 Package1 0 < SSO <=16
20 MHz to 100 MHz
100 MHz to 400 MHz
± 1% x (1/FOUT_CCC))
120
ps
ps
1. SSO data is based on LVCMOS 2.5 V MSIO and/or MSIOD bank I/Os.
DS0128 Datasheet Revision 11.0
111
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.22 JTAG
Table 284 • JTAG 1532 for 005, 010, 025, and 050 Devices
Unit
005
010
025
050
Parameter
Symbol
–1
–Std
–1
–Std
–1
–Std
–1
–Std
Clock to Q
(data out)
TTCK2Q
7.47
8.79
7.73
9.09
7.75
9.12
7.89
9.28
ns
ns
Reset to Q
(data out)
TRSTB2Q
7.65
9
6.43
–0.69
2.38
7.56
–0.59
2.8
6.13
–0.67
2.42
7.21
7.40
–0.30
2.09
8.70
Test data input TDISU
setup time
–1.05 –0.89
2.38 2.8
–0.57
2.85
–0.25 ns
Test data input TDIHD
hold time
2.45
0.33
ns
ns
Test mode
select setup
time
TTMSSU
–0.73 –0.62
–1.03
1.43
–1.21
1.68
–1.1
1.93
–0.94
2.27
0.28
0.16
Test mode
select hold
time
TTMDHD
1.36
1.6
0.19
ns
ResetB
removal time
TTRSTREM
TTRSTREC
FTCKMAX
–0.77 –0.65
–0.76 –0.65
–1.08
–1.07
–0.92
–0.91
–1.33
–1.34
–1.13
–1.14
–0.45
–0.45
–0.38 ns
–0.38 ns
ResetB
recovery time
TCK
maximum
frequency
25
21.25
25
21.25
25
21.25
25.00
21.25 MHz
Table 285 • JTAG 1532 for 060, 090, and 150 Devices
060
090
150
–Std
Parameter
Symbol
–1
–Std
9.86
10.04
–1
–1
–Std
–1
Unit
Clock to Q (data out)
TTCK2Q
8.38
8.54
–1.18
8.96
7.75
–1.31
10.54
9.12
8.66
8.79
10.19
10.34
–0.82
ns
ns
Reset to Q (data out) TRSTB2Q
Test data input setup
time
TDISU
–1.11
–0.96
ns
ns
ns
ns
Test data input hold
time
TDIHD
2.52
–0.97
1.7
2.97
–0.83
2
2.68
–1.02
1.67
3.15
–0.87
1.96
2.57
3.02
–0.45
1.2
Test mode select setup TTMSSU
time
–0.53
1.02
Test mode select hold TTMDHD
time
ResetB removal time
TTRSTREM
–1.21
–1.21
25
–1.03
–1.03
21.25
–0.76
–0.77
25
–0.65
–0.65
21.25
–1.03
–1.03
25
–0.88
–0.88
21.25
ns
ns
ResetB recovery time TTRSTREC
TCK maximum
frequency
FTCKMAX
MHz
2.3.23 System Controller SPI Characteristics
DS0128 Datasheet Revision 11.0
112
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the system controller characteristics in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 286 • System Controller SPI Characteristics for All Devices
Symbol
sp1
Description
Conditions
Min
20
Typ
Unit
ns
SC_SPI_SCK minimum period
SC_SPI_SCK minimum pulse width high
SC_SPI_SCK minimum pulse width low
sp2
10
ns
sp3
10
ns
sp41
SC_SPI_SCK, SC_SPI_SDO,
SC_SPI_SS rise time
(10%–90%) 1
I/O configuration: LVTTL 3.3 V–
20 mA
AC loading: 35 pF
Test conditions: Typical voltage,
25 °C
1.239
1.245
ns
sp51
SC_SPI_SCK, SC_SPI_SDO,
SC_SPI_SS fall time
(10%–90%) 1
I/O configuration: LVTTL 3.3 V–
20 mA
AC loading: 35 pF
Test conditions: Typical voltage,
25 °C
ns
sp6
sp7
Data from master (SC_SPI_SDO) setup
time
160
160
ns
ns
Data from master (SC_SPI_SDO) hold
time
sp8
sp9
SC_SPI_SDI setup time
SC_SPI_SDI hold time
20
20
ns
ns
1. For specific Rise/Fall Times, board design considerations and detailed output buffer resistances, use the corresponding IBIS
models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. Use
the supported I/O Configurations for the System Controller SPI in the following table.
Table 287 • Supported I/O Configurations for System Controller SPI (for MSIO Bank
Only)
Voltage Supply
3.3 V
I/O Drive Configuration
Unit
mA
mA
mA
mA
mA
20
16
12
8
2.5 V
1.8 V
1.5 V
1.2 V
4
DS0128 Datasheet Revision 11.0
113
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.24 Power-up to Functional Times
The following table lists the SmartFusion2 power-up to functional times in worst-case industrial
conditions when TJ = 100 °C, VDD = 1.14 V.
Table 288 • Power-up to Functional Times for SmartFusion2
Maximum Power-up to Functional Time for
SmartFusion2 (uS)
Symbol
From
To
Description 005
010
025
050
060
090
150
TPOR2OUT
POWER_ON Output
Fabric to
647
500
531
483
474
524
647
_RESET_N available at output
I/O
TPOR2MSSRST POWER_ON MSS_RESE Fabric to
644
3.6
497
3.6
528
3.6
480
3.4
468
4.9
518
4.8
641
4.8
_RESET_N T_N_M2F
MSS
TMSSRST2OUT MSS_RESET Output
MSS to
_N_M2F
available at output
I/O
TVDD2OUT
VDD
Output
available at minimum
I/O
VDD at its
3096 2975
2476 2487
3093 2972
3012 2959 2869
2496 2486 2406
3008 2956 2864
2992 3225
2563 2602
2987 3220
threshold
level to
output
TVDD2POR
VDD
POWER_O VDD at its
N_RESET_ minimum
N
threshold
level to
fabric
TVDD2MSSRST VDD
MSS_RESE VDD at its
T_N_M2F
minimum
threshold
level to MSS
TVDD2WPU
DEVRST_N DDRIO
Inbuf weak to Inbuf weak
pull pull
DEVRST_N 2500 2487
2509 2475 2507
2510 2478 2517
2493 2458 2486
2519 2617
2525 2620
2499 2595
DEVRST_N MSIO Inbuf DEVRST_N 2504 2491
weak pull
to Inbuf weak
pull
DEVRST_N MSIOD
DEVRST_N 2479 2468
Inbuf weak to Inbuf weak
pull
pull
Note: For more information about power-up times, see UG0331: SmartFusion2 Microcontroller Subsystem
User Guide.
DS0128 Datasheet Revision 11.0
114
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 17 • Power-up to Functional Timing Diagram for SmartFusion2
'(9567B1
933ꢀ9'',[
9''
5&26&Bꢅꢆ0+]
7ULVWDWH
,1%8)
+LJKꢇ=
79''ꢄ:38
,1%8)ꢁ:($.ꢁ38//ꢁ
ꢂ06,2ꢀ06,2'ꢀ''5,2ꢃꢁꢁ
79''ꢄ325
79''ꢄ066567
79''ꢄ287
7066567ꢄ287
7325ꢄ066567
32:(5B21B5(6(7B1
066B5(6(7B1B0ꢄ)
7325ꢄ287
7ULVWDWH
+LJKꢇ=
287%8)
The following table lists the IGLOO2 power-up to functional times in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 289 • Power-up to Functional Times for IGLOO2
Maximum Power-up to Functional Time for IGLOO2
(uS)
Symbol
From
To
Description
005
010
025
050
060
090
150
TPOR2OUT POWER_ON Output
_RESET_N available at
I/O
Fabric to
output
114
114
114
113
114
114
114
TVDD2OUT VDD
Output
available at
I/O
VDD at its
minimum
threshold level
to output
2587 2600
2474 2486
2607 2558 2591 2600 2699
2493 2445 2477 2486 2585
TVDD2POR VDD
POWER_ON_ VDD at its
RESET_N
minimum
threshold level
to fabric
TVDD2WPU DEVRST_N DDRIO Inbuf DEVRST_N to 2500 2487
2509 2475 2507 2519 2617
2510 2478 2517 2525 2620
2493 2458 2486 2499 2595
weak pull
Inbuf weak pull
DEVRST_N MSIO Inbuf
weak pull
DEVRST_N to 2504 2491
Inbuf weak pull
DEVRST_N MSIOD Inbuf DEVRST_N to 2479 2468
weak pull Inbuf weak pull
Note: For more information about power-up times, see UG0448: IGLOO2 FPGA High Performance Memory
Subsystem User Guide.
DS0128 Datasheet Revision 11.0
115
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 18 • Power-up to Functional Timing Diagram for IGLOO2
'(9567B1
933ꢀ9'',[
9''
5&26&Bꢅꢆ0+]
7ULVWDWH
,1%8)
+LJKꢇ=
79''ꢄ:38
,1%8)ꢁ:($.ꢁ38//ꢁ
ꢂ06,2ꢀ06,2'ꢀ''5,2ꢃꢁꢁ
79''ꢄ325
32:(5B21B5(6(7B1
7325ꢄ287
79''ꢄ287
7ULVWDWH
+LJKꢇ=
287%8)
2.3.25 DEVRST_N Characteristics
Table 290 • DEVRST_N Characteristics for All Devices
Parameter
Symbol
Max
1
Unit
us
DEVRST_N ramp rate
TRAMPDEVRSTN
DEVRST_N cycling rate FMAXPDEVRSTN
100
kHz
2.3.26 DEVRST_N to Functional Times
The following table lists the SmartFusion2 DEVRST_N to functional times in worst-case industrial
conditions when TJ = 100 °C, VDD = 1.14 V.
Table 291 • DEVRST_N to Functional Times for SmartFusion2
Maximum Power-up to Functional Time for
SmartFusion2 (uS)
Symbol
From
To
Description 005
010
025
050
060
090
150
TPOR2OUT
POWER_ON Output
Fabric to
518
501
527
521
422
419
694
_RESET_N available at output
I/O
TPOR2MSSRST
TMSSRST2OUT
POWER_ON MSS_RESE Fabric to
515
3.5
497
3.5
524
3.5
518
3.3
417
4.8
414
4.8
689
4.8
_RESET_N T_N_M2F
MSS
MSS_RESET Output
MSS to
_N_M2F
available at output
I/O
TDEVRST2OUT
DEVRST_N Output
VDD at its
706
768
715
691
641
635
871
available at minimum
I/O
threshold
level to
output
DS0128 Datasheet Revision 11.0
116
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 291 • DEVRST_N to Functional Times for SmartFusion2 (continued)
Maximum Power-up to Functional Time for
SmartFusion2 (uS)
Symbol
From
DEVRST_N POWER_O
N_RESET_ minimum
To
Description 005
010
025
050
060
090
150
TDEVRST2POR
VDD at its
233
289
216
213
237
234
219
N
threshold
level to
fabric
TDEVRST2MSSRST DEVRST_N MSS_RESE VDD at its
702
765
712
688
636
630
866
T_N_M2F minimum
threshold
level to MSS
TDEVRST2WPU
DEVRST_N DDRIO
DEVRST_N 208
202
202
202
197
197
197
193
193
193
216
216
216
215
215
215
215
215
215
Inbuf weak to Inbuf weak
pull
pull
DEVRST_N MSIO Inbuf DEVRST_N 208
weak pull
to Inbuf weak
pull
DEVRST_N MSIOD
DEVRST_N 208
pull
Inbuf weak to Inbuf weak
pull
Figure 19 • DEVRST_N to Functional Timing Diagram for SmartFusion2
9''ꢀ933ꢀ9'',[
5&26&Bꢅꢆ0+]
'(9567B1
7ULVWDWH
+LJKꢇ=
,1%8)
,1%8)ꢁ:($.ꢁ38//ꢁ
ꢂ06,2ꢀ06,2'ꢀ''5,2ꢃꢁꢁ
7'(9567ꢄ325
7066567ꢄ287
7325ꢄ066567
32:(5B21B5(6(7B1
066B5(6(7B1B0ꢄ)
7'(9567ꢄ066567
7'(9567ꢄ287
7325ꢄ287
7ULVWDWH
+LJKꢇ=
287%8)
DS0128 Datasheet Revision 11.0
117
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the IGLOO2 DEVRST_N to functional times in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 292 • DEVRST_N to Functional Times for IGLOO2
Maximum Power-up to Functional Time for IGLOO2
(uS)
Symbol
From
To
Description 005
010
025
050
060
090
150
TPOR2OUT
POWER_ON Output
_RESET_N available at output
I/O
Fabric to
114
314
116
113
113
115
115
114
TDEVRST2OUT DEVRST_N Output
VDD at its
353
238
314
201
307
195
343
230
341
229
341
227
available at minimum
I/O
threshold
level to
output
TDEVRST2POR DEVRST_N POWER_O VDD at its
N_RESET_ minimum
200
N
threshold
level to
fabric
TDEVRST2WPU DEVRST_N DDRIO
DEVRST_N 208
202
202
202
197
197
197
193
193
193
216
216
216
215
215
215
215
215
215
Inbuf weak to Inbuf weak
pull
pull
DEVRST_N MSIO Inbuf DEVRST_N 208
weak pull
to Inbuf weak
pull
DEVRST_N MSIOD
DEVRST_N 208
pull
Inbuf weak to Inbuf weak
pull
DS0128 Datasheet Revision 11.0
118
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 20 • DEVRST_N to Functional Timing Diagram for IGLOO2
9''ꢀ933ꢀ9'',[
5&26&Bꢅꢆ0+]
'(9567B1
7ULVWDWH
,1%8)
+LJKꢇ=
,1%8)ꢁ:($.ꢁ38//ꢁ
ꢂ06,2ꢀ06,2'ꢀ''5,2ꢃꢁꢁ
7'(9567ꢄ325
7'(9567ꢄ287
32:(5B21B5(6(7B1
287%8)
7325ꢄ287
7ULVWDWH
+LJKꢇ=
2.3.27 Flash*Freeze Timing Characteristics
The following table lists the Flash*Freeze entry and exit times in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 293 • Flash*Freeze Entry and Exit Times
Entry/Exit
Timing
FCLK = 3 MHz
Entry/Exit Timing
FCLK = 100MHz
005, 010, 025,
060, 090, and
Parameter
Symbol
150
050
All Devices
Unit
Conditions
Entry time
TFF_ENTRY 160
150
200
100
120
320
eNVM and MSS/HPMS PLL =
ON
μs
215
430
140
190
eNVM and MSS/HPMS PLL=
OFF
μs
μs
Exit time with
respect to the
MSS PLL Lock
TFF_EXIT
100
136
eNVM and MSS/HPMS PLL =
ON during F*F
eNVM = ON and MSS/HPMS
PLL = OFF during F*F and
MSS/HPMS PLL turned back
on at exit
μs
200
200
200
200
285
285
eNVM and MSS/HPMS PLL =
OFF during F*F and both are
turned back on at exit
μs
μs
eNVM = OFF and MSS/HPMS
PLL = ON during F*F and
eNVM turned back on at exit
DS0128 Datasheet Revision 11.0
119
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 293 • Flash*Freeze Entry and Exit Times (continued)
Entry/Exit
Entry/Exit Timing
FCLK = 100MHz
Timing
FCLK = 3 MHz
005, 010, 025,
060, 090, and
Parameter
Symbol
150
050
All Devices
Unit
Conditions
Exit time with
respect to the
fabric PLL lock1
TFF_EXIT
1.5
1.5
1.5
eNVM and MSS/HPMS PLL =
ON during F*F
ms
1.5
1.5
1.5
eNVM and MSS/HPMS PLL =
OFF during F*F and both are
turned back on at exit
ms
μs
μs
Exit time with
respect to the
fabric buffer
output
TFF_EXIT
21
65
15
55
21
65
eNVM and MSS/HPMS PLL =
ON during F*F
eNVM and MSS/HPMS PLL =
OFF during F*F and both are
turned back on at exit
1. PLL Lock Delay set to 1024 cycles (default).
2.3.28 DDR Memory Interface Characteristics
The following table lists the DDR memory interface characteristics in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 294 • DDR Memory Interface Characteristics
Supported Data Rate
Standard
DDR3
Min
667
667
50
Max
667
667
400
Unit
Mbps
Mbps
Mbps
DDR2
LPDDR
2.3.29 SFP Transceiver Characteristics
IGLOO2 and SmartFusion2 SerDes complies with small form-factor pluggable (SFP) requirements as
specified in SFP INF-80741. The following table provides the electrical characteristics.
The following table lists the SFP transceiver electrical characteristics in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 295 • SFP Transceiver Electrical Characteristics
Differential Peak-Peak Voltage
Pin
Direction
Output
Input
Min
1600
350
Max
2400
2400
Unit
mV
mV
RD+/-1
TD+/-2
1. Based on default SerDes transmitter settings for PCIe Gen1. Lower amplitudes are
available through programming changes to TX_AMP setting.
2. Based on Input Voltage Common-Mode (VICM) = 0 V. Requires AC Coupling.
DS0128 Datasheet Revision 11.0
120
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.30 SerDes Electrical and Timing AC and DC Characteristics
PCIe is a high-speed, packet-based, point-to-point, low-pin-count, serial interconnect bus. The IGLOO2
and SmartFusion2 SoC FPGAs has up to four hard high-speed serial interface blocks. Each SerDes
block contains a PCIe system block. The PCIe system is connected to the SerDes block.
The following table lists the transmitter parameters in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 296 • Transmitter Parameters
Symbol
Description
Min
Max
1.2
20
Unit
V
VTX-DIFF-PP
Differential swing (2.5 Gbps, 5.0 Gbps)
0.8
VTX-CM-AC-P Output common mode voltage (2.5 Gbps)
VTX-CM-AC-PP Output common mode voltage (5.0 Gbps)
VTX-RISE-FALL Rise and fall time (20% to 80%, 2.5 Gbps)
Rise and fall time (20% to 80%, 5.0 Gbps)
mV
mV
UI
100
0.125
0.15
80
UI
ZTX-DIFF-DC
LTX-SKEW
Output impedance–differential
120
Lane-to-lane TX skew within a SerDes block (2.5
Gbps)
500 ps + 2 UI ps
500 ps + 4 UI ps
dB
Lane-to-lane TX skew within a SerDes block (5.0
Gbps)
RLTX-DIFF
Return loss differential mode (2.5 Gbps)
–10
Return loss differential mode (5.0 Gbps)
0.05 GHz to 1.25 GHz
–10
–8
dB
dB
dB
1.25 GHz to 2.5 GHz
RLTX-CM
Return loss common mode (2.5 Gbps, 5.0 Gbps) –6
TX-LOCK-RST Transmit PLL lock time from reset
10
µs
VTX-AMP
100 mV setting
400 mV setting
800 mV setting
1200 mV setting
90
150
480
940
1400
mV
mV
mV
mV
320
660
950
DS0128 Datasheet Revision 11.0
121
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the receiver pa in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 297 • Receiver Parameters
Symbol
Description
Min
Typ
Max
Unit
VRX-IN-PP-CC
Differential input peak-to-peak sensitivity
(2.5 Gbps)
0.238
1.2
V
Differential input peak-to-peak sensitivity
(2.5 Gbps, de-emphasized)
0.219
0.300
0.300
1.2
1.2
1.2
V
V
V
Differential input peak-to-peak sensitivity
(5.0 Gbps)
Differential input peak-to-peak sensitivity
(5.0 Gbps, de-emphasized)
VRX-CM-AC-P
ZRX-DIFF-DC
REXT
Input common mode range (AC coupled)
Differential input termination
150
120
1,212
15
mV
80
100
External calibration resistor
1,188
1,200
CDR-LOCK-RST
RLRX-DIFF
CDR relock time from reset
µs
dB
Return loss differential mode (2.5 Gbps)
–10
–10
Return loss differential mode (5.0 Gbps)
0.05 GHz to 1.25 GHz
dB
1.25 GHz to 2.5 GHz
–8
–6
dB
dB
RLRX-CM
Return loss common mode (2.5 Gbps,
5.0 Gbps)
RX-CID1
CID limit PCIe Gen1/2
Signal detect limit
200
175
UI
VRX-IDLE-DET-DIFF-PP
65
mV
1. AC-coupled, BER = e-12, using synchronous clock.
Table 298 • SerDes Protocol Compliance
Protocol
Maximum Data Rate (Gbps)
–1
–Std
PCIe Gen 1
PCIe Gen 2
XAUI
2.5
Yes
Yes
Yes
Yes
Yes
Yes
5.0
3.125
3.2
Generic EPCS
Generic EPCS
2.5
Yes
DS0128 Datasheet Revision 11.0
122
IGLOO2 FPGA and SmartFusion2 SoC FPGA
The following table lists the SerDes reference clock AC specifications in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 299 • SerDes Reference Clock AC Specifications
Parameter
Symbol
FREFCLK
TRISE
Min
100
0.6
0.6
40
Max
160
4
Unit
MHz
V/ns
V/ns
%
Reference clock frequency
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock mismatch
Reference spread spectrum clock
TFALL
4
TCYC
60
MMREFCLK
SSCref
–300
0
300
5000
ppm
ppm
Table 300 • HCSL Minimum and Maximum DC Input Levels (Applicable to SerDes REFCLK Only)
Parameter
Symbol
Recommended DC Operating Conditions
VDDI 2.375 2.5
HCSL DC Input Voltage Specification
VI
HCSL Differential Voltage Specification
Min
Typ
Max
Unit
V
Supply voltage
DC Input voltage
2.625
2.625
0
V
Input common mode voltage
Input differential voltage
VICM
0.05
100
2.4
V
VIDIFF
1100
mV
Table 301 • HCSL Minimum and Maximum AC Switching Speeds (Applicable to SerDes REFCLK
Only)
Parameter
Symbol
HCSL AC Specifications
Maximum data rate (for MSIO I/O bank) FMAX
Min
Typ
Max
Unit
Mbps
350
HCSL Impedance Specifications
Termination resistance
Rt
100
2.3.31 SmartFusion2 Specifications
2.3.31.1 MSS Clock Frequency
The following table lists the maximum frequency for MSS main clock in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 302 • Maximum Frequency for MSS Main Clock
Symbol
Description
–1
–Std
Unit
M3_CLK
Maximum frequency for the MSS main clock 166
142
MHz
DS0128 Datasheet Revision 11.0
123
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2
2.3.31.2 SmartFusion2 Inter-Integrated Circuit (I C) Characteristics
This section describes the DC and switching of the IC interface. Unless otherwise noted, all output
characteristics given are for a 100 pF load on the pins. For timing parameter definitions, see Figure 21,
page 125.
The following table lists the I2C characteristics in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V
Table 303 • I2C Characteristics
Parameter
Symbol
Min
Typ
Max
Unit Conditions
Input low voltage
VIL
–0.3
0.8
V
V
V
See Single-Ended I/O Standards,
page 24 for more information. I/O
standard used for illustration: MSIO
bank–LVTTL 8 mA low drive.
Input high voltage
VIH
2
3.45
See Single-Ended I/O Standards,
page 24 for more information. I/O
standard used for illustration: MSIO
bank–LVTTL 8 mA low drive.
Hysteresis of schmitt
triggered inputs for VDDI
2 V
VHYS
0.05 × VDDI
See Table 28, page 23 for more
information.
>
Input current high
Input current low
Input rise time
IIL
IIH
Tir
10
10
µA
µA
See Single-Ended I/O Standards,
page 24 for more information.
See Single-Ended I/O Standards,
page 24 for more information.
1000 ns
Standard mode
Fast mode
300
300
300
0.4
ns
ns
ns
V
Input fall time
Tif
Standard mode
Fast mode
Maximum output voltage VOL
low (open drain) at 3 mA
sink current for VDDI > 2 V
See Single-Ended I/O Standards,
page 24 for more information. I/O
standard used for illustration: MSIO
bank–LVTTL 8 mA low drive.
Pin capacitance
Cin
10
pF
ns
ns
ns
ns
VIN = 0, f = 1.0 MHz
1
Output fall time from
VIHMin to VILMax1
tOF
21.04
5.556
19.887
5.218
VIHmin to VILMax, CLOAD = 400 pF
VIHmin to VILMax, CLOAD = 100 pF
VILMax to VIHmin, CLOAD = 400 pF
VILMax to VIHmin, CLOAD = 100 pF
1
Output rise time from
VILMax to VIHMin1
tOR
2,3
Output buffer maximum Rpull-up
pull-down resistance2, 3
50
2,4
Output buffer maximum Rpull-down
pull-up resistance2, 4
131.25
DS0128 Datasheet Revision 11.0
124
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 303 • I2C Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
400
100
Unit Conditions
Kbps Fast mode
Maximum data rate
DMAX
Kbps Standard mode
Pulse width of spikes
which must be
TFILT
50
ns
Fast mode
suppressed by the input
filter
1. These values are provided for MSIO Bank–LVTTL 8 mA Low Drive at 25 °C, typical conditions. For board design considerations
and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website:
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. These maximum values are provided for information only. Minimum output buffer resistance values depend on VDDIx, drive
strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the SoC Products Group website:
http://www.microsemi.com/soc/download/ibis/default.aspx.
3. R(PULL-DOWN-MAX) = (VOLspec)/IOLspec.
4. R(PULL-UP-MAX) = (VDDImax–VOHspec)/IOHspec.
The following table lists the I2C switching characteristics in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V
Table 304 • I2C Switching Characteristics
–1
Min
1
Std
Min
1
Parameter
Symbol
Unit
Low period of I2C_x_SCL TLOW
High period of I2C_x_SCL THIGH
PCLK cycles
PCLK cycles
PCLK cycles
PCLK cycles
PCLK cycles
PCLK cycles
PCLK cycles
1
1
START hold time
START setup time
DATA hold time
DATA setup time
STOP setup time
THD;STA
1
1
TSU;STA
THD;DAT
TSU;DAT
TSU;STO
1
1
1
1
1
1
1
1
Figure 21 • I2C Timing Parameter Definition
SDA
TRISE
tLOW
TFALL
SCL
tHIGH
tSU;STO
P
tSU;DAT
tSU;STA
tHD;DAT
tHD;STA
S
DS0128 Datasheet Revision 11.0
125
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.31.3 Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output
characteristics given are for a 35 pF load on the pins and all sequential timing characteristics are related
to SPI_x_CLK. For timing parameter definitions, see Figure 22, page 128.
The following table lists the SPI characteristics in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V
Table 305 • SPI Characteristics for All Devices
Symbol
Description
Min
Typ
Max Unit Conditions
SPIFMAX Maximum operating frequency
of SPI interface
20
MHz
sp1
sp2
sp3
sp4
SPI_[0|1]_CLK minimum period
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
SPI_[0|1]_CLK = PCLK/128
12
ns
ns
ns
µs
µs
µs
µs
24.1
48.2
0.1
0.19
0.39
0.77
SPI_[0|1]_CLK minimum pulse width high
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
SPI_[0|1]_CLK = PCLK/128
6
ns
ns
ns
µs
µs
µs
µs
12.05
24.1
0.05
0.095
0.195
0.385
SPI_[0|1]_CLK minimum pulse width low
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
SPI_[0|1]_CLK = PCLK/128
6
ns
ns
ns
µs
µs
µs
µs
ns
12.05
24.1
0.05
0.095
0.195
0.385
SPI_[0|1]_CLK, SPI_[0|1]_DO,
SPI_[0|1]_SS rise time (10%–
90%)1
2.77
I/O Configuration:
LVCMOS 2.5 V–
8 mA
AC loading: 35 pF
Test conditions:
Typical voltage,
25 °C
DS0128 Datasheet Revision 11.0
126
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 305 • SPI Characteristics for All Devices (continued)
Symbol
Description
Min
Typ
Max Unit Conditions
sp5
SPI_[0|1]_CLK, SPI_[0|1]_DO,
SPI_[0|1]_SS fall time (10%–
90%)1
2.906
ns
IO Configuration:
LVCMOS 2.5 V-8 mA
AC Loading: 35 pF
Test Conditions:
Typical Voltage,
25 °C
SPI master configuration (applicable for 005, 010, 025, and 050 devices)
sp6m
sp7m
sp8m
sp9m
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 8.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) – 2.5
12
2.5
SPI slave configuration (applicable for 005, 010, 025, and 050 devices)
sp6s
SPI_[0|1]_DO setup time2
(SPI_x_CLK_period/2) –
17.0
ns
sp7s
sp8s
sp9s
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) + 3.0
ns
ns
ns
2
7
SPI master configuration (applicable for 060, 090, and 150 devices)
sp6m
sp7m
sp8m
sp9m
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 7.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) – 9.5
15
-–2.5
SPI slave configuration (applicable for 060, 090, and 150 devices)
sp6s
SPI_[0|1]_DO setup time2
(SPI_x_CLK_period/2) –
16.0
ns
sp7s
sp8s
sp9s
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) - 3.5
ns
ns
ns
3
2.5
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS
models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx.
2. For allowable pclk configurations, see Serial Peripheral Interface Controller section in the UG0331: SmartFusion2 Microcontroller
Subsystem User Guide.
DS0128 Datasheet Revision 11.0
127
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Figure 22 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
SP1
SP4
SP5
SP3
SP2
90%
10%
50% 50%
50%
SPI_0_CLK
SPO = 0
10%
SPI_0_CLK
SPO = 1
90%
90%
SPI_0_SS
10%
SP4
10%
SP5
SP6
SP7
90%
90%
MSB
SP9
50%
50%
SPI_0_DO
SPI_0_DI
10%
10%
SP8
SP5
SP4
50%
50%
MSB
2.3.32 CAN Controller Characteristics
The following table lists the CAN controller characteristics in worst-case industrial conditions when TJ =
100 °C, VDD = 1.14 V.
Table 306 • CAN Controller Characteristics
Parameter
Description
–1
–Std
Unit
FCANREFCLK1
Internally sourced CAN reference
clock frequency
160
136
MHz
BAUDCANMAX
BAUDCANMIN
Maximum CAN performance baud
rate
1
1
Mbps
Mbps
Minimum CAN performance baud
rate
0.05
0.05
1. PCLK to CAN controller must be a multiple of 8 MHz.
2.3.33 USB Characteristics
The following table lists the USB characteristics in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 307 • USB Characteristics
Parameter
Description
–1
–Std
Unit
FUSBREFCLK Internally sourced USB reference clock 166
frequency
142
MHz
TUSBCLK
TUSBPD
TUSBSU
TUSBHD
USB clock period
16.66
9.0
6.0
0
16.66
9.0
6.0
0
ns
ns
ns
ns
Clock to USB data propagation delay
Setup time for USB data
Hold time for USB data
DS0128 Datasheet Revision 11.0
128
IGLOO2 FPGA and SmartFusion2 SoC FPGA
2.3.34 MMUART Characteristics
The following table lists the MMUART characteristics in worst-case industrial conditions when
TJ = 100 °C, VDD = 1.14 V.
Table 308 • MMUART Characteristics
Parameter
Description
–1
–Std
Unit
FMMUART_REF_CLK Internally sourced MMUART
reference clock frequency.
166
142
MHz
BAUDMMUARTTx
BAUDMMUARTRx
Maximum transmit baud rate
Maximum receive baud rate
10.375
10.375
8.875
8.875
Mbps
Mbps
2.3.35 IGLOO2 Specifications
2.3.35.1 HPMS Clock Frequency
The following table lists the maximum frequency for HPMS main clock in worst-case industrial conditions
when TJ = 100 °C, VDD = 1.14 V.
Table 309 • Maximum Frequency for HPMS Main Clock
Symbol
Description
–1
–Std
Unit
HPMS_CLK
Maximum frequency for the HPMS main clock
166
142
MHz
2.3.35.2 IGLOO2 Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output
characteristics given are for a 35 pF load on the pins and all sequential timing characteristics are related
to SPI_0_CLK. For timing parameter definitions, see Figure 23, page 131.
The following table lists the SPI characteristics in worst-case industrial conditions when TJ = 100 °C,
VDD = 1.14 V.
Table 310 • SPI Characteristics for All Devices
Symbol Description
Min
Typ
Max Unit
Conditions
SPIFMAX Maximum operating
frequency of SPI interface
20
MHz
sp1
SPI_[0|1]_CLK minimum period
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
12
ns
ns
ns
µs
µs
µs
µs
24.1
48.2
0.1
0.19
0.39
SPI_[0|1]_CLK = PCLK/128 0.77
DS0128 Datasheet Revision 11.0
129
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 310 • SPI Characteristics for All Devices (continued)
Symbol Description
Min
Typ
Max Unit
Conditions
sp2 SPI_[0|1]_CLK minimum pulse width high
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
6
ns
ns
ns
µs
µs
µs
µs
12.05
24.1
0.05
0.095
0.195
SPI_[0|1]_CLK = PCLK/128 0.385
sp3
SPI_[0|1]_CLK minimum pulse width low
SPI_[0|1]_CLK = PCLK/2
SPI_[0|1]_CLK = PCLK/4
SPI_[0|1]_CLK = PCLK/8
SPI_[0|1]_CLK = PCLK/16
SPI_[0|1]_CLK = PCLK/32
SPI_[0|1]_CLK = PCLK/64
6
ns
ns
ns
µs
µs
µs
µs
ns
12.05
24.1
0.05
0.095
0.195
SPI_[0|1]_CLK = PCLK/128 0.385
sp4
sp5
SPI_[0|1]_CLK,
2.77
I/O Configuration:
LVCMOS 2.5 V -
8 mA
AC loading: 35 pF
test conditions:
Typical voltage,
25 °C
SPI_[0|1]_DO, SPI_[0|1]_SS
rise time (10%–90%)1
SPI_[0|1]_CLK,
2.906
ns
I/O Configuration:
LVCMOS 2.5 V -
8 mA
SPI_[0|1]_DO, SPI_[0|1]_SS
fall time (10%–90%)1
AC loading: 35 pF
test conditions:
Typical voltage,
25 °C
SPI master configuration (applicable for 005, 010, 025, and 050 devices)
sp6m
sp7m
sp8m
sp9m
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 8.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) – 2.5
12
2.5
SPI slave configuration (applicable for 005, 010, 025, and 050 devices)
sp6s
sp7s
sp8s
sp9s
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 17.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) + 3.0
2
7
DS0128 Datasheet Revision 11.0
130
IGLOO2 FPGA and SmartFusion2 SoC FPGA
Table 310 • SPI Characteristics for All Devices (continued)
Symbol Description
Min
Typ
Max Unit
Conditions
SPI master configuration (applicable for 060, 090, and 150 devices)
sp6m
sp7m
sp8m
sp9m
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 7.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) – 9.5
15
-–2.5
SPI slave configuration (applicable for 060, 090, and 150 devices)
sp6s
sp7s
sp8s
sp9s
SPI_[0|1]_DO setup time2
SPI_[0|1]_DO hold time2
SPI_[0|1]_DI setup time2
SPI_[0|1]_DI hold time2
(SPI_x_CLK_period/2) – 16.0
ns
ns
ns
ns
(SPI_x_CLK_period/2) - 3.5
3
2.5
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS
models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx.
2. For allowable pclk configurations, see the Serial Peripheral Interface Controller section in the UG0331: SmartFusion2
Microcontroller Subsystem User Guide.
Figure 23 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
SP1
SP4
SP5
SP3
SP2
90%
10%
50% 50%
50%
SPI_0_CLK
SPO = 0
10%
SPI_0_CLK
SPO = 1
90%
90%
SPI_0_SS
10%
SP4
10%
SP5
SP6
SP7
90%
90%
MSB
SP9
50%
50%
SPI_0_DO
SPI_0_DI
10%
10%
SP8
SP5
SP4
50%
50%
MSB
DS0128 Datasheet Revision 11.0
131
相关型号：
©2020 ICPDF网 联系我们和版权申明