MAS17502FBXXX [MICROSEMI]
Microcontroller,;
| 型号： | MAS17502FBXXX |
| 厂家： | 
Microsemi |
| 描述： | Microcontroller, 微控制器 |
| 文件： | 总31页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
DS3565-3.4
MA17502
RADIATION HARD MIL-STD-1750A CONTROL UNIT
The MA17502 Control Unit is a component of the MAS281
BLOCK DIAGRAM
chip set. Other chips in the set include the MA17501 Execution
Unit and the MA17503 Interrupt Unit. Also available is the
peripheral MA31751 Memory Management Unit/Block
Protection Unit. In conjunction these chips implement the full
MIL-STD-1750A Instruction Set Architecture.
The MA17502 consisting of a microsequencer, a microcode
storage ROM, and an instruction mapping ROM - controls all
chip set operations. Table 1 provides brief signal definitions.
The MA17502 is offered in several speed and screening
grades, and in dual in-line, flatpack or leadless chip carrier
packaging. Screening options are described in this document.
For availability of speed grades, please contact GPS.
FEATURES
■ MIL-STD-1750A Instruction Set Architecture
■ Full Performance Over Military Temperature Range
■ 12-Bit Microsequencer
- Instruction Prefetch
- Pipelined Operation
- Subroutine Capability
■ On-Chip ROM
- 2K x 40-Bit Microcode Store
- 512 x 8-Bit Instruction Map
■ MAS281 Integrated Built-In Self Test
■ TTL Compatible System Interface
■ Low Power CMOS/SOS Technology
1.0 SYSTEM CONSIDERATIONS
The CU provides the microprogram storage and
sequencing resources for the chip set. The EU provides the
MAS281’s system synchronizing and arithmetic/logic
computational resources. The lU provides interrupt and fault
handling resources, DMA interface control signals, and the
three MIL-STD-1750A timers. The MMU/BPU may be
configured to provide 1M-word memory management (MMU)
and/or 1K-word memory block write protection (BPU) functions.
The MA17502 Control Unit (CU) is a component of the GPS
MAS281 chip set. The other chips in the set are the MA17501
Execution Unit (EU) and the MA17503 lnterrupt Unit (lU). Also
available is the peripheral MA31751 Memory Management
Unit/Block Protection Unit (MMU(BPU)). The Control Unit, in
conjunction with these chips, implements the full MIL-STD-
1750A lnstruction Set Architecture. Figure 1 depicts the
relationship between the chip set components.
MA17502
Status
8
4
8
Control
Physical Page
Address
Clock
1
MA17501
Execution
Unit
Control
10
16
20
Address/Data
Bus
Page
RAM
512 x 13
Control
MA17502
Control
Unit
1
M Bus
20
16
Data
13
9
Address
Control
Data
Control
Faults
10
7
16
7
MA31751
Block
Protection
& Memory
Management
Unit
1
3
3
Protection
RAM
128 x 16
MA17503
Interrupt
Unit
Interrupts
9
8
16
7
Address
Control
Timer
Controls
4
3
16
4
1
Power
Reset
4
1
MAS281 Chip Set
Figure 1: MAS281 Chip Set With Optional MA17504 and Support RAMs
Signature
l/O
Definition
AD00 - AD15
CC00 - CC11
CLKPC
CLK02
CS
I
External 16-Bit Address/Data Bus
12-Bit Microcode Address Bus
Precharge Clock
Phase 2 Clock
Chip Select
I/O
I
I
I
HOLD
IR
I
I
Hold Request Suspends lnternal Processor Functions
Interrupt Request
M00 - M19
I/O/Z
20-Bit Microcode Bus
NC
PIF
RESET
ROMONLY
T1
-
I
I
I
I
No Connection
Privileged lnstruction Fault
Rest Indicates Device Initialization
Indicates if Control Unit to be Used as ROM Only
Branch or Jump Control
Power (External), 5 Volts
Ground
VDD
GND
Table 1: Signal Definitions
2
MA17502
As shown in Figure 1, the MAS281 is the minimum
processor configuration consisting of an Execution Unit, a
Control Unit, and an Interrupt Unit. This configuration is
capable of accessing a 64K-word address space. Addition of
an MMU configured MA31751 allows access to a 1M-word
address space. This can also be configured as a BPU to
provide hardware support for 1K-word memory block write
protection.
The CU, as with all components of the MAS281 chip set, is
fabricated with CMOS/SOS process technology. Input and
output buffers associated with signals external to the MAS281
are TTL compatible.
Detailed descriptions of the CU’s companion chips are
provided in separate data sheets. Additional discussions on
chip set system considerations, interconnection details, and the
Digital Avionics lnstruction Set (DAlS) mix benchmarking
analysis are provided in separate applications notes.
ROM and the Microcode Storage ROM. The instruction
Mapping ROM access provides a pointer which is then used to
update the microprogram counter (PC); the Microcode Storage
ROM access provides the first microinstruction of the
sequence. Remaining microinstructions in a sequence are
accessed through the use of the four address generation
modes discussed above.
Iterative microprogram operations are achieved through the
use of the loop counter. The loop counter may be selectively
loaded from either the AD bus or directly from microcode. This
counter tracks the number of iterations remaining and, when
appropriate, issues a completion signal (CZ). When an iterative
operation is called for, the loop counter is loaded and the CU
control logic repeats a particular microinstruction sequence,
using the four address generation modes discussed above,
until the CZ signal is received.
2.2 INSTRUCTION MAPPING ROM
The CU instruction mapping ROM provides 512 8-bit words
of microcode instruction vector storage. The address space of
this ROM is mapped into a portion of the microcode storage
ROM’s address space. Hence, both ROMs are accessed
whenever the microcode address falls within this range. The
eight bits from the instruction mapping ROM serve as-the lower
eight bits of a 12-bit microcode address; the upper four bits are
a hardwired constant. The 12-bit microcode address formed
from the 4-bit constant and the mapping ROM’s eight bits are
loaded into the PC register of the microsequencer and serve as
a means to access nonsequential microcode addresses within
the address space allocated to both the instruction mapping
and microcode storage ROMs.
2.0 ARCHITECTURE
The Control Unit consists of a microsequencer, an
instruction mapping ROM, a microcode storage ROM, and
various buses. Details of these components are shown in
Figure 2 and are discussed below:
2.1 MICROSEQUENCER
The CU microsequencer is a 12-bit wide microcode address
generator. Major features of the microsequencer include a
microprogram counter (PC), a microprogram counter save
register (PC Save), microcode address increment logic,
instruction pipeline registers IA and IB, an iteration of loop
counter, a next microcode address source multiplexer, and
various pipelining latches. These features are represented in
Figure 2.
The 12-bit microcode address width allows the
microsequencer to access up to 4096 words of microcode. The
MIL-STD-1750A instructions are implemented as sequences of
microinstructions stored within the lower 2048 locations of this
address space. The address for each microinstruction in a
sequence is provided by the next microcode address source
multiplexer. This multiplexer, under control of the CU control
logic, select from one of six next address sources. Sequential,
direct jump, conditional jump, and subroutine address
generation modes are supported.
Sequential addressing is accomplished by providing a path
from the output of the next microcode address multiplexer to an
incrementer and back to the PC register input. Direct jumps are
supported by routing a portion of the microinstruction to one of
the next microcode address source multiplexer inputs.
Conditional jumps are determined in the ALU of the Execution
Unit which communicates the decision to the CU via the T1
signal. The T1 signal enables a portion of the microcode word
to create the new address. Subroutine jumps are accomplished
by loading the contents of the incremented PC register into the
PC Save register and then performing a direct jump. Upon
completion of the subroutine, the contents of the PC Save
register are used as the next microcode address.
2.3 MICROCODE ROM
The CU microcode ROM provides 2K (2048) 40-bit words of
storage capacity. All of the microcode required to implement
the full MIL-STD-1750A lnstruction Set Architecture (lSA) fits in
one such ROM.
2.4 BUSES
A 16-bit multiplexed Address/Data (AD) bus provides a
communications path between the CU, the other components
of the MAS281 chip set, the MA31751 MMU/BPU, and any
other devices mapped into the chip set’s address space. The
CU receives MIL-STD-1750A instructions, accessed from
system memory, over this bus and loads them into its
instruction pipeline registers.
A 20-bit multiplexed Microcode (M) bus provides a pathway
between the CU chip and the microcode decode logic on all
other chips which are under CU microcode control. The 40-bit
wide microinstructions from the CU’s microcode ROM are
multiplexed on chip as two 20-bit words and presented on the
interchip M bus during alternate phases of CLK02N. Microcode
bits 39 through 20 are placed on the M bus during the CLK02N
low phase and bits 19 through 0 during the high phase of
CLK02N. The M bus is bidirectional to permit microcode
memory expansion.
A 12-bit microcode address (CC) bus is used to route
microcode addresses from the next microcode address source
multiplexer to the microcode and instruction mapping ROMs as
shown in Figure 2.
A new microinstruction sequence begins when an opcode
residing in the lA or IB register is selected by the next
microcode address source multiplexer and used as an address
to simultaneously access both the CU’s Instruction Mapping
3
MA17502
Also, during external bus cycles, RDYN may be used to cause
the EU to prolong the CLK02N trailing low state to greater than
one OSC cycle; this allows the MAS281 chip set to interface
with slower external memory or inpuVoutput devices.
During DMA ((IU)DMAKN is low) or Hold ((EU)HLDAKN is
low), CLKPCN will remain low until the CPU takes control
again.
3.0 INTERFACE SIGNALS
All signal definitions are shown in Table 1. In addition, each
of these functions is provided with Electrostatic Discharge
(ESD) protection diodes. All unused inputs must be held to their
inactive state via a connection to VDD or GND.
Throughout this data sheet, active low signals are denoted
by either a bar over the signal name or by following the name
with an “N” suffix. e.g. HOLDN. Referenced signals that are not
found on the MA17502 are preceded by the originating chip’s
functional acronym in parentheses, e.g. (IU)DMAKN.
A description of each pin function, grouped according to
functional interface, follows. The function acronym is presented
first, followed by its definition, its type, and its detailed
description. Function type is either input, output, high
impedance (Hi-Z), or a combination thereof. Timing
characteristics of each of the functions described are provided
in Section 6.0.
3.3 BUSES
The following is a discussion of the communication buses
connecting the three-chip set. The AD Bus and M Bus are
mainly operand transfer buses, while the CC Bus is strictly for
providing microcode addresses to auxiliary CUs.
3.3.1 Address/Data Bus (AD Bus)
Input. These signals comprise the multiplexed address and
data bus. During external bus operations, the AD bus
accommodates the transfer of instructions, from memory and
l/O ports, to the MA17502. During internal bus operations, the
AD bus provides additional data to the Control Unit from the
Execution Unit. AD00 is the most significant bit position and
AD15 is the least significant bit position of both the 16-bit data
and 16-bit address. A high on this bus corresponds to a logic 1
and a low corresponds to a logic 0. lnformation on the AD Bus is
clocked into the CU by the high-to-low transition of CLKPCN.
3.1 POWER INTERFACE
The power interface consists of a single 5V VDD connection
and two common GND connections.
3.2 CLOCKS
The clock interface, discussed below, is the means by
which the synchronous, microcoded operation of the MAS281
is driven.
3.3.2 Microcode Bus (M Bus)
Input/Output/Hi-z. The M Bus is the 20-bit multiplexed
microcode bus. The 40-bit microcode instruction is multiplexed
onto the M Bus as two 20-bit words (µW1 and µW2). The first
half of the microcode word, µW1 (bits 39 through 20), is
assured valid on the high-to-low transition of CLK02N and µW2
(bits 19 through 0) is assured valid on the high-to-low transition
of CLKPCN. M00 corresponds to microcode bit 0 (µW1) or 20
(µW2) while M19 corresponds to microcode bit 19 (µW1) or 39
(µW2). A high level indicates a logic 1 and a low level indicates
a logic 0. A high level on CS allows the Control Unit to distribute
microcode over this bus, a low level places the bus in the high
impedance state.
3.2.1 Precharge Clock (CLKPCN)
Input. The MA17501 Execution Unit (EU), generates the
CLKPCN signal for the Control Unit. The Control Unit uses this
signal for most of its internal sequencing. During the low phase
of CLKPCN, the internal M Bus is precharged to the high state
to accelerate its response.
The normal CLKPCN period is defined by five OSC cycles
(two cycles low and three cycles high). When a microcode
branch is indicated by the EU, the low state of CLKPCN is
extended to three OSC cycles. During execution of Interrupt
Unit decoded XlO and microcode commands, the high state of
CLKPCN is extended to four OSC cycles. Also, during external
bus cycles, RDYN may be used to cause the EU to prolong the
high state of CLKPCN to greater than three OSC cycles; this
allows the MAS281 chip set to interface with slower external
memory or input/output devices.
During DMA or Hold states, CLKPCN is held low, thus
holding the internal M bus in the precharged state. Precharging
the internal M Bus forces the 20 bits of the external M Bus low.
3.3.3 Microcode Address Bus (CC Bus)
Input/Output/Hi-Z. The CC bus is provided for future
expansion and is left unconnected.
During DMA ((IU)DMAKN is low) or Hold ((EU)HLDAKN is
low), CLKPCN will remain low until the CPU takes control
again.
3.4 SEQUENCER CONTROL
3.2.2 Phase 2 Clock (CLK02N)
The following is a discussion of the microsequencer control
input signals. These signals support chip set functions that
require microcode branching based on the results of operations
performed in the Execution or Interrupt Units.
Input. The MA17501 generates the CLK02N signal for the
Control Unit. The CU then uses this signal, in conjunction with
CLKPCN, to control the distribution of microcode on the M Bus.
CLK02N is used to multiplex the 40-bit microcode instruction
into two 20-bit words (µW1 and µW2). The high-to-low edge of
CLK02N switches µW1 (bits 39 through 20) off the M Bus while
switching µW2 (bits 19 through 0) onto the M Bus.
The normal CLK02N period is defined by five OSC cycles
(one cycle low, three cycles high, one cycle low). When a
microcode branch is indicated by the EU, the high state of
CLK02N is extended to four cycles. During execution of
Interrupt Unit decoded XIO and microcode commands, the
trailing low state of CLK02N is extended to two OSC cycles.
3.4.1 Interrupt Request (IRN)
Input. A low on this input directs the CU to service pending
interrupt requests latched by the Interrupt Unit (IU). Upon
completion of the currently executing MIL-STD-1750A
instruction, the CU checks the IRN input. If IRN is low, then the
CU sequencer will branch to the microcoded interrupt service
routine; else the next MIL-STD-1750A instruction is mapped to
its microcode routine. The microcoded interrupt service routine
4
MA17502
Figure 2: MA17502 Control Unit Architecture
5
MA17502
stores the processor state, retrieves the highest priority
pending interrupt’s service routine processor state, and vectors
software execution to the user’s interrupt service routine. IRN
originates in the IU.
4.0 OPERATING MODES
The following discussions detail the MAS281 chip set
operating modes from the perspective of the Control Unit.
MAS281 operating modes involving the MA17502 include: (1)
Initialisation, (2) lnstruction Execution, (3) Interrupt Servicing,
(4) DMA Support, and (5) HOLD Support.
3.4.2 Privileged Instruction Fault (PIFN)
A low on this signal causes the CU to enable control of the
DMA interface (located in the Interrupt Unit), abort the currently
executing MIL-STD-1750A instruction and check the IRN input
for a pending level 1 interrupt caused by the IU latching a
memory protect (MPROEN), memory address (EXADEN), or
Bus Time-out fault. PIFN originates in the IU.
4.1 INITIALISATION
The MA17502 sequences the MAS281 chip set through the
microcoded initialisation routine in response to a high pulse on
the RESET input. This routine clears the chip set registers,
disables and masks interrupts’ reads the configuration register,
resets the output discrete register (if applicable), initialises the
MMU and BPU (if applicable), performs Built-in Test (BIT),
raises the StartUp ROM Enable discrete, clears and starts
timers A and B, resets the Trigger-Go counter, and loads the
instruction pipeline. The initialisation sequence is contained in
the first 33 locations of microcode ROM (an additional 14
locations contain the optional MMU and BPU initialisation
code). Because the initialisation sequence clears the Execution
Unit’s lnstruction Counter and Status Word (also the address
and processor state copies stored in the MMU(BPU), if
applicable), program execution begins with the instruction
located at address zero (page zero). Table 2 provides a
detailed breakdown of the initialisation sequence and Table 3
summarises the resulting initialised state.
BIT occupies 332 words of microcode storage ROM, and
consists of five subroutines that exercise the internal circuitry of
the MAS281, as outlined in Table 4. BIT begins by pulling the
Normal Power-UP ((IU)NPU) output low; this is the first time
after power-up that the state of NPU is guaranteed. If all five
BIT subroutines execute successfully, NPU is raised high.
If any part of BIT fails, an error code identifying the failed
subroutine is loaded into the Interrupt Unit Fault Register (via
the AD Bus), BlT is aborted, and NPU is left in the low state.
Table 4 defines the coding of the BIT results. (NPU is raised
high through microcode control of the lU in conjunction with the
(EU)lNTREN signal. The BIT error codes are loaded in the lU
Fault Register via the AD Bus under microcode control of the lU
in conjunction with the (EU)lNTREN signal.)
3.4.3 Branch or Jump Control (T1)
Input. A high on this input directs the CU microcode address
sequencer to branch execution to a nonsequential microcode
address. This signal is under the control of the Execution Unit’s
ALU and its level is dependent on the outcome of the presently
executing microcode instruction, e.g. conditional branch. T1
originates in the EU.
3.5 CONFIGURATION CONTROL
The following inputs are provided for control of multiple CU
systems. They allow for expansion of the microcode store to 4K
40-bit words.
3.5.1 ROM-Only (ROMONLYN)
Input. This signal is provided for future microcode
expansion and must be pulled up to VDD.
3.5.2 Chip Select (CS)
Input. A high on this signal enables the CU to drive the 20-
bit external M Bus. This signal is provided for future microcode
expansion and must be pulled up to VDD.
3.6 CPU CONTROL
Grouped under this heading are signals that have CPU-
wide control of normal operation. Each of these has the ability
to “freeze” the processor.
3.6.1 Hold Request (HOLDN)
ln the event of such a failure, the resulting chip set reset
state is dependent on where in BIT the error occurred and may
not be the same as that shown in Table 3. A BIT failure
indication in the fault register sets the level 1 pending interrupt.
Since initialisation disables and masks interrupts, the IRN input
will remain high; thus the interrupt will not be serviced
immediately.
The last action performed by the initialisation routine is to
load the instruction pipeline. lnstruction fetches start at memory
location zero (page zero) from the Start-Up ROM (if
implemented). Whether BlT passes or not, the processor will
begin instruction execution at this point.
Input. A low on this input will suspend internal processor
functions at the end of the currently executing MlL-STD1750A
instruction. When this signal becomes active, the CU
completes the currently executing MIL-STD-1750A instruction,
then branches to the Hold microcode routine and enters the
Hold state. The CU will resume normal operation by refilling the
instruction pipeline registers (IA and IB) upon release of
HOLDN.
3.6.2 System Reset (RESET)
Input. A high on this input for a duration of at least one
CLKPCN period will reset the MAS281 chip set by forcing the
Control Unit to microcode address zero. The high-to-low
transition of this input will cause the CU to begin executing the
MAS281 initialisation sequence starting with the first instruction
in microcode. Built-in Test (BIT) is performed as part of the
initialisation sequence. At the conclusion of initialisation and
successful execution of BIT, the MAS281 will be initialised as
shown in Table 3.
Note: To complete initialisation and pass BIT, interrupt and
fault inputs must be high for the duration of the initialisation
routine. Also, the Timers A and B must be clocked for BIT
success.
6
MA17502
Label Cycle
MAIN B1
1.
2.
3.
Enable Control of DMAE Output signal
-
Clear MAS281 Execution Unit Status Word (SW)
Clear Interrupt Mask (MK) (Internal l/O command, SKM, 2000H)
P
B1
B1
4.
Clear Pending lnterrupt Register (Pl) and Fault Register (FT) (lnternal l/O Command, CLlR, 2001H)
Clear Instruction Counter (IC)
P
B1
P
B1
P
5.
6.
7.
8.
9.
-
Disable Interrupts (Internal l/O Command, DSBL, 2003H)
-
Clear MMU Status Word (lnternal l/O Command, WSW, 200EH) (Note 1)
-
B1
P
10. Disable DMA Access (Internal l/O Command, DMAD, 4007H)
11.
-
B1
12. Read Configuration Register (Internal l/O Command, RCW, 8400H, CONFWN Drops low per Figure
25, Section 5.0)
P
P
13.
14.
-
-
B2
P
15. - (If Output Discrete Register Present, then Continue; Else, Skip to 18)
(16). -
I/O
B2
P
(17). Clear Output Discrete Register (External l/O Command)
19. - (If BPU present, then Branch to BPU; else, continue)
20.
-
B2
P
B2
P
21. - (If MMU present, then Branch to MMU; Else, Continue)
22. - (Setup Temporary Register to indicate No MMU Present)
23. - (Branch to MAS281 BIT)
24.
-
B1
25. Enable Start-Up ROM (Internal l/O Command, ESUR, 4004H; SURE Raises High per Figure 25,
Section 5.0)
P
26.
-
B1
B1
P
27. Clear and Start Timer A (Internal l/O Command, OTA, 400AH)
28. Reset the Trigger-Go timer (Internal l/O Command, GO, 400BH)
29.
-
B1
B2
M
30. Clear and Start Tlmer B (Internal l/O Command, OTB, 400EH)
31. - (Branch to Load Instruction Pipeline Routine)
32. Load data-ln register (Dl) and instruction Register A (IA) from [IC], Increment IC
33. Load Data-ln Register (Dl) and lnstruction Register a (lA) from [lC] ([lA] Moves to lB), lncrement lC
Map Instruction Register B (IB) into Microcode Routine
M
BPU
P
(1).
-
P
(2). - (Set Loop to Clear Memory Protect RAM)
I/O
(3). Clear a Location in MPRAM (Internal l/O Command, LMP, 50XXH), Increment Address; Do 128 Times
(4). - (Branch Back to 20.)
MMU
P
P
P
(1).
(2).
-
-
(3). - (Setup Loop to Load Instruction Page Registers (IPR) and Operand Page Registers (OPR) wlth
Sequential Values of 0 to 255)
P
P
(4).
(5).
-
-
I/O
(6). Load a Location in the IPR with the value of the Locatron Address (Internal l/O Command, WIPR,
51XYH)
I/O
(7). Load a Location in the OPR Increment Loaded Value with the Value of the Location Address (Internal
I/O Command, WOPR, 52XYH)
P
(8). - (Increment IPR Address)
P
B2
(9). - (Increment OPR Address - Repeat Loop [4. - 9.] 256 Times)
(10). - (Setup Temporary Register to Indicate MMU Present; Branch back to 23)
Notes:
1. This operation Is performed whether or not an MMU is present.
2. “-” indicates internal CPU operation.
3. Sequence numbers in “( )” are performed only under the stated conditions.
4. Each step enumerated above represents a single machine (SYNC) cycle of the type shown in the “Cycle” column.
“P” indicates a 5 OSC cycle, 60% duty cycle, machine cycle.
“I/O” and “M” indicate a 5 OSC cycle, 50% duty cycle, machine cycle.
“B1” indicates a 6 OSC cycle 50% duty cycle machine cycle.
“B2” indicates a 6 OSC cycle 66% duty cycle machlne cycle.
7
Table 2: MAS281 Initialisation Sequence
MA17502
MAS281
BIT Test
Coverage
BIT Fail Codes Cycles
(FT13, 14,15
)
Instruction Counter (IC)
Zeroed
Status Word (EU and MMU) (SW) Zeroed
Microcode Sequencer
IB Register Control
Barrel Shifter
Byte Operations and
Flags
Fault (FT)
Zeroed
1
100
221
Pending Interrupt (Pl)
Mask (MK)
Zeroed
Zeroed
General Register File (RO R15)
Interrupts
Zeroed
Disabled
DMA Access
TimerA
Timer B
Trigger-Go Timer
Disabled
Temporary Registers
(T0 - T7)
Microcode Flags
Multiply
Reset and Started
Reset and Started
Reset and Started
2
3
101
111
110
166
214
154
Divide
MMU
Page Registers
AL, W, E, Fields
PPA Field
Group Zero Enabled
Zeroed
Logical to Physical
Map
Interrupt Unit
MK, Pl, FT
Enable/Disable
Interrupts
BPU
Status Word Control
User Flags
General Registers
(R0 - R15)
4
5
Write Protect
Global Memory Protect
Zeroed
Enabled
Table 3: Initialisation State
Timer A
Timer B
111
-
763
26
BIT Pass/Fail
Overhead
Note: BIT pass is indicated by all zeros in FT bits 13, 14 and 15
Table 4: Built In Test (BIT) Summary
4.2 INSTRUCTION EXECUTION
driven low during execution of this instruction). Interrupt, DMA,
and Hold support are explained in more detail in following
sections.
The MIL-STD-1750A microcoded instruction subroutines
are stored in 1255 locations of microcode storage ROM. The
Control Unit receives instructions from memory, via the AD
Bus, through the instruction pipeline registers lA and IB. When
the previous instruction or special process (Interrupts or Hold)
has been completed, the new instruction residing in register IB
is selected by the next microcode address source multiplexer.
A 4-bit hardwired constant, appended by the instruction
opcode, is then used as the first address of a microcode
sequence which distributes the required control to execute the
instruction. The microsequencer generates the remaining
microcode addresses necessary to complete the sequence as
described in Section 2.0 of this data sheet entitled,
“Architecture”.
Upon completion of the current instruction, the CU will
accept the next instruction in the program unless an interrupt,
DMA, or Hold request is received. The interrupt and Hold
request share a common branch point in microcode. If an
interrupt and Hold request are both pending at the conclusion of
the MIL-STD-1750A instruction microcode routine, the Hold
request has priority and is serviced first. Upon release of the
Hold state, the first instruction will execute even if the interrupt
is still pending; when this instruction is complete the interrupt
will be serviced (assuming the HOLDN input has not been
4.3 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is controlled by the Execution
Unit (EU) in concert with the Interrupt Unit DMA interface. The
CU supports DMA by suspending processor control upon
completion of the current machine cycle. If DMA is enabled
((UI)DMAE signal, high) a DMA request ((IU)DMARN input,
low) to the MAS281 causes the lU to acknowledge with
DMAKN, low. When the EU receives the DMAKN (DMA
Acknowledge) signal from the lU, the CU clocks are suspended
(CLKPCN, low; CLK02N, high) halting the MAS281’s
microcode sequencing. Microinstruction execution remains
suspended until DMARN is removed. When DMARN is
removed, microcode execution resumes where DMARN had
interrupted it.
4.4 INTERRUPT HANDLING
Interrupts are handled by the interrupt Unit (IU) and
communicated to the CU via the lRN input. The CU checks the
status of the lRN (lnterrupt Request) signal after the completion
of each MlL-STD-1750A microcode instruction sequence. lf the
lRN signal is low, the CU initiates interrupt handling, otherwise
the CU processes a new instruction.
8
MA17502
IU interrupt handling is controlled by the CU through three
microcode bits - M04, M05, and M06. Upon receipt of the IRN
signal and after completion of the currently executing
instruction, the CU branches to a microcoded interrupt handling
routine. The microprogram sequence supplies microcoded
control to the lU for reading the highest priority pending
interrupt vector code, which also clears this pending interrupt.
Due to the similarity of interrupt and hold request handling
by the CU, if a Hold and interrupt request are pending at the
end of an instruction sequence the Hold has priority and will be
serviced.
4.5 HOLD SUPPORT
The CU accepts a Hold request in much the same way as
an interrupt request. After the completion of each MlL-STD-
1750A microcode instruction sequence, the CU checks the
status of the HOLDN signal. If the HOLDN signal is low, a
microcoded sequence suspends further internal processing
functions; otherwise, the CU processes a new instruction or
services interrupt requests (Hold requests have priority over
interrupt requests).
The Control Unit responds to an active HOLDN signal, upon
completion of the currently executing instruction, but branching
to a microprogrammed sequence of instructions that suspends
all internal operations. This sequence of microinstructions
allows the processor to resume instruction execution at the
point HOLDN was accepted when the CU regains control of the
processor. The MAS281 remains in the Hold state until HOLDN
is pulled high (if the Hold state was reached through the
hardware interface, HOLDN) or HOLDN is pulsed low (if the
Hold state was reached through software, BPT instruction).
HOLDN should be synchronised to AS falling.
5.0 SOFTWARE CONSIDERATIONS
The MAS281 chip set implements the full MlL-STD-1750A
instruction set. Table 6a gives a brief listing of this instruction
set and provides performance data for each instruction. Table
6b provides a summary of the l/O commands implemented in
MAS281 and MA31751 MMU/BPU hardware. A complete
description of this instruction set is provided in MIL-STD-1705A
(Notice 1). The register set available to the software
programmer is depicted in Figure 3. A discussion of data types,
addressing modes, and benchmarking considerations fol lows.
5.1 DATA TYPES
The MAS281 chip set supports 16-bit fixed-point single
precision, 32-bit fixed-point double-precision, 32-bit floating-
point, and 48-bit extended-precision floatingpoint data types.
Figure 4 depicts the formats of these data types.
All numerical data is represented in two’s complement form.
Floating-point numbers are represented by a fractional two’s
complement mantissa with an 8-bit two’s complement
exponent. The MAS281 expects all floating point operands to
be normalised. If they are not normalised, the results from an
instruction are not defined.
Figure 3: Register Set Model
9
MA17502
5.2 ADDRESSING MODES
The MAS281 chip set supports the eight addressing
modes specified in MIL-STD-1750A. These addressing
modes are shown in Figure 5 and are defined below.
5.2.1 Register Direct (R)
The register specified by the instruction (RB) contains
the required operand.
5.2.2 Memory Direct (D,DX)
Memory Direct (without indexing) is an addressing
mode in which the instruction contains the memory address
(A) of the required operand. ln Memory Direct (indexed),
the memory address of the required operand is specified by
the sum of the contents of an index register (RX) and the
instruction address field (A). Registers R1 through R15
may be specified for indexing.
5.2.3 Memory Indirect (I,IX)
Memory Indirect (without indexing) is an addressing
mode in which the memory address (A) specified by the
instruction contains the address of the required operand. In
Memory Indirect (pre-indexed), the sum of the contents of a
specified index register (RX) and the instruction address
field (A) is the address of the address of the required
operand. Registers R1 through R15 may be specified for
indexing.
5.2.4 Immediate Long (IM)
There are two formats that implement Immediate Long
Addressing; one allows indexing and one does not. For the
indexable format, if the specified index register (RX) is not
equal to zero, the contents of RX are added to the
immediate field to form the required operand, otherwise,
the immediate field contains the required operand .
5.2.5 Immediate Short (IS)
In this mode the required 4-bit operand is contained
within the 16-bit instruction. The Immediate Short
addressing mode accommodates two formats; one which
interprets the contents of the immediate field as positive
data and the other which interprets the contents of the
immediate field as negative data.
5.2.6 Immediate Short Positive (ISP)
The immediate operand is treated as a positive integer
between 1 and 16.
Figure 4: Data Formats
5.2.7 Immediate Short Negative (ISN)
5.2.9 Base Relative (B)
The immediate operand is treated as a negative integer
between 1 and 16. Its internal form is a two’s complement,
sign-extended 16-bit number.
There are two formats which implement Base Relative
Addressing; one allows indexing and one does not. For the non-
indexable form the contents of the instruction specified base
register (BR = BR' + 12) is added to the 8-bit displacement field
(DU) of the 16-bit instruction. For the indexable form, the sum of the
contents of a specified index register (RX) and a specified base
register (BR = BR' + 12) is the address of the required operand.
Registers R1 through R15 may be specified for indexing and the
base register may be R12 through R15.
5.2.8 Instruction Counter Relative (ICR)
This addressing mode is used for 16-bit branch
instructions. The contents of the instruction counter minus
two (the address of the current instruction) is added to the
sign-extended 8-bit displacement field (D) within the
instruction. This sum then points to the memory address to
which control may be transferred if a branch is to be taken.
10
MA17502
Figure 5: Addressing Modes
11
MA17502
5.2.10 Special (S)
This addressing mode is applicable to instructions that do
not follow the above formats.
Weighted averages provided in Table 6a, based on the
Sweeney (lBM Systems Journal, Vol. 4, No. 1, 1965)
guidelines, take a wide range of data dependencies into
consideration. Normalization and alignment operations are also
represented. Table 5 defines MAS281 throughput, at various
frequencies and wait states, for the DAIS mix using Sweeney
data dependencies.
It should be noted that using the Sweeney guidelines is a
conservative approach to benchmarking. If best case
assumptions are made and such operations as normalization
and alignment are not considered, MAS281 performance
figures are approximately 50% higher than those indicated in
Table 5.
5.3 BENCHMARKING
Table 6a defines the number and type of machine cycles
associated with each MIL-STD-1750A instruction. This
information may be used when benchmarking MAS281
performance. The Digital Avionics Instruction Set (DAIS) mix,
which defines a typical frequency of occurrence for MIL-STD-
1750A instructions, is used here for this purpose.
One problem with the DAlS mix, however, is that it does not
reflect the impact of data dependencies on system
performance. For example, a multiplication in which one
operand is zero may be performed much faster than one with
two non-zero operands. Also, the DAIS mix does not specify
such time consuming operations as normalization and
alignment.
Realistic benchmarks must therefore take both an
instruction mix and data dependencies into account. To this
end, machine cycle counts in Table 6a which have data
dependencies are annotated with either an “a” suffix to reflect
an average number of machine cycles (where each of several
possibilities is equally likely) or with a “wa” suffix to reflect a
weighted average number of machine cycles (where some data
possibilities are more likely than others). Weighted averages
are only applicable to floating-point operations.
Table 5: Throughput (KIPS)
12
MA17502
5.4 INSTRUCTION SUMMARY
Cycles*
P
Operation
Op Code/Ext
Mnemonic
Format
M
B
LOAD/STORE
Single Precision Load
81
LR
LB
R
B
BX
lSP
ISN
D,DX
IM,IMX
I,IX
1
2
2
1
1
3
2
4
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0X
4X 0
82
83
80
LBX
LlSP
LlSN
L
Ll M
Ll
85
84
Double-Precision Load
Single-Precision Store
87
0X
4X 1
86
88
DLR
DLB
DLBX
D L
R
B
BX
D,DX
I,IX
1
3
3
4
5
2
1
2
0
1
0
0
0
0
0
DLI
0X
4X 2
90
STB
STBX
ST
B
BX
D,DX
I,IX
2
2
3
4
2
2
1
1
0
0
0
0
94
STI
Store a Non-Negative
Constant
91
92
STC
STCI
D,DX
I,IX
3
4
1
1
0
0
Double-Precision Store
0X
4X 3
96
DSTB
DSTX
DST
B
BX
D,DX
I,IX
3
3
4
5
2
2
0
1
0
0
0
0
98
DSTl
Load Multiple Registers
Store Multiple Registers
INTEGER ARITHMETIC
Single-Precision lntegerAdd
89
99
LM
D,DX
D,DX
3 + n
3 + n
1
1
1
1
STM
A1
1X
4X 4
A2
A0
AR
AB
ABX
AISP
A
R
B
BX
ISP
D,DX
IM
1
2
2
1
3
2
1
2
2
1
1
1
0
0
0
0
0
0
4A 1
AIM
Increment Memory by a
Positive Integer
A3
A4
A5
INCM
ABS
D,DX
R
4
1
1
1
0
Single-Precision Absolute
Value of Register
1.5
2.5
1a
1a
Double-Precision Absolute
Value of Register
DABS
R
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a: Instruction Summary
13
MA17502
Cycles*
P
Operation
Op Code/Ext
Mnemonic
Format
M
B
Double-Precision Integer
Add
A7
A6
DAR
DA
R
D,DX
1
4
3
1
0
0
Single Precision Integer
Subtract
B1
1X
4X 5
B2
B0
SR
R
B
BX
ISP
D,DX
IM
1
2
2
1
3
2
1
2
2
1
1
1
0
0
0
0
0
0
SBB
SBBX
SISP
S
4A 2
SIM
Decrement Memory by a
Positive Integer
B3
B4
B5
DECM
NEG
D,DX
R
4
1
1
1
1
3
0
0
0
Single Precision Negate
Register
Double-Precision Negate
Register
DNEG
R
Double-Precision Integer
Subtract
B7
B6
DSR
DS
R
D,DX
1
4
3
1
0
0
Single Precision Integer
Multiply with 16-Bit Product
C1
C2
C3
C0
MSR
MISP
MISN
MS
R
1
1
1
3
2
6.5
7.5
7.5
6.5
6.5
4a
4a
4a
4a
4a
ISP
ISN
D,DX
IM
4A 4
MSIM
Single Precision Integer
Multiply with 32-Bit Product
C5
1X
4X 6
C4
4A 3
MR
MB
MBX
M
R
B
BX
D, DX
IM
1
2
2
3
2
5
7
7
5
5
3
3
3
3
3
MIM
Double-Precision Integer
Multiply
C7
C6
DMR
DM
R
D,DX
1
4
41
40
4.5a
4.5a
D1
D2
D3
D0
DVR
DISP
DISN
DV
R
1
1
1
3
2
20.25
20
20.5
20.25
20.25
5.5a
5.5a
5.5a
5.5a
5.5a
Single Precision Integer
Divide with 16-Bit Dividend
ISP
ISN
D,DX
IM
4A 6
DVIM
Single Precision Integer
Divide with 32-Bit Dividend
D5
1 X
4X 7
D4
4A 5
DR
DB
DBX
D
R
R
BX
D,DX
IM
1
2
2
3
2
21.75
22.75
22.75
21.75
22.75
6.5a
6.5a
6.5a
6.5a
6.5a
DIM
Double-Precision Integer
Divide
D7
D6
DDR
DD
R
D,DX
1
4
79.5
77.5
5.5a
5.5a
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
14
MA17502
Cycles*
P
Operation
Op Code/Ext
Mnemonic
Format
M
B
LOGICAL
Inclusive Logical OR
E1
3X
4X F
E0
4A 8
ORR
ORB
ORBX
OR
R
B
BX
D,DX
IM
1
2
2
3
2
0
1
1
0
0
0
0
0
0
0
ORIM
Logical AND
E3
3X
4X E
E2
4A 7
ANDR
ANDB
ANDX
AND
R
B
BX
D,DX
IM
1
2
2
3
2
0
1
1
0
0
0
0
0
0
0
ANDM
Exclusive Logical OR
Logical NAND
Set Bit
E5
E4
4A 9
XORR
XOR
XORM
R
D,DX
IM
1
3
2
0
0
0
0
0
0
E7
E6
4A B
NR
N
NIM
R
D,DX
IM
1
3
2
1
1
1
0
0
0
51
50
52
SBR
SB
SBI
R
D,DX
I,IX
1
4
5
0
1
2
0
0
0
Reset Bit
54
53
55
RBR
RB
RBI
R
D,DX
I,IX
1
4
5
1
1
2
0
0
0
Test Bit
57
56
58
TBR
TB
TBI
R
D, DX
I,IX
1
3
4
0
0
1
0
0
0
Test and Set Bit
59
5A
5C
5E
97
TSB
D,DX
R
4
1
1
1
4
0
0
1
0
3
2
1
1
1
0
Set Variable Bit in Register
Reset Variable Bit in Register
Test Variable Bit in Register
Store Register Through Mask
BYTE
SVBR
RVBR
TVBR
SRM
R
R
D,DX
Load From Upper Byte
Load From Lower Byte
Store Into Upper Byte
Store Into Lower Byte
Exchange Bytes in Register
8B
8D
8C
8E
9B
9D
9C
9E
EC
LUB
LUBl
LLB
LLBI
STUB
SUBI
STLB
SLBI
XBR
D,DX
I,IX
D,DX
I,IX
D,DX
I, IX
D,DX
I,IX
3
4
3
4
4
5
4
5
1
0
1
1
2
1
3
1
2
0
0
0
0
0
0
0
0
0
1
S
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
15
MA17502
Cycles*
P
Operation
Op Code/Ext
Mnemonic
Format
M
B
COMPARE
Single-Precision Compare
F1
3X
4X C
F2
F3
CR
CB
CBX
CISP
CISN
C
R
B
1
2
2
1
1
3
2
0
1
1
0
0
0
0
0
0
0
0
0
0
0
BX
ISP
ISN
D,DX
IM
F0
4A A
CIM
Compare Between Limits
Double-Precision Compare
F4
CBL
D,DX
4
2.75
1.75a
F7
F6
DCR
DC
R
D,DX
1
4
2
0
0
0
JUMP/BRANCH
Jump on Condition
70
71
JC
JCl
D,DX
I,IX
2
3
0.5
0.5
1a
1a
Jump to Subroutine
Subtract One and Jump
Branch Unconditionally
Branch if Equal to (zero)
Branch if Less than (zero)
Branch to Executive
Branch if Less than or Equal to (Zero)
Branch if Greater than (Zero)
Branch if Not Equal to (Zero)
Branch if Greater than or Equal to (Zero)
72
73
74
75
76
77
78
79
7A
7B
JS
SOJ
BR
BEz
BLT
BEX
BLE
BGT
BNZ
BGE
D,DX
D,DX
ICR
ICR
ICR
S
ICR
ICR
ICR
ICR
2
2
2
1.5
1.5
16
1.5
1.5
1.5
1.5
2
2.5
2
1
1
12
1
1
1
1
0
1a
0
1a
1a
3a
1a
1a
1a
1a
SHIFT
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic
Shift Left Cyclic
Double Shift Left Logical
Double Shift Right Logical
Double Shift Right Arithmetic
Double Shift Left Cyclic
Shift Logical, Count in Register
Shift Arithmetic, Count in Register
Shift Cyclic, Count in Register
Double Shift Logical, Count in Register
60
61
62
63
65
66
67
68
6A
6B
6C
6D
SLL
SRL
SRA
SLC
DSLL
DSRL
DSRA
DSLC
SLR
SAR
SCR
DSLR
DSAR
DSCR
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
2
2
3
1
1.5
1
2.25
3.19
3.5
0
0
0
0
0
0
0
0
3
3.50a
3.25a
4a
4.94a
3a
Double Shift Arithmetic, Count in Register 6E
Double Shift Cyclic, Count in Register 6F
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
16
MA17502
Cycles*
P
Operation
CONVERT
Op Code/Ext
Mnemonic
Format
M
B
Convert Floating-Point to 16-Bit
Integer
E8
E9
EA
EB
FIX
R
R
R
R
1
1
1
1
4.25
3
4.5a
2a
Convert 16-Bit Integer to Floating-
Point
FLT
Convert Extended-Precision
Floating-Point to 32-Bit lnteger
EFIX
EFLT
12.25
7.5
6.25a
3.5a
Convert 32-Bit Integer to
Extended-Precision Floating-Point
STACK
Stack lC and Jump to Subroutine
7E
7F
8F
9F
SJS
D,DX
4
3
3
1
0
Unstack lC and return from
Subroutine
URS
S
S
S
Pop Multiple registers off the
Stack
POPM
PSHM
2.5 + n 2.25 + n
(n=0-15) (n=0-15)
4.25a
2a
Push Multiple Registers onto the
Stack
1 + n
4.5 + n
(n=0-15) (n=0-15)
I/O (See l/O Command Summary)
Execute l/O
Vectored l/O
48
49
XIO**
VIO**
IM,IMX
D,DX
3
-
3.583
-
6.277a
-
SPECIAL
Built-ln Function Call
4F
93
BIF
S
S
Move Multiple Words, Memory-to-
Memory
MOV
1 + 4n
1
1 + 3n
2
1 + 2na
0
Exchange Words in Registers
Load Status
ED
XWR
R
7D
7C
LST**
LSTI**
D,DX
I,IX
8
9
2
2
3
4
No Operation
Break Point
FF
FF
NOP
BPT
S
S
1
3
2
4
2
4
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles). ** Privileged instruction.
a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
17
MA17502
Cycles*
P
Operation
Op Code/Ext
Mnemonic
Format
M
B
FLOATING-POINT
Extended-Precision Floating-
Point Load
8A
9A
AC
BC
EFL
D,DX
D,DX
R
5
5
1
1
0
1
Extended-Precision Floating-
Point Store
EFST
FABS
FNEG
0
1
Floating-Point Absolute Value
of Register
1 .75
3.25
3.25a
3.75a
Floating-Point Negate Register
Floating-Point Compare
R
F9
3X
4X D
F8
FCR
FCB
FCBX
FC
R
B
BX
D,DX
1
2
2
3
2.75
2.75
2.75
1.75
2.875wa
2.875wa
2.875wa
2 875wa
Extended-Precision Floating-
Point Compare
FB
FA
EFCR
EFC
R
D,DX
1
3.25
2.75
2.875wa
2.875wa
4.25a
Floating-Point Add
A9
2X
4X 8
A8
FAR
FAB
FABX
FA
R
B
BX
D,DX
1
3
3
4
7.625
6.625
6.625
5.625
8.25wa
8.25wa
8.25wa
8.25wa
Extended-Precision Floating-
Point Add
AB
AA
EFAR
EFA
R
D,DX
1
5
21.3125 10.5625wa
19.3125 10.5625wa
Floating-Point Subtract
B9
2X
4X 9
B8
FSR
FSB
FSBX
FS
R
B
BX
D,DX
1
3
3
4
8.625
7.625
7.625
6.625
8.625wa
8.625wa
8.625wa
8.625wa
Extended-Precision Floating-
Point Subtract
BB
BA
EFSR
EFS
R
D,DX
1
5
23.0625 11.8125wa
21.0625 11.8125wa
Floating-Point Multiply
C9
2X
4X A
C8
FMR
FMB
FMBX
FM
R
B
BX
D,DX
1
3
3
4
12.75a
12.75a
12.75a
11.75a
6.25wa
6.25wa
6.25wa
6.25wa
Extended-Precision Floating-
point Multiply
CB
CA
EFMR
EFM
R
D,DX
1
5
59.75
57.75
6.25wa
6.25wa
Floating-Point Divide
D9
2X
4X B
D8
FDR
FDB
FDBX
FD
R
B
BX
D,DX
1
3
3
4
31.5
30. 5
30.5
29.5
32.75wa
32.75wa
32.75wa
32.75wa
Extended-Precision Floating-
Point Divide
DB
DA
EFDR
EFD
R
D,DX
1
5
102.625 47.875wa
100.625 47.875wa
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists,
wa = weighted average favouring one or more possible alternatives.
Table 6a (continued): Instruction Summary
18
MA17502
5.5 INTERNAL I/O COMMAND SUMMARY
Cycles*
P
Command
Code (Hex)
Operation
Mnemonic
M
B
Implemented in MAS281
Set Fault Register
0401
2000
2001
2002
2003
2004
2005
200A
200E
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
SFR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3a
3
3
3
3
3
3
3
3
3
3
3
9
9
9
9
9
9
9
9
8.5a
9
9
9
9
9
9
9
9
9
Set Interrupt Mask
Clear Interrupt request
Enable Interrupts
SMK
CLIR
ENBL
DSBL
RPI
Disable Interrupts
Reset Pending Interrupt
Set Pending Interrupt Register
Reset Normal Power Up Discrete
Write Status Word
Enable Start-Up ROM
Disable Start-Up ROM
Direct Memory Access Enable
Direct MemoryAccess Disable
Ti mer A Start
Ti mer A Halt
Output Timer A
Reset Trigger-Go
Timer B Start
SPI
RNS
WSW
ESUR
DSUR
DMAE
DMAD
TAS
TAH
OTA
GO
TBS
TBH
OTB
Timer B Halt
Output Timer B
9
9
Read Configuration Word
Read Fault Register Without Clear
Read Interrupt Mask
Read Pending Interrupt Register
Read Status Word
Read and Clear Fault Register
Input Timer A
Input Timer B
8400
8401
A000
A004
A00E
A00F
C00A
C00E
RCW
RFR
RMK
RPIR
RSW
RCFR
ITA
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
4
4
4
4
4
4
4
4
ITB
Implemented in BPU
Memory Protect Enable
Load Memory Protect RAM
Read Memory Protect RAM
4003
50XX
D0XX
MPEN
LMP
RMP
2
2
2
4
4
3
8
8
3
Implemented in MMU
Write Instruction Page Register
Write Operand Page Register
Read Memory Fault Status
Read Instruction Page Register
Read Operand Page Register
51XY
52XY
A00D
D1XY
D2XY
WIPR
WOPR
RMFS
RIPR
2
2
2
2
2
4
4
3
3
3
8
8
3
3
3
ROPR
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one
alternative exists.
Table 6b: Internal I/O Command Summary
19
MA17502
6.0 TIMING CHARACTERISTICS
This section provides the detailed timing specifications for
the MA17502. Figure 6 depicts the test load used to obtain
timing data. Figures 7 through 9 depict the timing waveforms
associated with various MA17502 signals. Table 7 provides
values for parameters specified in the timing waveforms. All
timing values provided in Table 7 are valid over the full military
temperature range (-55°C to +125°C), and are measured from
50% point to 50% point (50% of VDD supply voltage, unless
otherwise specified). Crosshatching in Figure 7 indicates either
a “don’t care” or indeterminate state.
Figure 6: Test Load
Subgroup Definition
1
2
3
Static characteristics specified in Table 9 at +25°C
Static characteristics specified in Table 9 at +125°C
Static characteristics specified in Table 9 at -55°C
Functional tests at +25°C
7
8a
8b
9
10
11
Functional tests at +125°C
Functional tests at -55°C
Switching characteristics specified in Table 7b at +25°C
Switching characteristics specified in Table 7b at +125°C
Switching characteristics specified in Table 7b at -55°C
Table 7a: Definition of Subgroups
No. Parameter
Test Condition (1) (2)
Min
Max
Units
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLKPC ↑ to Microword 1 Valid
Load 1
Load 1
Load 1
Load 1
-
-
5
95
41
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK02 ↓ to Microword 2 Valid
Microword 1 after CLK02 ↓
Microword 2 after CLKPC ↓
AD Bus to CLKPC ↓
T1 to CLKPC ↑
PIF to CLKPC ↑
IR to CLKPC ↑
HOLD to CLKPC ↓
RESET to CLKPC ↓
AD Bus after CLKPC ↓
HOLD after CLKPC ↓
RESET after CLKPC ↓
T1, PlF, lR after CLKPC ↓
25
10
20
20
20
15
15
15
15
15
0
-
-
-
-
-
-
-
-
-
-
-
Mil-Std-883, Method 5005, Subgroup 9, 10, 11
Notes: 1. TA = +25°C, -55°C and +125°C tested at VDD = 4.5V and 5.5V.
2. Unless otherwise noted: VIL ≥ 0.0V, VIHTTL ≤ 4.0V; timing measured from 50% to 50% point.
Table 7b: Timing Parameter Values
20
MA17502
Figure 7: Basic Timing
Figure 8: RESET Timing
Figure 9: HOLD Timing
21
MA17502
7.0 ABSOLUTE MAXIMUM RATINGS
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Parameter
Min
-0.5
-0.3
-20
-55
-65
Max
7
Units
V
Supply Voltage
Input Voltage
VDD+0.3
+20
V
Current Through Any Pin
Operating Temperature
Storage Temperature
mA
°C
125
150
°C
Table 8: Absolute Maximum Ratings
8.0 DC ELECTRICAL CHARACTERISTICS
Total Dose Radiation Not
Exceeding 3x105 Rad(Si)
Symbol Parameter
Conditions
Min
Typ
Max
Units
VDD
VIHC
VILC
VIHT
VILT
VOHC
VOLC
IIL
Supply Voltage
VSS = 0
4.5
5.0
5.5
-
V
V
CMOS Input High Voltage (Note 1)
CMOS Input Low Voltage (Note 1)
TTL Input High Voltage (Note 2)
TTL Input Low Voltage (Note 2)
-
-
-
-
VDD-1
-
-
-
-
-
-
-
-
-
-
VSS+1
-
V
2.0
V
-
0.8
-
V
CMOS Output High Voltage (Note 1) IOH = -1.4mA, VDD = 4.5V
4.0
V
CMOS Output Low Voltage (Note 1)
Input Leakage Current (Note 3)
Output Leakage Current (Note 3)
IOL = 2mA, VDD = 5.5V
-
-
-
-
0.5
±10
±50
-300
V
VDD = 5.5V, VIN = 0V or 5.5V
VDD = 5.5V, VO = 0V or 5.5V
µA
µA
µA
IOZ
IIPU
CS or ROMONLYN Input Pull-up
Current (Note 4)
VDD = 5.5V,
CS or ROMONLYN = 0V
IDDOP
IDDST
Operating Supply Current
VDD = 5.5V,
CLKPCN = CLK02N = 4MHz
-
-
25
5
35
10
mA
mA
Static Supply Current
VDD = 5.5V,
CLKPCN = CLK02N = 0MHz
VDD = 5V±10%, over full operating temperature range.
Mil-Std-883, Method 5005, Subgroup 1, 2, 3
Notes: 1. The following signals are CMOS compatible:
a) CMOS inputs: CS, ROMONLYN, T1, IRN, PIFN, CLK02N and CLKPCN
b) CMOS I/O signals: Microcode bus (M00-M19) and Microcode address bus (CC00-CC11)
2. The following signals are TTL compatible:
a) TTL inputs: Address/Data Bus (AD00-AD15), RESET and HOLDN
3. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C
4. CS and ROMONLYN inputs are provided for future microcode expansion and have internal pullup resistors. These
signals should be high for normal operation.
Table 9: DC Electrical Characteristics
22
MA17502
9.0 PACKAGING INFORMATION
Millimetres
Ref
Inches
Min.
Nom.
Max.
5.715
1.53
0.508
0.36
82.04
-
Min.
Nom.
Max.
0.225
0.060
0.020
0.014
3.230
-
A
A1
b
-
-
-
-
0.38
-
0.015
-
0.35
-
0.014
-
c
0.229
-
0.009
-
D
-
-
-
-
e
-
2.54 Typ.
-
0.100 Typ.
e1
H
-
22.86 Typ.
-
-
0.900 Typ.
-
4.71
-
-
-
-
5.38
23.4
1.27
1.53
0.185
-
-
-
-
0.212
0.920
0.050
0.060
Me
Z
-
-
-
-
-
-
W
XG413
D
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
Figure 10a: 64-Pin Ceramic DIL - Package Style C
23
MA17502
1
2
IRN
VDD
64 HOLDN
63 RESET
62 T1
3
PIFN
AD00
AD01
AD02
AD03
AD04
AD05
AD06
4
61 NC
5
60 NC
6
59 GND
58 NC
7
8
57 ROMONLYN
56 CC11
55 CC10
54 CC09
53 CC08
52 CC07
51 CC06
50 CC05
49 CC04
48 CC03
47 CC02
46 CC01
45 CC00
44 M00
43 CS
9
10
AD07 11
AD08 12
AD09 13
AD10 14
AD11 15
AD12 16
AD13 17
AD14 18
AD15 19
CLK02N 20
Top
View
21
22
23
24
CLKPCN
M19
M18
42 GND
41 M01
40 M02
39 M03
38 M04
37 M05
36 M06
35 M07
34 NC
M17
M16 25
M15 26
M14 27
M13 28
M12 29
M11 30
M10 31
M09 32
33 M08
Figure 10b: Pin Assignments
24
MA17502
Millimetres
Inches
Ref
Min.
1.905
-
Nom.
Max.
2.21
-
Min.
0.075
-
Nom.
Max.
0.087
-
A
b1
D
E
-
-
0.51
0.020
18.08
18.08
-
-
18.62
18.62
-
0.712
0.712
-
-
0.733
0.733
-
-
1.02
-
-
0.040
-
e
Z
1.40
1.78
0.055
0.070
XG493
D
A
e
b
Z
1
Pad 1
Bottom
View
E
Radius r
3 corners
Figure 11a: 64-Pad Leadless Chip Carrier - Package Style L
25
MA17502
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AD04
AD03
AD02
AD01
AD00
PIFN
VDD
IRN
8
7
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
M16
M15
M14
M13
M12
M11
M10
M09
M08
NC
6
5
4
3
2
Bottom
View
1
HOLDN
RESET
T1
64
63
62
61
60
59
58
57
M07
M06
M05
M04
M03
M02
NC
NC
GND
NC
ROMONLYN
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Figure 11b: Pin Assignments
26
MA17502
Millimetres
Inches
Ref
Min.
-
Nom.
Max.
2.72
2.24
0.51
0.30
24.51
-
Min.
-
Nom.
Max.
0.107
0.088
0.020
0.012
0.960
-
A
-
-
A1
1.83
0.41
0.20
23.88
-
-
0.072
0.016
0.008
0.940
-
-
b
-
-
c
-
-
D1, D2
-
-
e
j1
j2
L
2.54
1.02
0.51
-
0.050
0.040
0.020
-
-
-
-
-
-
-
-
-
10.16
1.65
10.54
2.16
0.400
0.065
0.415
0.085
Z
-
-
XG540
A
A1
L
D1
j1
Z
Pin 1
b
e
D2
Top View
j2
Figure 12a: 68-Lead Topbraze Flatpack - Package Style F
27
MA17502
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
M15
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
AD04
AD03
AD02
AD01
AD00
PIFN
VDD
NC
M14
M13
M12
M11
M10
M09
M08
NC
7
6
5
4
3
2
Top View
1
IRN
NC
68
67
66
65
64
63
62
61
HOLDN
RESET
T1
M07
M06
M05
M04
M03
M02
M01
NC
NC
NC
GND
NC
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Figure 12b: Pin Assignments
28
MA17502
10.0 RADIATION TOLERANCE
Total Dose (Function to specification)*
Transient Upset (Stored data loss)
Transient Upset (Survivability)
Neutron Hardness (Function to specification)
Single Event Upset**
3x105 Rad(Si)
1x1011 Rad(Si)/sec
>1x1012 Rad(Si)/sec
>1x1015 n/cm2
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample devices
from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
<1x10-10 Errors/bit day
Not possible
Latch Up
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
GEC Plessey Semiconductors can provide radiation testing
compliant with Mil-Std-883 method 1019 Ionizing Radiation
(total dose) test.
Table 10: Radiation Hardness Parameters
11.0 ORDERING INFORMATION
Unique Circuit Designator
MAx17502xxxxx
Radiation Tolerance
S
R
Q
Radiation Hard Processing
100 kRads (Si) Guaranteed
300 kRads (Si) Guaranteed
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Package Type
C
F
L
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
Rel 0
C
D
E
B
S
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
29
MA17502
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK Tel: (01793) 518527/518566
Fax: (01793) 518582
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3565-3.4 April 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only
and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure
to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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