MAS5101CB [MICROSEMI]

SRAM,;


型号：	MAS5101CB
厂家：	Microsemi
描述：	SRAM, 静态存储器
文件：	总11页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THIS DOCUMENT IS FOR MAINTENANCE

PURPOSES ONLY AND IS NOT

RECOMMENDED FOR NEW DESIGNS

MA5101

MARCH 1995

DS3579-3.2

MA5101

RADIATION HARD 256 x 4 BIT STATIC RAM

The MA5101 1k Static RAM is configured as 256 x 4 bits and

manufactured using CMOS-SOS high performance, radiation hard,

3µm technology.

The design uses a 6 transistor cell and has full static operation with

no clock or timing strobe required. Address input buffers are deselected

when CE is in the low state and minimum standby current is drawn.

FEATURES

■ 3µm CMOS-SOS Technology

■ Latch-up Free

■ Fast Access Time 90ns Typical

■ Total Dose 10⁶Rad(Si)

■ Transient Upset >10¹⁰Rad(Si)/sec

■ SEU <10^-10Errors/bitday

■ Single 5V Supply

Operation Mode CS CE OE WE

I/O

Power

Read

Write

D OUT

D IN

■ Three State Output

ISB1

ISB2

■ Low Standby Current 10µA Typical

■ -55°C to +125°C Operation

Output Disable

High Z

Standby

High Z

■ All Inputs and Outputs Fully TTL or CMOS

Compatible

■ Fully Static Operation

Figure 1: Truth Table

D11

D12

D13

D14

Figure 2: Block Diagram

MA5101

CHARACTERISTICS AND RATINGS

Stresses above those listed may cause permanent

damage to the device. This is a stress rating only and

functlonal operation of the device at these condltions,

or at any other condition above those indicated in the

operations section of this specification, is not Implied

Exposure to absolute maxlmum rating conditions for

extended perlods may affect device reliability.

Symbol

V_CC

V_I

Parameter

Min.

-0.5

-0.3

-55

Max.

Units

Supply Voltage

Input Voltage

V_DD+0.3

125

T_A

Operating Temperature

Storage Temperature

°C

T_S

-65

150

Figure 3: Absolute Maximum Ratings

Notes for Tables 4 and 5:

1. Characteristics apply to pre radiation at T_A= -55°C to +125°C with V_DD= 5V ±10% and to post 100k Rad(Si) total dose

radiation at T_A= 25°C with V_DD= 5V ±10% (characteristics at higher radiation levels available on request).

2. Worst case at T_A= +125°C, guaranteed but not tested at T_A= -55°C.

GROUP A SUBGROUPS 1, 2, 3.

Symbol Parameter

Conditions

Min.

Typ.

Max.

Units

V_DD

V_lH

V_lL

Supply voltage

4.5

5.0

5.5

V_DD

0.8

Input High Voltage

V_DD/2

Input Low Voltage

V_SS

V_OH

V_OL

I_LI

Output High Voltage

I_OH1= -1mA

2.4

Output Low Voltage

I_OL= 2mA

0.4

±10

±20

Input Leakage Current (note 2)

Output Leakage Current (note 2)

Dynamic Operating Current

V_IN= V_DDor V_SSall inputs

= V_DD/2, V_OUT= 0 to V_DD

µA

I_LO

I_DD

CS = V_IL, f_RC= 1MHz, CE, A_0-7

switching, outputs open, all other

inputs V_DD

I_SB

Standby Supply Current

Selected Supply Current

CE = 0.2V

1000

µA

CS = V_SS, CE = V_DD- 0.2V

Figure 4: Electrical Characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

V_DR

I_DDR

V_CCfor Data Retention

Data Retention Current

CE = V_SS

2.0

CE = V_SS, V_DR= 2.0V

750

µA

Figure 5: Data Retention Characteristics

MA5101

AC CHARACTERISTICS

Conditions of Test for Tables 5 and 6:

1. Input pulse = V_SSto 3.0V.

2. Times measurement reference level = 1.5V.

3. Input Rise and Fall times £5ns.

4. Output load 1TTL gate and CL = 60pF.

5. Transition is measured at ±500mV from steady state.

6. This parameter is sampled and not 100% tested.

Notes for Tables 6 and 7:

Characteristics apply to pre-radiation at T_A= -55°C to +125°C with V_DD= 5V±10% and to post 100k

Rad(Si) total dose radiation at T_A= 25°C with V_DD= 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.

Symbol

Parameter

Min Max

Units

T_AVAVR

T_AVQV

Read Cycle Time

140

130

140

Address Access Time

T_EHQV

Chip Select Access Time

T_SLQV

Chip Enable Access Time

T_EHQX(5,6)

T_SLQX(5,6)

T_ELQZ(5,6)

T_SHQZ(5,6)

T_AXQX

Chip Selection to Output in Low Z

Chip Enable to Output in Low Z

Chip Deselection to Output in High Z

Chip Disable to Output in High Z

Output Hold from Address Change

Output Enable Access Time

Output Enable to Output in Low Z

Output Enable to Output in High Z

T_GLQV

T_GLQX(5,6)

T_GHQZ(5,6)

Figure 6: Read Cycle AC Electrical Characteristics

Symbol

Parameter

Min Max

Units

T_AVAVW

T_EHWH

Write Cycle Tlme

140

Chip Selection to End of Write

Chip Enable to End of Write

Address Valid to End of Write

Address Set Up Time

T_SLWH

T_AVWH

T_AVWL

T_WLWH

Write Pulse Width

T_WHAV

Write Recovery Time

T_WLQZ(5,6)

T_DVWH

Wnte to Output in High Z

Data to Write Time Overlap

Data Hold from Write

T_WHDX

T_WHQX(5,6)

T_EHWL

Output Active from End to Write

Chip Enable to Write Low

Chip Selection to Write Low

T_SLWL

Figure 7: Write Cycle AC Electrical Characteristics

MA5101

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

C_IN

Input Capacitance

Output Capacitance

V_l= 0V

C_OUT

V_I/O= 0V

Note: T_A= 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.

Figure 8: Capacitance

Symbol

Parameter

Conditions

F_T

Basic Functionality

V_DD= 4.5V - 5.5V, FREQ = 1MHz

V_IL= V_SS, V_IH= V_DD, V_OL£ 1.5V, V_OH³ 1.5V

TEMP = -55°C to +125°C, GPS PATTERN SET

GROUP A SUBGROUPS 7, 8A, 8B

Figure 9: Functionality

Subgroup

Definition

Static characteristics specified in Tables 4 and 5 at +25°C

Static characteristics specified in Tables 4 and 5 at +125°C

Static characteristics specified in Tables 4 and 5 at -55°C

Functional characteristics specified in Table 9 at +25°C

Functional characteristics specified in Table 9 at +125°C

Functional characteristics specified in Table 9 at -55°C

Switching characteristics specified in Tables 6 and 7 at +25°C

Switching characteristics specified in Tables 6 and 7 at +125°C

Switching characteristics specified in Tables 6 and 7 at -55°C

Figure 10: Definition of Subgroups

MA5101

TIMING DIAGRAMS

TAVAVR

ADDRESS

TAVQV

TSLQV

TAXQX

TSLQX

TSHQZ

HIGH

IMPEDANCE

DATA OUT

DATA VALID

TEHQX

TEHQV

TELQZ

TGLQX

TGLQV

TGHQZ

1. WE is high for Read Cycle.

2. Address Vaild prior to or coincident with CS transition low or CE transition high.

Figure 11a: Read Cycle 1

TAVAVR

ADDRESS

TAVQV

TAXQX

DATA OUT

DATA VALID

1. WE is high for Read Cycle.

2. Device is continually selected. CS, OE low, CE high.

Figure 11b: Read Cycle 2

MA5101

TAVAVW

ADDRESS

TAVWH

TWHAV (3)

TAVWL

TWLWH (2)

(4)

TAXQX

(5)

TEHWL (7)

TWLQZ

TSLWL

(7)

TWLQH

(6)

HIGH

IMPEDANCE

DATA OUT

DATA IN

TDVWH

TWHDX

DATA VALID

TSLWH

TEHWH

1. WE must be high during all address transitions.

2. A write occurs during the overlap (T_WLWH) of a low CS, a high CE and a low WE.

3. T_WHAVis measured from either CS orWE going high or CE going low, whichever is the earlier, to the end

of the write cycle.

4. If the CS low or CE high transition occurs simultaneously with, or after, the WE low transition, the output

remains in the high impedance state.

5. DATA OUT is the write data of the current cycle, if selected.

6. DATA OUT is the read data of the next address,if selected.

7. T_SLWLand T_EHWLmust be met to prevent memory corruption.

8. OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle).

Figure 12: Write Cycle

MA5101

OUTLINES AND PIN ASSIGNMENTS

M_E

Seating Plane

A₁

e₁

15°

22 Vdd

21 A4

Millimetres

Inches

Ref

Min.

Nom.

Max.

5.715

1.53

0.59

0.36

27.94

Min.

Nom.

Max.

0.225

0.060

0.023

0.014

1.100

0.38

0.015

0.35

0.014

0.20

0.008

Top

View

17 CE

16 DO4

15 DI4

14 DO3

13 DI3

12 DO2

2.54 Typ.

0.100 Typ.

10.16 Typ.

0.400 Typ.

Vss

DI1

4.71

5.38

17.95

1.35

1.53

0.185

0.212

0.313

0.053

0.060

DO1 10

DI2 11

XG462

Figure 13: 28-Lead Ceramic DIL (Solder Seal) - Package Style C

MA5101

Package

Burnin

Function

Option C

Via

Direct

Static 1 Static 2 Static 3

Radiation

LOAD

F10

F11

F12

VSS

DI1

DO1

DI2

DO2

DI3

DO3

DI4

DO4

OEB

CSB

WEB

VDD

Direct

1. F0=150kHz, F1=F0/2, F2=F0/4, F3=F0/8 etc.

2. Burnin R=4K7.

3. Radiation R=10k.

Figure 14: Burnin and Radiation Configuration

MA5101

RADIATION TOLERANCE

Total Dose (Function to specification)*

Transient Upset (Stored data loss)

Transient Upset (Survivability)

Neutron Hardness (Function to specification)

Single Event Upset**

1x10⁵Rad(Si)

5x10¹⁰Rad(Si)/sec

>1x10¹²Rad(Si)/sec

>1x10¹⁵n/cm²

Total Dose Radiation Testing

For product procured to guaranteed total dose radiation

levels, each wafer lot will be approved when all sample

devices from each lot pass the total dose radiation test.

The sample devices will be subjected to the total dose

radiation level (Cobalt-60 Source), defined by the ordering

code, and must continue to meet the electrical parameters

specified in the data sheet. Electrical tests, pre and post

irradiation, will be read and recorded.

3.4x10^-9Errors/bit day

Not possible

Latch Up

* Other total dose radiation levels available on request

** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit

GEC Plessey Semiconductors can provide radiation

testing compliant with MIL-STD-883 test method 1019,

Ionizing Radiation (Total Dose).

Figure 15: Radiation Hardness Parameters

SINGLE EVENT UPSET CHARACTERISTICS

UPSET BIT

CROSS-SECTION

(cm²/bit)

Ion LET (MeV.cm²/mg)

Figure 16: Typical Per-Bit Upset Cross-Section vs Ion LET

MA5101

ORDERING INFORMATION

Unique Circuit Designator

MAx5101xxxxx

Radiation Tolerance

Radiation Hard Processing

30 kRads (Si) Guaranteed

50 kRads (Si) Guaranteed

100 kRads (Si) Guaranteed

QA/QCI Process

(See Section 9 Part 4)

Test Process

(See Section 9 Part 3)

Package Type

Ceramic DIL (Solder Seal)

Assembly Process

(See Section 9 Part 2)

Reliability Level

Rel 0

Rel 1

Rel 2

Rel 3/4/5/STACK

Class B

Class S

For details of reliability, QA/QC, test and assembly

options, see ‘Manufacturing Capability and Quality

Assurance Standards’ Section 9.

HEADQUARTERS OPERATIONS

CUSTOMER SERVICE CENTRES

• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07

• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55

• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993

GEC PLESSEY SEMICONDUCTORS

Cheney Manor, Swindon,

Wiltshire, SN2 2QW, United Kingdom.

Tel: (01793) 518000

• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510

• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023

• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872

• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36

• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260

• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK

Tel: (01793) 518527/518566 Fax: (01793) 518582

Fax: (01793) 518411

GEC PLESSEY SEMICONDUCTORS

P.O. Box 660017,

1500 Green Hills Road, Scotts Valley,

California 95067-0017,

United States of America.

Tel: (408) 438 2900

Fax: (408) 438 5576

These are supported by Agents and Distributors in major countries world-wide.

TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.

This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to

be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or

service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide

only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of

any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose

failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.

MAS5101CB [MICROSEMI]

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