MAX24505EXG+ [MICROSEMI]
Clock Generator, 750MHz, CMOS, PBGA81, CSBGA-81;
| 型号： | MAX24505EXG+ |
| 厂家： | 
Microsemi |
| 描述： | Clock Generator, 750MHz, CMOS, PBGA81, CSBGA-81 时钟 外围集成电路 晶体 |
| 文件： | 总4页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Short Form Data Sheet
April 2012
MAX24505, MAX24510
5 or 10 Output Any-Rate Clock Multipliers
with Internal EEPROM
General Description
Features
♦
Input Clocks
The MAX24505 and MAX24510 are flexible, high-
performance clock multiplier/synthesizer ICs with two
independent APLLs. Each APLL performs any-to-any
frequency conversion. From any input clock frequency
9.72MHz to 750MHz these devices can produce
frequency-locked APLL output frequencies up to
750MHz and as many as 10 differential output clock
signals that are integer divisors of the APLL
frequencies. Output jitter is typically 0.35 to 0.5ps RMS
(12kHz to 20MHz) on all outputs and can be as low as
0.24ps RMS. Each device can configure itself from
internal EEPROM so that clock signals are available
immediately after power-up or reset.
♦
♦
♦
♦
One Crystal or CMOS Input
Three Differential or CMOS Inputs
Differential to 750MHz, CMOS/TTL to 125MHz
Clock Selection By Pin or Register Control
♦
Two APLLs Plus 5 or 10 Output Clocks
♦
APLLs Perform High Resolution Fractional-N
Clock Multiplication
Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
♦
♦
♦
♦
♦
Output Jitter 0.35 to 0.5ps RMS Typical on All
Outputs, Can Be As Low As 0.24ps RMS
Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
Applications
Frequency Conversion and Synthesis Applications in a
Wide Variety of Equipment Types
♦
General Features
♦
Automatic Self-Configuration at Power-Up
from Internal EEPROM Memory
♦
♦
♦
SPI™ Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40 to +85°C Operating Temp. Range
Ordering Information
PART
OUTPUTS
PIN-PACKAGE
MAX24505EXG+
MAX24510EXG+
5
81-CSBGA (10mm)2
81-CSBGA (10mm)2
10
Block Diagram
DIV1
DIV2
DIV3
DIV4
DIV5
DIV6
DIV7
DIV8
DIV9
OC1POS/NEG
OC2POS/NEG
OC3POS/NEG
OC4POS/NEG
OC5POS/NEG
OC6POS/NEG
OC7POS/NEG
OC8POS/NEG
OC9POS/NEG
OC10POS/NEG
APLL1
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
A
B
MAX24510 only
MAX24510 only
IC1POS/NEG
APLL2
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
IC2POS/NEG
IC3POS/NEG
XIN
C
D
XO
XOUT
EEPROM
DIV10
SPI Interface
JTAG
and HW Control and Status Pins
1
Short Form Data Sheet
MAX24505, MAX24510
1. Application Examples
Figure 1-1. Asynchronous Ethernet Clocks
XIN
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
Any combination of 25MHz,
125MHz, 156.25MHz and
25MHz
related Ethernet frequencies
XOUT
Any combination of differential or
2x single-ended signal format
Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card
Synchronous Ethernet
Clocks: any combination
of 25M, 125M, 156.25M
and related frequencies
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
19.44M,
25M, etc.
From dual
redundant
timing functions
IC1P/N
IC2P/N
Any combination of differential or
2x single-ended signal format
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
SDH/SONET Clocks:
Nx6.48MHz to 622.08MHz
2
Short Form Data Sheet
MAX24505, MAX24510
2. Detailed Features
2.1
APLL Features
Two independent APLLs
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•
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•
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Very high-resolution fractional scaling (i.e. non-integer multiplication)
Output jitter is typically 0.35 to 0.5ps RMS and can be as low as 0.24ps RMS (12kHz to 20MHz)
Telecom output frequencies include 622.08MHz for SONET/SDH and 625MHz for Synchronous Ethernet
Bypass mode for each APLL supports system testing and allows the devices to be used in fanout
applications
2.2
Output Clock Features
•
•
•
•
•
•
•
•
Up to five (MAX24505) or ten (MAX24510) low-jitter output clocks
Each output can be one differential output or two CMOS/TTL outputs
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL components
Each output can be any integer divisor of an APLL output clock
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can also produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Per-output delay adjustment
Per-output enable/disable
2.3
General Features
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•
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SPI serial microprocessor interface
Automatic self-configuration at power-up from internal EEPROM memory
Four general-purpose I/O pins
Register set can be write-protected
Internal compensation for local oscillator frequency error
3
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