NX2305 [MICROSEMI]

SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES; 与NMOS LDO控制器， POWER GOOD ＆支持单电源12V同步PWM控制器


型号：	NX2305
厂家：	Microsemi
描述：	SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES 与NMOS LDO控制器， POWER GOOD ＆支持单电源12V同步PWM控制器控制器
文件：	总19页 (文件大小：579K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Evaluation board available.

NX2305

SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER

WITH NMOS LDO CONTROLLER, POWER GOOD & ENABLES

PRELIMINARY DATA SHEET

Pb Free Product

FEATURES

DESCRIPTION

n 12V PWM controller plus LDO controller

The NX2305 controller IC is a combination synchronous

Buck and LDO controller IC designed to convert single

12V supply to low cost dual on board supply applica-

tions. The synchronous controller is used for high cur-

rent high efficiency step down DC to DC converter appli-

cations while the LDO controller in conjunction with an

external low cost N ch MOSFET can be used as a very

low drop out regulator in applications such as converting

3.3V to 2.5V output. Internal UVLO keeps both regula-

tors off until the supply voltage exceeds 9V where inde-

pendent internal digital soft starts get initiated to ramp

up both outputs.The switching section has hiccup cur-

rent limit by sensing the Rdson of synchronous MOSFET.

The LDO controller has Feedback Under Voltage Lock

Out as a short circuit protection.Other features includes:

12V gate drive capability , Adaptive dead band control,

Power good flag for the switcher controller and separate

Enable pins for independent power sequencing.

n Hiccup current limit by sensing Rdson of MOSFET

12V high side and low side driver

n Fixed internal 300kHz for switching controller

n Dual Independent Digital Soft Start Function

n Adaptive Deadband Control

n Enable pin available to program the Vbus UVLO

n Shut Down switching and LDO via pulling down

EnSW or ENLDO pins

n Pb-free and RoHS compliant

APPLICATIONS

PCI Graphic Card on board converters

Mother board On board DC to DC applications

On board Single Supply 12V DC to DC such as

12V to 3.3V, 2.5V or 1.8V

Set Top Box and LCD Display

TYPICAL APPLICATION

R14

C11

open

C12

1uF

0.1uF

VCC

5V REG

PVCC

10k

L1 1uH

1N4148

VIN2

VIN1

+12V

PGOOD

+3.3V

100uF

LDO OUT

180uF

47uF

BST

0.1uF

C10 150pF

VOUT2

+1.6V/2A

IRFR3709Z

HDRV

LDO FB

ENLDO

L2 2.2uH

VOUT1

150uF

25mohm

+1.8V/10A

2 x 470uF

R10

VIN2

+3.3V

OCP

LDRV

PGND

R11

1.4k

0.75k

IRFR3709Z

1.1k

10k

HI=SD

3.9nF

R12

6.8k

VIN1

+12V

ENSW

10k

R13

1.4k

COMP

5.6nF

AGND

HI=SD

C13 100pF

Figure1 - Typical application of NX2305

ORDERING INFORMATION

Device

NX2305CMTR

NX2305CSTR

Temperature

0 to 70^oC

Package

MLPQ-16L

SOIC -16L

Frequency

300kHz

Pb-Free

Yes

0 to 70^oC

Rev.5.0

08/19/08

NX2305

ABSOLUTE MAXIMUM RATINGS

Vcc to PGND & BST to SW voltage .................... -0.3V to 16V

BST to PGND Voltage ...................................... -0.3V to 35V

SW to PGND .................................................... -2V to 35V

All other pins .................................................... -0.3V to 6.5V

Storage Temperature Range ............................... -65^oC to 150^oC

Operating Junction Temperature Range ............... -40^oC to 125^oC

CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to

the device. This is a stress only rating and operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied.

PACKAGE INFORMATION

16-LEAD PLASTIC MLPQ

16-LEAD PLASTIC SOIC

q_JA» 83^oC/W

q_JA» 46^oC/W

16 15 14

BST

HDRV

OCP

HDRV

GND

COMP

PGOOD

EN-SW

EN-LDO

5V REG

PGOOD

EN-SW

EN-LDO

PGND 2

AGND

LDRV

PVCC

LDRV

PVCC

VCC

LDO-OUT

LDO-FB

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc =12V, V_BST-V_SW=12V, ENSW=ENLDO=3V, and T_A

= 0 to 70^oC. Typical values refer to T_A= 25^oC.

PARAMETER

Reference Voltage

Ref Voltage

SYM

Test Condition

Min

8.2

TYP

MAX Units

V_REF

0.8

0.2

Ref Voltage line regulation

Supply Voltage(Vcc&V_BST

V_CCVoltage Range

V_CCSupply Current

(Static)

10V<=Vcc<=14V

)

V_CC

I_CC(Static) ENSW=LOW

ENLDO=LOW

PV_CCSupply Current

(Dynamic)

I_CC

(Dynamic)

C_L=3300pF

8.5

V_BSTVoltage Range

V_BSTto V_SW

V_BSTSupply Current(Static)

V_BST(Static) ENSW=LOW

ENLDO=LOW

0.2

Rev.5.0

08/19/08

NX2305

PARAMETER

V_BSTSupply Current

(Dynamic)

SYM

V_BST

Test Condition

C_L=3300PF

Min

TYP

9.2

MAX Units

(dynamic)

Under Voltage Lockout

V_CC-Threshold

V_CC_UVLO V_CCRising (NOTE1)

V_CCFalling (NOTE1)

6.8

V_CChysterises

300

Oscillator (Rt)

Frequency

F_S

300

1.1

KHz

Ramp-Amplitude Voltage

Max Duty Cycle

Min duty Cycle

V_RAMP

Error Amplifiers

Open Loop Gain

Transconductance

Comp SD threshold

Input Bias Current

EN & SS

2000

0.2

umho

100

Soft Start time

Tss

6.8

1.24

Enable HI Threshold

Enable Hysterises

V_ENTHH

V_ENTHL

High Side Driver, Hdrv, BST,

SW (C_L=3300pF)

Output Impedance , Sourcing R_source(Hdrv)

Current

I=200mA

3.6

ohm

Output Impedance , Sinking

Current

R_sink(Hdrv)

Rise Time

Fall Time

THdrv(Rise)

THdrv(Fall)

10% to 90%

90% to 10%

Deadband Time

Tdead(L to Ldrv going Low to Hdrv going

High, 10% to 10%

Low Side Driver , Ldrv,

PVcc, Pgnd(C_L=3300pF)

Output Impedance, Sourcing R_source(Ldrv)

Current

I=200mA

2.2

ohm

Output Impedance, Sinking

Current

R_sink(Ldrv)

Rise Time

TLdrv(Rise)

TLdrv(Fall)

10% to 90%

90% to 10%

Fall Time

Deadband Time

Tdead(H to SW going Low to Ldrv going

L) High, 10% to 10%

LDO Controller

FB Pin- Bias Current

High Output Voltage

Low Output Voltage

High Output Source Current

11.1

0.2

1.9

Rev.5.0

08/19/08

NX2305

PARAMETER

Open Loop Gain

SYM

Test Condition

GBNT(Note 2)

Min

TYP

MAX Units

FB Under Voltage trip point

Power Good(Pgood)

Threshold Voltage as % of

Vref

FB ramping up

Hysteresis

OCP Adjust

OCP Current Setting

NOTE1: VCC is connected to ENSW pin via a resistor divider. In VCC UVLO test, ENSW pin is open.

NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).

Rev.5.0

08/19/08

NX2305

PIN DESCRIPTIONS

PIN SYMBOL

PIN DESCRIPTION

IC’s supply voltage. This pin biases the internal logic circuits. A high freq 1uF ceramic capacitor

is placed as close as possible to and connected to this pin and ground pin. The maximum rating

of this pin is 16V.

VCC

This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as

close as possible to and connected to these pins and SW pin.

BST

A resistor divider is connected from the LDO bus voltage to this pin that holds off the LDO soft start

until this threshold is reached. An external low cost MOSFET can be connected to this pin for

external enable control.

ENLDO

A resistor divider is connected from the respective switcher BUS voltage to this pin that holds off

the controller's soft start until this threshold is reached. An external low cost MOSFET can be

connected to this pin for external enable control.

ENSW

This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output

of the switching regulator to set the output DC voltage.

This pin is the output of error amplifier and is used to compensate the voltage control feedback

loop.

COMP

OCP

This pin is connected to the drain of the external low side MOSFET and is the input of the over

current protection(OCP) comparator. An internal current source 40uA is flown to the external

resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit

point is this voltage divided by the Rds-on. Once this threshold is reached the Hdrv and Ldrv pins

are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048

switching cycles.

This pin is connected to source of high side FET and provides return path for the high side driver.

It is also used to hold the low side driver low until this pin is brought low by the action of high side

turning off. LDRV can only go high if SW is below 1V threshold .

High side gate driver output.

Low side gate driver output.

HDRV

LDRV

PVCC

Supply voltage for the low side fet driver. A high frequency 1uF ceramic cap must be connected

from this pin to the PGND pin as close as possible.

LDO controller feedback input. This pin is connected via resistor divider to the output of the

switching regulator to set the output DC voltage.If the LDOFB pin is pulled below 0.4V, an internal

comparator after a delay pulls down LDOOUT pin and initiates the HICCUP circuitry. During the

startup this latch is not activated, allowing the LDOFB pin to come up and follow the soft started

Vref voltage.

LDO_FB

LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum

rating of this pin is 16V.

LDO_OUT

5V REG

Output of an internal 5V regulator.

Rev.5.0

08/19/08

NX2305

PIN SYMBOL

PIN DESCRIPTION

An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When

FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state.

PGOOD

Power ground pin for low side driver. In SOIC16 package, PGND andAGND are combined

together called GND.

PGND

A((

Analog ground. In MLPD16 package, pad isAGND.

AGND

Rev.5.0

08/19/08

NX2305

BLOCK DIAGRAM

PGOOD

BST

0.9Vref

/0.85Vref

1.25V

0.8V

Bias

Generator

5VREG

Bias

Regulator

UVLO

POR

VCC

90k

20k

START

ENSW_HI

HDRV

ENSW

V_ENTHH

V_ENTHL

COMP

0.2V

Control

Logic

START

0.8V

PWM

OSC

ramp

PVCC

LDRV

PGND

Digital

start Up

0.6V

CLAMP

OCP

40uA

1.3V

CLAMP

COMP

OCP

Hiccup Logic

0.4

START

OCP

comparator

GND

FBLDO

ENLDO

LDOOUT

LDO digital

start up

POR

ENSW_HI

1.25/1.15

Figure 2 - Simplified block diagram of the NX2305

Rev.5.0

08/19/08

NX2305

APPLICATION INFORMATION

V -V_OUTV_OUT

I_RIPPLE

L_OUT

...(2)

Symbol Used In Application Information:

12V-1.8V 1.8V

= 2.3A

VIN

- Input voltage

- Output voltage

- Output current

2.2uH

12V 300kHz

VOUT

IOUT

Output Capacitor Selection

∆VRIPPLE - Output voltage ripple

Output capacitor is basically decided by the

amount of the output voltage ripple allowed during steady

state(DC) load condition as well as specification for the

load transient. The optimum design may require a couple

of iterations to satisfy both condition.

- Switching frequency

- Inductor current ripple

∆IRIPPLE

Design Example

Power stage design requirements:

VIN=12V

Based on DC Load Condition

The amount of voltage ripple during the DC load

condition is determined by equation(3).

VOUT=1.8V

DI_RIPPLE

IOUT =10A

DV_RIPPLE= ESR´ DI_RIPPLE

...(3)

8´ F ´ C_OUT

∆VRIPPLE <=20mV

∆VTRAN<=100mV @ 10A step

FS=300kHz

Where ESR is the output capacitors' equivalent

series resistance,C_OUTis the value of output capacitors.

Typically when large value capacitors are selected

such as Aluminum Electrolytic,POSCAP and OSCON

types are used, the amount of the output voltage ripple

is dominated by the first term in equation(3) and the

second term can be neglected.

Output Inductor Selection

The selection of inductor value is based on induc-

tor ripple current, power rating, working frequency and

efficiency. Larger inductor value normally means smaller

ripple current. However if the inductance is chosen too

large, it brings slow response and lower efficiency. Usu-

ally the ripple current ranges from 20% to 40% of the

output current. This is a design freedom which can be

decided by design engineer according to various appli-

cation requirements. The inductor value can be calcu-

lated by using the following equations:

For this example, POSCAP are chosen as output

capacitors, the ESR and inductor current typically de-

termines the output voltage ripple.

DV_RIPPLE

DI_RIPPLE

20mV

2.3A

ESR_desire

= 8.7mW

...(4)

If low ESR is required, for most applications, mul-

tiple capacitors in parallel are better than a big capaci-

tor. For example, for 20mV output ripple, POSCAP

2R5TPE470M9 with 9mW are chosen.

V -V_OUTV_OUT

L_OUT

I_RIPPLE

...(1)

I_RIPPLE=k ´ I_OUTPUT

E S R _E´ DI_{R IPPLE}

N =

...(5)

D V_{R IPPLE}

where k is between 0.2 to 0.4.

Select k=0.3, then

Number of Capacitor is calculated as

12V-1.8V 1.8V

9mW´ 2.3A

N =

L_OUT

0.3´ 10A 12V 300kHz

L_OUT=1.7uH

20mV

N =1.03

Choose LOUT=2.2uH, then coilcraft inductor

DO5010P-222HC is a good choice.

Current Ripple is calculated as

The number of capacitor has to be round up to a

integer. Choose N =2.

Rev.5.0

08/19/08

NX2305

If ceramic capacitors are chosen as output ca- put inductor is smaller than the critical inductance, the

pacitors, both terms in equation (3) need to be evalu- voltage droop or overshoot is only dependent on the ESR

ated to determine the overall ripple. Usually when this of output capacitor. For low frequency capacitor such

type of capacitors are selected, the amount of capaci- as electrolytic capacitor, the product of ESR and ca-

tance per single unit is not sufficient to meet the tran-

sient specification, which results in parallel configura-

tion of multiple capacitors.

pacitance is high and L £ L_critis true. In that case, the

transient spec is mostly like to dependent on the ESR

of capacitor.

For example, one 100uF, X5R ceramic capacitor

with 2mW ESR is used. The amount of output ripple is

Most case, the output capacitor is multiple capaci-

tor in parallel. The number of capacitor can be calcu-

lated by the following

2.3A

DV_RIPPLE= 2mW´ 2.3A +

8´ 300kHz´ 100uF

ESR_E´ DI_step

V_OUT

N =

´ t ²

...(9)

= 4.6mV +9.6mV =14.2mV

2´ L´ C_E´ DV

tran

Although this meets DC ripple spec, however it

needs to be studied for transient requirement.

where

if L £ L_crit

L´ DI

t =

Based On Transient Requirement

Typically, the output voltage droop during transient

is specified as

step

...(10)

- ESR_E´ C_E

if L ³ L_crit

V_OUT

< DV

@step load ∆I

tran

droop

STEP

For example, assume voltage droop during tran-

sient is 100mV for 10A load step.

During the transient, the voltage droop during the

transient is composed of two sections. One section is

dependent on the ESR of capacitor, the other section is

a function of the inductor, output capacitance as well

as input, output voltage. For example, for the over-

shoot when load from high load to light load with a

∆I_STEPtransient load, if assuming the bandwidth of

system is high enough, the overshoot can be esti-

mated as the following equation.

If the POSCAP 2R5TPE470M9 (470uF, 9mohm

ESR) is used, the crticial inductance is given as

ESR_E´ C_E´ V_OUT

L_crit

DI_step

9mW´ 470mF´ 1.8V

= 0.76mH

10A

The selected inductor is 2.2uH which is bigger than

critical inductance. In that case, the output voltage tran-

sient not only dependent on the ESR, but also capaci-

tance.

V_OUT

DV_overshoot= ESR ´ DI_step

´ t ²

...(6)

2´ L´ C_OUT

where is the a function of capacitor,etc.

number of capacitor is

if L £ L_crit

L´ DI_step

t =

- ESR_E´ C_E

L´ DI

t =

step

V_OUT

...(7)

...(8)

- ESR ´ C_OUT

if L ³ L_crit

V_OUT

2.2mH´ 10A

- 9mW´ 470mF = 7.97us

where

ESR ´ C_OUT´ V_OUTESR_E´ C_E´ V_OUT

1.8V

L_crit

ESR_E´ DI_step

V_OUT

N =

´ t ²

DI_step

2´ L´ C_E´ DV

tran

where ESR_Eand C_Erepresents ESR and capaci-

tance of each capacitor if multiple capacitors are used

in parallel.

9mW´ 10A

1.8V

2´ 2.2mH´ 470mF´ 100mV

´ (7.97us)²

100mV

=1.44

The above equation shows that if the selected out-

Rev.5.0

08/19/08

NX2305

The number of capacitors has to satisfied both ripple

and transient requirement. Overall, we choose N=2.

It should be considered that the proposed equa-

tion is based on ideal case, in reality, the droop or over-

shoot is typically more than the calculation. The equa-

tion gives a good start. For more margin, more capaci-

tors have to be chosen after the test. Typically, for high

frequency capacitor such as high quality POSCAP es-

pecially ceramic capacitor, 20% to 100% (for ceramic)

more capacitors have to be chosen since the ESR of

capacitors is so low that the PCB parasitic can affect

the results tremendously. More capacitors have to be

selected to compensate these parasitic parameters.

F_Z1

F_Z2

...(11)

...(12)

...(13)

...(14)

2´ p ´ R₄´ C₂

2´ p ´ (R₂+ R₃)´ C₃

2´ p ´ R₃´ C₃

C₁´ C₂

2´ p ´ R₄´

C₁+ C₂

where FZ1,FZ2,FP1 and FP2 are poles and zeros in

the compensator.

The transfer function of type III compensator for

transconductance amplifier is given by:

Compensator Design

V_e

1- g_m´ Z_f

Due to the double pole generated by LC filter of the

power stage, the power system has 180^ophase shift ,

and therefore, is unstable by itself. In order to achieve

accurate output voltage and fast transient response,

compensator is employed to provide highest possible

bandwidth and enough phase margin. Ideally, the Bode

plot of the closed loop system has crossover frequency

between 1/10 and 1/5 of the switching frequency, phase

margin greater than 50^oand the gain crossing 0dB with -

20dB/decade. Power stage output capacitors usually

decide the compensator type. If electrolytic capacitors

are chosen as output capacitors, type II compensator

can be used to compensate the system, because the

zero caused by output capacitor ESR is lower than cross-

over frequency. Otherwise type III compensator should

be chosen.

V_OUT

1+ g_m´ Z_in+ Z_in/R₁

For the voltage amplifier, the transfer function of

compensator is

V_e

- Z_f

V_OUT

Z_in

To achieve the same effect as voltage amplifier,

the compensator of transconductance amplifier must

satisfy this condition: R4>>2/gm.And it would be desir-

able if R1||R2||R3>>1/gm can be met at the same time.

Vout

Zin

A. Type III compensator design

For low ESR output capacitors, typically such as

Sanyo oscap and poscap, the frequency of ESR zero

caused by output capacitors is higher than the cross-

over frequency. In this case, it is necessary to compen-

sate the system with type III compensator. The follow-

ing figures and equations show how to realize the type III

compensator by transconductance amplifier.

Vref

Figure 3 - Type III compensator using

transconductance amplifier

Rev.5.0

08/19/08

NX2305

R₂´ V_REF

10kW´ 0.8V

Case 1: F_LC<F_O<F_ESR

R₁=

= 8kW

V_OUT-V_REF

1.8V-0.8V

Choose R₁=8kW.

3. Set zero F_Z2= F_LCand F_p1=F_ESR

power stage

4. Calculate R₄and C₃with the crossover

frequency at 1/10~ 1/5 of the switching frequency. Set

F_O=25kHz.

40dB/decade

C₃=

´ (

)

2´ p ´ R₂

loop gain

´ (

)

ESR

2´ p ´ 10kW 3.5kHz 37.6kHz

=4.1nF

20dB/decade

V_OSC2´ p ´ F_O´ L

R₄=

´ C_out

C₃

1.1V 2´ p ´ 25kHz´ 2.2uH

compensator

´ 940uF

12V

=10.4kW

3.9nF

Choose C₃=3.9nF, R₄=10.2k.

5. Calculate C₂with zero F_z1at 75% of the LC

double pole by equation (11).

F_Z1

F_O

F_P2

F_Z2

FP1

C₂=

Figure 4 - Bode plot of Type III compensator

(F_LC<F_O<F_ESR

2´ p ´ F_Z1´ R₄

)

2´ p ´ 0.75´ 3.5kHz ´ 10.2kW

= 5.95nF

Typical design example of type III compensator in

which the crossover frequency is selected as

F_LC<F_O<F_ESRand F_O<=1/10~1/5F_sis shown as the

following steps.

Choose C₂=5.6nF.

6. Calculate C₁by equation (14) with pole F_p2at

half the switching frequency.

1. Calculate the location of LC double pole F_LC

and ESR zero F_ESR

C₁=

2´ p ´ R₄´ F

2´ p ´

_OUT´ C_OUT

2´ p ´ 10.2kW´ 150kHz

= 104pF

2´ p ´ 2.2uH´ 940uF

Choose C₁=100pF.

= 3.5kHz

7. Calculate R₃by equation (13).

ESR

R₃=

2´ p ´ ESR´ C_OUT

2´ p ´ F ´ C₃

2´ p ´ 4.5mW´ 940uF

2´ p ´ 37.6kHz´ 3.9nF

=1.1k W

= 37.6kHz

2. Set R₂equal to 10kW.

Choose R₃=1.1kW.

Rev.5.0

08/19/08

NX2305

Case 2: F_LC<F_ESR<F_O

2. Set R₂equal to 15kW.

R₂´ V_REF

15kW´ 0.8V

R₁=

= 12kW

V_OUT-V_REF

1.8V-0.8V

Choose R₁=12kW.

3. Set zero F_Z2= F_LCand F_p1=F_ESR

4. Calculate C₃.

power stage

40dB/decade

C₃=

´ (

)

2´ p ´ R₂

ESR

´ (

)

loop gain

2´ p ´ 15kW 2.77kHz 8.16kHz

=2.5nF

Choose C₃=2.7nF.

5. Calculate R₃.

20dB/decade

R₃=

compensator

2´ p ´ F ´ C₃

2´ p ´ 8.16kHz´ 2.7nF

= 7.22kW

F_Z1

F_O

F_P2

F_Z2

FP1

Choose R₃=7.32kW.

6. Calculate R₄with F_O=30kHz.

V_OSC2´ p ´ F_O´ L R₂´ R₃

R₄=

Figure 5 - Bode plot of Type III compensator

(F_LC<F_ESR<F_O)

ESR

R₂+ R₃

1.1V 2´ p ´ 30kHz ´ 2.2uH 15kW´ 7.32kW

12V

=14.3kW

Choose R₄=14.3kW.

13mW

15kW+ 7.32kW

If electrolytic capacitors are used as output

capacitors, typical design example of type III

compensator in which the crossover frequency is

selected as F_LC<F_ESR<F_Oand F_O<=1/10~1/5F_sis shown

as the following steps. Here one SANYO MV-WG1500

with 13 mW is chosen as output capacitor.

5. Calculate C₂with zero F_z1at 75% of the LC

double pole by equation (11).

C₂=

2´ p ´ F ´ R₄

1. Calculate the location of LC double pole F_LC

and ESR zero F_ESR

2´ p ´ 0.75´ 2.77kHz´ 14.3kW

= 3.9nF

Choose C₂=3.9nF.

6. Calculate C₁by equation (14) with pole F_p2at

half the switching frequency.

2´ p ´

_OUT´ C_OUT

2´ p ´ 2.2uH´ 1500uF

= 2.77kHz

C₁=

2´ p ´ R₄´ F

ESR

2´ p ´ ESR´ C_OUT

2´ p ´ 14.3kW´ 150kHz

= 74pF

2´ p ´ 13mW´ 1500uF

Choose C₁=82pF.

= 8.16kHz

Rev.5.0

08/19/08

NX2305

B. Type II compensator design

If the electrolytic capacitors are chosen as power

stage output capacitors, usually the Type II compensa-

tor can be used to compensate the system.

For this type of compensator, F_Ohas to satisfy

F_LC<F_ESR<<F_O<=1/10~1/5F_s.

Vout

Vref

Case 1:

Type II compensator can be realized by simple

RC circuit as shown in figure 7. R₃and C₁introduce a

zero to cancel the double pole effect. C₂introduces a

Figure 7 - Type II compensator with

transconductance amplifier(case 1)

pole to suppress the switching noise.

To achieve the same effect as voltage amplifier,

the compensator of transconductance amplifier must

The following parameters are used as an ex-

ample for type II compensator design, three 1500uF

with 19mohm Sanyo electrolytic CAP 6MV1500WGL

are used as output capacitors. Coilcraft DO5010P-

152HC 1.5uH is used as output inductor. See figure

19. The power stage information is that:

satisfy this condition: R₃>>1/gm and R₁||R₂>>1/gm. The

following equations show the compensator pole zero lo-

cation and constant gain.

R₃

Gain=

... (15)

... (16)

... (17)

R₂

VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.

1.Calculate the location of LC double pole F_LC

F =

2´ p ´ R₃´ C₁

and ESR zero F_ESR

F »

2´ p ´ R₃´ C₂

2´ p ´

_OUT´ C_OUT

2´ p ´ 1.5uH´ 4500uF

= 1.94kHz

power stage

loop gain

40dB/decade

20dB/decade

ESR

2´ p ´ ESR´ C_OUT

2´ p ´ 6.33mW´ 4500uF

= 5.6kHz

2.Set crossover frequency FO=30kHz>>F_ESR

3. Set R₂equal to10kW. Based on output voltage,

using equation 21, the final selection of R₁is 20kW.

4.Calculate R₃value by the following equation.

compensator

Gain

V_{O S C}2 ´ p ´ F_O´ L

R ₃=

´ R ₂

V_in

E S R

1.1V 2 ´ p ´ 30kHz ´ 1.5uH

´ 10kW

^LCF_ESR

F_O

12V

=37.2kW

6.33m W

Choose R₃=37.4kW.

Figure 6 - Bode plot of Type II compensator

Rev.5.0

08/19/08

NX2305

5. Calculate C₁by setting compensator zero F_Z

at 75% of the LC double pole.

power stage

loop gain

C₁=

2´ p ´ R₃´ F

40dB/decade

2´ p ´ 37.4kW´ 0.75´ 1.94kHz

=2.9nF

Choose C₁=2.7nF.

6. Calculate C₂by setting compensator pole

at half the swithing frequency.

20dB/decade

C ₂

p ´ R ´ F_s

compensator

Gain

p ´ 3 7 . 4k W ´ 1 5 0 k H z

= 5 7 p F

Choose C₂=56pF.

Case 2:

^LCF_ESR

F_O

Type II compensator can also be realized by simple

RC circuit without feedback as shown in figure 9. R3 and

C1 introduce a zero to cancel the double pole effect. C2

introduces a pole to suppress the switching noise. The

following equations show the compensator pole zero lo-

cation and constant gain.

Figure 8 - Bode plot of Type II compensator

Vout

Vref

R₁

Gain=g_m´

´ R₃

... (18)

... (19)

... (20)

R₁+R₂

F =

2´ p ´ R₃´ C₁

F »

2´ p ´ R₃´ C₂

Figure 9 - Type II compensator with

transconductance amplifier

For this type of compensator, F_Ohas to satisfy

F_LC<F_ESR<<F_O<=1/10~1/5F_s.

The following is parameters for type II compensa-

tor design. Input voltage is 12V, output voltage is 3.3V,

output inductor is 1.5uH, output capacitors are two 680uF

with 41mW electrolytic capacitors.

1.Calculate the location of LC double pole F_LC

and ESR zero F_ESR

Rev.5.0

08/19/08

NX2305

Output Voltage Calculation

Output voltage is set by reference voltage and ex-

ternal voltage divider. The reference voltage is fixed at

0.8V. The divider consists of two ratioed resistors so

that the output voltage applied at the Fb pin is 0.8V when

the output voltage is at the desired value. The following

equation and picture show the relationship between

V_OUT, V_REFand voltage divider.

2´ p ´

_OUT´ C_OUT

2´ p ´ 1.5uH´ 1360uF

= 3.5kHz

ESR

2´ p ´ ESR´ C_OUT

Vout

2´ p ´ 20.5mW´ 1360uF

= 5.7kHz

2.Set R₂equal to10.2kW. Using equation 21, the

final selection of R₁is 3.24kW.

3. Set crossover frequency at 1/10~ 1/5 of the

swithing frequency, here FO=30kHz.

Vref

4.Calculate R₃value by the following equation.

Figure 10 - Voltage divider

V_OSC2 ´ p ´ F_O´ L

R₁+R₂

R₁

R₃=

R_ESR

g_m

R ₂´ V_REF

R₁=

1.1V 2´ p ´ 30kHz´ 1.5uH

...(21)

V_OUT-V_REF

20.5W

10.2kW+3.24kW

3.24kW

2mA/V

where R2 is part of the compensator, and the

value of R1 value can be set by voltage divider.

See compensator design for R₁and R₂selection.

=2.6kW

Choose R₃=2.61kW.

Input Capacitor Selection

5. Calculate C₁by setting compensator zero F_Z

at 75% of the LC double pole.

Input capacitors are usually a mix of high frequency

ceramic capacitors and bulk capacitors. Ceramic ca-

pacitors bypass the high frequency noise, and bulk ca-

pacitors supply current to the MOSFETs. Usually 1uF

ceramic capacitor is chosen to decouple the high fre-

quency noise.The bulk input capacitors are decided by

voltage rating and RMS current rating. The RMS current

C₁=

2´ p ´ R₃´ F

2´ p ´ 2.61kW´ 0.75´ 3.5kHz

=23nF

in the input capacitors can be calculated

as:

Choose C₁=22nF.

6. Calculate C₂by setting compensator pole

at half the swithing frequency.

I_RMS= I_OUT´ D ´ 1-D

V_OUT

D =

C ₂=

p ´ R ₃´ F_s

...(22)

VIN = 12V, VOUT=1.8V, IOUT=10A, using equation

(22), the result of input RMS current is 3.6A.

For higher efficiency, low ESR capacitors are

recommended.

p ´ 2 . 61k W ´ 3 0 0 k H z

= 4 0 6 p F

Choose C₁=390pF.

Rev.5.0

08/19/08

NX2305

One Sanyo OS-CON 16SVP180M 16V 180uF

where QHGATE is the high side MOSFETs gate

20mW with 3.64A RMS rating are chosen as input bulk charge,QLGATE is the low side MOSFETs gate charge,VHGS

capacitors.

is the high side gate source voltage, and V_LGSis the low

side gate source voltage.

This power dissipation should not exceed maxi-

mum power dissipation of the driver device.

Power MOSFETs Selection

The NX2305 requires two N-Channel power

MOSFETs. The selection of MOSFETs is based on

maximum drain source voltage, gate source voltage,

maximum current rating, MOSFET on resistance and

power dissipation. The main consideration is the power

Soft Start and Enable

NX2305 has digital soft start for switching control-

ler and has one enable pin for this start up. When the

Power Ready (POR) signal is high and the voltage at

enable pin is above V_ENTHH,the internal digital counter

starts to operate and the voltage at positive input of Error

amplifier starts to increase, the feedback network will

force the output voltage follows the reference and starts

the output slowly. After 2048 cycles, the soft start is

complete and the output voltage is regulated to the de-

sired voltage decided by the feedback resistor divider.

loss contribution of MOSFETs to the overall converter

efficiency. In this design example, two IRFR3709Z are

used. They have the following parameters: V_DS=30V,R_DSON

=6.5mW,Q_GATE=17nC.

There are two factors causing the MOSFET power

loss:conduction loss, switching loss.

Conduction loss is simply defined as:

_HCON=I_OUT²´ D´ R_DS(ON)´ K

_LCON=I_OUT²´ (1- D)´ R_DS(ON)´ K

P_TOTAL=P + P

...(23)

HCON

LCON

Vbus

where the RDS(ON) will increases as MOSFET junc-

tion temperature increases, K is RDS(ON) temperature

dependency. As a result, RDS(ON) should be selected for

the worst case, in which K approximately equals to 1.4

at 125^oC according to IRFR3709Z datasheet. Conduc-

tion loss should not exceed package rating or overall

system thermal budget.

POR

ENSW or

ENLDO

Digital

start

OFF

10k

ENTHH

ENTHL

Figure 11 - Enable and Shut down the NX2305

with Enable pin.

Switching loss is mainly caused by crossover

conduction at the switching transition. The total

switching loss can be approximated.

The start up of NX2305 can be programmed through

resistor divider at Enable pin. For example, if the input

bus voltage is 12V and we want NX2305 starts when

Vbus is above 8V. We can select

P_SW

´ V ´ I_OUT´ T_SW´ F

IN S

...(24)

where IOUT is output current, TSW is the sum of T_R

and T_Fwhich can be found in mosfet datasheet, and FS

is switching frequency. Switching loss PSW is frequency

dependent.

(8V - V_ENTHH)´ R₂

R₁=

V_ENTHH

The NX2305 can be turned off by pulling down the

Enable pin by extra signal MOSFET as shown in the

above Figure. When Enable pin is below V_ENTHL,the digi-

tal soft start is reset to zero. In addition, all the high side

and low side driver is off and no negative spike will be

generated during the turn off.

Also MOSFET gate driver loss should be consid-

ered when choosing the proper power MOSFET.

MOSFET gate driver loss is the loss generated by dis-

charging the gate capacitor and is dissipated in driver

circuits.It is proportional to frequency and is defined as:

P_gate= (Q_HGATE´ V_HGS+ Q_LGATE´ V_LGS)´ F_S

...(25)

Rev.5.0

08/19/08

NX2305

R_RDSON= (V_LDOIN- V_LDOOUT)´ I_LOAD

= (3.3V - 2.5V) / 2A = 0.4W

Over Current Protection

Over current protection for NX2305 is achieved by

sensing current through the low side MOSFET. An inter-

nal current source of 40uA flows through an external re-

sistor connected from OCP pin to SW node sets the

over current protection threshold. When synchronous FET

is on, the voltage at node SW is given as

V_SW=-I_L´ R_DSON

Most of MOSFETs can meet the requirement. More

important is that MOSFET has to be selected right pack-

age to handle the thermal capability. For LDO, maxi-

mum power dissipation is given as

P_LOSS= (V_LDOIN- V_LDOOUT)´ I_LOAD

= (3.3V - 2.5V)´ 2A =1.6W

The voltage at pin OCP is given as

Select IR MOSFET IRFR3706 with 9mW R_DSONis

I_OCP´ R_OCP+V_SW

sufficient.

When the voltage is below zero, the over current

occurss as shown in figure 12.

LDO Compensation

The diagram of LDO controller including VCC regu-

vbus

lator is shown in figure 13.

OCP

40uA

LDO input

OCP

Vref

OCP

comparator

Figure 12 - Over current protection

ESR

Rload

The over current limit can be set by the following

equation

I_SET= I_OCP´ R_OCP/R_DSON

Figure 13 - NX2305 LDO controller.

If the MOSFET R_DSON=9mW, and the current limit

is set at 15A, then

For most low frequency capacitor such as electro-

lytic, POSCAP, OSCON, etc, the compensation param-

eter can be calculated as follows.

_SET´ R_DSON15A´ 9mW

R_OCP

= 3.375kW

I_OCP

40uA

Choose R_OCP=4kW

g_m´ ESR

C_C=

LDO Selection Guide

4´ p ´ F_O´ R_f11+g_m´ ESR

NX2305 offers a LDO controller. The selection of

MOSFET to meet LDO is more straight forward. The

selection is that the Rdson of MOSFET should meet

the dropout requirement. For example.

V_LDOIN=3.3V

where F_Ois the desired crossover frequency.

Typically, in this LDO compensation, crossover

frequency F_Ohas to be higher than zero caused by ESR.

F_Ois typically around several tens kHz to a few hundred

kHz. For this example, we select Fo=100kHz. g_mis the

forward trans-conductance of MOSFET.

For IRFR3706, g_m=53.

V_LDOOUT=2.5V

I_Load=2A

The maximum Rdson of MOSFET should be

Select R_f1=5kohm.

Output capacitor is Sanyo POSCAP 4TPE150MI

with 150uF, ESR=18mohm.

Rev.5.0

08/19/08

NX2305

channel for 2048 cycles and start to restart system again.

53 ´ 18mW

C_C=

=77pF

4 ´ p ´ 100kHz ´ 5kW 1+53 ´ 18mW

Layout Considerations

Choose C_C=82pF. For electrolytic or POSCAP, R_C

is typically selected to be zero.

The layout is very important when designing high

frequency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

R_f2is determined by the desired output voltage.

R_f1´ V_REF

R_f2=

There are two sets of components considered in

the layout which are power components and small sig-

nal components. Power components usually consist of

input capacitors, high-side MOSFET, low-side MOSFET,

inductor and output capacitors. A noisy environment is

generated by the power components due to the switch-

ing power. Small signal components are connected to

sensitive pins or nodes. A multilayer layout which in-

cludes power plane, ground plane and signal plane is

recommended .

V_LDOOUT- V_REF

5kW´ 0.8V

1.6V - 0.8V

=5kW

Choose R_f2=5kW.

When ceramic capacitors or some low ESR bulk

capacitors are chosen as LDO output capacitors, the

zero caused by output capacitor ESR is so high that

crossover frequency F_Ohas to be chosen much higher

than zero caused by R_Cand C_Cand much lower than

zero caused by ESR . For example, 10uF ceramic is

used as output capacitor. We select Fo=100kHz,

R_f1=5kohm and select MOSFET MTD3055(g_m=5). R_C

and C_Ccan be calculated as follows.

Layout guidelines:

1. First put all the power components in the top

layer connected by wide, copper filled areas. The input

capacitor, inductor, output capacitor and the MOSFETs

should be close to each other as possible. This helps

to reduce the EMI radiated by the power loop due to the

high switching currents through them.

2´ p ´ F_O´ C_O

R_C=R_f1´

0.5´ g_m

2´ p ´ 100kHz´ 10uF

2. Low ESR capacitor which can handle input RMS

ripple current and a high frequency decoupling ceramic

cap which usually is 1uF need to be practically touch-

ing the drain pin of the upper MOSFET, a plane connec-

tion is a must.

=5kW´

0.5´ 5S

=12.56kW

Choose R_C=12.7kW.

10´ C_O

C_C=

3. The output capacitors should be placed as close

as to the load as possible and plane connection is re-

quired.

R_C´ g_m

10´ 10uF

12.7kW´ 5S

4. Drain of the low-side MOSFET and source of

the high-side MOSFET need to be connected thru a plane

ans as close as possible.A snubber nedds to be placed

as close to this junction as possible.

=1.6nF

Choose C_C=1.5nF.

5. Source of the lower MOSFET needs to be con-

nected to the GND plane with multiple vias. One is not

enough. This is very important. The same applies to the

output capacitors and input capacitors.

Current Limit for LDO

Current limit of LDO is achieved by sensing the

LDO feedback voltage. When LDO_FB pin is below 0.4V,

the IC goes into hiccup mode. The IC will turn off all the

6. Hdrv and Ldrv pins should be as close to

MOSFET gate as possible. The gate traces should be

Rev.5.0

08/19/08

NX2305

wide and short.A place for gate drive resistors is needed

to fine tune noise if needed.

7. Vcc capacitor, BST capacitor or any other by-

passing capacitor needs to be placed first around the IC

and as close as possible. The capacitor on comp to

GND or comp back to FB needs to be place as close to

the pin as well as resistor divider.

8. The output sense line which is sensing output

back to the resistor divider should not go through high

frequency signals.

9. All GNDs need to go directly thru via to GND

plane.

10. The feedback part of the system should be

kept away from the inductor and other noise sources,

and be placed close to the IC.

11. In multilayer PCB, separate power ground and

analog ground. These two grounds must be connected

together on the PC board layout at a single point. The

goal is to localize the high current path to a separate

loop that does not interfere with the more sensitive ana-

log control function.

R14

C11

open

C12

1uF

VCC

5V REG

PVCC

BST

10k

L1 1uH

VOUT1

+1.8V

1N4148

VIN1

+12V

PGOOD

100uF

LDO OUT

180uF

47uF

C10

150pF

0.1uF

IR3709

VOUT2

+1.2V/2A

HDRV

LDO FB

ENLDO

L2 2.2uH

VOUT1

150uF

25mohm

+1.8V/10A

VOUT1

+1.8V

R10

1500uF

13mohm

OCP

LDRV

PGND

R11

1.4k

IR3711

0.75k

22.1k

49.9k

HI=SD

820pF

R12

6.8k

VIN1

+12V

ENSW

40.2k

R13

1.4k

COMP

1.8nF

AGND

HI=SD

C13 27pF

Figure 14 - Typical application of NX2305 with single power supply

Rev.5.0

08/19/08

NX2305 [MICROSEMI]

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