NX2307CSTR [MICROSEMI]
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER; 单电源12V同步PWM控制器
| 型号： | NX2307CSTR |
| 厂家： | 
Microsemi |
| 描述： | SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER |
| 文件： | 总22页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX2307
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER
ADVANCE DATA SHEET
Pb Free Product
FEATURES
DESCRIPTION
n 12V Gate Driver
n
n
The NX2307 controller IC is a compact synchronous Buck
controller IC with 8 lead SOIC8 package designed for
step down DC to DC converter applications. The NX2307
controller is optimized to convert single supply 12V bus
voltage to as low as 0.8V output voltage. Internal UVLO
keeps the regulator off until the supply voltage exceeds
7V where internal digital soft starts get initiated to ramp
up output. The NX2307 employs fixed current limiting
followed by HICCUP feature. Other features includes:
12V gate drive capability , Converter Shutdown by pull-
ing COMP pin to Gnd, Adaptive dead band control.
Bus voltage operation from 7V to 15V
Fixed hiccup current limit by sensing Rdson of
Synchronous MOSFET
n Internal 300kHz
n Internal Digital Soft Start Function
n Adaptive deadband Control
n Shut Down via pulling COMP pin
n Pb-free and RoHS compliant
APPLICATIONS
n
n
n
Graphic Card on board converters
Vddq Supply in mother board applications
On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n
Set Top Box and LCD Display
TYPICAL APPLICATION
L2 1uH
Vin
+12V
C4
100uF
C5
1uF
Cin
16SVP180M
16V,180uF
R6
10
D1 MBR0530T1
C3
1uF
5
1
C6
0.1uF
BST
Vcc
M1
IRFR3706
2
8
4
Hdrv
7
6
COMP
M3
L1 1.5uH
HI=SD
Vout
R4
SW
5.36k
+1.8V 10A
Co
R1
C7
200pF
4SEPC560M
560uF,7mohm
1.43k
M2
Ldrv
C2
6.8nF
IRFR3706
R2
10k
FB
C1
2.7nF
Gnd
3
R3
8k
Figure1 - Typical application of NX2307
ORDERING INFORMATION
Device
NX2307CSTR
Temperature
0 to 70oC
Package
SOIC - 8L
Frequency
300kHz
Pb-Free
Yes
Rev. 3.2
06/22/06
1
NX2307
ABSOLUTE MAXIMUM RATINGS
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
ESD Susceptibility ........................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
8-LEAD PLASTIC SOIC
qJA » 130oC/W
BST
HDrv
Gnd
1
2
3
4
8
7
6
5
SW
COMP
Fb
LDrv
Vcc
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, VBST-VSW=12V, and TA = 0 to 70oC. Typical
values refer to TA = 25oC.
PARAMETER
Reference Voltage
Ref Voltage
SYM
Test Condition
Min
TYP
MAX Units
VREF
0.8
0.2
V
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
VCC Supply Current
(Static)
10V<=VCC<=14V
%
VCC
V
7
14
14
ICC (Static) Outputs not switching
5
mA
VCC Supply Current
(Dynamic)
ICC
(Dynamic)
CL=3300PF
17
mA
Supply Voltage(VBST)
VBST Voltage Range
VBST Supply Current
VBST to VSW
V
7
VBST
CL=3300PF
12
mA
(Dynamic)
Under Voltage Lockout
VCC-Threshold
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
6.6
0.3
V
V
VCC-Hysteresis
Rev. 3.2
06/22/06
2
NX2307
PARAMETER
Oscillator (Rt)
SYM
Test Condition
Min
TYP
MAX Units
Frequency
FS
300
1.1
94
KHz
V
Ramp-Amplitude Voltage
Max Duty Cycle
Min Duty Cycle
Error Amplifiers
Transconductance
Input Bias Current
Comp SD threshold
Soft Start
VRAMP
%
%
0
2000
0.2
umho
nA
Ib
100
V
Soft Start time
Tss
6.8
mS
High Side
Driver(CL=3300pF)
Output Impedance , Sourcing Rsource(Hdrv)
Current
I=200mA
I=200mA
3.6
1
ohm
ohm
Output Impedance , Sinking
Current
Rsink(Hdrv)
Rise Time
THdrv(Rise)
THdrv(Fall)
10% to 90%
90% to 10%
30
20
50
ns
ns
ns
Fall Time
Deadband Time
Tdead(L to Ldrv going Low to Hdrv going
H)
High, 10% to 10%
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing Rsource(Ldrv)
Current
I=200mA
I=200mA
2.2
1
ohm
ohm
Output Impedance, Sinking
Current
Rsink(Ldrv)
Rise Time
TLdrv(Rise)
TLdrv(Fall)
10% to 90%
90% to 10%
30
20
50
ns
ns
ns
N
Fall Time
Deadband Time
Tdead(H to SW going Low to Ldrv going
L) High, 10% to 10%
Fixed OCP
OCP voltage threshold
240
mV
Rev. 3.2
06/22/06
3
NX2307
PIN DESCRIPTIONS
PIN #
PIN SYMBOL
PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as
possible to and connected to this pin and ground pin. The maximum rating of this
pin is 16V.
5
VCC
This pin supplies voltage to high side FET driver.A high freq minimum 0.1uF
ceramic capacitor is placed as close as possible to and connected to this pin
and SW pin.
1
3
6
7
BST
GND
FB
Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor
divider to the output of the switching regulator to set the output DC voltage.
COMP
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut down
pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft
start is reset.
This pin is connected to source of high side FETs and provide return path for the
high side driver. It is also used to hold the low side driver low until this pin is
brought low by the action of high side turning off. LDRV can only go high if SW is
below 1V threshold .
8
SW
2
4
HDRV
LDRV
High side gate driver output.
Low side gate driver output.
Rev. 3.2
06/22/06
4
NX2307
BLOCK DIAGRAM
Bias
Regulator
VCC
1.25V
0.8V
Bias
Generator
BST
UVLO
POR
OC
6.6/6.3V
START
HDRV
SW
COMP
0.2V
Control
Logic
0.8V
START
OSC
ramp
PWM
OC
VCC
Digital
start Up
S
R
LDRV
Q
FB
0.6V
CLAMP
1.3V
CLAMP
240mV
COMP
Hiccup Logic
START
OCP
comparator
GND
Figure 2 - Simplified block diagram of the NX2307
Rev. 3.2
06/22/06
5
NX2307
J12V
BUS
1
2
12V
4
3
1
2
12V GND
12V GND
R15
2k
PWR
J1
1
2
11
3.3V
3.3V
12
13
14
15
16
17
18
19
20
3.3V
GND
5V
-12V
GND
PS_ON
GND
GND
GND
-5V
3
R24
1k
4
5
GND
5V
C6
6
100u/16V
R2
10
7
L1
GND
PWR_OK
5VSB
12V
DO1608C-102
8
C2
1u
9
5V
C5B
10
5V
D1
1u
MBR0530T1
U1
C5A
16SVP180M
JSW
1
1
M3
OP
BST
R11
4
VOUT
OP
R3
C4
0.1u
M1
IRF3706
OUT
1
2
2
8
HDRV
SW
0
(1.5uH, 4m)
JVOUT
DO5010P-152HC
SW
1
L2
M4
OP
C8
C9
OP
C12
.1u
R12
R20 4SEPC560M
10
OP
R4
M2
IRF3706
D3
OP
4
3
LDRV
GND
0
C19
470pF
R8
6
7
FB
10k
C7
R6
COMP
*
5.49k
6800p
C20
C13
2700p
R7
OP
1.43k
C10
200p
R13
R9
R10
OP
R5
OP
8.06k
OP
C11
OP
SW
Figure 3- Demo board schematic based on ORCAD
Rev. 3.2
06/22/06
6
NX2307
Bill of Materials
Item
Quantity
Reference
Value
Manufacture
1
2
3
2
2
1
VOUT,BUS
C5B,C2
C4
CON2
1u
0.1u
4
5
1
1
C5A
C6
16SVPA180M
100u/16V
SANYO
6
1
C7
6800p
7
1
C8
4SEPC560M
SANYO
8
11
M3,D3,M4,R5,C9,R10,C10, OP
R11,C11,R12,R13
9
1
1
1
1
1
2
1
1
1
1
2
1
2
2
1
1
1
1
1
1
1
C12
C13
C19
C10
D1
JVOUT,JSW
J1
J12V
L1
.1u
2700p
470pF
200p
MBR0530T1
SCOPE TP
ATX con
ATX-12V
DO3316P-102
DO5010P-152HC
IRF3706
LED
10
0
5.49k
1.43k
10k
8.06k
2k
1k
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Tektronics
Coilcraft
Coilcraft
International Rectifier
L2
M1,M2
PWR
R2,R20
R3,R4
R6
R7
R8
R9
R15
R24
U1
NX2307-SOIC8
NEXSEM INC.
Rev. 3.2
06/22/06
7
NX2307
Demoboard waveforms
Figure 4 - Output ripple for power output
Figure 6 - Start up time
Figure 5 - Output voltage transient response for
load current 0A-5A
Figure 7 - Prebias startup
Figure 9 - Short circuit protection
Figure 8 - Shutdown via pulling comp pin down
Rev. 3.2
06/22/06
8
NX2307
APPLICATION INFORMATION
V -VOUT VOUT
1
IN
IRIPPLE
=
´
´
´
LOUT
V
F
S
IN
...(2)
Symbol Used In Application Information:
12V-1.8V 1.8V
1
=
´
= 3.4A
VIN
- Input voltage
- Output voltage
- Output current
1.5uH
12V 300kHz
VOUT
IOUT
Output Capacitor Selection
∆VRIPPLE - Output voltage ripple
Output capacitor is basically decided by the amount
of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
FS
- Switching frequency
- Inductor current ripple
∆IRIPPLE
Design Example
Power stage design requirements:
VIN=12V
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
VOUT=1.8V
DIRIPPLE
IOUT =10A
DVRIPPLE = ESR´ DIRIPPLE
+
...(3)
8´ F ´ COUT
∆VRIPPLE <=25mV
∆VTRAN<=100mV @ 5A step
FS=300kHz
S
Where ESR is the output capacitors' equivalent se-
ries resistance,COUT is the value of output capacitors.
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
Output Inductor Selection
The selection of inductor value is based on induc-
tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu-
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli-
cation requirements. The inductor value can be calcu-
lated by using the following equations:
For this example, OSCON are chosen as output
capacitors, the ESR and inductor current typically de-
termines the output voltage ripple.
DVRIPPLE
DIRIPPLE
25mV
3.4A
ESRdesire
=
=
= 7.3mW
...(4)
If low ESR is required, for most applications, mul-
tiple capacitors in parallel are better than a big capaci-
tor. For example, for 25mV output ripple, OSCON
4SEPC560M with 7mW are chosen.
V -VOUT VOUT
1
IN
LOUT
=
´
´
IRIPPLE
V
F
S
IN
...(1)
IRIPPLE =k ´ IOUTPUT
E S R E ´ DIR IPPLE
N =
...(5)
D VR IPPLE
where k is between 0.2 to 0.4.
Select k=0.4, then
Number of Capacitor is calculated as
12V-1.8V 1.8V
1
7mW´ 3.4A
N =
LOUT
=
´
´
0.4´ 10A 12V 300kHz
LOUT =1.3uH
25mV
N =0.95
Choose LOUT=1.5uH, then coilcraft inductor
DO5010P-152HC is a good choice.
Current Ripple is calculated as
The number of capacitor has to be round up to a
integer. Choose N =1.
Rev. 3.2
06/22/06
9
NX2307
If ceramic capacitors are chosen as output ca-
pacitors, both terms in equation (3) need to be evalu-
ated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capaci-
tance per single unit is not sufficient to meet the tran-
sient specification, which results in parallel configura-
tion of multiple capacitors.
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and L £ Lcrit is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
For example, one 100uF, X5R ceramic capacitor
with 2mW ESR is used. The amount of output ripple is
Most case, the output capacitor is multiple capaci-
tor in parallel. The number of capacitor can be calcu-
lated by the following
3.4A
DVRIPPLE = 2mW´ 3.4A +
8´ 300kHz´ 100uF
ESRE ´ DIstep
VOUT
N =
where
+
´ t 2
= 6.8mV +14.1mV = 20.9mV
...(9)
DV
2´ L´ CE ´ DV
tran
tran
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
0
if L £ Lcrit
ì
ï
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
L´ DI
step
t =
í
ï
î
...(10)
- ESRE ´ CE
if L ³ Lcrit
VOUT
DV
< DV
@step load ∆I
tran
droop
STEP
For example, assume voltage droop during tran-
sient is 100mV for 5A load step.
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over-
shoot when load from high load to light load with a
∆ISTEP transient load, if assuming the bandwidth of
system is high enough, the overshoot can be esti-
mated as the following equation.
If the OSCON 4SEPC560M (560uF, 7mohm
ESR) is used, the crticial inductance is given as
ESRE ´ CE ´ VOUT
Lcrit
=
=
DIstep
7mW´ 560mF´ 1.8V
=1.42mH
5A
The selected inductor is 1.5uH which is bigger than
critical inductance. In that case, the output voltage tran-
sient not only dependent on the ESR, but also capaci-
tance.
VOUT
DVovershoot = ESR ´ DIstep
+
´ t 2
...(6)
2´ L´ COUT
where is the a function of capacitor,etc.
t
number of capacitor is
0
if L £ Lcrit
ì
ï
L´ DIstep
t =
- ESRE ´ CE
t = L´ DI
í
step
...(7)
...(8)
VOUT
- ESR ´ COUT
if L ³ Lcrit
ï
VOUT
î
1.5mH ´ 5A
=
- 7mW´ 560mF = 0.25us
where
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT
1.8V
Lcrit
=
=
ESRE ´ DIstep
DVtran
VOUT
DIstep
DIstep
N =
+
´ t 2
2´ L´ CE ´ DV
tran
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
7mW´ 5A
1.8V
2´ 1.5mH´ 560mF´ 100mV
=
+
´ (0.25us)2
100mV
= 0.35
The above equation shows that if the selected out-
Rev. 3.2
06/22/06
10
NX2307
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we choose N=1.
It should be considered that the proposed equa-
tion is based on ideal case, in reality, the droop or over-
shoot is typically more than the calculation. The equa-
tion gives a good start. For more margin, more capaci-
tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es-
pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
1
FZ1
FZ2
=
=
=
=
...(11)
...(12)
...(13)
...(14)
2´ p ´ R4 ´ C2
1
2´ p ´ (R2 + R3 )´ C3
1
F
P1
2´ p ´ R3 ´ C3
1
F
P2
C1 ´ C2
2´ p ´ R4 ´
C1 + C2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
Compensator Design
Ve
1- gm ´ Zf
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with -
20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than cross-
over frequency. Otherwise type III compensator should
be chosen.
=
VOUT
1+ gm ´ Zin + Zin /R1
For the voltage amplifier, the transfer function of
compensator is
Ve
- Zf
=
VOUT
Zin
To achieve the same effect as voltage amplifier, the
compensator of transconductance amplifier must sat-
isfy this condition: R4>>2/gm. And it would be desir-
able if R1||R2||R3>>1/gm can be met at the same time.
Zf
Vout
Zin
R3
C1
C2
R4
R2
R1
C3
A. Type III compensator design
Fb
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross-
over frequency. In this case, it is necessary to compen-
sate the system with type III compensator. The follow-
ing figures and equations show how to realize the type III
compensator by transconductance amplifier.
Ve
gm
Vref
Figure 10 - Type III compensator using
transconductance amplifier(C1 can also be
connected from comp pin to ground)
Rev. 3.2
06/22/06
11
NX2307
Case 1: FLC<FO<FESR(for most ceramic or low
ESR POSCAP, OSCON)
2. Set R2 equal to 10kW.
R2 ´ VREF
10kW´ 0.8V
R1=
=
= 8kW
VOUT -VREF
1.8V-0.8V
Choose R1=8.06kW.
3. Set zero FZ2 = FLC and Fp1 =FESR, calculate C3.
power stage
LC
F
1
1
1
C3 =
´ (
-
)
40dB/decade
2´ p ´ R2
F
F
p1
z2
1
1
1
=
´ (
-
)
2´ p ´ 10kW 5.5kHz 40.6kHz
=2.5nF
loop gain
ESR
F
Choose C3=2.7nF.
4. Calculate R4 with the crossover frequency at 1/
10~ 1/5 of the switching frequency. Set FO=30kHz.
20dB/decade
compensator
VOSC 2´ p ´ FO ´ L
R4 =
´
´ Cout
V
C3
1.1V 2´ p ´ 30kHz´ 1.5uH
in
=
´
´ 560uF
12V
=5.38kW
2.7nF
FZ1
FO
FP2
FZ2
F
P1
Choose R4=5.36kW.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
Figure 11 - Bode plot of Type III compensator
(FLC<FO<FESR
)
1
C2 =
2´ p ´ FZ1 ´ R4
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the
following steps.
1
=
2´ p ´ 0.75´ 5.5kHz ´ 5.36kW
= 7.1nF
Choose C2=6.8nF.
1. Calculate the location of LC double pole FLC
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
and ESR zero FESR
.
1
F
=
=
1
LC
C1 =
2´ p ´
L
OUT ´ COUT
2´ p ´ R4 ´ F
P2
1
1
=
2´ p ´ 1.5uH´ 560uF
2´ p ´ 5.36kW´ 150kHz
= 197pF
= 5.5kHz
Choose C1=200pF.
1
FESR
=
7. Calculate R3 by equation (13) with Fp1 =FESR
.
2 ´ p ´ ESR ´ COUT
1
=
2 ´ p ´ 7mW´ 560uF
= 40.6kHz
Rev. 3.2
06/22/06
12
NX2307
1
1
R3 =
F
=
=
2´ p ´ F ´ C3
ESR
P1
2´ p ´ ESR´ COUT
1
1
=
2´ p ´ 40.6kHz´ 2.5nF
=1.45kW
2´ p ´ 15mW´ 2000uF
= 5.3kHz
Choose R3 =1.43kW.
2. Set R2 equal to 15kW.
Case 2: FLC<FESR<FO(for electrolytic capacitors)
R2 ´ VREF
15kW´ 0.8V
R1=
=
= 12kW
power stage
VOUT -VREF
1.8V-0.8V
LC
F
Choose R1=12kW.
3. Set zero FZ2 = FLC and Fp1 =FESR
4. Calculate C3 .
.
40dB/decade
ESR
F
1
1
1
C3 =
´ (
-
)
2´ p ´ R2
Fz2
F
p1
loop gain
1
1
1
=
´ (
-
)
2´ p ´ 15kW 1.8kHz 5.3kHz
=2.4nF
20dB/decade
Choose C3=2.7nF.
5. Calculate R3 .
compensator
1
R3 =
2´ p ´ F ´ C3
P1
1
=
2´ p ´ 5.3kHz ´ 2.7F
FZ1
FO
FP2
FZ2
F
P1
= 11.1k W
Figure 12 - Bode plot of Type III compensator
(FLC<FESR<FO)
Choose R3 =11kW.
6. Calculate R4 with FO=30kHz.
VOSC 2 ´ p ´ FO ´ L R2 ´ R3
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is selected
as FLC<FESR<FO and FO<=1/10~1/5Fs is shown as the
following steps. Here two SANYO MV-WG1000 with
30 mW is chosen as output capacitor, output inductor is
2.2uH. See figure 18.
R4 =
´
´
V
ESR
R2 + R3
in
1.1V 2 ´ p ´ 30kHz ´ 2.2uH 15kW´ 11kW
=
´
´
12V
=16kW
Choose R4=16kW.
15mW
15kW+ 11k W
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1. Calculate the location of LC double pole FLC
1
and ESR zero FESR
.
C2 =
2 ´ p ´ FZ1 ´ R4
1
1
F
=
=
LC
2´ p ´
L
OUT ´ COUT
2 ´ p ´ 0.75 ´ 1.8kHz ´ 16kW
= 4.2nF
1
=
Choose C2=4.7nF.
2´ p ´ 2.2uH´ 2000uF
= 1.8kHz
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
Rev. 3.2
06/22/06
13
NX2307
1
C1 =
2 ´ p ´ R4 ´ FP2
power stage
loop gain
1
=
2 ´ p ´ 16kW´ 150kHz
= 66pF
40dB/decade
Choose C1=68pF.
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa-
tor can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<FESR<<FO<=1/10~1/5Fs.
20dB/decade
compensator
Gain
Case 1:
Type II compensator can be realized by simple
RC circuit as shown in figure 14. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
P
F
F
F
Z
LCFESR
FO
pole to suppress the switching noise.
To achieve the same effect as voltage amplifier, the
compensator of transconductance amplifier must sat-
Figure 13 - Bode plot of Type II compensator
C2
isfy this condition: R3>>1/gm and R1||R2>>1/gm. The
following equations show the compensator pole zero lo-
cation and constant gain.
Vout
C1
R3
R2
Fb
R3
Ve
Gain=
... (15)
... (16)
... (17)
R2
R1
1
Vref
F =
z
2´ p ´ R3 ´ C1
1
F »
p
2´ p ´ R3 ´ C2
Figure 14 - Type II compensator with
transconductance amplifier(case 1)
The following parameters are used as an ex-
ample for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P-
152HC 1.5uH is used as output inductor. See figure
19. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.
1.Calculate the location of LC double pole FLC
and ESR zero FESR
.
Rev. 3.2
06/22/06
14
NX2307
Case 2:
1
F
=
=
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 15. R3
and C1 introduce a zero to cancel the double pole effect.
C2 introduces a pole to suppress the switching noise.
The following equations show the compensator pole zero
location and constant gain.
LC
2´ p ´
L
OUT ´ COUT
1
2´ p ´ 1.5uH´ 4500uF
= 1.94kHz
1
F
=
ESR
2´ p ´ ESR´ COUT
R1
Gain=gm ´
´ R3
... (18)
... (19)
... (20)
1
R1+R2
=
2´ p ´ 6.33mW´ 4500uF
1
= 5.6kHz
F =
z
2´ p ´ R3 ´ C1
2.Set crossover frequency FO=30kHz>>FESR
.
1
F »
p
3. Set R2 equal to10kW. Based on output
2´ p ´ R3 ´ C2
voltage, using equation 21, the final selection of R1 is
20kW.
4.Calculate R3 value by the following equation.
Vout
VO S C 2 ´ p ´ FO ´ L
R 3 =
´
´ R 2
R2
Vin
E S R
Fb
1.1V 2 ´ p ´ 30kHz ´ 1.5uH
Ve
R3
=
´
´ 10kW
gm
12V
=37.2kW
6.33m W
R1
Vref
C2
Choose R3 =37.4kW.
C1
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
1
C1=
Figure 15 - Type II compensator with
2´ p ´ R3 ´ F
z
transconductance amplifier(case 2)
1
=
2´ p ´ 37.4kW´ 0.75´ 1.94kHz
=2.9nF
The following is parameters for type II compensa-
tor design. Input voltage is 12V, output voltage is 2.5V,
output inductor is 2.2uH, output capacitors are two 680uF
with 41mW electrolytic capacitors. See figure 20.
1.Calculate the location of LC double pole FLC
Choose C1=2.7nF.
F
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
p
1
C 2 =
and ESR zero FESR
.
p ´ R ´ Fs
3
1
1
=
F
=
LC
p ´ 3 7 . 4k W ´ 1 5 0 k H z
2´ p ´
L
OUT ´ COUT
= 5 7 p F
1
=
Choose C2=56pF.
2´ p ´ 2.2uH´ 1360uF
= 2.9kHz
Rev. 3.2
06/22/06
15
NX2307
Output Voltage Calculation
1
F
=
=
Output voltage is set by reference voltage and ex-
ternal voltage divider. The reference voltage is fixed at
0.8V. The divider consists of two ratioed resistors so
ESR
2´ p ´ ESR´ COUT
1
2´ p ´ 20.5mW´ 1360uF
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
= 5.7kHz
2.Set R2 equal to10kW. Using equation 18, the fi-
nal selection of R1 is 4.7kW.
equation applies to figure 17, which shows the relation-
ship between VOUT , VREF and voltage divider.
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
Vout
4.Calculate R3 value by the following equation.
R2
Fb
VOSC 2´ p ´ FO ´ L
VOUT
1
R3 =
´
´
´
V
RESR
gm VREF
in
R1
1.1V 2´ p ´ 30kHz´ 2.2uH
1
=
´
´
Vref
12
20.5mW
2mA/V
2.5V
0.8V
´
Figure 16 - Voltage divider
=2.9kW
R 2 ´ VREF
Choose R3 =2.87kW.
R1=
...(21)
VOUT -VREF
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
1
C1=
2´ p ´ R3 ´ F
z
Input Capacitor Selection
1
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca-
pacitors bypass the high frequency noise, and bulk ca-
pacitors supply switching current to the MOSFETs. Usu-
ally 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are de-
cided by voltage rating and RMS current rating. The RMS
=
2´ p ´ 2.87kW´ 0.75´ 2.9kHz
=25nF
Choose C1=27nF.
F
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
p
1
C 2 =
current in the input capacitors can be calculated
as:
p ´ R 3 ´ Fs
1
=
p ´ 2 .87k W ´ 1 5 0 k H z
IRMS = IOUT ´ D ´ 1-D
= 3 6 9 p F
VOUT
D =
Choose C2=390pF.
V
IN
...(22)
VIN = 12V, VOUT=1.8V, IOUT=10A, the result of input
RMS current is 3.6A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OS-CON 16SVP180M 16V
180uF 20mW with 3.64A RMS rating are chosen as
input bulk capacitors.
Rev. 3.2
06/22/06
16
NX2307
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Power MOSFETs Selection
The NX2307 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2307, the current limit is decided by
the RDSON of the low side mosfet. When synchronous
FET is on, and the voltage on SW pin is below 240mV,
the over current occurs. The over current limit can be
calculated by the following equation.
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used. They have the following parameters: VDS=30V, ID
=75A,RDSON =9mW,QGATE =23nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
ISET = 240mV/RDSON
The MOSFET RDSON is calculated in the worst case
situation, then the current limit for MOSFET IRFR3706
is
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K
PTOTAL =P + P
P
...(23)
240mV
RDSON
240mV
ISET
=
=
= 17A
1.4´ 9mW
HCON
LCON
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3706 datasheet. Conduction
loss should not exceed package rating or overall sys-
tem thermal budget.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch-
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
1
PSW
=
´ V ´ IOUT ´ TSW ´ F
IN S
...(24)
2
where IOUT is output current, TSW is the sum of TR ing power. Small signal components are connected to
and TF which can be found in mosfet datasheet, and FS sensitive pins or nodes. A multilayer layout which in-
is switching frequency. Swithing loss PSW is frequency cludes power plane, ground plane and signal plane is
dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
recommended .
Layout guidelines:
1. First put all the power components in the top
MOSFET gate driver loss is the loss generated by dis- layer connected by wide, copper filled areas. The input
charging the gate capacitor and is dissipated in driver capacitor, inductor, output capacitor and the MOSFETs
circuits.It is proportional to frequency and is defined as: should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
Pgate = (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS
...(25)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is the low
side gate source voltage.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch-
Rev. 3.2
06/22/06
17
NX2307
ing the drain pin of the upper MOSFET, a plane connec-
tion is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is re-
quired.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible.A snubber nedds to be placed
as close to this junction as possible.
5. Source of the lower MOSFET needs to be con-
nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other by-
passing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be kept
away from the inductor and other noise sources, and be
placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana-
log control function.
Rev. 3.2
06/22/06
18
NX2307
TYPICALAPPLICATIONS
L2 1uH
Vin
+12V
C4
100uF
C5
1uF
Cin
16MV1000WGL
16V,1000uF
R6
10
D1 MBR0530T1
C3
1uF
5
1
C6
0.1uF
BST
Vcc
M1
2
8
4
half FDS6912A
Hdrv
7
6
COMP
M3
L1 2.2uH
HI=SD
Vout
R4
16k
SW
+1.8V 5A
Co
R1
C7
68pF
2 x MV1000WG
1000uF,30mohm
11k
M2
Ldrv
C2
4.7nF
half FDS6912A
R2
15k
FB
C1
2.7nF
Gnd
3
R3
12k
Figure 17 - NX2307 application with electrolytic capacitor and type III compensator
L2 1uH
Vin
+12V
C4
100uF
C5
1uF
Cin
16SVP180M
16V,180uF
R6
10
D1 MBR0530T1
C3
1uF
5
1
C6
0.1uF
BST
Vcc
M1
IRFR3709
2
8
4
Hdrv
7
6
COMP
M3
L1 1.5uH
HI=SD
Vout
R4
SW
37.4k
+1.2V 12A
Co
C7
62pF
3 x 6MV1500WGL
1500uF,13mohm
M2
Ldrv
C2
2.7nF
IRFR3709
R2
10k
FB
Gnd
3
R3
20k
Figure 18 - NX2307 application with type II compensator(case 1)
Rev. 3.2
06/22/06
19
NX2307
L2 1uH
Vin
+12V
C4
100uF
C5
1uF
Cin
16SVP180M
16V,180uF
R6
10
D1 MBR0530T1
C3
1uF
5
1
C6
0.1uF
BST
Vcc
M1
IRFR3706
2
8
4
Hdrv
7
6
COMP
M3
L1 2.2uH
HI=SD
Vout
R4
SW
2.87k
+2.5V 9A
Co
C7
390pF
2 x (680uF,41mohm)
M2
Ldrv
C2
27nF
IRFR3706
R2
10k
FB
Gnd
3
R3
4.7k
Figure 19 - NX2307 application with type II compensator(case 2)
Rev. 3.2
06/22/06
20
NX2307
SOIC8 PACKAGE OUTLINE DIMENSIONS
Rev. 3.2
06/22/06
21
NX2307
Rev. 3.2
06/22/06
22
相关型号：
NX2415
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER AND DIFFERENTIAL CURRENT SENSE
MICROSEMI
NX2415CMTR
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER AND DIFFERENTIAL CURRENT SENSE
MICROSEMI
NX2422
TWO PHASE SYNCHRONOUS PWM CONTROLLER WITH INTEGRATED FET DRIVER, DIFFERENTIAL CURRENT SENSE & 5V BIAS REGULATOR
MICROSEMI
©2020 ICPDF网 联系我们和版权申明