NX2309CMTR [MICROSEMI]
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER; 与NMOS LDO控制器单电源12V同步PWM控制器型号: | NX2309CMTR |
厂家: | Microsemi |
描述: | SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER WITH NMOS LDO CONTROLLER |
文件: | 总16页 (文件大小:445K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Evaluation board available.
NX2309
SINGLE SUPPLY 12V SYNCHRONOUS PWM CONTROLLER
WITH NMOS LDO CONTROLLER
PRELIMINARY DATA SHEET
Pb Free Product
FEATURES
DESCRIPTION
n 12V PWM controller plus LDO controller
The NX2309 controller IC is a combination synchronous
Buck and LDO controller IC designed to convert single
12V supply to low cost dual on board supply applica-
tions. The synchronous controller is used for high cur-
rent high efficiency step down DC to DC converter appli-
cations while the LDO controller in conjunction with an
external low cost N ch MOSFET can be used as a very
low drop out regulator in applications such as converting
3.3V to 2.5V output. Internal UVLO keeps both regula-
tors off until the supply voltage exceeds 9V where inde-
pendent internal digital soft starts get initiated to ramp
up both outputs.The switching section has fixed hiccup
current limit by sensing the Rdson of synchronous
MOSFET. The LDO controller has Feedback Under
Voltage Lock Out as a short circuit protection.Other fea-
tures includes: 12V gate drive capability , Adaptive dead
band control.
n Fixed hiccup current limit by sensing Rdson of
MOSFET
n
12V high side and low side driver
n Fixed internal 300kHz for switching controller
n Dual Independent Digital Soft Start Function
n Adaptive Deadband Control
n Shut Down switching via pulling down COMP pin
n Pb-free and RoHS compliant
APPLICATIONS
n
n
n
PCI Graphic Card on board converters
Mother board On board DC to DC applications
On board Single Supply 12V DC to DC such as
12V to 3.3V, 2.5V or 1.8V
n
Set Top Box and LCD Display
TYPICAL APPLICATION
10
R14
C12
1uF
M3
VOUT1
+1.8V
IRFR3706
VCC
D1 MBR0530T1
L1 1uH
LDO OUT
LDO FB
C9
47uF
VIN1
+12V
C10150pF
C3
47uF
C2
VOUT2
+1.2V/2A
BST
180uF
C4
0.1uF
C8
R8
5k
R9
10k
M1
150uF
25mohm
IRFR3709Z
HDRV
SW
L2 1.5uH
VOUT1
+1.8V/10A
COMP
C7
R5
4SEPC560M
560uF,7mohm
C13
200pF
5.36k
M2
IRFR3709Z
LDRV
C5
R2
1.43k
6.8nF
R3
10k
FB
C6
2.7nF
GND
R4
8k
Figure1 - Typical application of NX2309
ORDERING INFORMATION
Device
NX2309CUTR
NX2309CMTR
Temperature
Package
MSOP - 10L
MLPD - 10L
Frequency
300kHz
300kHz
Pb-Free
Yes
Yes
0 to 70oC
0 to 70oC
Rev. 2.0
12/19/05
1
NX2309
ABSOLUTE MAXIMUM RATINGS(NOTE1)
Vcc to PGND & BST to SW voltage .................... -0.3V to 16V
BST to PGND Voltage ...................................... -0.3V to 35V
SW to PGND .................................................... -2V to 35V
All other pins .................................................... -0.3V to 6.5V
Storage Temperature Range ............................... -65oC to 150oC
Operating Junction Temperature Range ............... -40oC to 125oC
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to
the device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
10-LEAD PLASTIC MLPD
qJA » 52oC/W
qJA » 200oC/W
BST
BST
1
2
3
1
10
9
10
9
SW
SW
HDrv 2
COMP
FB
COMP
FB
HDrv
NC
Gnd
(PAD)
8
3
4
5
Gnd
LDrv
Vcc
8
7
LDO_FB
LDO_OUT
LDO_FB
LDrv
VCC
4
5
7
6
6
LDO_OUT
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =12V, VBST-VSW=12V, and TA = 0 to 70oC. Typical
values refer to TA = 25oC.
PARAMETER
Reference Voltage
Ref Voltage
SYM
Test Condition
Min
TYP
MAX Units
VREF
0.8
0.2
V
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
VCC Supply Current
(Static)
10V<=VCC<=14V
%
VCC
V
7
14
14
ICC (Static) Outputs not switching
5
mA
VCC Supply Current
(Dynamic)
ICC
(Dynamic)
CL=3300PF
17
mA
Supply Voltage(VBST)
VBST Voltage Range
VBST Supply Current
VBST to VSW
V
7
VBST
CL=3300PF
12
mA
(Dynamic)
Under Voltage Lockout
VCC-Threshold
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
6.6
0.3
V
V
VCC-Hysteresis
Rev. 2.0
12/19/05
2
NX2309
PARAMETER
Oscillator
SYM
Test Condition
Min
TYP
MAX Units
Frequency
FS
300
1.1
95
KHz
V
Ramp-Amplitude Voltage
Max Duty Cycle
Min Duty Cycle
Error Amplifiers
Open Loop Gain
Transconductance
Input Bias Current
EN & SS
VRAMP
%
%
0
50
65
dB
umho
nA
gm
Ib
2000
100
Soft Start time
Tss
6.8
0.2
mS
V
Comp SD threshold
High Side Driver, Hdrv, BST,
SW (CL=3300pF)
Output Impedance , Sourcing Rsource(Hdrv)
Current
I=200mA
I=200mA
3.6
1
ohm
ohm
Output Impedance , Sinking
Current
Rsink(Hdrv)
Rise Time
THdrv(Rise)
THdrv(Fall)
10% to 90%
90% to 10%
30
20
50
ns
ns
ns
Fall Time
Deadband Time
Tdead(L to Ldrv going Low to Hdrv going
H)
High, 10% to 10%
Low Side Driver , Ldrv,
PVcc, Pgnd(CL=3300pF)
Output Impedance, Sourcing Rsource(Ldrv)
Current
I=200mA
I=200mA
2.2
1
ohm
ohm
Output Impedance, Sinking
Rsink(Ldrv)
Current
N
Rise Time
TLdrv(Rise)
TLdrv(Fall)
10% to 90%
90% to 10%
30
20
50
ns
ns
ns
Fall Time
Deadband Time
Tdead(H to SW going Low to Ldrv going
L) High, 10% to 10%
LDO Controller
FB Pin- Bias Current
High Output Voltage
Low Output Voltage
High Output Source Current
Low Output Sink Current
Open Loop Gain
nA
V
100
11.1
0.2
1.9
0.9
V
mA
mA
db
%
GBNT(NOTE 2)
50
FB Under Voltage trip point
Fixed OCP
50
OCP Voltage Threshold
240
mV
Rev. 2.0
12/19/05
3
NX2309
NOTE1: In actual circuit application, the ENSW pin is used to program converter start up and hysteresis threshold
voltage.
NOTE2: This parameter is guaranteed by design but not tested in production(GBNT).
PIN DESCRIPTIONS
PIN #
PIN SYMBOL
PIN DESCRIPTION
Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as
possible to and connected to this pin and ground pin. The maximum rating of this
pin is 16V.
5
VCC
This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic
capacitor is placed as close as possible to and connected to this pin and SW
pin.
1
3
8
9
BST
GND
FB
Power ground.
This pin is the error amplifiers inverting input. This pin is connected via resistor
divider to the output of the switching regulator to set the output DC voltage.
COMP
This pin is the output of the error amplifier and together with FB pin is used to
compensate the voltage control feedback loop. This pin is also used as a shut down
pin. When this pin is pulled below 0.2V, both drivers are turned off and internal soft
start is reset.
This pin is connected to source of high side FETs and provide return path for the
high side driver. It is also used to hold the low side driver low until this pin is
brought low by the action of high side turning off. LDRV can only go high if SW is
below 1V threshold .
10
SW
2
4
6
HDRV
LDRV
High side gate driver output.
Low side gate driver output.
LDO_FB
LDO controller feedback input. This pin is connected via resistor divider to the out-
put of the switching regulator to set the output DC voltage.If the LDOFB pin is pulled
below 0.4V, an internal comparator after a delay pulls down LDOOUT pin and ini-
tiates the HICCUP circuitry. During the startup this latch is not activated, allowing
the LDOFB pin to come up and follow the soft started Vref voltage.
7
LDO_OUT
LDO controller output. This pin is controlling the gate of an external NCH MOSFET.
The maximum rating of this pin is 16V.
Rev. 2.0
12/19/05
4
NX2309
BLOCK DIAGRAM
Bias
VCC
Regulator
1.25V
0.8V
Bias
Generator
BST
UVLO
POR
7.2/6.8V
START
HDRV
SW
COMP
0.2V
OC
Control
Logic
START
0.8V
VCC
OSC
ramp
PWM
OC
Digital
start Up
S
R
LDRV
Q
FB
0.6V
CLAMP
1.3V
CLAMP
COMP
240mV
Hiccup Logic
0.4
START
OCP
comparator
GND
LDOFB
LDOOUT
LDO digital
start up
POR
Figure 2 - Simplified block diagram of the NX2309
Rev. 2.0
12/19/05
5
NX2309
APPLICATION INFORMATION
V -VOUT VOUT
1
IN
IRIPPLE
=
´
´
´
LOUT
V
F
S
IN
...(2)
Symbol Used In Application Information:
12V-1.8V 1.8V
1
=
´
= 3.4A
VIN
- Input voltage
- Output voltage
- Output current
1.5uH
12V 300kHz
VOUT
IOUT
Output Capacitor Selection
∆VRIPPLE - Output voltage ripple
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during steady
state(DC) load condition as well as specification for the
load transient. The optimum design may require a couple
of iterations to satisfy both condition.
FS
- Switching frequency
- Inductor current ripple
∆IRIPPLE
Design Example
Power stage design requirements:
VIN=12V
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(3).
VOUT=1.8V
DIRIPPLE
IOUT =10A
DVRIPPLE = ESR´ DIRIPPLE
+
...(3)
8´ F ´ COUT
∆VRIPPLE <=25mV
∆VTRAN<=100mV @ 5A step
FS=300kHz
S
Where ESR is the output capacitors' equivalent
series resistance,COUT is the value of output capacitors.
Typically when large value capacitors are selected
such as Aluminum Electrolytic,POSCAP and OSCON
types are used, the amount of the output voltage ripple
is dominated by the first term in equation(3) and the
second term can be neglected.
Output Inductor Selection
The selection of inductor value is based on induc-
tor ripple current, power rating, working frequency and
efficiency. Larger inductor value normally means smaller
ripple current. However if the inductance is chosen too
large, it brings slow response and lower efficiency. Usu-
ally the ripple current ranges from 20% to 40% of the
output current. This is a design freedom which can be
decided by design engineer according to various appli-
cation requirements. The inductor value can be calcu-
lated by using the following equations:
For this example, OSCON are chosen as output
capacitors, the ESR and inductor current typically de-
termines the output voltage ripple.
DVRIPPLE
DIRIPPLE
25mV
3.4A
ESRdesire
=
=
= 7.3mW
...(4)
If low ESR is required, for most applications, mul-
tiple capacitors in parallel are better than a big capaci-
tor. For example, for 25mV output ripple, OSCON
4SEPC560M with 7mW are chosen.
V -VOUT VOUT
1
IN
LOUT
=
´
´
IRIPPLE
V
F
S
IN
...(1)
IRIPPLE =k ´ IOUTPUT
E S R E ´ DIR IPPLE
N =
...(5)
D VR IPPLE
where k is between 0.2 to 0.4.
Select k=0.4, then
Number of Capacitor is calculated as
12V-1.8V 1.8V
1
7mW´ 3.4A
N =
LOUT
=
´
´
0.4´ 10A 12V 300kHz
LOUT =1.3uH
25mV
N =0.95
Choose LOUT=1.5uH, then coilcraft inductor
DO5010P-152HC is a good choice.
Current Ripple is calculated as
The number of capacitor has to be round up to a
integer. Choose N =1.
Rev. 2.0
12/19/05
6
NX2309
If ceramic capacitors are chosen as output ca-
pacitors, both terms in equation (3) need to be evalu-
ated to determine the overall ripple. Usually when this
type of capacitors are selected, the amount of capaci-
tance per single unit is not sufficient to meet the tran-
sient specification, which results in parallel configura-
tion of multiple capacitors.
put inductor is smaller than the critical inductance, the
voltage droop or overshoot is only dependent on the ESR
of output capacitor. For low frequency capacitor such
as electrolytic capacitor, the product of ESR and ca-
pacitance is high and L £ Lcrit is true. In that case, the
transient spec is mostly like to dependent on the ESR
of capacitor.
For example, one 100uF, X5R ceramic capacitor
with 2mW ESR is used. The amount of output ripple is
Most case, the output capacitor is multiple capaci-
tor in parallel. The number of capacitor can be calcu-
lated by the following
3.4A
DVRIPPLE = 2mW´ 3.4A +
8´ 300kHz´ 100uF
ESRE ´ DIstep
VOUT
N =
where
+
´ t 2
= 6.8mV +14.1mV = 20.9mV
...(9)
DV
2´ L´ CE ´ DV
tran
tran
Although this meets DC ripple spec, however it
needs to be studied for transient requirement.
0
if L £ Lcrit
ì
ï
Based On Transient Requirement
Typically, the output voltage droop during transient
is specified as
t = L´ DI
í
step
...(10)
- ESRE ´ CE
if L ³ Lcrit
ï
VOUT
î
DV
< DV
@step load ∆I
tran
droop
STEP
For example, assume voltage droop during tran-
sient is 100mV for 5A load step.
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section is
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over-
shoot when load from high load to light load with a
∆ISTEP transient load, if assuming the bandwidth of
system is high enough, the overshoot can be esti-
mated as the following equation.
If the OSCON 4SEPC560M (560uF, 7mohm
ESR) is used, the crticial inductance is given as
ESRE ´ CE ´ VOUT
Lcrit
=
=
DIstep
7mW´ 560mF´ 1.8V
=1.42mH
5A
The selected inductor is 1.5uH which is bigger than
critical inductance. In that case, the output voltage tran-
sient not only dependent on the ESR, but also capaci-
tance.
VOUT
DVovershoot = ESR ´ DIstep
+
´ t 2
...(6)
2´ L´ COUT
where is the a function of capacitor,etc.
t
number of capacitor is
0
if L £ Lcrit
ì
ï
L´ DIstep
t =
- ESRE ´ CE
t = L´ DI
í
step
...(7)
...(8)
VOUT
- ESR ´ COUT
if L ³ Lcrit
ï
VOUT
î
1.5mH ´ 5A
=
- 7mW´ 560mF = 0.25us
where
ESR ´ COUT ´ VOUT ESRE ´ CE ´ VOUT
1.8V
Lcrit
=
=
ESRE ´ DIstep
DVtran
VOUT
N =
+
´ t 2
DIstep
DIstep
2´ L´ CE ´ DV
tran
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
7mW´ 5A
1.8V
2´ 1.5mH´ 560mF´ 100mV
=
+
´ (0.25us)2
100mV
= 0.35
The above equation shows that if the selected out-
Rev. 2.0
12/19/05
7
NX2309
The number of capacitors has to satisfied both ripple
and transient requirement. Overall, we choose N=1.
It should be considered that the proposed equa-
tion is based on ideal case, in reality, the droop or over-
shoot is typically more than the calculation. The equa-
tion gives a good start. For more margin, more capaci-
tors have to be chosen after the test. Typically, for high
frequency capacitor such as high quality POSCAP es-
pecially ceramic capacitor, 20% to 100% (for ceramic)
more capacitors have to be chosen since the ESR of
capacitors is so low that the PCB parasitic can affect
the results tremendously. More capacitors have to be
selected to compensate these parasitic parameters.
1
FZ1
FZ2
=
=
=
=
...(11)
...(12)
...(13)
...(14)
2´ p ´ R4 ´ C2
1
2´ p ´ (R2 + R3 )´ C3
1
F
P1
2´ p ´ R3 ´ C3
1
F
P2
C1 ´ C2
2´ p ´ R4 ´
C1 + C2
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
the compensator.
The transfer function of type III compensator for
transconductance amplifier is given by:
Compensator Design
Ve
1- gm ´ Zf
Due to the double pole generated by LC filter of the
power stage, the power system has 180o phase shift ,
and therefore, is unstable by itself. In order to achieve
accurate output voltage and fast transient response,
compensator is employed to provide highest possible
bandwidth and enough phase margin. Ideally, the Bode
plot of the closed loop system has crossover frequency
between 1/10 and 1/5 of the switching frequency, phase
margin greater than 50o and the gain crossing 0dB with -
20dB/decade. Power stage output capacitors usually
decide the compensator type. If electrolytic capacitors
are chosen as output capacitors, type II compensator
can be used to compensate the system, because the
zero caused by output capacitor ESR is lower than cross-
over frequency. Otherwise type III compensator should
be chosen.
=
VOUT
1+ gm ´ Zin + Zin /R1
For the voltage amplifier, the transfer function of
compensator is
Ve
- Zf
=
VOUT
Zin
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R4>>2/gm.And it would be desir-
able if R1||R2||R3>>1/gm can be met at the same time,
Zf
Vout
Zin
R3
C1
C2
R4
R2
R1
C3
A. Type III compensator design
Fb
For low ESR output capacitors, typically such as
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the cross-
over frequency. In this case, it is necessary to compen-
sate the system with type III compensator. The follow-
ing figures and equations show how to realize the type III
compensator by transconductance amplifier.
Ve
gm
Vref
Figure 3 - Type III compensator using
transconductance amplifier
Rev. 2.0
12/19/05
8
NX2309
Case 1: FLC<FO<FESR(for most ceramic or low
ESR POSCAP, OSCON)
2. Set R2 equal to 10kW.
R2 ´ VREF
10kW´ 0.8V
R1=
=
= 8kW
VOUT -VREF
1.8V-0.8V
Choose R1=8.06kW.
3. Set zero FZ2 = FLC and Fp1 =FESR, calculate C3.
power stage
LC
F
1
1
1
C3 =
´ (
-
)
40dB/decade
2´ p ´ R2
F
F
p1
z2
1
1
1
=
´ (
-
)
2´ p ´ 10kW 5.5kHz 40.6kHz
=2.5nF
loop gain
ESR
F
Choose C3=2.7nF.
4. Calculate R4 with the crossover frequency at 1/
10~ 1/5 of the switching frequency. Set FO=30kHz.
20dB/decade
compensator
VOSC 2´ p ´ FO ´ L
R4 =
´
´ Cout
V
C3
1.1V 2´ p ´ 30kHz´ 1.5uH
in
=
´
´ 560uF
12V
=5.38kW
2.7nF
FZ1
FO
FP2
FZ2
F
P1
Choose R4=5.36kW.
5. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
Figure 4 - Bode plot of Type III compensator
(FLC<FO<FESR
1
)
C2 =
2´ p ´ FZ1 ´ R4
Typical design example of type III compensator in
which the crossover frequency is selected as
FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the
following steps.
1
=
2´ p ´ 0.75´ 5.5kHz ´ 5.36kW
= 7.1nF
Choose C2=6.8nF.
1. Calculate the location of LC double pole FLC
6. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
and ESR zero FESR
.
1
1
F
=
=
LC
C1 =
2´ p ´
L
OUT ´ COUT
2´ p ´ R4 ´ F
P2
1
1
=
2´ p ´ 1.5uH´ 560uF
2´ p ´ 5.36kW´ 150kHz
= 197pF
= 5.5kHz
Choose C1=200pF.
1
FESR
=
7. Calculate R3 by equation (13) with Fp1 =FESR.
2 ´ p ´ ESR ´ COUT
1
=
2 ´ p ´ 7mW´ 560uF
= 40.6kHz
Rev. 2.0
12/19/05
9
NX2309
1
1
R3 =
F
=
=
2´ p ´ F ´ C3
ESR
P1
2´ p ´ ESR´ COUT
1
1
=
2´ p ´ 40.6kHz´ 2.5nF
=1.45kW
2´ p ´ 15mW´ 2000uF
= 5.3kHz
Choose R3 =1.43kW.
2. Set R2 equal to 15kW.
Case 2: FLC<FESR<FO(for electrolytic capacitors)
R2 ´ VREF
15kW´ 0.8V
R1=
=
= 12kW
power stage
VOUT -VREF
1.8V-0.8V
LC
F
Choose R1=12kW.
3. Set zero FZ2 = FLC and Fp1 =FESR
4. Calculate C3 .
.
40dB/decade
ESR
F
1
1
1
C3 =
´ (
-
)
2´ p ´ R2
Fz2
F
p1
loop gain
1
1
1
=
´ (
-
)
2´ p ´ 15kW 1.8kHz 5.3kHz
=2.4nF
20dB/decade
Choose C3=2.7nF.
5. Calculate R3 .
compensator
1
R3 =
2´ p ´ F ´ C3
P1
1
=
2´ p ´ 5.3kHz ´ 2.7F
FZ1
FO
FP2
FZ2
F
P1
= 11.1k W
Figure 5 - Bode plot of Type III compensator
(FLC<FESR<FO)
Choose R3 =11kW.
6. Calculate R4 with FO=30kHz.
VOSC 2 ´ p ´ FO ´ L R2 ´ R3
If electrolytic capacitors are used as output
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<FESR<FO and FO<=1/10~1/5Fs is shown
as the following steps. Here two SANYO MV-WG1000
with 30 mW is chosen as output capacitor, output inductor
is 2.2uH. See figure 18.
R4 =
´
´
V
ESR
R2 + R3
in
1.1V 2 ´ p ´ 30kHz ´ 2.2uH 15kW´ 11kW
=
´
´
12V
=16kW
Choose R4=16kW.
15mW
15kW+ 11k W
7. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
1. Calculate the location of LC double pole FLC
1
and ESR zero FESR
.
C2 =
2 ´ p ´ FZ1 ´ R4
1
1
F
=
=
LC
2´ p ´
L
OUT ´ COUT
2 ´ p ´ 0.75 ´ 1.8kHz ´ 16kW
= 4.2nF
1
=
Choose C2=4.7nF.
2´ p ´ 2.2uH´ 2000uF
= 1.8kHz
8. Calculate C1 by equation (14) with pole Fp2 at
half the switching frequency.
Rev. 2.0
12/19/05
10
NX2309
1
C1 =
2 ´ p ´ R4 ´ FP2
power stage
loop gain
1
=
2 ´ p ´ 16kW´ 150kHz
= 66pF
40dB/decade
Choose C1=68pF.
B. Type II compensator design
If the electrolytic capacitors are chosen as power
stage output capacitors, usually the Type II compensa-
tor can be used to compensate the system.
For this type of compensator, FO has to satisfy
FLC<FESR<<FO<=1/10~1/5Fs.
20dB/decade
compensator
Gain
Case 1:
Type II compensator can be realized by simple
RC circuit as shown in figure 14. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
P
F
F
F
Z
LCFESR
FO
pole to suppress the switching noise.
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
Figure 6 - Bode plot of Type II compensator
C2
satisfy this condition: R3>>1/gm and R1||R2>>1/gm. The
following equations show the compensator pole zero lo-
cation and constant gain.
Vout
C1
R3
R2
Fb
R3
Ve
Gain=
... (15)
... (16)
... (17)
R2
R1
1
Vref
F =
z
2´ p ´ R3 ´ C1
1
F »
p
2´ p ´ R3 ´ C2
Figure 7 - Type II compensator with
transconductance amplifier(case 1)
The following parameters are used as an ex-
ample for type II compensator design, three 1500uF
with 19mohm Sanyo electrolytic CAP 6MV1500WGL
are used as output capacitors. Coilcraft DO5010P-
152HC 1.5uH is used as output inductor. See figure
19. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=300kHz.
1.Calculate the location of LC double pole FLC
and ESR zero FESR
.
Rev. 2.0
12/19/05
11
NX2309
Case 2:
1
F
=
=
Type II compensator can also be realized by simple
RC circuit without feedback as shown in figure 15. R3
and C1 introduce a zero to cancel the double pole effect.
C2 introduces a pole to suppress the switching noise.
The following equations show the compensator pole zero
location and constant gain.
LC
2´ p ´
L
OUT ´ COUT
1
2´ p ´ 1.5uH´ 4500uF
= 1.94kHz
1
F
=
ESR
2´ p ´ ESR´ COUT
R1
Gain=gm ´
´ R3
... (18)
... (19)
... (20)
1
R1+R2
=
2´ p ´ 6.33mW´ 4500uF
1
= 5.6kHz
F =
z
2´ p ´ R3 ´ C1
2.Set crossover frequency FO=30kHz>>FESR
.
1
F »
p
3. Set R2 equal to10kW. Based on output voltage,
using equation 21, the final selection of R1 is 20kW.
4.Calculate R3 value by the following equation.
2´ p ´ R3 ´ C2
VO S C 2 ´ p ´ FO ´ L
Vout
R 3 =
´
´ R 2
Vin
E S R
R2
1.1V 2 ´ p ´ 30kHz ´ 1.5uH
=
´
´ 10kW
Fb
12V
=37.2kW
6.33m W
Ve
R3
gm
R1
Vref
Choose R3 =37.4kW.
C2
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
C1
1
C1=
2´ p ´ R3 ´ F
z
Figure 8 - Type II compensator with
1
=
2´ p ´ 37.4kW´ 0.75´ 1.94kHz
transconductance amplifier(case 2)
=2.9nF
The following is parameters for type II compensa-
tor design. Input voltage is 12V, output voltage is 2.5V,
output inductor is 2.2uH, output capacitors are two 680uF
with 41mW electrolytic capacitors. See figure 20.
1.Calculate the location of LC double pole FLC
Choose C1=2.7nF.
F
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
p
1
C 2 =
p ´ R ´ Fs
3
and ESR zero FESR
.
1
=
p ´ 3 7 . 4k W ´ 1 5 0 k H z
1
F
=
LC
= 5 7 p F
2´ p ´
L
OUT ´ COUT
1
Choose C2=56pF.
=
2´ p ´ 2.2uH´ 1360uF
= 2.9kHz
Rev. 2.0
12/19/05
12
NX2309
0.8V. The divider consists of two ratioed resistors so
that the output voltage applied at the Fb pin is 0.8V when
the output voltage is at the desired value. The following
equation applies to figure 9, which shows the relation-
ship between VOUT , VREF and voltage divider.
1
F
=
=
ESR
2´ p ´ ESR´ COUT
1
2´ p ´ 20.5mW´ 1360uF
= 5.7kHz
2.Set R2 equal to10kW. Using equation 18, the fi-
nal selection of R1 is 4.7kW.
Vout
3. Set crossover frequency at 1/10~ 1/5 of the
swithing frequency, here FO=30kHz.
R2
Fb
4.Calculate R3 value by the following equation.
R1
Vref
VOSC 2´ p ´ FO ´ L
VOUT
1
R3 =
´
´
´
V
RESR
gm VREF
in
1.1V 2´ p ´ 30kHz´ 2.2uH
1
Figure 9 - Voltage divider
=
´
´
12
20.5mW
2mA/V
2.5V
0.8V
=2.9kW
R 2 ´ VREF
´
R1=
...(21)
VOUT -VREF
where R2 is part of the compensator, and the
value of R1 value can be set by voltage divider.
See compensator design for R1 and R2 selection.
Choose R3 =2.87kW.
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
Input Capacitor Selection
1
C1=
Input capacitors are usually a mix of high frequency
ceramic capacitors and bulk capacitors. Ceramic ca-
pacitors bypass the high frequency noise, and bulk ca-
pacitors supply switching current to the MOSFETs. Usu-
ally 1uF ceramic capacitor is chosen to decouple the
high frequency noise.The bulk input capacitors are de-
cided by voltage rating and RMS current rating. The RMS
current in the input capacitors can be calculated as:
2´ p ´ R3 ´ F
z
1
=
2´ p ´ 2.87kW´ 0.75´ 2.9kHz
=25nF
Choose C1=27nF.
F
6. Calculate C2 by setting compensator pole
at half the swithing frequency.
p
1
C 2 =
IRMS = IOUT
´
D ´ 1-D
p ´ R 3 ´ Fs
VOUT
1
D =
=
V
p ´ 2 .87k W ´ 1 5 0 k H z
IN
...(22)
= 3 6 9 p F
VIN = 12V, VOUT=1.8V, IOUT=10A, using equation
(19), the result of input RMS current is 3.6A.
For higher efficiency, low ESR capacitors are
recommended.
Choose C2=390pF.
One Sanyo OS-CON 16SVP180M 16V 180uF
20mW with 3.64A RMS rating are chosen as input bulk
capacitors.
Output Voltage Calculation
Output voltage is set by reference voltage and ex-
ternal voltage divider. The reference voltage is fixed at
Rev. 2.0
12/19/05
13
NX2309
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Power MOSFETs Selection
The NX2309 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
Over Current Limit Protection
Over current Limit for step down converter is
achieved by sensing current through the low side
MOSFET. For NX2309, the current limit is decided by
the RDSON of the low side mosfet. When synchronous
FET is on, and the voltage on SW pin is below 240mV,
the over current occurs. The over current limit can be
calculated by the following equation.
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two IRFR3706 are
used.They have the following parameters: VDS=30V, ID
=75A,RDSON =9mW,QGATE =23nC.
There are two factors causing the MOSFET power
loss:conduction loss, switching loss.
Conduction loss is simply defined as:
ISET = 240mV/RDSON
The MOSFET RDSON is calculated in the worst case
situation, then the current limit for MOSFET IRFR3706
is
P
HCON =IOUT2 ´ D´ RDS(ON) ´ K
LCON=IOUT2 ´ (1- D)´ RDS(ON) ´ K
PTOTAL =P + P
P
240mV
RDSON
240mV
...(23)
ISET
=
=
= 17A
1.4´ 9mW
HCON
LCON
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected for
the worst case, in which K approximately equals to 1.4
at 125oC according to IRFR3706 datasheet. Conduction
loss should not exceed package rating or overall sys-
tem thermal budget.
LDO Selection Guide
NX2309 offers a LDO controller. The selection of
MOSFET to meet LDO is more straight forward. The
selection is that the Rdson of MOSFET should meet the
dropout requirement. For example.
VLDOIN =1.8V
VLDOOUT =1.2V
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
ILoad =2A
The maximum Rdson of MOSFET should be
RRDSON = (VLDOIN - VLDOOUT )´ ILOAD
= (1.8V - 1.2V) / 2A = 0.3W
1
PSW
=
´ V ´ IOUT ´ TSW ´ F
IN S
...(24)
2
Most of MOSFETs can meet the requirement. More
important is that MOSFET has to be selected right pack-
age to handle the thermal capability. For LDO, maxi-
mum power dissipation is given as
and TF which can be found in mosfet datasheet, and FS
is switching frequency. Swithing loss PSW is frequency
dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined as:
PLOSS = (VLDOIN - VLDOOUT )´ ILOAD
= (1.8V- 1.2V)´ 2A =1.2W
Select IR MOSFET IRFR3706 with 9mW RDSON is
sufficient.
P
= (QHGATE ´ VHGS + QLGATE ´ VLGS )´ FS
...(25)
gate
LDO Compensation
where QHGATE is the high side MOSFETs gate
The diagram of LDO controller including VCC regu-
charge,QLGATE is the low side MOSFETs gate charge,VHGS
is the high side gate source voltage, and VLGS is the low
side gate source voltage.
lator is shown in above figure 9. For low frequency ca-
Rev. 2.0
12/19/05
14
NX2309
pacitor such as electrolytic, POSCAP, OSCON, etc, The
compensation parameter can be calculated as follows.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
gm ´ ESR
1
CC =
´
2´ p ´ FO ´ Rf1 1+gm ´ ESR
where FO is the desired loop gain.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side MOSFET,
inductor and output capacitors. A noisy environment is
generated by the power components due to the switch-
ing power. Small signal components are connected to
sensitive pins or nodes. A multilayer layout which in-
cludes power plane, ground plane and signal plane is
recommended .
LDO input
Vref
R
f1
ESR
R
f2
Rload
Rc
Cc
Co
Layout guidelines:
Figure 10 - NX2309 LDO controller.
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps to
reduce the EMI radiated by the power loop due to the
high switching currents through them.
Typically, FO has to be higher than zero caused by
ESR. FO is typically around several tens kHz to a few
hundred kHz. For this example, we select Fo=100kHz.
gm is the forward trans-conductance of MOSFET.
For IRFR3706, gm=53.
2. Low ESR capacitor which can handle input RMS
ripple current and a high frequency decoupling ceramic
cap which usually is 1uF need to be practically touch-
ing the drain pin of the upper MOSFET, a plane connec-
tion is a must.
Select Rf1=5kohm.
Output capacitor is Sanyo POSCAP 4TPE150MI
with 150uF, ESR=18mohm.
1
53´ 18mW
CC =
´
=155pF
2´ p ´ 100kHz´ 5kW 1+53´ 18mW
3. The output capacitors should be placed as close
as to the load as possible and plane connection is re-
quired.
Choose CC=150pF.
For electrolytic or POSCAP, RC is typically selected
to be zero.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a plane
ans as close as possible.A snubber nedds to be placed
as close to this junction as possible.
Rf2 is determined by the desired output voltage
Rf 2 = Rf1 ´ VREF /(VLDOOUT - VREF
= 5kW´ 0.8V /(1.2V - 0.8) =10kW
Choose Rf2=10kW.
)
5. Source of the lower MOSFET needs to be con-
nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to the
output capacitors and input capacitors.
Current Limit for LDO
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
Current limit of LDO is achieved by sensing the
LDO feedback voltage. When LDO_FB pin is below 0.4V,
the IC goes into hiccup mode. The IC will turn off all the
channel for 2048 cycles and start to restart system again.
Rev. 2.0
12/19/05
15
NX2309
7. Vcc capacitor, BST capacitor or any other by-
passing capacitor needs to be placed first around the IC
and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive ana-
log control function.
Rev. 2.0
12/19/05
16
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明