RT3PE600L-CQ256YB_技术文档

1 – Radiation-Tolerant ProASIC3 Low Power

Spaceflight FPGA Overview

General Description

The radiation-tolerant (RT) ProASIC3 family of Microsemi flash FPGAs dramatically reduces dynamic

power consumption by 40% and static power by 50%. These power savings are coupled with

performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and

advanced features. The RT ProASIC3 FPGA is based on the ProASIC3EL family of low power FPGAs.

Microsemi's proven Flash*Freeze technology enables RT ProASIC3 device users to shut off dynamic

power instantaneously and switch the device to static mode without the need to switch off clocks or

power supplies, and retaining internal states of the device. This greatly simplifies power management. In

addition, optimized software tools using power-driven layout provide instant push-button power

reduction.

Nonvolatile flash technology gives RT ProASIC3 devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). RT ProASIC3 devices offer dramatic dynamic power

savings, giving FPGA users flexibility to combine low power with high performance.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

RT ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). RT ProASIC3

devices support devices from 600 k system gates to 3 million system gates with up to 504 kbits of true

dual-port SRAM and 620 user I/Os.

Flash*Freeze Technology

RT ProASIC3 devices offer the proven Flash*Freeze technology, which allows instantaneous switching

from an active state to a static state. When Flash*Freeze mode is activated, RT ProASIC3 devices enter

a static state while retaining the contents of registers and SRAM. Power is conserved without the need

for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined with

in-system programmability, which enables users to quickly and easily upgrade and update their designs

in the final stages of manufacturing or in the field. The ability of RT ProASIC3 devices to support a 1.2 V

core voltage allows for an even greater reduction in power consumption, which enables low total system

power.

When the RT ProASIC3 device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is

retained.

The availability of low power modes, combined with a reprogrammable, single-chip, single-voltage

solution, make RT ProASIC3 devices suitable for low power data transfer and manipulation in military-

temperature applications where available power may be limited (e.g., in battery-powered equipment); or

where heat dissipation may be limited (e.g., in enclosures with no forced cooling).

Flash Advantages

Low Power

The RT ProASIC3 family of flash-based FPGAs provides a low power advantage, and when coupled with

high performance, enables designers to make power-smart choices using

reprogrammable, and live-at-power-up device.

a

single-chip,

RT ProASIC3 devices offer 40% dynamic power and 50% static power savings by reducing the core

operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero^®System-on-Chip

(SoC) software offers up to 30% additional power reduction. With Flash*Freeze technology, an RT

ProASIC3 device is able to retain device SRAM and logic while dynamic power is reduced to a minimum,

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Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview

without the need to stop clock or power supplies. Combining these features provides a low power,

feature-rich, and high-performance solution.

Security

Nonvolatile, flash-based RT ProASIC3 devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. RT ProASIC3 devices incorporate FlashLock, which

provides a unique combination of reprogrammability and design security without external overhead,

advantages that only an FPGA with nonvolatile flash programming can offer.

RT ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest

level of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in RT ProASIC3 devices can be encrypted prior to loading, using the

industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the

National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. RT

ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the

most comprehensive programmable logic device security solution available today. RT ProASIC3 devices

with AES-based security provide a high level of protection for remote field updates over public networks

such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves.

Security, built into the FPGA fabric, is an inherent component of the RT ProASIC3 family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. The RT ProASIC3 family, with FlashLock and AES security,

is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected

with industry-standard security, making remote ISP possible. An RT ProASIC3 device provides the best

available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based RT ProASIC3

FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load

device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and

system reliability.

Live at Power-Up

Flash-based RT ProASIC3 devices support Level 0 of the LAPU classification standard. This feature

helps in system component initialization, execution of critical tasks before the processor wakes up, setup

and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature

of flash-based RT ProASIC3 devices greatly simplifies total system design and reduces total system

cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and

brownouts in system power will not corrupt the device's flash configuration, and unlike SRAM-based

FPGAs, the device will not have to be reloaded when system power is restored. This enables the

reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout

detection, and clock generator devices from the PCB design. Flash-based RT ProASIC3 devices simplify

total system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based RT ProASIC3 devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms are designed to prevent access to all

the programming information and enable the highest level of security available for remote updates of the

FPGA logic. Designers can perform remote in-system reprogramming to support future design iterations

and field upgrades with confidence that valuable intellectual property is protected and very unlikely to be

compromised or copied. ISP can be performed using the industry-standard AES algorithm. The RT

ProASIC3 family device architecture mitigates the need for ASIC migration at higher volumes. This

makes the RT ProASIC3 family a cost-effective ASIC replacement.

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Advanced Flash Technology

The RT ProASIC3 family offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary RT ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The

RT ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the RT ProASIC3 core tile, as either a three-input lookup table (LUT)

equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are

connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the

device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is

possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming

of RT ProASIC3 devices via an IEEE 1532 JTAG interface.

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

ISP AES

Decryption*

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Figure 1-1 • RT ProASIC3 Device Architecture Overview

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Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview

Flash*Freeze Technology

RT ProASIC3 devices offer proven Flash*Freeze technology, which enables designers to

instantaneously shut off dynamic power consumption while retaining all SRAM and register information.

Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by

activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition,

I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks

can still be driven or can be toggling without impact on power consumption; all core registers and SRAM

cells retain their states. I/Os are tristated during Flash*Freeze mode or can be set to a certain state using

weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks,

JTAG pins, or PLLs. Flash*Freeze technology allows the user to switch to active mode on demand, thus

simplifying the power management of the device.

The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is

safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode

usage is not planned, which is advantageous because of the inherent low power static and dynamic

capabilities of the RT ProASIC3 device. Refer to Figure 1-2 for an illustration of entering/exiting

Flash*Freeze mode.

Actel RT ProASIC3

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-2 • RT ProASIC3 Flash*Freeze Mode

VersaTiles

The RT ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®

core tiles. The RT ProASIC3 VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

User Nonvolatile FlashROM

RT ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM

can be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

FlashROM is written using the standard RT ProASIC3 IEEE 1532 JTAG programming interface. The core

can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to provide a high level of security when loading data over public networks, as in security keys

stored in the FlashROM for a user design.

FlashROM can be programmed via the JTAG programming interface, and its contents can be read back

either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and

which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The RT ProASIC3 development software solution, Libero SoC, has extensive support for the FlashROM.

One such feature is auto-generation of sequential programming files for applications requiring a unique

serial number in each part. Another feature allows the inclusion of static data for system version control.

Data for the FlashROM can be generated quickly and easily using Libero SoC software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

RT ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit port and

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

RT ProASIC3 space-flight FPGAs provide designers with flexible clock conditioning circuit (CCC)

capabilities. Each member of the RT ProASIC3 family contains six CCCs, located at the four corners and

the centers of the east and west sides. All six CCC blocks are equipped with a PLL. All six CCC blocks

are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock

spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

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Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Overview

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time is 300 µs

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f_{OUT_CCC}

Global Clocking

RT ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The RT ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for RT ProASIC3 devices. RT

ProASIC3 FPGAs support different I/O standards, including single-ended, differential, and voltage-

referenced. The I/Os are organized into banks, with eight banks per device. The configuration of these

banks determines the I/O standards supported. For RT ProASIC3, each I/O bank is subdivided into V_REF

minibanks, which are used by voltage-referenced I/Os. V_REFminibanks contain 8 to 18 I/Os. All the I/Os

in a given minibank share a common V_REFline. Therefore, if any I/O in a given V_REFminibank is

configured as a V_REFpin, the remaining I/Os in that minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-data-rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

RT ProASIC3 banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support

up to 20 loads.

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2 – Radiation-Tolerant ProASIC3 Low Power

Spaceflight Flash FPGAs DC and Switching

Characteristics

General Specifications

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

absolute maximum ratings are stress ratings only; functional operation of the device at these or any other

conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on

page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

V

VJTAG

VPUMP

VCCPLL

Programming voltage

Analog power supply (PLL)

VCCI and VMV²DC I/O buffer supply voltage

VI

I/O input voltage

–0.3 V to 3.6 V (when I/O hot insertion mode is

enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is

lower (when I/O hot-insertion mode is disabled)

T_STG

T_J

Storage temperature

Junction temperature

–65 to +150

+150

°C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7.

2. VMV pins must be connected to the corresponding VCCI pins. Refer to the "Pin Descriptions" section on page 3-1 for

further information.

3. For recommended operating limits, refer to Table 2-2 on page 2-2.

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions^1,2

Symbol

T_A

Parameter

Ambient temperature

Military

–55 to 125

1.425 to 1.575

1.14 to 1.575

1.4 to 3.6

Units

°C

V

T_J

Junction temperature

VCC⁶

1.5 V DC core supply voltage³

1.2 – 1.5 V Wide Range DC core supply voltage⁴

JTAG DC voltage

V

VJTAG⁶

V

VPUMP^5,6

Programming voltage

Programming mode

3.15 to 3.45

0

V

Operation

V

VCCPLL⁶

Analog power supply (PLL)

1.5 V DC core supply voltage³

1.425 to 1.575

V

1.2 – 1.5 V DC core supply voltage⁴1.14 to 1.575

V

VCCI and VMV⁶1.2 V DC supply voltage⁴

1.2 V Wide Range DC supply voltage⁴

1.14 to 1.26

1.14 to 1.575

1.425 to 1.575

1.7 to 1.9

V

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.0 V DC supply voltage⁷

3.3 V DC supply voltage

LVDS differential I/O

V

2.3 to 2.7

V

2.7 to 3.6

3.0 to 3.6

V

2.375 to 2.625

3.0 to 3.6

LVPECL differential I/O

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

3. For RT ProASIC3 devices operating at VCC = 1.5 V core voltage.

4. For RT ProASIC3 devices operating at VCC = 1.2 V core voltage and VCCI ≥ VCC.

5. VPUMP should be tied to 0 V to optimize total ionizing dose performance during operation in spaceflight applications.

6. See the "Pin Descriptions" section on page 3-1 for instructions and recommendations on tie-off and supply grouping.

7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

8. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard

are given in Table 2-18 on page 2-20.

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

110

100

90

80

70

60

50

40

30

20

10

0

HTR

Lifetime

(yrs)

Tj (°C)

70

85

100

105

102.7

43.8

20.0

15.6

110

115

120

125

130

12.3

9.7

7.7

6.2

5.0

135

140

145

150

4.0

3.3

2.7

2.2

70 85 100 105 110 115 120 125 130 135 140 145 150

Temperature (ºC)

Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.

Figure 2-1 • High-Temperature Data Retention (HTR)

Table 2-3 • Overshoot and Undershoot Limits

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/Undershoot

VCCI and VMV

(125ºC)

0.72 V

0.82 V

0.72 V

0.81 V

0.69 V

0.70 V

N/A

2.7 V or less

10%

5%

3 V

10%

5%

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

N/A

1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

2. This table does not provide PCI overshoot/undershoot limits.

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

Sophisticated power-up management circuitry is designed into every ProASIC^®3 device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2

on page 2-5 and Figure 2-3 on page 2-6.

There are five regions to consider during power-up.

RT ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5 and

Figure 2-3 on page 2-6).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and Figure 2-

3 on page 2-6 for more details).

When PLL power supply voltage and/or VCC levels drop below the V_CCbrownout levels (0.75 V

± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-

Down Behavior of Low Power Flash Devices" chapter of the Radiation-Tolerant ProASIC3 FPGA Fabric

User’s Guide for information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

V

= 0.85 V ± 0.25 V

a

Deactivation trip point:

= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

V

d

VCCI

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

Min VCCI datasheet specification

V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

a

V

= 0.8 V ± 0.3 V

d

Figure 2-2 • Devices Operating at 1.5 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage

Levels

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

(except differential inputs)

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Activation trip point:

V

= 0.85 V ± 0.2 V

a

Deactivation trip point:

Region 1: I/O buffers are OFF

V

= 0.75 V ± 0.2 V

d

VCCI

Activation trip point:

= 0.9 V ± 0.15 V

Deactivation trip point:

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

V

a

V

= 0.8 V ± 0.15 V

d

Figure 2-3 • Devices Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage

Levels

2-6

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Thermal Characteristics

Introduction

The temperature variable in the Libero SoC software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction temperature to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = ΔT + T_A

EQ 1

where:

T_A= Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θ_ja* P

θ_ja= Junction-to-ambient of the package. θ_janumbers are located in Table 2-4.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θ_jcand the junction-to-ambient air thermal resistivity is

θ_ja. The thermal characteristics for θ_jaare shown for two air flow rates. The recommended maximum

junction temperature is 125°C. EQ 2 shows a sample calculation of the recommended maximum power

dissipation allowed for a 484-pin CCGA package with the junction at 125°C and with the case

temperature maintained at 70°C.

Max. junction temp. (°C) – Max. case temp. (°C)

Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------

θ_jc(°C/W)

EQ 2

Table 2-4 • Package Thermal Resistivities

θ_ja

Package Type

Device

Count θ_jb

θ_jcStill Air 200 ft./min. 500 ft./min. Units

Ceramic Column Grid Array (CCGA) RT3PE600L

484

TBD TBD

TBD

11.9

TBD

C/W

RT3PE3000L 484

RT3PE3000L 896

TBD TBD

3.5 2.8

Temperature and Voltage Derating Factors

Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 125°C, VCC = 1.14 V)

Junction Temperature

Array Voltage VCC (V)

–55°C

0.86

0.82

0.79

0.77

0.74

0.71

0.70

0.66

0.63

–40°C

0.87

0.83

0.80

0.77

0.75

0.72

0.70

0.67

0.64

0°C

0.90

0.86

0.83

0.80

0.77

0.74

0.73

0.69

0.67

25°C

0.92

0.88

0.84

0.82

0.79

0.76

0.75

0.71

0.68

70°C

85°C

0.97

0.93

0.89

0.87

0.84

0.80

0.79

0.75

0.72

125°C

1.14

1.2

0.96

0.92

0.88

0.86

0.83

0.79

0.78

0.74

0.71

1.00

0.96

0.92

0.90

0.86

0.83

0.82

0.77

0.74

1.26

1.3

1.35

1.4

1.425

1.5

1.575

Revision 5

2-7

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Calculating Power Dissipation

Quiescent Supply Current

Table 2-6 • Power Supply State per Mode

Power Supply Configurations¹

Modes/Power Supplies

Flash*Freeze³

Sleep

VCC

On

VCCPLL

On

VCCI

On

VJTAG

On

VPUMP²

On/off/floating

Off

On

Off

Shutdown

Off

Static and Active³

On

On/off/floating

Notes:

1. Off: Power Supply level = 0 V.

2. VPUMP should be tied to 0 V to optimize total ionizing dose performance during operation in spaceflight applications.

3. Even though the power supply configuration in Flash*Freeze and Static and Active mode is the same, the device’s

clocks and inputs are shut off in Flash*Freeze mode.

Table 2-7 • Quiescent Supply Current (IDD) Characteristics, Flash*Freeze Mode^*

Core Voltage

1.2 V

RT3PE600L

RT3PE3000L

Units

mA

Nominal (25°C)

0.55

0.83

9

2.75

4.2

17

1.5 V

Typical maximum (25°C)

Military maximum (125°C)

1.2 V

1.5 V

12

20

1.2 V

65

165

185

1.5 V

85

Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Under Flash*Freeze conditions, VCCI, VPUMP.

and VCCPLL currents are negligible. Values do not include I/O static contribution (PDC6 and PDC7).

Table 2-8 • Quiescent Supply Current (IDD) Characteristics, Sleep Mode (VCC = 0 V)*

Core Voltage

RT3PE600L

RT3PE3000L

Units

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

1.8

1.9

2.2

2.5

1.8

1.9

2.2

2.5

µA

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

Note: IDD = N

× ICCI. Values do not include I/O static contribution (PDC6 and PDC7), which is shown in Table 2-15

BANKS

on page 2-13.

2-8

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-9 • Quiescent Supply Current (IDD) Characteristics Shutdown Mode

Core Voltage

1.2 V / 1.5 V

RT3PE600L

RT3PE3000L

Units

µA

Nominal (25°C)

Military (125ºC)

0

µA

Table 2-10 • Quiescent Supply Current (IDD), Static Mode and Active Mode¹

Core Voltage

RT3PE600L

RT3PE3000L

Units

ICCA Current²

Nominal (25°C)

1.2 V

1.5 V

1.2 V

1.5 V

1.2 V

1.5 V

0.55

0.83

9

2.75

4.2

17

mA

Typical maximum (25°C)

Military maximum (125°C)

ICCI or IJTAG Current³

12

20

65

165

185

85

VCCI / VJTAG = 1.2 V (per bank)

Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI / VJTAG = 1.5 V (per bank)

Typical (25°C)

1.2 V / 1.5 V

VCCI / VJTAG = 1.8 V (per bank)

Typical (25°C)

VCCI / VJTAG = 2.5 V (per bank)

Typical (25°C)

VCCI / VJTAG = 3.3 V (per bank)

Typical (25°C)

Notes:

1. IDD = NBANKS × ICCI + ICCA. JTAG counts as one bank when powered.

2. Includes VCC , VCCPLL, and VPUMP currents. VPUMP and VCCPLL currents are negligible.

3. Values do not include I/O static contribution (PDC6 and PDC7).

Revision 5

2-9

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Power per I/O Pin

Table 2-11 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Static Power Dynamic Power PAC9

VCCI (V) PDC6 (mW)¹

(µW/MHz)²

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

3.3 V LVCMOS Wide Range

3.3 V LVCMOS – Schmitt trigger Wide Range

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

3.3

–

16.34

24.49

16.34

24.49

4.71

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

6.13

1.66

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

1.2 V LVCMOS³

1.2 V LVCMOS (JESD8-11) – Schmitt trigger³

1.2 V LVCMOS Wide Range³

1.2 V LVCMOS Schmitt trigger Wide Range³

3.3 V PCI

1.78

1.01

0.97

0.60

0.53

0.60

0.53

17.76

19.10

17.76

19.10

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

3.3

2.90

2.13

2.81

2.57

0.17

1.38

3.21

7.14

3.54

2.91

2.61

0.79

3.26

7.97

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

2.5

3.3

2.26

5.71

0.89

1.94

LVPECL

Notes:

1. PDC6 is the static power measured on VCCI for voltage referenced and differential I/O standards. Single-ended I/O

standards do not have the PDC6 static component. Refer to the "Power Calculation Methodology" section on page 2-13

for details on how to calculate total static and dynamic power.

2. PAC9 is the total dynamic power measured on VCCI.

3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V and VCCI ≥ VCC.

2-10

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Static Power

PDC7 (mW)²

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

3.3 V PCI

5

3.3

2.5

1.8

1.5

1.2

3.3

–

148.00

83.23

54.58

37.05

17.94

5

10

204.61

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

10

20

30

3.3

2.5

3.3

2.5

1.5

2.5

3.3

–

24.08

13.52

24.10

13.54

26.22

27.18

105.65

116.48

114.67

131.69

2.5 V GTL

–

3.3 V GTL+

–

2.5 V GTL+

–

HSTL (I)

7.08

13.88

16.69

25.91

26.02

42.21

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS

–

2.5

3.3

7.70

89.58

LVPECL

19.42

167.86

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power measured on VCCI for voltage referenced and differential I/O standards. Single-ended I/O

standards do not have the PDC7 static component. Refer to the "Power Calculation Methodology" section on page 2-13

for details on how to calculate total static and dynamic power.

3. PAC10 is the total dynamic power measured on VCCI.

Revision 5

2-11

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-13 • Different Components Contributing to Dynamic Power Consumption in Devices Operating at

1.2 V VCC

Device-Specific Dynamic Power

(µW/MHz)

Parameter

PAC1

Definition

RT3PE3000L

8.34

RT3PE600L

3.99

Clock contribution of a Global Rib

PAC2

Clock contribution of a Global Spine

4.28

2.22

PAC3

Clock contribution of a VersaTile row

0.94

PAC4

Clock contribution of a VersaTile used as a sequential module

First contribution of a VersaTile used as a sequential module

0.08

PAC5

0.05

0.19

PAC6

Second contribution of a VersaTile used as a sequential

module

PAC7

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.11

0.45

PAC8

PAC9

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

Average contribution of a RAM block during a read operation

Average contribution of a RAM block during a write operation

Dynamic contribution for PLL

See Table 2-11 on page 2-10.

PAC10

PAC11

PAC12

PAC13

See Table 2-12 on page 2-11.

25.00

30.00

1.74

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet

calculator or the SmartPower tool in the Libero SoC software.

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in RT ProASIC3 Devices at

1.5 V VCC

Device-Specific Dynamic

Power (µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

RT3PE3000L RT3PE600L

13.03

6.69

1.46

0.13

6.24

3.47

1.46

0.13

PAC2

Clock contribution of a Global Spine

PAC3

Clock contribution of a VersaTile row

PAC4

Clock contribution of a VersaTile used as a sequential module

First contribution of a VersaTile used as a sequential module

PAC5

0.07

0.29

PAC6

Second contribution of a VersaTile used as a sequential

module

PAC7

Contribution of a VersaTile used as a combinatorial module

Average contribution of a routing net

0.29

0.70

PAC8

PAC9

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

Average contribution of a RAM block during a read operation

Average contribution of a RAM block during a write operation

Dynamic contribution for PLL

See Table 2-11 on page 2-10.

PAC10

PAC11

PAC12

PAC13

See Table 2-12 on page 2-11.

25.00

30.00

2.60

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or the SmartPower tool in the Libero SoC software.

2-12

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-15 • Different Components Contributing to the Static Power Consumption in RT ProASIC3 Devices

Device-Specific Dynamic Power

Parameter

PDC0

Definition

Array static power in Sleep mode

(µW)

0 mW

PDC1

Array static power in Active mode

See Table 2-10 on page 2-9.

See Table 2-7 on page 2-8.

1.42 mW

PDC2

Array static power in Static (Idle) mode

PDC3

Array static power in Flash*Freeze mode

Static PLL contribution at 1.2 V operating core voltage

Static PLL contribution 1.5 V operating core voltage

Bank quiescent power (VCCI-dependent)

PDC4

2.55 mW

PDC5

See Table 2-7 on page 2-8,

Table 2-8 on page 2-8, Table 2-10

on page 2-9.

PDC6

PDC7

I/O input pin static power (standard-dependent)

I/O output pin static power (standard-dependent)

See Table 2-11 on page 2-10.

See Table 2-12 on page 2-11.

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

spreadsheet calculator or SmartPower tool in Libero SoC.

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on

page 2-15.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on

page 2-15.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-17 on page 2-15. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (PDC0 or PDC1 or PDC2 or PDC3) + N_BANKS* PDC5 + N_INPUTS* PDC6 + N_OUTPUTS* PDC7

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_BANKSis the number of I/O banks powered in the design.

N

Revision 5

2-13

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the Global Resources chapter in the RT ProASIC3

FPGA Fabric User's Guide.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in

"Spine Architecture" section of the Global Resources chapter in the RT ProASIC3

FPGA Fabric User's Guide.

F_CLKis the global clock signal frequency.

N

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + α₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on

page 2-15.

F

_CLKis the global clock signal frequency.

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* α₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on

page 2-15.

F_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * α₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

α₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on

page 2-15.

F

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* α₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-15.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* α₂/ 2 * β₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

α₂is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-15.

β₁is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-15.

F

_CLKis the global clock signal frequency.

2-14

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* β₂+ PAC12 * N_BLOCK* F_WRITE-CLOCK* β₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

β₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

β₃is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on

page 2-15.

PLL Contribution—P

PLL

P_PLL= PDC4 + PAC1₃*F_CLKOUT

F_CLKOUTis the output clock frequency.¹

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

α₁

α₂

10%

Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

β₁

β₂

β₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (P_AC13* F_CLKOUTproduct) to the total PLL contribution.

Revision 5

2-15

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVPECL

t

= 0.78 ns

t

= 0.67 ns

PD

t

= 1.59 ns

DP

I/O Module

(Non-Registered)

Combinational Cell

Y

LVTTL Output Drive Strength = 12 mA

High Slew Rate

t

= 2.09 ns

DP

t

= 1.21 ns

PD

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

Output Drive Strength = 8 mA

High Slew Rate

LVTTL

t

= 1.84 ns

PY

t

= 2.38 ns

DP

LVPECL

t

= 0.70 ns

PD

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

LVCMOS 1.5 V

Output Drive Strength = 4 mA

High Slew Rate

t

= 0.33 ns

= 0.36 ns

ICLKQ

ISUD

t

= 2.84 ns

DP

t

= 0.65 ns

PD

Input LVTTL

Clock

I/O Module

Register Cell

(Registered)

Register Cell

Combinational Cell

Y

t

= 1.49 ns

PY

D

Q

D

Q

D

t

Q

LVTTL 3.3 V Output Drive

Strength = 12 mA

I/O Module

t

= 0.65 ns

PD

t

= 2.09 ns

High Slew Rate

(Non-Registered)

DP

t

= 0.76 ns

= 0.59 ns

CLKQ

= 0.81 ns

= 0.43 ns

t

= 0.76 ns

= 0.59 ns

OCLKQ

CLKQ

LVDS,

B-LVDS,

M-LVDS

SUD

t

OSUD

SUD

Input LVTTL

Clock

Input LVTTL

Clock

t

= 2.11 ns

PY

t

= 1.49 ns

t

= 1.49 ns

PY

Figure 2-4 • Timing Model

Operating Conditions: –1 Speed, Military Temperature Range (T_J= 125°C), Worst-Case

VCC = 1.14 V (example for RT3PE3000L and RT3PE600L)

2-16

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

V_trip

VIL

PAD

VCC

50%

Y

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-5 • Input Buffer Timing Model and Delays (example)

Revision 5

2-17

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-6 • Output Buffer Model and Delays (example)

2-18

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example)

Revision 5

2-19

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-18 • Summary of Maximum and Minimum DC Output Levels

Software Default Settings

Equiv.

Software

VOL

VOH

IOL IOH

Default

Drive

Strength

Drive Option¹Slew

Strgth. (mA) Rate

Max.

V

Min.

V

I/O Standard

mA

–55 ≤ T_J≤ 100 100 < T_J≤ 125 –55 ≤ T_J≤ 100 100 < T_J≤ 125 –55 ≤ T_J≤ 125

(°C)

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12

High

0.4

2.4

12

3.3 V LVCMOS 100 µA

Wide Range^1,2

0.2

VCCI – 0.2

1.7

VCCI – 0.2

1.7

0.1

2.5 V LVCMOS 12 mA

12

2

High

0.7

12

2

12

2

1.8 V LVCMOS

12 mA

0.45

VCCI – 0.45 VCCI – 0.45

1.5 V LVCMOS 12 mA

1.2 V LVCMOS^3,42 mA

High 0.25 * VCCI 0.25 * VCCI 0.75 * VCCI 0.75 * VCCI

1.2 V LVCMOS 100 µA

Wide Range^1,3,4

2

High

0.1

VCCI – 0.1

0.1

3.3 V PCI

Per PCI Specification

3.3 V PCI-X

Per PCI-X Specification

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20⁵

35

33

8

15⁵

15

18

14

21

20⁵

35

33

8

15⁵

15

18

14

21

High

0.4

0.5

–

20

35

33

8

20

35

33

8

–

0.6

0.75

–

0.6

–

0.4

0.5

VCCI – 0.4

VCCI – 0.5

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

0.4

15

18

14

21

15

18

14

21

0.54

0.35

0.7

0.54

0.44

0.7

VCCI – 0.62 VCCI – 0.62

VCCI – 0.43 VCCI – 0.43

VCCI – 1.1

VCCI – 0.9

VCCI – 1.1

VCCI – 0.9

0.5

0.625

1. The minimum drive strength for any 1.2 V LVCMOS or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V and VCCI ≥ VCC.

4. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

5. Output drive strength is below JEDEC specification.

6. Output slew rate can be extracted using the IBIS models.

2-20

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-19 • Summary of Maximum and Minimum DC Input Levels

Software Default Settings

VIL

VIH

IIL¹

µA

IIH²

µA

Min.

Max.

V

Min.

V

Max.

V

I/O Standard

V

–55 ≤ T_J≤ 125 (°C)

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS³

1.2 V LVCMOS Wide Range³

3.3 V PCI

–0.3

0.8

2

3.6

15

0.8

2

0.7

1.7

0.35 * VCCI

0.3 * VCCI

0.65 * VCCI

0.7 * VCCI

Per PCI Specification

3.3 V PCI-X

Per PCI-X Specification

3.3 V GTL

–0.3

VREF – 0.05

VREF – 0.1

VREF – 0.2

VREF + 0.05

VREF + 0.1

VREF + 0.2

3.6

15

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input current

is larger when operating outside recommended ranges.

3. Applicable to RT ProASIC3 devices operating at VCC = 1.2 V core voltage and VCCI ≥ VCC.

Revision 5

2-21

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-20 • Summary of AC Measuring Points*

Input/Output

Input Reference

Board Termination Measuring Trip

Standard

Supply Voltage Voltage (VREF_TYP) Voltage (VTT_REF)

Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

3.3 V

–

1.4 V

–

1.4 V

–

1.2 V

1.8 V LVCMOS

–

0.90 V

1.5 V LVCMOS

–

0.75 V

1.2 V LVCMOS*

–

0.6V

1.2 V LVCMOS – Wide Range*

3.3 V PCI

–

0.6 V

–

0.285 * VCCI (RR)

0.615 * VCCI (FF))

0.285 * VCCI (RR)

0.615 * VCCI (FF)

VREF

–

3.3 V PCI-X

3.3 V

–

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

3.3 V

2.5 V

3.3 V

2.5 V

1.5 V

2.5 V

3.3 V

2.5 V

3.3 V

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Note: *Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only

Table 2-21 • I/O AC Parameter Definitions

Parameter

t_DP

Parameter Definition

Data to Pad delay through the Output Buffer

t_PY

Pad to Data delay through the Input Buffer

t_DOUT

t_EOUT

t_DIN

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

t_HZ

Enable to Pad delay through the Output Buffer—High to Z

Enable to Pad delay through the Output Buffer—Z to High

Enable to Pad delay through the Output Buffer—Low to Z

t_ZH

t_LZ

t_ZL

Enable to Pad delay through the Output Buffer—Z to Low

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

2-22

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

1.2 V Core Operating Voltage

Table 2-22 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, Worst Case VCC = 1.14 V,

Worst Case VCCI

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High

5

– 0.68 2.09 0.05 1.49 2.03 0.44 2.12 1.56 2.76 3.06 3.99 3.43

– 0.68 3.01 0.05 1.86 2.69 0.44 3.01 2.22 4.03 4.42 4.89 4.09

3.3 V LVCMOS 100 µA 12 mA High

Wide Range²

2.5 V LVCMOS 12 mA

1.8 V LVCMOS 12 mA

1.5 V LVCMOS 12 mA

12 mA High

2 mA High

5

– 0.68 2.12 0.05 1.73 2.17 0.44 2.15 1.74 2.84 2.95 4.03 3.62

– 0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27 3.81

– 0.68 2.71 0.05 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63 4.12

– 0.68 4.39 0.05 2.25 3.19 0.44 4.24 3.74 4.34 4.09 6.11 5.61

1.2 V LVCMOS

2 mA

1.2 V LVCMOS 100 µA

Wide Range³

3.3 V PCI

Per PCI

spec

–

High 10 25⁴0.68 2.37 0.05 2.31 3.13 0.44 2.40 1.68 2.77 3.06 4.28 3.56

3.3 V PCI-X

Per PCI-X

spec

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁵20 mA⁵High 10 25 0.68 1.75 0.05 1.99

20 mA⁵20 mA⁵High 10 25 0.68 1.79 0.05 1.93

–

0.44 1.71 1.75

0.44 1.82 1.79

0.44 1.76 1.73

0.44 1.89 1.77

0.44 2.73 2.65

0.44 2.59 2.28

0.44 1.82 1.55

0.44 1.86 1.49

0.44 1.98 1.55

0.44 1.77 1.41

–

3.59 3.62

3.70 3.67

3.64 3.61

3.77 3.64

4.60 4.52

4.47 4.16

1.82 1.55

1.86 1.49

1.98 1.55

1.77 1.41

35 mA

33 mA

8 mA

35 mA High 10 25 0.68 1.74 0.05 1.99

33 mA High 10 25 0.68 1.86 0.05 1.93

8 mA High 20 25 0.68 2.68 0.05 2.34

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15 mA⁵15 mA⁵High 20 50 0.68 2.55 0.05 2.34

15 mA

18 mA

14 mA

21 mA

24 mA

15 mA High 30 25 0.68 1.80 0.05 1.78

18 mA High 30 50 0.68 1.83 0.05 1.78

14 mA High 30 25 0.68 1.95 0.05 1.71

21 mA High 30 50 0.68 1.75 0.05 1.71

–

High

–

– 0.68 1.59 0.05 2.11

– 0.68 1.51 0.05 1.84

–

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-48 for

connectivity. This resistor is not required during normal operation.

5. Output drive strength is below JEDEC specification.

6. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-23

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.5 V Core Voltage

Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst Case VCCI

Standard

3.3 V LVTTL / 12 mA

3.3 V LVCMOS

12 mA High

5

–

0.52 1.97 0.03 1.23 1.78 0.34 1.99 1.46 2.63 2.89 3.23 2.71

0.52 2.89 0.03 1.61 2.44 0.34 2.88 2.12 3.89 4.25 4.12 3.36

3.3 V LVCMOS 100 µA 12 mA High

Wide Range²

2.5 V LVCMOS 12 mA

1.8 V LVCMOS 12 mA

1.5 V LVCMOS 12 mA

12 mA High

5

–

0.52 2.01 0.03 1.49 1.93 0.34 2.02 1.65 2.71 2.78 3.27 2.89

0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51 3.08

0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87 3.39

3.3 V PCI

Per PCI

spec

–

High 10 25³0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V PCI-X

Per PCI-X

spec

–

High 10 25³0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA⁴20 mA⁴High 10 25 0.52 1.68 0.03 1.79

20 mA⁴20 mA⁴High 10 25 0.52 1.72 0.03 1.73

–

0.34 1.58 1.68

0.34 1.69 1.72

0.34 1.63 1.66

0.34 1.76 1.69

0.34 2.59 2.55

0.34 2.46 2.19

0.34 1.69 1.46

0.34 1.73 1.39

0.34 1.84 1.45

0.34 1.64 1.31

–

2.83 2.92

2.93 2.97

2.88 2.90

3.00 2.94

3.84 3.79

3.71 3.43

1.69 1.46

1.73 1.39

1.84 1.45

1.64 1.31

35 mA

33 mA

8 mA

35 mA High 10 25 0.52 1.66 0.03 1.79

33 mA High 10 25 0.52 1.75 0.03 1.73

8 mA High 20 25 0.52 2.57 0.03 2.14

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

15 mA⁴15 mA⁴High 20 50 0.52 2.44 0.03 2.14

15 mA

18 mA

14 mA

21 mA

24 mA

15 mA High 30 25 0.52 1.68 0.03 1.58

18 mA High 30 50 0.52 1.72 0.03 1.58

14 mA High 30 25 0.52 1.83 0.03 1.51

21 mA High 30 50 0.52 1.63 0.03 1.51

–

High

–

0.52 1.75 0.04 2.18

0.52 1.65 0.04 1.89

–

LVPECL

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-13 on page 2-48 for

connectivity. This resistor is not required during normal operation.

4. Output drive strength is below JEDEC specification.

5. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-24

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Detailed I/O DC Characteristics

Table 2-24 • Input Capacitance

Symbol

C_IN

Definition

Input capacitance

Input capacitance on the clock pin

Conditions

Min. Max. Units

V_IN= 0, f = 1.0 MHz

8

pF

C_INCLK

Table 2-25 • I/O Output Buffer Maximum Resistances¹

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

(Ω) ²

(Ω) ³

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

8 mA

100

50

25

17

11

300

150

75

12 mA

16 mA

50

24 mA

33

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

4 mA

Same as regular 3.3 V LVCMOS

100

50

200

100

50

8 mA

12 mA

25

16 mA

20

40

24 mA

11

22

1.8 V LVCMOS

2 mA

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

20

22

16 mA

20

22

1.5 V LVCMOS

2 mA

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

33

37

1.2 V LVCMOS⁴

1.2 V LVCMOS Wide Range⁴

3.3 V PCI/PCI-X

3.3 V GTL

2 mA

158

25

158

75

100 µA

Per PCI/PCI-X specification

20 mA⁵

35 mA

11

–

2.5 V GTL

14

–

3.3 V GTL+

12

–

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

3.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only.

5. Output drive strength is below JEDEC specification.

Revision 5

2-25

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Table 2-25 • I/O Output Buffer Maximum Resistances¹(continued)

R_PULL-DOWN

R_PULL-UP

Standard

2.5 V GTL+

HSTL (I)

Drive Strength

33 mA

(Ω) ²

15

(Ω) ³

–

8 mA

15 mA⁵

50

25

31

15

69

32

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

25

15 mA

27

18 mA

13

14 mA

44

21 mA

18

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

3.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only.

5. Output drive strength is below JEDEC specification.

Table 2-26 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

(Ω)

VCCI

Min.

Max.

95 k

Min.

13 k

17 k

23 k

17 k

25 k

17 k

Max.

45 k

3.3 V

10 k

11 k

19 k

20 k

30 k

20 k

3.3 V (wide range I/Os)

95 k

45 k

2.5 V

100 k

85 k

74 k

1.8 V

110 k

156 k

300 k

1.5 V

120 k

450 k

1.2 V

1.2 V (wide range I/Os)

Notes:

1.

2.

R

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN)

= VOLspec / I

(WEAK PULL-DOWN-MAX)

(WEAK PULL-DOWN-MIN)

2-26

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-27 • I/O Short Currents IOSH/IOSL

Drive Strength

4 mA

IOSH (mA)¹

IOSL (mA)¹

3.3 V LVTTL / 3.3 V LVCMOS

25

51

27

54

8 mA

12 mA

16 mA

24mA

100 µA

4 mA

103

132

268

109

127

181

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

Same as regular 3.3 V LVCMOS

16

32

18

37

8 mA

12 mA

16 mA

24 mA

2 mA

65

74

83

87

169

9

124

11

1.8 V LVCMOS

4 mA

17

22

6 mA

35

44

8 mA

45

51

12 mA

16 mA

2 mA

91

74

91

74

1.5 V LVCMOS

13

16

4 mA

25

33

6 mA

32

39

8 mA

66

55

12 mA

2 mA

66

55

1.2 V LVCMOS

TBD

1. V LVCMOS Wide Range

3.3 V PCI/PCIX

100 µA

Per PCI/PCI-X

Specification

Per PCI Curves

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 mA²

35 mA

33 mA

8 mA

268

169

268

169

32

181

124

181

124

39

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA

18 mA²

14 mA

21 mA

66

55

83

87

169

51

124

54

103

109

1. T = 100°C

J

2. Output drive strength is below JEDEC specification.

Revision 5

2-27

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Table 2-28 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input

Buffers Applicable

Input Buffer Configuration

Hysteresis Value (typical)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

1.2 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

40 mV

The length of time an I/O can withstand I_{OSH OSL}

/I

events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection, but

such protection would only be needed in extremely prolonged stress conditions.

Table 2-29 • Duration of Short Circuit Event before Failure

Temperature

–55ºC

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

110°C

125°C

6 months

3 months

1 month

Table 2-30 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.)

No requirement

Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

10 ns *

20 years (110°C)

10 years (100°C)

LVDS/B-LVDS/

No requirement

M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low, the rise

time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more

susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization

of the system to ensure that there is no excessive noise coupling into input signals.

2-28

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-31 • Minimum and Maximum DC Output Levels

3.3 V LVTTL / 3.3 V LVCMOS

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 <T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 <T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

4 mA

0.4

0.5

2.4

4

25

51

27

54

8 mA

8

12 mA

16 mA

24 mA

12

16

24

12

16

24

103

132

268

109

127

181

Note: Software default selection highlighted in gray.

Table 2-32 • Minimum and Maximum DC Input Levels

3.3 V LVTTL / 3.3 V LCMOS

VIL

VIH

IIL¹

µA

IIH²

µA

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (ºC)

3.6

–55 ≤ T_J≤ 125 (ºC)

–0.3

0.8

2

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-33 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C

_LOAD(pF)

0

3.3

1.4

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

Revision 5

2-29

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-34 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 6.04 0.05 1.75 2.38 0.52 6.14 4.84 2.68 2.43 8.35

7.05

6.00

6.34

5.40

5.81

4.95

5.70

4.85

5.71

4.86

ns

0.68 5.13 0.05 1.49 2.03 0.44 5.22 4.12 2.28 2.07 7.10

0.80 4.93 0.05 1.75 2.38 0.52 5.02 4.14 3.02 3.05 7.22

0.68 4.20 0.05 1.49 2.03 0.44 4.27 3.52 2.57 2.59 6.14

0.80 4.15 0.05 1.75 2.38 0.52 4.22 3.61 3.25 3.43 6.43

0.68 3.53 0.05 1.49 2.03 0.44 3.59 3.07 2.76 2.92 5.47

0.80 3.93 0.05 1.75 2.38 0.52 3.99 3.49 3.29 3.54 6.20

0.68 3.34 0.05 1.49 2.03 0.44 3.40 2.97 2.80 3.01 5.27

0.80 3.81 0.05 1.75 2.38 0.52 3.87 3.51 3.36 3.94 6.08

0.68 3.24 0.05 1.49 2.03 0.44 3.30 2.98 2.86 3.35 5.17

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 3.40 0.05 1.75 2.38 0.52 3.45 2.60 2.68 2.58 5.66

4.81

4.09

4.29

3.65

4.04

3.43

3.99

3.40

3.93

3.34

ns

0.68 2.89 0.05 1.49 2.03 0.44 2.94 2.21 2.28 2.19 4.81

0.80 2.79 0.05 1.74 2.38 0.52 2.84 2.08 3.02 3.19 5.04

0.68 2.38 0.05 1.49 2.03 0.44 2.41 1.77 2.57 2.72 4.29

0.80 2.45 0.05 1.75 2.38 0.52 2.49 1.83 3.25 3.59 4.70

0.68 2.09 0.05 1.49 2.03 0.44 2.12 1.56 2.76 3.06 3.99

0.80 2.40 0.05 1.75 2.38 0.52 2.43 1.79 3.30 3.70 4.64

0.68 2.04 0.05 1.49 2.03 0.44 2.07 1.52 2.81 3.15 3.95

0.80 2.42 0.05 1.75 2.38 0.52 2.46 1.72 3.37 4.10 4.66

0.68 2.06 0.05 1.49 2.03 0.44 2.09 1.47 2.86 3.49 3.97

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-30

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

1.5 V DC Core Voltage

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

Drive

Strength

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 5.90 0.04 1.45 2.09 0.40 5.98 4.73 2.52 2.24 7.45

6.19

5.27

5.49

4.67

4.96

4.22

4.84

4.12

4.86

4.13

ns

0.52 5.02 0.03 1.23 1.78 0.34 5.09 4.02 2.15 1.90 6.34

0.61 4.80 0.04 1.45 2.09 0.40 4.86 4.02 2.87 2.85 6.32

0.52 4.08 0.03 1.23 1.78 0.34 4.13 3.42 2.44 2.43 5.38

0.61 4.02 0.04 1.45 2.09 0.40 4.06 3.49 3.09 3.23 5.53

0.52 3.42 0.03 1.23 1.78 0.34 3.46 2.97 2.63 2.75 4.70

0.61 3.79 0.04 1.45 2.09 0.40 3.84 3.38 3.14 3.34 5.30

0.52 3.23 0.03 1.23 1.78 0.34 3.26 2.87 2.67 2.84 4.51

0.61 3.67 0.04 1.45 2.09 0.40 3.72 3.39 3.20 3.74 5.18

0.52 3.13 0.03 1.23 1.78 0.34 3.16 2.88 2.72 3.18 4.41

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 3.26 0.04 1.45 2.09 0.40 3.30 2.48 2.52 2.38 4.76

3.95

3.36

3.43

2.92

3.18

2.71

3.14

2.67

3.07

2.61

ns

0.52 2.77 0.03 1.23 1.78 0.34 2.80 2.11 2.15 2.03 4.05

0.61 2.66 0.04 1.45 2.09 0.40 2.68 1.97 2.87 3.00 4.15

0.52 2.26 0.03 1.23 1.78 0.34 2.28 1.67 2.44 2.55 3.53

0.61 2.32 0.04 1.45 2.09 0.40 2.33 1.72 3.09 3.40 3.80

0.52 1.97 0.03 1.23 1.78 0.34 1.99 1.46 2.63 2.89 3.23

0.61 2.26 0.04 1.45 2.09 0.40 2.28 1.67 3.15 3.51 3.74

0.52 1.92 0.03 1.23 1.78 0.34 1.94 1.42 2.68 2.98 3.18

0.61 2.28 0.04 1.45 2.09 0.40 2.30 1.61 3.21 3.90 3.77

0.52 1.94 0.03 1.23 1.78 0.34 1.96 1.37 2.73 3.32 3.20

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-31

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-38 • Minimum and Maximum DC Output Levels

3.3 V LVCMOS Wide Range

Equiv.

Software

Default

Drive

VOL

VOH

IOL

µA

IOH

µA

IOSH

IOSL

Drive

Strength

Max.

V

Min.

V

Max.

mA

Max.

mA

Option¹

–55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC)

–55 ≤ T_J≤ 100 (ºC)

100 µA

Notes:

2 mA

4 mA

0.2

VCCI – 0.2

100

25

27

6 mA

51

54

8 mA

51

54

12 mA

16 mA

24 mA

103

132

268

109

127

181

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-A specification.

3. Software default selection highlighted in gray.

Table 2-39 • Minimum and Maximum DC Input and Output Levels

3.3 V LVCMOS Wide Range

1

2

VIL

VIH

I_IL

I_IH

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125

–0.3

0.8

2

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

Table 2-40 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C_LOAD(pF)

0

3.3

1.4

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

2-32

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equiv.

Software

Default

Drive

Strength Speed

Strength Option¹Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std.

–1

0.80 9.08 0.05 2.18 3.16 0.52 9.08 7.17 3.85 3.40 11.28 9.38 ns

0.68 7.72 0.05 1.86 2.69 0.44 7.72 6.10 3.28 2.89 9.60 7.98 ns

0.80 7.37 0.05 2.18 3.16 0.52 7.37 6.10 4.38 4.35 9.58 8.31 ns

0.68 6.27 0.05 1.86 2.69 0.44 6.27 5.19 3.73 3.70 8.15 7.07 ns

0.80 6.17 0.05 2.18 3.16 0.52 6.17 5.30 4.73 4.94 8.37 7.51 ns

0.68 5.24 0.05 1.86 2.69 0.44 5.24 4.51 4.03 4.20 7.12 6.38 ns

0.80 5.82 0.05 2.18 3.16 0.52 5.82 5.12 4.80 5.11 8.03 7.33 ns

0.68 4.95 0.05 1.86 2.69 0.44 4.95 4.36 4.09 4.34 6.83 6.23 ns

0.80 5.64 0.05 2.18 3.16 0.52 5.64 5.14 4.90 5.72 7.85 7.35 ns

0.68 4.80 0.05 1.86 2.69 0.44 4.80 4.38 4.17 4.87 6.67 6.25 ns

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-42 • 3.3 V LVCMOS Wide Range High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equiv.

Software

Default

Drive

Strength Speed

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

Strength Option¹

t_ZHt_LZt_HZt_ZLSt_ZHSUnits

0.80 5.00 0.05 2.18 3.16 0.52 5.00 3.77 3.85 3.62 7.21 5.97 ns

100 µA

Notes:

4 mA

Std.

–1

0.68 4.25 0.05 1.86 2.69 0.44 4.25 3.21 3.28 3.08 6.13 5.08 ns

0.80 4.07 0.05 2.18 3.16 0.52 4.07 2.98 4.38 4.57 6.27 5.19 ns

0.68 3.46 0.05 1.86 2.69 0.44 3.46 2.54 3.73 3.89 5.33 4.41 ns

0.80 3.54 0.05 2.18 3.16 0.52 3.54 2.60 4.73 5.19 5.74 4.81 ns

0.68 3.01 0.05 1.86 2.69 0.44 3.01 2.22 4.03 4.42 4.89 4.09 ns

0.80 3.45 0.05 2.18 3.16 0.52 3.45 2.54 4.82 5.36 5.66 4.74 ns

0.68 2.94 0.05 1.86 2.69 0.44 2.94 2.16 4.10 4.56 4.81 4.03 ns

0.80 3.49 0.05 2.18 3.16 0.52 3.49 2.44 4.91 5.98 5.69 4.64 ns

0.68 2.97 0.05 1.86 2.69 0.44 2.97 2.07 4.18 5.08 4.84 3.95 ns

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to the Table 2-5 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

Revision 5

2-33

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.5 V DC Core Voltage

Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equiv.

Software

Default

Drive

Strength Speed

Strength Option¹Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std.

–1

0.61 8.94 0.04 1.89 2.86 0.40 8.92 7.06 3.69 3.20 10.39 8.53 ns

0.52 7.61 0.03 1.61 2.43 0.34 7.59 6.00 3.14 2.72 8.84 7.25 ns

0.61 7.23 0.04 1.89 2.86 0.40 7.21 5.99 4.22 4.15 8.68 7.45 ns

0.52 6.15 0.03 1.61 2.43 0.34 6.14 5.09 3.59 3.53 7.39 6.34 ns

0.61 6.03 0.04 1.89 2.86 0.40 6.01 5.18 4.57 4.74 7.47 6.65 ns

0.52 5.13 0.03 1.61 2.43 0.34 5.11 4.41 3.89 4.03 6.36 5.66 ns

0.61 5.68 0.04 1.89 2.86 0.0 5.66 5.01 4.64 4.91 7.13 6.47 ns

0.52 4.83 0.03 1.61 2.43 0.34 4.82 4.26 3.95 4.18 6.06 5.51 ns

0.61 5.50 0.04 1.89 2.86 0.40 5.48 5.03 4.74 5.52 6.95 6.49 ns

0.52 4.68 0.03 1.61 2.43 0.34 4.66 4.28 4.03 4.70 5.91 5.52 ns

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-44 • 3.3 V LVCMOS Wide Range High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equiv.

Software

Default

Drive

Strength Speed

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

Strength Option¹

t_ZHt_LZt_HZt_ZLSt_ZHSUnits

0.61 4.86 0.04 1.89 2.86 0.40 4.84 3.65 3.69 3.42 6.29 5.12 ns

100 µA

Notes:

4 mA

Std.

–1

0.52 4.14 0.03 1.61 2.43 0.34 4.12 3.11 3.14 2.91 5.35 4.35 ns

0.61 3.93 0.04 1.89 2.86 0.40 3.91 2.86 4.22 4.38 5.36 4.33 ns

0.52 3.34 0.03 1.61 2.43 0.34 3.32 2.44 3.59 3.72 4.56 3.68 ns

0.61 3.40 0.04 1.89 2.86 0.40 3.38 2.49 4.57 4.99 4.83 3.95 ns

0.52 2.89 0.03 1.61 2.43 0.34 2.88 2.12 3.89 4.25 4.11 3.36 ns

0.61 3.31 0.04 1.89 2.86 0.40 3.29 2.42 4.66 5.16 4.75 3.89 ns

0.52 2.82 0.03 1.61 2.43 0.34 2.80 2.06 3.96 4.39 4.04 3.31 ns

0.61 3.35 0.04 1.89 2.86 0.40 3.33 2.32 4.76 5.78 4.78 3.79 ns

0.52 2.85 0.03 1.61 2.43 0.34 2.83 1.98 4.05 4.91 4.07 3.22 ns

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

3. Software default selection highlighted in gray.

2-34

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-45 • Minimum and Maximum DC Output Levels

2.5 V LVCMOS

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Max.

V

Min.

V

Max.

mA

Max.

mA

Drive Strength

–55 ≤ T_J≤ 125 (°C)

–55 ≤ T_J≤ 100 (°C)

4 mA

0.7

1.7

4

16

32

18

37

8 mA

8

12 mA

16 mA

24 mA

12

16

24

12

16

24

65

74

83

87

169

124

Note: Software default selection highlighted in gray.

Table 2-46 • Minimum and Maximum DC Input Levels

2.5 V LVCMOS

1

2

VIL

VIH

I_IL

I_IH

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (°C)

–0.3

–55 ≤ T_J≤ 125 (°C)

3.6

–55 ≤ T_J≤ 125 (°C)

0.7

1.7

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-47 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C

_LOAD(pF)

0

2.5

1.2

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

Revision 5

2-35

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-48 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 6.87 0.05 2.04 2.56 0.52 6.99 5.83 2.70 2.19 9.20

8.03

6.83

7.14

6.08

6.50

5.53

6.36

5.41

6.38

5.43

ns

0.68 5.84 0.05 1.73 2.17 0.44 5.95 4.96 2.29 1.86 7.82

0.80 5.62 0.05 2.04 2.56 0.52 5.72 4.84 3.08 2.90 7.92

0.68 4.78 0.05 1.73 2.17 0.44 4.86 4.20 2.62 2.47 6.74

0.80 4.73 0.05 2.04 2.56 0.52 4.81 4.30 3.34 3.38 7.01

0.68 4.02 0.05 1.73 2.17 0.44 4.09 3.65 2.84 2.87 5.97

0.80 4.46 0.05 2.04 2.56 0.52 4.53 4.16 3.39 3.50 6.74

0.68 3.79 0.05 1.73 2.17 0.44 3.86 3.54 2.89 2.98 5.73

0.80 4.34 0.05 2.04 2.56 0.52 4.41 4.17 3.47 3.96 6.62

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

0.68 3.69 0.05 1.73 2.17

0.4

3.75 3.55 2.95 3.36 5.63

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-49 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.80 3.51 0.05 2.04 2.56 0.52 3.56 3.13 2.70 2.27 5.77

5.33

4.53

4.61

3.92

4.25

3.62

4.19

3.56

4.10

3.49

ns

0.68 2.98 0.05 1.73 2.17 0.44 3.03 2.66 2.29 1.93 4.91

0.80 2.87 0.05 2.04 2.56 0.52 2.92 2.40 3.08 3.01 5.12

0.68 2.44 0.05 1.73 2.17 0.44 2.48 2.05 2.62 2.56 4.36

0.80 2.50 0.05 2.04 2.56 0.52 2.53 2.05 3.34 3.47 4.74

0.68 2.12 0.05 1.73 2.17 0.44 2.15 1.74 2.84 2.95 4.03

0.80 2.43 0.05 2.04 2.56 0.52 2.47 1.98 3.39 3.59 4.67

0.68 2.07 0.05 1.73 2.17 0.44 2.10 1.69 2.89 3.06 3.97

0.80 2.44 0.05 2.04 2.56 0.52 2.48 1.90 3.47 4.08 4.68

0.68 2.08 0.05 1.73 2.17 0.44 2.11 1.61 2.95 3.47 3.98

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-36

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

1.5 V DC Core Voltage

Table 2-50 • 2.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

Drive

Strength

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 6.73 0.04 1.75 2.26 0.40 6.83 5.71 2.54 1.99 8.30

7.18

6.10

6.29

5.35

5.65

4.80

5.51

4.69

5.52

4.70

ns

0.52 5.73 0.03 1.49 1.93 0.34 5.81 4.86 2.16 1.69 7.06

0.61 5.48 0.04 1.75 2.26 0.40 5.56 4.82 2.92 2.71 7.02

0.52 4.66 0.03 1.49 1.93 0.34 4.73 4.10 2.48 2.30 5.98

0.61 4.59 0.04 1.75 2.26 0.40 4.65 4.18 3.18 3.18 6.12

0.52 3.91 0.03 1.49 1.93 0.34 3.96 3.56 2.71 2.70 5.20

0.61 4.32 0.04 1.75 2.26 0.40 4.38 4.04 3.24 3.31 5.84

0.52 3.68 0.03 1.49 1.93 0.34 3.72 3.44 2.75 2.81 4.97

0.61 4.20 0.04 1.75 2.26 0.40 4.26 4.06 3.31 3.76 5.72

0.52 3.58 0.03 1.49 1.93 0.34 3.62 3.45 2.82 3.20 4.87

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-51 • 2.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.61 3.37 0.04 1.75 2.26 0.40 3.41 3.01 2.54 2.08 4.87

4.48

3.81

3.75

3.19

3.40

2.89

3.33

2.84

3.25

2.76

ns

0.52 2.87 0.03 1.49 1.93 0.34 2.90 2.56 2.16 1.77 4.14

0.61 2.74 0.04 1.75 2.26 0.40 2.76 2.29 2.92 2.82 4.23

0.52 2.33 0.03 1.49 1.93 0.34 2.35 1.95 2.48 2.40 3.60

0.61 2.36 0.04 1.75 2.26 0.40 2.38 1.93 3.19 3.27 3.84

0.52 2.01 0.03 1.49 1.93 0.34 2.02 1.65 2.71 2.78 3.27

0.61 2.29 0.04 1.75 2.26 0.40 2.31 1.87 3.24 3.40 3.77

0.52 1.95 0.03 1.49 1.93 0.34 1.96 1.59 2.75 2.89 3.21

0.61 2.31 0.04 1.75 2.26 0.40 2.32 1.78 3.31 3.89 3.79

0.52 1.96 0.03 1.49 1.93 0.34 1.98 1.52 2.82 3.31 3.22

8 mA

Std.

–1

12 mA

16 mA

24 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-37

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-52 • Minimum and Maximum DC Output Levels

1.8 V LVCMOS

VOL

VOH

IOL

IOH

mA

IOSH

IOSL

Drive

Strength

Max.

V

Min.

V

Max.

mA

Max

mA³

mA

–55 ≤ T_J≤ 125 (°C)

–55 ≤ T_J≤ 100 (°C)

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

0.45

VCCI – 0.45

2

4

2

4

9

11

22

44

51

74

17

35

45

91

6

8

12

16

12

16

Note: Software default selection highlighted in gray.

Table 2-53 • Minimum and Maximum DC Input Levels

1.8 V LVCMOS

VIL

VIH

IIL¹

IIH²

µA

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (°C)

0.65 * VCCI

–55 ≤ T_J≤ 125 (°C)

–0.3

0.35 * VCCI

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-54 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C

_LOAD(pF)

0

1.8

0.9

–

5

Note: *Measuring point = Vtrip. See Table 2-20 on page 2-22 for a complete table of trip points.

2-38

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-55 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.80 9.16 0.05 2.00 2.82 0.52 9.32 7.69 2.77 1.20 11.53 9.89

ns

0.68 7.79 0.05 1.70 2.40 0.44 7.93 6.54 2.36 1.02 9.81

0.80 7.55 0.05 2.00 2.82 0.52 7.68 6.48 3.23 2.76 9.88

0.68 6.42 0.05 1.70 2.40 0.44 6.53 5.51 2.75 2.35 8.41

0.80 6.40 0.05 2.00 2.82 0.52 6.51 5.65 3.54 3.34 8.71

0.68 5.44 0.05 1.70 2.40 0.44 5.54 4.80 3.01 2.84 7.41

0.80 6.01 0.05 2.00 2.82 0.52 6.12 5.48 3.61 3.50 8.32

8.42

8.68

7.38

7.85

6.68

7.69

6.54

7.70

6.55

7.70

6.55

Std.

–1

Std.

–1

Std.

–

0.68

5.11 0.05 1.70 2.40 0.44 5.20 4.66 3.07 2.98 7.08

Std.

–1

0.80 5.90 0.05 2.00 2.82 0.52 6.00 5.49 3.71 4.08 8.21

0.68 5.02 0.05 1.70 2.40 0.44 5.11 4.67 3.16 3.47 6.98

0.80 5.90 005 2.00 2.82 0.52 6.00 5.49 3.71 4.08 8.21

0.68 5.02 0.05 1.70 2.40 0.44 5.11 4.67 3.16 3.47 6.98

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-56 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.80 4.14 0.05 2.00 2.82 0.52 4.21 4.05 2.76 1.23 6.42

6.26

5.32

5.21

4.43

4.70

3.99

4.60

3.91

4.48

3.81

4.48

3.81

ns

0.68 3.52 0.05 1.70 2.40 0.44 3.58 3.45 2.35 1.04 5.46

0.80 3.36 0.05 2.00 2.82 0.52 3.41 3.01 3.22 2.85 5.62

0.68 2.86 0.05 1.70 2.40 0.44 2.90 2.56 2.74 2.42 4.78

0.80 2.88 0.05 2.00 2.82 0.52 2.93 2.49 3.54 3.43 5.13

0.68 2.45 0.05 1.70 2.40 0.44 2.49 2.12 3.01 2.92 4.36

0.80 2.79 0.05 2.00 2.82 0.52 2.83 2.40 3.60 3.59 5.04

0.68 2.37 0.05 1.70 2.40 0.44 2.41 2.04 3.06 3.05 4.29

0.80 2.78 0.05 2.00 2.82 0.52 2.82 2.28 3.71 4.21 5.02

0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27

0.80 2.78 0.05 2.00 2.82 0.52 2.82 2.28 3.71 4.21 5.02

0.68 2.36 0.05 1.70 2.40 0.44 2.40 1.94 3.16 3.58 4.27

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-39

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.5 V DC Core Voltage

Table 2-57 • 1.8 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.61 9.02 0.04 1.69 2.52 0.40 9.17 7.57 2.61 1.01 10.63 9.04

ns

0.52 7.68 0.03 1.44 2.14 0.34 7.80 6.44 2.22 0.86 9.04

0.61 7.41 0.04 1.69 2.52 0.40 7.52 6.36 3.07 2.56 8.99

0.52 6.30 0.03 1.44 2.14 0.34 6.40 5.41 2.62 2.18 7.64

0.61 6.26 0.04 1.69 2.52 0.40 6.35 5.53 3.38 3.14 7.82

0.52 5.33 0.03 1.44 2.14 0.34 5.40 4.71 2.88 2.67 6.65

0.61 5.88 0.04 1.69 2.52 0.40 5.96 5.37 3.45 3.30 7.42

0.52 5.00 0.03 1.44 2.14 0.34 5.07 4.57 2.94 2.81 6.32

0.61 5.76 0.04 1.69 2.52 0.40 5.85 5.38 3.55 3.88 7.31

0.52 4.90 0.03 1.44 2.14 0.34 4.97 4.57 3.02 3.30 6.22

7.69

7.83

6.66

7.00

5.95

6.83

5.81

6.84

5.82

6.84

5.82

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Std.

–1

0.61 5.76 0.04 1.69 2.52

040

5.85 5.38 3.55 3.88 7.31

0.52 4.90 0.03 1.44 2.14 0.34 4.97 4.57 3.02 3.30 6.22

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-58 • 1.8 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.61 4.01 0.04 1.69 2.52 0.40 4.06 3.94 2.60 1.03 5.52

5.40

4.60

4.36

3.71

3.84

3.27

3.75

3.19

3.63

3.08

3.63

3.08

ns

0.52 3.41 0.03 1.44 2.14 0.34 3.45 3.35 2.21 0.88 4.70

0.61 3.22 0.04 1.69 2.52 0.40 3.26 2.89 3.07 2.65 4.72

0.52 2.74 0.03 1.44 2.14 0.34 2.77 2.46 2.61 2.26 4.02

0.61 2.74 0.04 1.69 2.52 0.40 2.77 2.38 3.38 3.23 4.23

0.52 2.33 0.03 1.44 2.14 0.34 2.36 2.02 2.88 2.75 3.60

0.52 2.65 0.04 1.69 2.52 0.40 2.68 2.28 3.45 3.40 4.14

0.51 2.26 0.03 1.44 2.14 0.34 2.28 1.94 2.93 2.89 3.52

0.61 2.64 0.04 1.69 2.52 0.40 2.66 2.16 3.55 4.01 4.13

0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51

0.61 2.64 0.04 1.69 2.52 0.40 2.66 2.16 3.55 4.01 4.13

0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-40

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-59 • Minimum and Maximum DC Output Levels

1.5 V LVCMOS

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strength

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 125 (°C)

–55 ≤ T_J≤ 100 (°C)

2 mA

4 mA

6 mA

8 mA

12 mA

0.25 * VCCI

0.75 * VCCI

2

4

13

25

32

66

16

33

39

55

4

6

8

12

Note: Software default selection highlighted in gray.

Table 2-60 • Minimum and Maximum DC Input Levels

1.5 V LVCMOS

VIL

VIH

IIL¹

µA

IIH²

µA

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (°C)

0.65 * VCCI 3.6

–55 ≤ T_J≤ 125 (°C)

–0.3

0.35 * VCCI

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

Table 2-61 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C_LOAD(pF)

0

1.5

0.75

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

Revision 5

2-41

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-62 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.80 9.53 0.05 2.19 3.06 0.52 9.69 7.88 3.38 2.67 11.90 10.09

ns

0.68 8.10 0.05 1.86 2.61 0.44 8.25 6.71 2.87 2.27 10.12 8.58

0.80 8.14 0.05 2.19 3.06 0.52 8.28 6.89 3.74 3.34 10.49 9.09

Std.

–1

0.68 6.93 0.05 1.85 2.61 0.44 7.05 5.86 3.18 2.84 8.92

0.80 7.64 0.05 2.19 3.06 0.52 7.78 6.70 3.82 3.52 9.98

0.68 6.50 0.05 1.86 2.61 0.44 6.61 5.70 3.25 2.99 8.49

0.80 7.55 0.05 2.19 3.06 0.52 7.68 6.71 3.41 4.19 9.88

0.68 6.42 0.05 1.86 2.61 0.44 6.53 5.71 2.90 3.56 8.41

0.80 7.55 0.05 2.19 3.06 0.52 7.68 6.71 3.41 4.19 9.89

0.68 6.42 0.05 1.86 2.61 0.44 6.53 5.71 2.90 3.56 8.41

7.74

8.91

7.58

8.91

7.58

8.91

7.58

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-63 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.80 3.91 0.05 2.19 3.06 0.52 3.98 3.54 3.37 2.78 6.18

5.75

4.89

5.11

4.35

4.99

4.24

4.84

4.12

4.84

4.12

ns

0.68 3.33 0.05 1.86 2.61 0.44 3.38 3.01 2.86 2.36 5.26

0.80 3.34 0.05 2.19 3.06 0.52 3.39 2.90 3.73 3.45 5.60

0.68 2.84 0.05 1.86 2.61 0.44 2.88 2.47 3.17 2.93 4.76

0.80 3.23 0.05 2.19 3.06 0.52 3.28 2.78 3.81 3.64 5.48

0.68 2.74 0.05 1.86 2.61 0.44 2.79 2.37 3.24 3.09 4.66

0.80 3.19 0.05 2.19 3.06 0.52 3.24 2.63 3.93 4.33 5.45

0.68 2.71 0.05 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63

0.80 3.19 0.05 2.19 3.06 0.52 3.24 2.63 3.93 4.33 5.45

0.68 2.71 0.05 1.86 2.61 0.44 2.76 2.24 3.34 3.69 4.63

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-42

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

1.5 V DC Core Voltage

Table 2-64 • 1.5 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Speed

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

Drive

Strength

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.61 9.39 0.04 1.88 2.77 0.40 9.54 7.77 3.22 2.47 11.00 9.24

ns

0.52 7.99 0.03 1.60 2.35 0.34 8.11 6.61 2.74 2.10 9.36

0.61 8.01 0.04 1.88 2.77 0.40 8.13 6.77 3.58 3.14 9.59

0.52 6.81 0.03 1.60 2.35 0.34 6.91 5.76 3.05 2.67 8.16

0.61 7.51 0.04 1.88 2.77 0.40 7.62 6.59 3.66 3.32 9.09

0.52 6.39 0.03 1.60 2.35 0.34 6.48 5.60 3.12 2.83 7.73

0.61 7.41 0.04 1.88 2.77 0.40 7.52 6.59 3.41 3.99 8.99

0.52 6.30 0.03 1.60 2.35 0.34 6.40 5.61 2.90 3.40 7.64

0.61 7.41 0.04 1.88 2.77 0.40 7.52 6.59 3.41 3.99 8.99

0.52 6.30 0.03 1.60 2.35 0.34 6.40 5.61 2.90 3.40 7.64

7.86

8.24

7.01

8.05

6.85

8.06

6.85

8.06

6.85

Std.

–1

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-65 • 1.5 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.61 3.78 0.04 1.88 2.77 0.40 3.82 3.43 3.21 2.58 5.29

4.89

4.16

4.25

3.62

4.13

3.52

3.98

3.39

3.98

3.39

ns

0.52 3.21 0.03 1.60 2.35 0.34 3.25 2.92 2.73 2.20 4.50

0.61 3.20 0.04 1.88 2.77 0.40 3.23 2.79 3.57 3.25 4.70

0.52 2.72 0.03 1.60 2.35 0.34 2.75 2.37 3.04 2.77 4.00

0.61 3.09 0.04 1.88 2.77 0.40 3.12 2.67 3.65 3.44 4.59

0.52 2.63 0.04 1.60 2.35 0.34 2.65 2.27 3.11 2.93 3.90

0.61 3.05 0.04 1.88 2.77 0.40 3.09 2.52 3.77 4.14 4.55

0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87

0.61 3.05 0.04 1.88 2.77 0.40 3.09 2.52 3.77 4.14 4.55

0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-43

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V

applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-66 • Minimum and Maximum DC Output Levels

1.2 V LVCMOS

Applicable to I/Os Operating at 1.2 V Core Voltage

VOL

VOH

IOL

IOH

mA

IOSH

IOSL

Drive

Strength

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 125 (°C)

–55 ≤ T_J≤ 100 (°C)

2 mA

0.25 * VCCI

0.75 * VCCI

2

TBD

Note: Software default selection highlighted in gray.

Table 2-67 • Minimum and Maximum DC Input and Output Levels

1.2 V LVCMOS

Applicable to I/Os Operating at 1.2 V Core Voltage¹

VIL

VIH

IIL²

IIH³

µA

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (°C)

–0.3 0.35 * VCCI

–55 ≤ T_J≤ 125 (°C)

0.65 * VCCI 3.6

–55 ≤ T_J≤ 125 (°C)

5

Notes:

1. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only.

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

Datapath

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-12 • AC Loading

Table 2-68 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C_LOAD(pF)

0

1.2

0.6

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

2-44

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-69 • 1.2 V LVCMOS Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

Std.

–1

0.80 12.61 0.05 2.65 3.75 0.52 12.10 9.50 5.11 4.66 14.31 11.71

0.68 10.72 0.05 2.25 3.19 0.44 10.30 8.08 4.35 3.97 12.17 9.96

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-70 • 1.2 V LVCMOS High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.80

0.68

5.16 0.05 2.65 3.75 0.52

4.39 0.05 2.25 3.19 0.44

4.98 4.39 5.10 4.81 7.19 6.60

4.24 3.74 4.34 4.09 6.11 5.61

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-45

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

1.2 V LVCMOS Wide Range

Table 2-71 • Minimum and Maximum DC Output Levels

1.2 V LVCMOS Wide Range

Applicable to I/Os Operating at 1.2 V Core Voltage

VOL

VOH

IOL

IOH

µA

IOSH

IOSL

Equiv. Software

Default Drive

Drive

Strength

Max.

V

Min.

V

Max.

mA

Max.

mA

Strength Option¹

µA

–55 ≤ T_J≤ 125 (°C)

100 100

–55 ≤ T_J≤ 100 (°C)

TBD TBD

100 µA

2 mA

0.25 * VCCI

0.75 * VCCI

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

Table 2-72 • Minimum and Maximum DC Input Levels

1.2 V LVCMOS Wide Range

Applicable to I/Os Operating at 1.2 V Core Voltage¹

VIL

VIH

IIL²

µA

IIH³

µA

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (°C)

–0.3 0.3 * VCCI

–55 ≤ T_J≤ 125 (°C)

0.7 * VCCI 3.6

–55 ≤ T_J≤ 125 (°C)

5

Notes:

1. Applicable to RT ProASIC3 devices operating at 1.2 V core voltage only.

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

Table 2-73 • 1.2 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C_LOAD(pF)

0

1.2

0.6

–

5

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

2-46

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-74 • 1.2 V LVCMOS Wide Range Low Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive

Strength

Speed

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLSt_ZHSUnits

2 mA

Std.

–1

0.80 12.61 0.05 2.65 3.75 0.52 12.10 9.50 5.11 4.66 14.31 11.71

0.68 10.72 0.05 2.25 3.19 0.44 10.30 8.08 4.35 3.97 12.17 9.96

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-75 • 1.2 V LVCMOS Wide Range High Slew

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive

Speed

Strength

Grade t_DOUTt_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.80

0.68

5.16 0.05 2.65 3.75 0.52

4.39 0.05 2.25 3.19 0.44

4.98 4.39 5.10 4.81 7.19 6.60

4.24 3.74 4.34 4.09 6.11 5.61

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-47

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-76 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

VIH

VOL

VOH IOL IOH

IOSH

IOSL

IIL¹IIH²

µA⁴µA⁴

Min.

V

Max.

V

Min.

V

Max.

V

Min.

Max.

mA³

Max.

mA³

Drive Strength

Per PCI specification

Notes:

V

mA mA

Per PCI curves

5

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.Currents are measured at 100°C junction temperature

and maximum voltage.

3. Currents are measured at 125°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the database; Microsemi loadings for

enable path characterization are described in Figure 2-13.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-13 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-77.

Table 2-77 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

C

_LOAD(pF)

0

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

–

10

Note: Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

2-48

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

1.2 V DC Core Voltage

Table 2-78 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.68 0.52

3.13 0.44

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.80 2.78

0.68 2.37

0.05 2.71

0.05 2.31

2.83 1.97

2.40 1.68

3.26 3.59

2.77 3.06

5.03 4.18

4.28 3.56

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

1.5 V DC Core Voltage

Table 2-79 • 3.3 V PCI/PCI-X

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUT

3.38 0.40

2.88 0.34

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

Std.

–1

0.61 2.65

0.52 2.25

0.04 2.39

0.03 2.03

2.67 1.86

2.27 1.58

3.10 3.40

2.64 2.89

4.14 3.33

3.52 2.83

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-49

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input

buffer and an open-drain output buffer. The V_CCIpin should be connected to 3.3 V.

Table 2-80 • Minimum and Maximum DC Output Levels

3.3 V GTL

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (°C) 100 < T_J≤ 125 (°C)–55 ≤ T_J≤ 100 (°C) 100 < T_J≤ 125 (°C) –55 ≤ T_J≤ 125 (°C) –55 ≤ T_J≤ 100 (°C)

20 mA*

0.4

0.5

–

20

268

181

Note: *Output drive strength is below JEDEC specification.

Table 2-81 • Minimum and Maximum DC Input Levels

3.3 V GTL

VIL

VIH

IIL¹

µA⁵

IIH²

µA⁵

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (°C)

VREF – 0.05

–55 ≤ T_J≤ 125 (°C)

VREF + 0.05 3.6

–55 ≤ T_J≤ 125 (°C)

–0.3

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

GTL

25

Test Point

10 pF

Figure 2-14 • AC Loading

Table 2-82 • 3.3 V GTL AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

10

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-50

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-83 • 3.3 V GTL

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V,

VREF = 0.8 V

Speed

Grade

t_DOUT

0.80

t_DP

2.05

1.75

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.22

3.59

t_ZHS

4.26

3.62

Units

ns

Std.

–1

2.34

1.99

2.01

1.71

2.05

1.75

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-84 • 3.3 V GTL

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V

Speed

Grade

t_DOUT

0.61

t_DP

1.97

1.68

t_DIN

0.04

0.03

t_PY

2.11

1.79

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.32

2.83

t_ZHS

3.43

2.92

Units

ns

Std.

–1

1.86

1.58

1.97

1.68

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-51

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-85 • Minimum and Maximum DC Output Levels

2.5 V GTL

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (°C) 100 < T_J≤ 125 (°C) –55 ≤ T_J≤ 100 (°C) 100 < T_J≤ 125 (°C) –55 ≤ T_J≤ 125 (°C) –55 ≤ T_J≤ 100 (°C)

20 mA*

0.4

0.5

–

20

169

124

Note: *Output drive strength is below JEDEC specification.

Table 2-86 • Minimum and Maximum DC Input Levels

VIL

VIH

IIL¹

µA

IIH²

µA

Min.

V

Max.

V

Min.

V

Max.

V

100 < T_J≤ 125 (ºC)

VREF + 0.05 3.6

100 < T_J≤ 125 (ºC)

–0.3

VREF – 0.05

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.Output drive strength is below JEDEC specification.

V_TT

GTL

25

Test Point

10 pF

Figure 2-15 • AC Loading

Table 2-87 • 2.5 V GTL AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

10

Note: *Measuring point = Vtrip. See Table 2-20 on page 2-22 for a complete table of trip points.

2-52

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-88 • 2.5 V GTL

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V, VREF = 0.8 V

Speed

Grade

t_DOUT

0.80

t_DP

2.11

1.79

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

2.11

1.79

t_LZ

t_HZ

t_ZLS

4.34

3.70

t_ZHS

4.31

3.67

Units

ns

Std.

–1

2.27

1.93

2.14

1.82

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-89 • 2.5 V GTL

Military-Case Conditions: TJ = 125°C, VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 0.8 V

Speed

Grade

t_DOUT

0.61

t_DP

2.02

1.72

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.45

2.93

t_ZHS

3.49

2.97

Units

ns

Std.

2.04

1.73

1.98

1.69

2.02

1.72

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-53

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-90 • Minimum and Maximum DC Output Levels

3.3 V GTL+

VOL

VOH

IOL

mA

I_OH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

35 mA

0.6

0.75

–

35

268

181

Table 2-91 • Minimum and Maximum DC Input Levels

3.3 V GTL+

VIL

VIH

IIL¹

µA

IIH²

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (ºC)

VREF – 0.1

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.1 3.6

–55 ≤ T_J≤ 125 (ºC)

–0.3

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-16 • AC Loading

Table 2-92 • 3.3 V GTL+ AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

V_TT(typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

10

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-54

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-93 • 3.3 V GTL+

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed

Grade

t_DOUT

0.80

t_DP

2.04

1.74

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.28

3.64

t_ZHS

4.24

3.61

Units

ns

Std.

–1

2.34

1.99

2.07

1.76

2.03

1.73

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-94 • 3.3 V GTL+

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed

Grade

t_DOUT

0.61

t_DP

1.95

1.66

t_DIN

0.04

0.03

t_PY

2.11

1.79

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.38

2.88

t_ZHS

3.41

2.90

Units

ns

Std.

1.92

1.63

1.95

1.66

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-55

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The V_CCIpin should be connected to 2.5 V.

Table 2-95 • Minimum and Maximum DC Output Levels

2.5 V GTL+

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

33 mA

0.6

0.75

–

33

169

124

Table 2-96 • Minimum and Maximum DC Input Levels

2.5 V GTL+

VIL

VIH

IIL¹

µA⁵

IIH²

µA⁵

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (ºC)

VREF – 0.1

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.1

–55 ≤ T_J≤ 125 (ºC)

–0.3

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

GTL+

25

Test Point

10 pF

Figure 2-17 • AC Loading

Table 2-97 • 2.5 V GTL+ AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C

_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

10

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-56

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-98 • 2.5 V GTL+

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V, VREF = 1.0 V

Speed

Grade

t_DOUT

0.80

t_DP

2.19

1.86

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.43

3.77

t_ZHS

4.28

3.64

Units

ns

Std.

–1

2.27

1.93

2.22

1.89

2.08

1.77

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-99 • 2.5 V GTL+

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.0 V

Speed

Grade

t_DOUT

0.61

t_DP

2.05

1.75

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

3.53

3.00

t_ZHS

3.46

2.94

Units

ns

Std.

2.04

1.73

2.07

1.76

1.99

1.69

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-57

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT

ProASIC3 devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-100 • Minimum and Maximum DC Input and Output Levels

HSTL Class I

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

8 mA

0.4

VCCI – 0.4

8

32

39

Table 2-101 • Minimum and Maximum DC Input and Output Levels

IIL¹

I_IH

2

VIL VIH

Min.

V

Max.

V

Min.

V

Max.

V

µA⁵

–55 ≤ T_J≤ 125 (ºC)

–0.3 VREF – 0.1

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.1

–55 ≤ T_J≤ 125 (ºC)

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

HSTL

Class I

50

Test Point

20 pF

Figure 2-18 • AC Loading

Table 2-102 • HSTL Class I AC Waveforms, Measuring Points, and Capacitive Loads

Measuring Point*

Input Low (V)

Input High (V)

(V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-58

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-103 • HSTL Class I

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V,

VREF = 0.75 V

Speed

Grade

t_DOUT

0.80

t_DP

3.15

2.68

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

3.11

2.65

t_LZ

t_HZ

t_ZLS

5.41

4.60

t_ZHS

5.32

4.52

Units

ns

Std.

–1

2.76

2.34

3.20

2.73

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-104 • HSTL Class I

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

t_DOUT

0.61

t_DP

3.02

2.57

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.51

3.84

t_ZHS

4.46

3.79

Units

ns

Std.

–1

2.52

2.14

3.05

2.59

3.00

2.55

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-59

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). RT

ProASIC3 devices support Class II. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-105 • Minimum and Maximum DC Output Levels

HSTL Class II

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

15 mA*

0.4

0.5

VCCI – 0.4

VCCI – 0.5

15

66

55

Note: *Output drive strength is below JEDEC specification.

Table 2-106 • Minimum and Maximum DC Input Levels

HSTL Class II

VIL

VIH

IIL¹

IIH²

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (ºC)

–0.3 VREF – 0.1

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.1 3.6

–55 ≤ T_J≤ 125 (ºC)

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

HSTL

Class II

25

Test Point

20 pF

Figure 2-19 • AC Loading

Table 2-107 • HSTL Class II AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

20

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-60

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-108 • HSTL Class II

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V,

VREF = 0.75 V

Speed

Grade

t_DOUT

0.80

t_DP

3.00

2.55

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.25

4.47

t_ZHS

4.89

4.16

Units

ns

Std.

–1

2.76

2.34

3.05

2.59

2.69

2.28

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-109 • HSTL Class II

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

t_DOUT

0.61

t_DP

2.86

2.44

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.36

3.71

t_ZHS

4.04

3.43

Units

ns

Std.

–1

2.52

2.14

2.89

2.46

2.57

2.19

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-61

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-110 • Minimum and Maximum DC Output Levels

SSTL 2 Class I

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

0.54 0.54 VCCI – 0.62 VCCI – 0.62 15 15 83 87

15 mA

Table 2-111 • Minimum and Maximum DC Input Levels

SSTL 2 Class I

VIL

VIH

IIL¹

IIH²

µA

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (ºC)

–0.3 VREF – 0.2

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.2 3.6

–55 ≤ T_J≤ 125 (ºC)

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

SSTL2

Class I

50

Test Point

25

30 pF

Figure 2-20 • AC Loading

Table 2-112 • SSTL2 Class I AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

30

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-62

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-113 • SSTL2 Class I

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

t_DOUT

0.80

t_DP

2.11

1.80

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.14

1.82

t_ZHS

1.83

1.55

Units

ns

Std.

–1

2.09

1.78

2.14

1.82

1.83

1.55

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-114 • SSTL2 Class I

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

t_DOUT

0.61

t_DP

1.98

1.68

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.99

1.69

t_ZHS

1.71

1.46

Units

ns

Std.

1.85

1.58

1.99

1.69

1.71

1.46

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-63

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). RT ProASIC3 devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-115 • Minimum and Maximum DC Output Levels

SSTL2 Class II

VOL

VOH

IOL

mA

IOH

mA

IOSH

IOSL

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

18 mA

0.35

0.44

VCCI – 0.43

18

169

124

Table 2-116 • Minimum and Maximum DC Input Levels

SSTL2 Class II

VIL

VIH

IIL1

IIH²

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (ºC)

–0.3 VREF – 0.2

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.2 3.6

–55 ≤ T_J≤ 125 (ºC)

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

SSTL2

Class II

25

Test Point

25

30 pF

Figure 2-21 • AC Loading

Table 2-117 • SSTL2 Class II AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

30

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-64

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-118 • SSTL2 Class II

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

t_DOUT

0.80

t_DP

2.15

1.83

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.18

1.86

t_ZHS

1.75

1.49

Units

ns

Std.

–1

2.09

1.78

2.18

1.86

1.75

1.49

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-119 • SSTL2 Class II

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

t_DOUT

0.61

t_DP

2.02

1.72

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.03

1.73

t_ZHS

1.64

1.39

Units

ns

Std.

1.85

1.58

2.03

1.73

1.64

1.39

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-65

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-120 • Minimum and Maximum DC Output Levels

SSTL3 Class I

VOL

VOH

IOL

mA

IOH

mA

IOSL

IOSH

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

0.7 0.7 VCCI – 1.1 VCCI – 1.1 14 14 51 54

14 mA

Table 2-121 • Minimum and Maximum DC Input Levels

SSTL3 Class I

VIL

VIH

IIL¹

IIH2

µA

Min.

V

Max.

V

Min.

V

Max.

V

µA

–55 ≤ T_J≤ 125 (ºC)

–0.3 VREF – 0.2

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.2

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

SSTL3

Class I

50

Test Point

25

30 pF

Figure 2-22 • AC Loading

Table 2-122 • SSTL3 Class I AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

30

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-66

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-123 • SSTL3 Class I

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

t_DOUT

0.80

t_DP

2.29

1.95

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.32

1.98

t_ZHS

1.82

1.55

Units

ns

Std.

–1

2.00

1.71

2.32

1.98

1.82

1.55

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-124 • SSTL3 Class I

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

t_DOUT

0.61

t_DP

2.15

1.83

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.17

1.84

t_ZHS

1.70

1.45

Units

ns

Std.

1.77

1.51

2.17

1.84

1.70

1.45

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). RT ProASIC3 devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-125 • Minimum and Maximum DC Output Levels

SSTL3 Class II

VOL

VOH

IOL

mA

IOH

mA

IOSL

IOSH

Drive

Strgth.

Max.

V

Min.

V

Max.

mA

Max.

mA

–55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC) 100 < T_J≤ 125 (ºC) –55 ≤ T_J≤ 125 (ºC) –55 ≤ T_J≤ 100 (ºC)

0.5 0.625 VCCI – 0.9 VCCI – 0.9 21 21 103 109

21 mA

Table 2-126 • Minimum and Maximum DC Input Levels

SSTL3 Class II

VIL

VIH

IIL¹

µA⁴

IIH²

µA⁴

Min.

V

Max.

V

Min.

V

Max.

V

–55 ≤ T_J≤ 125 (ºC)

VREF + 0.2

–55 ≤ T_J≤ 125 (ºC)

–0.3

VREF – 0.2

3.6

5

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL (max.).

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH (min.) < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

V_TT

SSTL3

Class II

25

Test Point

25

30 pF

Figure 2-23 • AC Loading

Table 2-127 • SSTL3 Class II AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

30

Note: *Measuring point = V . See Table 2-20 on page 2-22 for a complete table of trip points.

trip

2-68

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Timing Characteristics

Table 2-128 • SSTL3 Class II

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

t_DOUT

0.80

t_DP

2.05

1.75

t_DIN

0.05

t_PY

t_EOUT

0.52

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2.08

1.77

t_ZHS

1.65

1.41

Units

ns

Std.

–1

2.00

1.71

2.08

1.77

1.65

1.41

0.68

0.44

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-129 • SSTL3 Class II

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

t_DOUT

0.61

t_DP

1.91

1.63

t_DIN

0.04

0.03

t_PY

t_EOUT

0.40

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

1.92

1.64

t_ZHS

1.54

1.31

Units

ns

Std.

1.77

1.51

1.92

1.64

1.54

1.31

–1

0.52

0.34

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by software when the user instantiates a

differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, military ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-

LVDS) configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

P

N

165 Ω

Z₀= 50 Ω

140 Ω

Z₀= 50 Ω

INBUF_LVDS

+

–

100 Ω

Figure 2-24 • LVDS Circuit Diagram and Board-Level Implementation

2-70

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Table 2-130 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

Supply Voltage

Output Low Voltage

VOL

1.075

1.425

0.91

V

Output High Voltage

VOH

1.25

0.65

0

V

IOL ¹

1.16

2.925

5

mA

V

Output Lower Current

Output High Current

IOH ¹

Input Voltage

VI

IIH ²

µA

mV

V

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage

IIL ²

5

VODIFF

VOCM

VICM

VIDIFF

Notes:

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

mV

1. IOL/IOH is defined by VODIFF/(Resistor Network).

2. Currents are measured at 125°C junction temperature.

Table 2-131 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

1.075

Input High (V)

Measuring Point* (V)

1.325

Cross point

Note: *Measuring point = V

See Table 2-20 on page 2-22 for a complete table of trip points.

trip.

Timing Characteristics

1.2 V DC Core Voltage

Table 2-132 • LVDS

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Speed Grade

t_DOUT

0.80

t_DP

1.87

1.59

t_DIN

0.05

t_PY

2.48

2.11

Units

ns

Std.

–1

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

1.5 V DC Core Voltage

Table 2-133 • LVDS

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade

t_DOUT

0.61

t_DP

1.75

1.48

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

2.18

1.86

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Revision 5

2-71

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

B-LVDS/M-LVDS**

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-25. The input and output buffer delays are available in

the LVDS section in Table 2-130 on page 2-71.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60 Ω and

R_T= 70 Ω, given Z₀= 50 Ω (2") and Z_stub= 50 Ω (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-25 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-72

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-26. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

N

OUTBUF_LVPECL

100 Ω

Z = 50 Ω

0

INBUF_LVPECL

+

–

187 W

Z = 50 Ω

100 Ω

0

N

Figure 2-26 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-134 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

3.3

Min.

Max.

Units

V

3.0

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

V

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97 0.625

1.98 1.762

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

2.57

1.01

300

V

VIDIFF

mV

Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.64

1.94

Cross point

Note: *Measuring point = Vtrip. See Table 2-20 on page 2-22 for a complete table of trip points.

Revision 5

2-73

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

1.2 V DC Core Voltage

Table 2-136 • LVPECL

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

0.80

t_DP

1.78

1.51

t_DIN

0.05

t_PY

Units

ns

Std.

–1

2.16

1.84

0.68

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

1.5 V DC Core Voltage

Table 2-137 • LVPECL

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

0.61

t_DP

1.65

1.40

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

–1

1.89

1.61

0.52

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-74

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

DFN1E1P1

G

E

EOUT

B

A

H

I

PRE

J

D

Q

DFN1E1P1

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

INBUF

CLKBUF

Postive-Edge Triggered

Figure 2-27 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Revision 5

2-75

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Table 2-138 • Parameter Definition and Measuring Nodes

Measuring Nodes

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

(from, to)*

H, DOUT

F, H

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-27 on page 2-75 for more information.

2-76

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

CLR

BB

AA

DD

CLR

LL

HH

JJ

D

Q

CLR

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-28 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Revision 5

2-77

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Table 2-139 • Parameter Definition and Measuring Nodes

Measuring Nodes

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

(from, to)*

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-28 on page 2-77 for more information.

2-78

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

CLK

Data

t_IHD

50%

1

0

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-29 • Input Register Timing Diagram

Revision 5

2-79

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

Table 2-140 • Input Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V

Parameter

t_ICLKQ

Description

Clock-to-Q of the Input Data Register

–1 Std. Units

0.33 0.39 ns

0.36 0.43 ns

0.00 0.00 ns

0.51 0.60 ns

0.00 0.00 ns

0.63 0.74 ns

0.00 0.00 ns

0.31 0.36 ns

0.00 0.00 ns

0.31 0.36 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-141 • Input Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V

Parameter

t_ICLKQ

Description

Clock-to-Q of the Input Data Register

–1 Std. Units

0.25 0.30 ns

0.28 0.33 ns

0.00 0.00 ns

0.39 0.46 ns

0.00 0.00 ns

0.48 0.56 ns

0.00 0.00 ns

0.24 0.28 ns

0.00 0.00 ns

0.24 0.28 ns

0.19 0.22 ns

0.31 0.36 ns

0.28 0.32 ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

2-80

Revision 5

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-30 • Output Register Timing Diagram

Revision 5

2-81

Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs DC and Switching Characteristics

Timing Characteristics

Table 2-142 • Output Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, Worst-Case VCC = 1.14 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.81 0.96

0.43 0.51

0.00 0.00

0.61 0.71

0.00 0.00

1.11 1.31

0.00 0.00

0.31 0.36

0.00 0.00

0.31 0.36

0.19 0.22

0.31 0.36

0.28 0.32

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width High for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-7 for derating values.

Table 2-143 • Output Data Register Propagation Delays

Military-Case Conditions: T_J= 125°C, VCC = 1.425 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

–1 Std. Units

0.62 0.73

0.33 0.39

0.00 0.00

0.46 0.55

0.00 0.00

0.85 1.00

0.00 0.00

0.24 0.28