RTSX32SU-CQ208EV [MICROSEMI]
Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 310MHz, 2880-Cell, CMOS, CQFP208, CERAMIC, QFP-208;
| 型号： | RTSX32SU-CQ208EV |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 2880 CLBs, 48000 Gates, 310MHz, 2880-Cell, CMOS, CQFP208, CERAMIC, QFP-208 时钟 栅 可编程逻辑 |
| 文件： | 总100页 (文件大小：5065K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Designed for Space
Specifications
•
SEU-Hardened Registers Eliminate the Need to Implement
Triple-Module Redundancy (TMR)
•
•
•
•
0.25 µm Metal-to-Metal Antifuse Process (UMC)
48,000 to 108,000 Available System Gates
Up to 2,012 SEU-Hardened Flip-Flops
– Immune to Single Event Upsets (SEU) to LET > 40 MeV-
th
2
cm /mg,
Up to 360 User-Programmable I/O Pins
–10
– SEU Rate
<
10
Upset/Bit-Day in Worst-Case
Geosynchronous Orbit
Up to 100 krad (Si) Total Ionizing Dose (TID)
Features
•
•
•
•
•
Very Low Power Consumption (Up to 68 mW at Standby)
3.3 V and 5 V Mixed Voltage
Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, TTL, and
CMOS
– Parametric Performance Supported with Lot-Specific Test
Data
Single-Event Latch-Up (SEL) Immunity to LET > 104
TH
MeVcm2/mg
•
•
TM1019.5 Test Data Available
QML Certified Devices
– 5 V Input Tolerance and 5 V Drive Strength
– Slow Slew Rate Option
– Configurable Weak Resistor Pull-Up/Down for Tristated
Outputs at Power-Up
High Performance
– Hot-Swap Compliant with Cold-Sparing Support
Secure Programming Technology Designed to Protect Against
Reverse Engineering and Design Theft
100% Circuit Resource Utilization with 100% Pin Locking
Unique In-System Diagnostic and Verification Capability with
Silicon Explorer II
Deterministic, User-Controllable Timing
JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 – Dedicated JTAG Reset (TRST) Pin
•
•
•
230 MHz System Performance
310 MHz Internal Performance
9.5 ns Input Clock to Output Pad
•
•
•
Processing Flows
•
•
•
•
•
B-Flow – MIL-STD-883B
E-Flow – Extended Flow
EV-Flow – Class V Equivalent Flow Processing Consistent with
MIL-PRF 38535
Prototyping Options
•
•
Commercial SX-A Devices for Functional Verification
RTSX-SU PROTO Devices with Same Functional and Timing
Characteristics as Flight Unit in a Non-Hermetic Package
Table 1 • RTSX-SU Product Profile
Device
RTSX32SU
RTSX72SU
Capacity
Typical Gates
System Gates
32,000
48,000
72,000
108,000
Logic Modules
Combinatorial Cells
SEU-Hardened Register Cells (Dedicated Flip-Flops)
2,880
1,800
1,080
6,036
4,024
2,012
Maximum Flip-Flops
Maximum User I/Os
Clocks
1,980
227
3
4,024
360
3
Quadrant Clocks
Speed Grades
0
4
Std., –1
Std., –1
Package (by pin count)
CQ
CG
CC
84, 208, 256
256
208, 256
624
January 2012
i
© 2012 Microsemi Corporation
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Ordering Information
RTSX72SU
1
CQ
256
B
Application (T emperature Range)
B= MIL-STD-883 Class B
E= E-Flow (Space Level Flow)
= Military Temperature
M
= Class V Equivalent Flow Processing
Consistent with MIL-PRF-38535
= Prototyping Flow
EV
PROTO
Package Lead Count
Package Type
=
CQ Ceramic Quad Flat Pack
=
CG Ceramic Column Grid Aray
=
CC Ceramic Chip Carrier Land Grid
Speed Grade
Blank = Standard Speed
1 = Approximately 15% Faster than Standard
Part Number
RTSX32SU 32,000 RadTolerant Typical Gates
=
RTSX72SU 72,000 RadTolerant Typical Gates
=
RTSX-SU Device Status
RTSX-SU Devices
RTSX32SU
Status
Production
Production
RTSX72SU
ii
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Ceramic Device Resources
User I/Os (including clock buffers)
Device
CQ84
62
CQ208
173
CQ256
227
CC256
202
–
CG624
–
RTSX32SU
RTSX72SU
–
170
212
360
Temperature Grade and Application Offering
Package
CQ84
RTSX32SU
B, E, EV, PROTO
B, E, EV, PROTO
B, E, EV, PROTO
M, B, E, EV, PROTO
–
RTSX72SU
–
CQ208
CQ256
CC256
CG624
B, E, EV, PROTO
B, E, EV, PROTO
–
B, E, EV, PROTO
Note: M = Military Temperature
B = MIL-STD-883 Class B
E = E-Flow
EV = Microsemi SoC Products Group V Equivalent Flow (Class V Processing Consistent with MIL-PRF-38535)
PROTO = RTSX-SU prototype units.
Speed Grade and Temperature Grade Matrix
RTSX32SU
RTSX72SU
STD
–1
✓
✓
✓
✓
Notes:
1. Data applies to M, B, E, EV, and PROTO flow devices.
2. Contact your Microsemi SoC Products Group representative for availability.
Revision 8
iii
RTSX-SU Radiation-Tolerant FPGAs (UMC)
QML Certification
Microsemi has achieved full QML certification, demonstrating that quality management procedures, processes, and controls are in
place and comply with MIL-PRF-38535 (the performance specification used by the U.S. Department of Defense for monolithic
integrated circuits).
MIL-STD-883 Class B Product Flow
Table 2 • MIL-STD-883 Class B Product Flow* for RTSX32SU and RTSX72SU
883–Class B
Step
Screen
883 Method
Requirement
100%
1
2
3
4
5
Internal Visual
2010, Test Condition B
1010, Test Condition C
Temperature Cycling
100%
Constant Acceleration
2001, Test Condition B or D, Y1, Orientation Only
100%
Particle Impact Noise Detection
2020, Condition A
1014
100%
Seal
a.Fine
b.Gross
100%
100%
6
7
Visual Inspection
2009
100%
100%
Pre-Burn-In
Electrical Parameters
In accordance with applicable Microsemi
device specification
8
9
Dynamic Burn-In
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C
100%
100%
Interim (Post-Burn-In)
Electrical Parameters
In accordance with applicable Microsemi
device specification
10
11
Percent Defective Allowable
5%
All Lots
100%
Final Electrical Test
a.Static Tests
In accordance with applicable Microsemi
device specification, which includes a, b, and
(1)25°C
(Subgroup 1, Table I)
(2)–55°C and +125°C
(Subgroups 2, 3, Table I)
b.Functional Tests
(1)25°C
5005
5005
100%
(Subgroup 7, Table I)
(2)–55°C and +125°C
(Subgroups 8A and 8B, Table I)
c.Switching Tests at 25°C
(Subgroup 9, Table I)
5005
5005
100%
100%
5005
2009
12.
External Visual
Note: *For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical
visual are performed after solder column attachment.
iv
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Extended Flow
Table 3 • Extended Flow for RTSX32SU and RTSX72SU1,2
Step
Screen
Destructive In-Line Bond Pull3
Internal Visual
Method
Requirement
Sample
100%
1
2
3
4
5
6
7
8
9
2011, Condition D
2010, Condition A
Serialization
100%
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic
1010, Condition C
100%
2001, Condition B or D, Y1 Orientation Only
2020, Condition A
100%
100%
2012 (one view only)
100%
Pre-Burn-In Test
In accordance with applicable Microsemi device specification
100%
Dynamic Burn-In
1015, Condition D, 240 hours at 125°C or 120 hours at 150°C
minimum
100%
10 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
100%
100%
11 Static Burn-In
1015, Condition C, 72 hours at 150°C or 144 hours at 125°C
minimum
12 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
100%
13 Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters at 25°C
All Lots
14 Final Electrical Test
In accordance with Microsemi applicable device specification
which includes a, b, and c:
100%
100%
a.Static Tests
(1)25°C
5005
5005
(Subgroup 1, Table1)
(2)–55°C and +125°C
(Subgroups 2, 3, Table 1)
b.Functional Tests
100%
(1)25°C
5005
5005
(Subgroup 7, Table 15)
(2)–55°C and +125°C
(Subgroups 8A and B, Table 1)
c.Switching Tests at 25°C
(Subgroup 9, Table 1)
100%
100%
5005
1014
15 Seal
a.Fine
b.Gross
16 External Visual
2009
100%
Notes:
1. Microsemi offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Microsemi
offers this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883,
Class S. The exceptions to Method 5004 are shown in notes 2 and 4 below.
2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual
are performed after solder column attachment.
3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Microsemi substitutes a destructive bond-pull
to Method 2011 Condition D on a sample basis only.
4. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Microsemi will NOT perform any
radiation testing, and this requirement must be waived in its entirety.
5. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed).
Revision 8
v
RTSX-SU Radiation-Tolerant FPGAs (UMC)
EV Flow (Class V Flow Equivalent Processing)
Table 4 • EV Flow (Class V Equivalent Flow Processing) for RTSX32SU and RTSX72SU1, 2, 3
Step
Screen
Destructive Bond Pull
Method
Requirement
Extended Sample
100%
1
2
3
4
5
2011, Condition D
2010, Condition A
Internal Visual
Serialization
100%
Temperature Cycling
Constant Acceleration
1010, Condition C, 50 cycles minimum
2001, Y1 Orientation Only
100%
100%
2001, Test Condition B or D, Y1, Orientation Only
2020, Condition A
6
7
8
Particle Impact Noise Detection
Radiographic (X-Ray)
100%
100%
100%
2012, One View (Y1 Orientation) Only
Pre-Burn-In Electrical Parameters
In accordance with applicable Microsemi device
specification
9
Dynamic Burn-In
1015, Condition D,
100%
240 hours at 125°C or 120 hours at 150°C
minimum
10
11
12
Interim (Post-Dynamic-Burn-In) Electrical
Parameters
In accordance with applicable Microsemi device
specification
100%
100%
100%
Static Burn-In
1015, Condition C, 72 hours at 150°C or 144
hours at 125°C minimum
Interim (Post-Static-Burn-In) Electrical
Parameters
In accordance with applicable Microsemi device
specification
13
14
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
5% Overall, 3% Functional Parameters at 25°C
All Lots
100%
In accordance with applicable Microsemi device
specification, which includes a, b, and c:
a. Static Tests
(1) 25°C
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
(2) –55°C and +125°C
5005, Table 1, Subgroup 9
c. Switching Tests at 25°C
Seal (Fine & Gross Leak Test)
External Visual
15
16
1014
100%
100%
2009
17
Wafer Lot Specific Life Test (Group C)
MIL-PRF-38535, Appendix B, sec. B.4.2.c
All Wafer Lots
Notes:
1. Microsemi offers EV flow for users requiring full compliance to MIL-PRF-38535 class V requirement.
The EV process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow
devices) with the intention to be in full compliance to MIL-PRF-38535 Table IA and Appendix B requirement, but without the
official class V certification from DSCC.
2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual
are performed after solder column attachment.
3. As an enhancement to the Au ball bonding process control, two set-up units are required to go through 300°C bake for 60
minutes prior to the wire pull test. The minimum bond strength limit is 3.0 grams force, with no Au ball Lift mode (Au ball-to-Al
pad separation) allowed regardless of bond strength.
vi
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Table of Contents
General Description
Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Programmable Interconnect Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Low-Cost Prototyping Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Detailed Specifications
General Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
Package Pin Assignments
CQ84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
CC256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
CG624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Export Administration Regulations (EAR) or International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . 4-4
Revision 8
I
1 – General Description
RTSX-SU radiation-tolerant FPGAs are enhanced versions of Microsemi’s SX-A family of devices,
specifically designed for enhanced radiation performance.
Featuring SEU-hardened D-type flip-flops that offer the benefits of Triple Module Redundancy (TMR)
without the associated overhead, the RTSX-SU family is a unique product offering for space applications.
Manufactured using 0.25 µm technology at the United Microelectronics Corporation (UMC) facility in
Taiwan, RTSX-SU offers levels of radiation survivability far in excess of typical CMOS devices.
Device Architecture
RTSX-SU architecture, derived from the highly successful SX-A sea-of-modules architecture, has been
designed to improve upset and total-dose performance in radiation environments.
With three layers of metal interconnect in the RTSX32SU and four metal layers in RTSX72SU, the RTSX-
SU family provides efficient use of silicon by locating the routing interconnect resources between the top
two metal layers. This completely eliminates the channels of routing and interconnect resources between
logic modules as found in traditional FPGAs. In a sea-of-modules architecture, the entire floor of the
FPGA is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or
routing.
The RTSX-SU architecture adds several enhancements over the SX-A architecture to improve its
performance in radiation environments, such as SEU-hardened flip-flops, wider clock lines, and stronger
clock drivers.
Programmable Interconnect Elements
Interconnection between logic modules is achieved using Microsemi’s patented metal-to-metal
programmable antifuse interconnect elements. The antifuses are normally open circuit and form a
permanent, low-impedance connection when programmed.
The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with
barrier metals and has a programmed (“on” state) resistance of 25 Ω with capacitance of 1.0 fF for low
signal impedance (Figure 1-1 on page 1-2).
Revision 8
1-1
General Description
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 4
Metal 3
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug Contact
Silicon Substrate
Figure 1-1 • RTSX-SU Family Interconnect Elements
These antifuse interconnects reside between the top two layers of metal and thereby enable the sea-of-
modules architecture in an FPGA.
The extremely small size of these interconnect elements gives the RTSX-SU family abundant routing
resources and provides excellent protection against design theft. Reverse engineering is virtually
impossible because it is extremely difficult to distinguish between programmed and unprogrammed
antifuses. Additionally, since RTSX-SU is a nonvolatile, single-chip solution, there is no configuration
bitstream to intercept.
The RTSX-SU interconnect (i.e., the antifuses and metal tracks) also has lower capacitance and
resistance than that of any other device of similar capacity, leading to the fastest signal propagation in the
industry for the radiation tolerance offered.
I/O Structure
The RTSX-SU family features a flexible I/O structure that supports 3.3 V LVTTL, 5 V TTL, 5 V CMOS,
and 3.3 V and 5 V PCI. All I/O standards are hot-swap compliant, cold-sparing capable, and 5 V tolerant
(except for 3.3 V PCI).
In addition, each I/O on an RTSX-SU device can be configured as an input, an output, a tristate output, or
a bidirectional pin. Mixed I/O standards are allowed and can be set on a pin-by-pin basis. High or low
slew rate can be set on individual output buffers (except for PCI, which defaults to high slew), as well as
the power-up configuration (either pull-up or pull-down).
Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can
achieve clock-to-output-pad timing as fast as 9.5 ns. In most FPGAs, I/O cells that have embedded
latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in
RTSX-SU FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with
any other device in the system, which in turn, enables parallel design of system components and reduces
overall design time.
1-2
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Logic Modules
The RTSX-SU family provides two types of logic modules to the designer (Figure 1-2 on page 1-4): the
register cell (R-cell) and the combinatorial cell (C-cell).
The C-cell implements a range of combinatorial functions with up to five inputs. Inclusion of the DB input
and its associated inverter function dramatically increases the number of combinatorial functions that can
be implemented in a single module from 800 options (as in previous architectures) to more than 4,000 in
the RTSX-SU architecture. An example of the improved flexibility enabled by the inversion capability is
the ability to integrate a three-input exclusive-OR function into a single C-cell. This facilitates the
construction of nine-bit parity-tree functions. At the same time, the C-cell structure is extremely
synthesis-friendly, simplifying the overall design and reducing synthesis time.
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals. The R-cell registers feature programmable clock polarity,
selectable on a register-by-register basis. This provides additional flexibility during mapping of
synthesized functions into the RTSX-SU FPGA. The clock source for the R-cell can be chosen from the
hardwired clock, the routed clocks, or the internal logic.
While each SEU-hardened R-cell appears as a single D-type flip-flop to the user, each is implemented
employing triple redundancy to achieve a LET threshold of greater than 40 MeV-cm2/mg. Each TMR R-
cell consists of three master-slave latch pairs, each with asynchronous, self-correcting feedback paths.
The output of each latch on the master or slave side is voted with the outputs of the other two latches on
that side. If one of the three latches is struck by an ion and starts to change state, the voting with the
other two latches prevents the change from feeding back and permanently latching. Care was taken in
the layout to ensure that a single ion strike could not affect more than one latch (see the "R-Cell" section
on page 2-31 for more details).
Microsemi has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There
are two types of clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell
and two R-cells.
To increase design efficiency and device performance, Microsemi has further organized these modules
into SuperClusters. SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-
wide group containing one Type 1 cluster and one Type 2 cluster. RTSX-SU devices feature more
SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly
more combinatorial logic than flip-flops (Figure 1-2 on page 1-4).
Revision 8
1-3
General Description
Routing
R-cells and C-cells within Clusters and SuperClusters can be connected through the use of two
innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast
and predictable interconnection of modules within Clusters and SuperClusters. This routing architecture
also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest
possible performance (Figure 1-3 and Figure 1-4).
DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring
R-cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately below it. Only one programmable connection is used
in a FastConnect path, delivering a maximum interconnect propagation delay of 0.4 ns.
In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented
routing resources known as segmented routing and high-drive routing. Microsemi’s segmented routing
structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact
combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic
place-and-route software to minimize signal propagation delays.
C-Cell
R-Cell
Routed
Data Input
S0
D0
D1
S1
PRE
CLR
Y
D2
D3
Direct
Connect
Input
D
Q
Y
Sb
Sa
HCLK
CLKA,
CLKB,
DB
Internal Logic
CKS
CKP
A0 B0
A1 B1
Cluster 1
Cluster 1
Cluster 2
Cluster 1
Type 1 SuperCluster
Type 2 SuperCluster
Figure 1-2 • R-Cell, C-Cell and Cluster Organization
1-4
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
DirectConnect
• No antifuses for
smallest routing delay
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 1 SuperClusters
Figure 1-3 • DirectConnect and FastConnect for SuperCluster 1’s
DirectConnect
• No antifuses for
smallest routing delay
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 2 SuperClusters
Figure 1-4 • DirectConnect and FastConnect for SuperCluster 2’s
Revision 8
1-5
General Description
Global Resources
Microsemi’s high-drive routing structure provides three clock networks: hardwired clocks (HCLK), routed
clocks (CLKA, CLKB), and quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) (Table 1-1).
Table 1-1 • RTSX-SU Global Resources
RTSX32SU
RTSX72SU
Routed Clocks (CLKA, CLKB)
2
1
0
2
1
4
Hardwired Clocks (HCLK)
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell.
HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock
signal, enabling the 9.5 ns clock-to-out (pad-to-pad) performance of the RTSX-SU devices.
The second type of clock, routed clocks (CLKA, CLKB), are global clocks that can be sourced from either
external pins or internal logic signals within the device. CLKA and CLKB may be connected to sequential
cells (R-cells) or to combinational logic (C-cells).
The last type of clock, quadrant clocks, are only found in the RTSX72SU. Similar to the routed clocks, the
four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) can be sourced from external pins or from
internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the
chip, or they can be grouped together to drive multiple quadrants.
Design Environment
The RTSX-SU radiation-tolerant family of FPGAs is fully supported by both Libero® Integrated Design
Environment (IDE) software and Designer FPGA development software. Libero IDE is a design
management environment, seamlessly integrating design tools while guiding the user through the design
flow, managing all design and log files, and passing necessary design data among tools. Additionally,
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes Synplify® from Synplicity®, ViewDraw from
Mentor Graphics, ModelSim™ HDL Simulator from Mentor Graphics®, WaveFormer Lite™ from
SynaptiCAD™, and Designer software from Microsemi. Refer to the Libero flow (located on the
Microsemi SoC Products Group website) diagram for more information.
Designer software is a place-and-route tool and provides a comprehensive suite of backend support
tools for FPGA development. The Designer software includes timing-driven place-and-route, and a
world-class integrated static timing analyzer and constraints editor. With the Designer software, a user
can select and lock package pins while only minimally impacting the results of place-and-route.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Designer software is compatible with the most popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys®, and Cadence Design Systems. The
Designer software is available for both the Windows and UNIX operating systems.
Programming
Programming support is provided through Microsemi's Silicon Sculptor series programmers, single-site
programmers driven via a PC-based GUI. Factory programming is available as well.
1-6
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Low-Cost Prototyping Solution
Since the enhanced radiation characteristics of radiation-tolerant devices are not required during the
prototyping phase of the design, Microsemi has developed two prototyping solutions for RTSX-SU. For
early design development and functional verification Microsemi offers the commercial SX-A devices,
while for final flight design verification in hardware, Microsemi offers the RTSX-SU PROTO device that
has the same fit, form and function as the flight silicon.
Prototyping with SX-A Units
The prototyping solution consists of two parts:
•
•
A well-documented design flow that allows the customer to target an RTSX-SU design to the
equivalent commercial SX-A device
Either footprint-compatible packages or prototyping sockets to adapt commercial SX-A packages
to the RTSX-SU package footprints
This methodology provides the user with a cost-effective solution while maintaining the short time-to-
market associated with Microsemi FPGAs. Please see the application note Prototyping for the RTSX-S
Enhanced Aerospace FPGA for more details.
Prototyping with RTSX-SU PROTO Units
The RTSX-SU PROTO units offer a prototyping solution that can be used for final timing verification of
the flight design. The RTSX-SU PROTO prototype units have the same timing attributes as the RTSX-SU
flight units.
Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in
their part number, and "PROTO" is marked on devices to indicate that they are not intended for space
flight. They also are not intended for applications, which require the quality of space-flight units, such as
qualification of space-flight hardware. RT-PROTO units offer no guarantee of hermeticity, and no
MIL-STD-883B processing. At a minimum, users should plan on using class B level devices for all
qualification activities.
The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full
military temperature range. The RT-PROTO units will also be offered in –1 or standard speed grades, so
as to enable customers to validate the timing attributes of their space designs using actual flight silicon.
In-System Diagnostic and Debug Capabilities
The RTSX-SU family of FPGAs includes internal probe circuitry, allowing the designer to dynamically
observe and analyze any signal inside the FPGA without disturbing normal device operation. Two
individual signals can be brought out to two multipurpose pins (PRA and PRB) on the device. The probe
circuitry is accessed and controlled via Silicon Explorer II, Microsemi's integrated verification and logic
analysis tool, which attaches to the serial port of a PC and communicates with the FPGA via the JTAG
port.
Revision 8
1-7
General Description
Figure 1-5 shows Silicon Explorer II and its connections.
RTSX-SU FPGA
TDI*
TCK*
TMS*
Silicon Explorer II
Serial Connection
TDO*
PRA*
PRB*
Note: *Refer to the "Pin Descriptions" section on page 2-11 for more information.
Figure 1-5 • Probe Setup
Radiation Survivability
The RTSX-SU RadTolerant devices have varying total-dose radiation survivability. The ability of these
devices to survive radiation effects is both device and lot dependent.
Total-dose results are summarized in two ways. The first summary is indicated by the maximum total-
dose level achieved before the device fails to meet an individual performance specification but remains
functional. For Microsemi FPGAs, the parameter that first exceeds the specification is ICC (standby
supply current). The second summary is indicated by the maximum total dose achieved prior to the
functional failure of the device.
Microsemi provides total-dose radiation test data on each lot. Reports are available on the Microsemi
SoC Products Group website or from local sales representatives. Listings of available lots and devices
can also be provided.
For a radiation performance summary, see Radiation Data. This summary also shows single event upset
(SEU) and single event latch-up (SEL) testing that has been performed on Microsemi FPGAs.
All radiation performance information is provided for informational purposes only and is not guaranteed.
Total dose effects are lot-dependent, and Microsemi does not guarantee that future devices will continue
to exhibit similar radiation characteristics. In addition, actual performance can vary widely due to a variety
of factors, including but not limited to, characteristics of the orbit, radiation environment, proximity to the
satellite exterior, the amount of inherent shielding from other sources within the satellite, and actual bare
die variations. For these reasons, it is the sole responsibility of the user to determine whether the device
will meet the requirements of the specific design.
Summary
The RTSX-SU family of radiation-tolerant FPGAs extends Microsemi’s highly successful offering of
FPGAs for radiation environments with the industry’s first FPGA designed specifically for enhanced
radiation performance.
1-8
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Related Documents
Application Notes
Simultaneous Switching Noise and Signal Integrity
http://www.microsemi.com/soc/documents/SSN_AN.pdf
Implementation of Security in Actel Antifuse FPGAs
http://www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf
Using A54SX72A and RT54SX72S Quadrant Clocks
http://www.microsemi.com/soc/documents/QCLK_AN.pdf
Actel eX, SX-A and RTSX-S I/Os
http://www.microsemi.com/soc/documents/AntifuseIO_AN.pdf
IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families
http://www.microsemi.com/soc/documents/SX_SXAJTAG_AN.pdf
Prototyping for the RT54SX-S Enhanced Aerospace FPGA
http://www.microsemi.com/soc/documents/RTSXS_Proto_AN.pdf
Actel CQFP to FBFA Adapter Socket Instructions
http://www.microsemi.com/soc/documents/CQ352-FPGA_Adapter_AN.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications
http://www.microsemi.com/soc/documents/HotSwapColdSparing_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
http://www.microsemi.com/soc/documents/libguide_ug.pdf
SmartGen Core Reference Guide
http://www.microsemi.com/soc/documents/gen_refguide_ug.pdf
Libero SoC User's Guide
http://www.microsemi.com/soc/documents/libero_ug.pdf
Silicon Sculptor Software v5.0 for Silicon Sculptor II and Silicon Sculptor 3 Programmer User’s Guide
http://www.microsemi.com/soc/documents/SiliSculptII_Sculpt3_ug.pdf
Silicon Explorer User’s Guide
http://www.microsemi.com/soc/documents/Silexpl_ug.pdf
White Papers
Design Security in Nonvolatile Flash and Antifuse FPGAs
http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf
Understanding Actel Antifuse Device Security
http://www.microsemi.com/soc/documents/AntifuseSecurityWP.pdf
Revision 8
1-9
2 – Detailed Specifications
General Conditions
Table 2-1 • Supply Voltages
VCCA
2.5 V
2.5 V
VCCI
3.3 V
5 V
Maximum Input Tolerance
Maximum Output Drive
5 V*
5 V
3.3 V
5 V
Note: *3.3 V PCI is not 5 V tolerant
Table 2-2 • Characteristics for All I/O Configurations
I/O Standard
TTL, LVTTL
3.3 V PCI
Hot Swappable
Slew Rate Control
Yes. Affects falling edge outputs only
No. High slew rate only
Power-Up Resistor*
Pull-up or Pull-down
Pull-up or Pull-down
Pull-up or Pull-down
Yes
No
5 V PCI
Yes
No. High slew rate only
Note: *The pull-ups range from 25–35 Kohms and pull-downs range from 45–55 Kohm. The resistance values depend
on VCCI, temperature, drive strength selection, and process. For board-level considerations and accurate
modelling, use the corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/download/ibis/milaero.aspx.
Revision 8
2-1
Detailed Specifications
Operating Conditions
Absolute Maximum Conditions
Stresses beyond those listed in Table 2-3 may cause permanent damage to the device. Exposure to
absolute maximum rated conditions may affect device reliability. Devices should not be operated outside
the recommendations in Table 2-4.
Table 2-3 • Absolute Maximum Conditions1
Symbol
TJ
Parameter
Limits
–55 to 150
–0.3 to 3.3
Units
°C
V
Junction Temperature
VCCA
VCCA
VCCI
VI
AC Core Supply Voltage2
DC Core Supply Voltage
DC I/O Supply Voltage
Input Voltage3, 4
–0.3 to 3.0
V
–0.3 to 6.0
V
–0.5 to 6.0
V
VI
Input Voltage for PCI Inputs
Output Voltage
–0.5 to VCCI + 0.5
–0.5 to 6.0
–65 to 150
V
VO
V
TSG
Storage Temperature
°C
Notes:
1. Absolute maximum conditions are meant for short periods of transients only. They are not meant for
operation of device for extended periods of time.
2. The AC transient VCCA limit is for radiation-induced transients less than 10 µs duration and not intended
for repetitive use. Core voltage spikes from a single event transient will not negatively affect the reliability
of the device if, for this non-repetitive event, the transient does not exceed 3.3 V at any time and the total
time that the transient exceeds 2.75 V does not exceed 10 µs in duration.
3. For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns.
Current during the transition must not exceed 95 mA.
4. For AC signals, the 5 V non-PCI input signals may overshoot during transitions to VCCI + 1.2 V for no
longer than 11 ns. The 3.3V non-PCI input signals may overshoot during transitions to 6.0 V for no longer
than 11 ns. Current during the transition must not exceed 95 mA. Refer to PCI specifications for the PCI
input overshoot limit.
Table 2-4 • Recommended Operating Conditions
Parameter
Limits
–55 to +125
2.25 to 2.75
3.0 to 3.6
4.5 to 5.5
25
Units
°C
V
Temperature Range
2.5 V Core Supply Voltage
3.3 V I/O Supply Voltage
5 V I/O Supply Voltage
ICC (maximum) Standby Current (ICCA + ICCI
V
V
)
mA
Power-Up and Power-Cycling
The RTSX-SU family does not require any specific power-up or power-cycling sequence.
2-2
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Power Dissipation
A critical element of system reliability is the ability of electronic devices to safely dissipate the heat
generated during operation. The thermal characteristics of a circuit depend on the device and package
used, the operating temperature, the operating current, and the system's ability to dissipate heat.
A complete power evaluation should be performed early in the design process to help identify potential
heat-related problems in the system and to prevent the system from exceeding the device’s maximum
allowed junction temperature.
The actual power dissipated by most applications is significantly lower than the power the package can
dissipate. However, a thermal analysis should be performed for all projects. To perform a power
evaluation, follow these steps:
1. Estimate the power consumption of the application.
2. Calculate the maximum power allowed for the device and package.
3. Compare the estimated power and maximum power values.
Table 2-5 • RTSX-SU Standby Current
Device
Temperature
25°C (typical)
125°C
ICCA (mA)
ICCI (mA)
RTSX72SU
3
10
1.5
5
7
15
7
RTSX32SU
25°C (typical)
125°C
15
Estimating Power Dissipation
The total power dissipation for the RTSX-SU family is the sum of the DC power dissipation and the AC
power dissipation:
PTotal = PDC + PAC
EQ 1
DC Power Dissipation
The power due to standby current is typically a small component of the overall power. The DC power
dissipation is defined as:
PDC = ICCA * VCCA + ICCI * VCCI
EQ 2
Revision 8
2-3
Detailed Specifications
AC Power Dissipation
The power dissipation of the RTSX-SU family is usually dominated by the dynamic power dissipation.
Dynamic power dissipation is a function of frequency, equivalent capacitance, and power supply voltage.
The AC power dissipation is defined as follows:
PAC(32SU)
=
PC-Cells + PR-Cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer
EQ 3
EQ 4
PAC(72SU)
=
PC-Cells + PR-Cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer
or:
PAC(32SU)
=
=
VCCA2 * [(m * CEQCM * fm)C-Cells + (m * CEQSM * fm)R-Cells + (n * CEQI * fn)Input Buffer
(p * (CEQO + CL) * fp)Output Buffer + (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))CLKA
(0.5 * (q2 * CEQCR * fq2) + (r2 * fq2))CLKB + (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1))HCLK
+
+
]
EQ 5
PAC(72SU)
VCCA2 * [(mc * CEQCM * fmc)C-Cells + (mS * CEQSM * fmS)R-Cells
(n * CEQI * fn)Input Buffer + (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))RCLKA
+
+
(0.5 * (q2 * CEQCR * fq2) + (r2 * fq2))RCLKB + (0.5 * (s1 * CEQHV * fs1) + (CEQHF * fs1)HCLK
+
(0.5 * (qcA * CEQCQ * FqcA) + (r_cq * FqcA))QCLKA + (0.5 * (qcB * CEQCQ * FqcB) +
(r_cq * FqcB))QCLKB + (0.5* (qcC * CEQCQ * FqcC) + (r_cq * FqcC))QCLKC
(0.5 * (qcD * CEQCQ * FqcD) + (r_cq * FqcD QCLKD] +
VCCI2 * [(p * (Ceqo + CL) * fp)Output Buffer
+
)
]
EQ 6
Where:
CEQCM = Equivalent capacitance of combinatorial modules (C-Cells) in pF
CEQSM = Equivalent capacitance of sequential modules (R-Cells) in pF
C
EQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
EQCR = Equivalent capacitance of CLKA/B in pF
EQHV = Variable capacitance of HCLK in pF
C
C
CEQHF = Fixed capacitance of HCLK in pF
CL = Output load capacitance in pF
f
m = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
q1 = Average CLKA rate in MHz
f
f
q2 = Average CLKB rate in MHz
fs1 = Average HCLK rate in MHz
FqcA,B,C,D = Average QCLKA,QCLKB,QCLKC,QCLKD rate in MHz
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
2-4
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
p = Number of output buffers switching at fp
q1 = Number of clock loads on CLKA
q2 = Number of clock loads on CLKB
qcA, qcB, qcC, qcD = Number of clock loads on QCLKA, QCLKB, QCLKC, QCLKD
r1 = Fixed capacitance due to CLKA
r2 = Fixed capacitance due to CLKB
r_cq = Fixed capacitance due to QCLKA, QCLKB, QCLKC or QCLKD
s1 = Number of clock loads on HCLK
x = Number of I/Os at logic low
y = Number of I/Os at logic high
Table 2-6 • Fixed Power Parameters
Parameter
CEQCM
CEQSM
CEQI
RTSX32SU
3.00
3.00
1.40
7.40
3.50
4.30
300
RTSX72SU
3.00
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
3.00
1.30
CEQO
CEQCR
CEQHV
CEQHF
CEQCQ
r1
7.40
3.50
4.30
690
–
3.5
100
245
r2
100
245
r_cq
–
61.25
Revision 8
2-5
Detailed Specifications
Guidelines for Estimating Power
The following guidelines are meant to represent worst-case scenarios; they can be generally used to
predict the upper limits of power dissipation:
Logic Modules (m) = 20% of modules
Inputs Switching (n) = # inputs/4
Outputs Switching (p) = # output/4
CLKA Loads (q1) = 20% of R-cells
CLKB Loads (q2) = 20% of R-cells
Load Capacitance (CL) = 35 pF
Average Logic Module Switching Rate (fm) = f/10
Average Input Switching Rate (fn) =f/5
Average Output Switching Rate (fp) = f/10
Average CLKA Rate (fq1) = f/2
Average CLKB Rate (fq2) = f/2
Average HCLK Rate (fs1) = f
HCLK loads (s1) = 20% of R-cells
To assist customers in estimating the power dissipations of their designs, Microsemi has published the
eX, SX-A and RT54SX-S Power Calculator worksheet.
2-6
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Thermal Characteristics
Introduction
The temperature variable in Microsemi’s Designer software refers to the junction temperature, not the
ambient, case, or board temperatures. This is an important distinction because dynamic and static power
consumption cause the chip junction to be higher than the ambient, case, or board temperatures. EQ 7,
EQ 8, and EQ 9 give the relationship between thermal resistance, temperature gradient and power.
Tj – Ta
----------------
θja
=
P
EQ 7
EQ 8
EQ 9
Tj – Tc
----------------
P
θjc
=
=
Tj – Tb
----------------
P
θjb
Where:
θ
θ
= Junction-to-air thermal resistance of the package. θ numbers are located in Table 2-7.
ja
ja
= Junction-to-case thermal resistance of the package. θ numbers are located in
jc
jc
Table 2-7.
θ
= Junction-to-board thermal resistance of the package. θjb for a 624-pin CCGA is located
jb
in the notes for Table 2-7.
Tj = Junction Temperature
Ta = Ambient Temperature
Tb = Board Temperature
Tc = Case Temperature
= Power
P
Revision 8
2-7
Detailed Specifications
Package Thermal Characteristics
The device thermal characteristics θjc and θja are given in Table 2-7. The thermal characteristics for θja
are shown with two different air flow rates. Note that the absolute maximum junction temperature is
150°C.
Table 2-7 • Package Thermal Characteristics
θja
Pin
Package Type
Count
θjc Still Air θja 1.0m/s θja 2.5m/s Units
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
84
2.0 1
2.0 1
2.0 1
0.5 1
40
22
33.0
19.8
16.5
17.3
30.0
18.0
15.0
15.7
°C/W
°C/W
°C/W
°C/W
208
256
208
20
Ceramic Quad Flat Pack (CQFP) with
heatsink
21.0
Ceramic Quad Flat Pack (CQFP) with
heatsink
256
0.5 1
19.0
15.7
14.2
°C/W
Ceramic Chip Carrier Land Grid (CCLG)
Ceramic Column Grid Array (CCGA)
Notes:
256
624
1.1 1
6.5 2
12.1
8.9
10.0
8.5
9.1
8.0
°C/W
°C/W
1.
θ for CQFP and CCLG packages refers to the thermal resistance between the junction and the bottom of
jc
the package.
for the CCGA 624 refers to the thermal resistance between the junction and the top surface of the
2.
θ
jc
package. Thermal resistance from junction to board (θ ) for CG624 package is 3.4 °C/W.
jb
Maximum Allowed Power Dissipation
Shown below are example calculations to estimate the maximum allowed power dissipation for a given
device based on two different thermal environments while maintaining the device junction temperature at
or below worst-case military operating conditions (125°C).
Example 1:
This example assumes that there is still air in the environment. The heat flow is shown by the arrows in
Figure 2-1 on page 2-8. The maximum ambient air temperature is assumed to be 50°C. The device
package used is the 624-pin CCGA.
Max. Junction Temp. – Max. Ambient Temp.
125°C – 50°C
--------------------------------------------------------------------------------------------------------------------
-----------------------------------
=
Maximum Allowed Power =
θja
8.9°C/W
EQ 10
Air
Solder Columns
PCB
Figure 2-1 • Hear Flow when Air is Present
2-8
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Example 2:
This example assumes that the primary heat conduction path will be through the bottom of the package
(neglecting the heat conducted through the package pins) to the board for a package mounted with
thermal paste. The heat flow is shown by the arrows in Figure 2-2. The maximum board temperature is
assumed to be 70°C. The device package used is the CQ352. The thermal resistance (θcb) of the thermal
paste is assumed to be 0.58 °Χ/Ω.
Tj – Tj
---------------
θjb
Tj – Tb
---------------------
125°C – 70°C
2.0°C/W + 0.58°C/W
------------------------------------------------------
= 21.32 W
Max. Allowed Power =
=
=
θ
jc + θcb
EQ 11
Thermal Adhesive
PCB
Figure 2-2 • Heat Flow in a Vacuum
Timing Derating
RTSX-SU devices are manufactured in a CMOS process; therefore, device performance is dependent on
temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing. The derating
factors shown in Table 2-8 should be applied to all timing data contained within this datasheet.
Table 2-8 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Military Conditions, TJ = 125°C, VCCA = 2.25 V)
Junction Temperature (Tj)
VCCA
2.25
–55°C
0.71
–40°C
0.72
0°C
0.78
0.73
0.69
25°C
0.80
0.75
0.70
70°C
0.90
0.84
0.79
85°C
0.94
0.87
0.82
125°C
1.00
2.50
0.67
0.67
0.93
2.75
0.62
0.63
0.88
Note: The user can set the junction temperature in Microsemi’s Designer software to be any integer
value in the range of –55°C to 175°C, and the core voltage to be any value between 2.25 V and
2.75 V.
Revision 8
2-9
Detailed Specifications
Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.8 ns
= 1.0 ns
I/O Module
I/O Module
RD1
RD2
t
= 0.7 ns
INYH
t
= 3.8 ns
DHL
t
= 1.2 ns
PD
t
t
t
= 0.8 ns
RD1
= 1.5 ns
RD4
= 2.9 ns
RD8
I/O Module
t
t
t
t
= 3.8 ns
Register
Cell
DHL
D
Q
t
t
RD1
= 0.8 ns
= 0.0 ns
= 0.8 ns
SUD
HD
t
= 2.5 ns
ENZL
Routed
Clock
t
= 5.3 ns
RCKH
t
= 1.0 ns
(100% Load)
RCO
I/O Module
= 3.8 ns
DHL
Register
Cell
I/O Module
t
= 0.7 ns
INYH
D
Q
t
t
t
RD1
= 0.8 ns
= 0.0 ns
= 0.8 ns
SUD
= 2.5 ns
ENZL
HD
Hardwired
Clock
t
t
RCO
= 3.9 ns
= 1.0 ns
HCKH
Figure 2-3 • RTSX-SU Timing Model
Values shown for RTSX32SU, –1, 0 krad (Si), 5 V TTL worst-case military conditions
Table 2-9 • Hardwired Clock
External Setup
Clock-to-Out (pad-to-pad)
= tHCKH + tRCO + tRD1 + tDHL
= 3.9 + 1.0 + 0.8 + 3.8 = 9.5 ns
= (tINYH + tRD2 + tSUD) – tHCKH
= 0.7 + 1.0 + 0.8 – 3.9 = –1.4 ns
Table 2-10 • Routed Clock
External Setup
Clock-to-Out (pad-to-pad)
= (tINYH + tRD2 + tSUD) – tRCKH
= 0.7 + 1.0 + 0.8 – 5.3= –2.8 ns
= tRCKH + tRCO + tRD1 + tDHL
= 5.3+ 1.0 + 0.8 + 3.8 = 10.9 ns
2-10
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
I/O Specifications
Pin Descriptions
Supply Pins
GND
Ground
Low supply voltage.
VCCI
Supply Voltage
Supply voltage for I/Os. See Table 2-1 on page 2-1.
VCCA Supply Voltage
Supply voltage for Array. See Table 2-1 on page 2-1.
Global Pins
CLKA/B
Routed Clock A and B
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL,
LVTTL, 3.3 V PCI, or 5 V PCI specifications. The clock input is buffered prior to clocking the R-cells.
When not used, this pin must be set Low or High on the board. When used, this pin should be held Low
or High during power-up to avoid unwanted static power.
For RTSX72SU, these pins can be configured as user I/Os. When used, this pin offers a built-in
programmable pull-up or pull-down resistor active during power-up only.
QCLKA/B/C/D
Quadrant Clock A, B, C, and D / I/O
These four pins are the quadrant clock inputs and are only found on the RTSX72SU. They are clock
inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI or
5 V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be
grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the core cells.
These pins can be configured as user I/Os. When not used, these pins must not be left floating. They
must be set Low or High on the board. When used, these pins offer a built-in programmable pull-up or
pull-down resistor, active during power-up only.
HCLK
Dedicated (Hardwired) Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL, LVTTL,
3.3 V PCI or 5 V PCI specifications. This input is buffered prior to clocking the R-cells. It offers clock
speeds independent of the number of R-cells being driven. When not used, this pin must not be left
floating. It must be set to Low or High on the board. When used, this pin should be held Low or High
during power-up to avoid unwanted static power.
Revision 8
2-11
Detailed Specifications
JTAG/Probe Pins
1
PRA/PRB , I/O
Probe A/B
The probe pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time
diagnostic output of any signal path within the device. The probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
1
TCK , I/O
Test Clock
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active
when the TMS pin is set Low (Table 2-34 on page 2-45). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
1
TDI , I/O
Test Data Input
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS
pin is set Low (Table 2-34 on page 2-45). This pin functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
2
TDO , I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set Low
(Table 2-34 on page 2-45). This pin functions as an I/O when the boundary scan state machine reaches
the logic reset state. When Silicon Explorer II is being used, TDO will act as an output when the
checksum command is run. It will return to user I/O when checksum is complete.
2
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set Low, the TCK, TDI, and TDO pins are boundary scan pins (Table 2-34 on
page 2-45). Once the boundary scan pins are in test mode, they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset” state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic reset” state is reached five TCK cycles after the
TMS pin is set High. In dedicated test mode, TMS functions as specified in the IEEE 1149.1
specifications.
1. Microsemi SoC Products Group recommends that you use a series termination resistor on every probe connector (TDI,
TCK, TDO, PRA, and PRB). The series termination is used to prevent data transmission corruption (i.e., due to reflection
from the FPGA to the probe connector) during probing and reading back the checksum. With an internal set-up we have
seen 70-ohm termination resistor improved the signal transmission. Since the series termination depends on the setup,
Microsemi SoC Products Group recommends users calculate the termination resistor for their own setup. Below is a
guideline on how to calculate the resistor value.
The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace
impedance.
Z0 = Rs + Zd
Z0 = trace impedance (Silicon Explorer’s breakout cable’s resistance + PCB trace impedance), Rs= series termination, Zd=
probe signal’s driver impedance.
The termination resistor should be placed as close as possible to the driver.
Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and
hence the driver impedances needs to be calculated from the SX08/SX16/SX32 IBIS Model IBIS Model (Mixed Voltage
Operation). PRA, PRB, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS
Model.
Silicon Explorer’s breakout cable’s resistance is usually close to 1 ohm.
2. Microsemi SoC Products Group recommends that you use a series termination resistor on every probe connector (TDI,
TCK, TDO, PRA, and PRB). The series termination is used to prevent data transmission corruption (i.e., due to reflection
from the FPGA to the probe connector) during probing and reading back the checksum. With an internal set-up we have
seen 70-ohm termination resistor improved the signal transmission. Since the series termination depends on the setup,
Microsemi SoC Products Group recommends users to calculate the termination resistor for their own setup. Below is a
guideline on how to calculate the resistor value.
The resistor value should be chosen so that the sum of it and the probe signal’s driver impedance equals the effective trace
impedance.
Z0 = Rs + Zd
Z0 = trace impedance (Silicon Explorer’s breakout cable’s resistance + PCB trace impedance), Rs= series termination, Zd=
probe signal’s driver impedance.
The termination resistor should be placed as close as possible to the driver.
Among the probe signals, TDI, TCK, and TMS are driven by Silicon Explorer. A54SX16 is used in Silicon Explorer and
hence the driver impedances needs to be calculated from the SX08/SX16/SX32 IBIS Model (Mixed Voltage Operation).
PRA, PRB, and TDO are driven by the FPGA and driver impedance can also be calculated from the IBIS Model.
Silicon Explorer’s breakout cable’s resistance is usually close to 1 ohm.
2-12
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize or rest the boundary scan
circuit. The TRST pin is equipped with an internal pull-up resistor. For flight applications, the TRST pin
should be hardwired to GND.
User I/O
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output levels are
compatible with standard TTL, LVTTL, 3.3 V/5 V PCI, or 5 V CMOS specifications. Unused I/O pins are
automatically tristated by the Designer software. Care must be exercised when using JTAG (HIGHZ
command) to tristate all I/Os because the pull-ups and pull-downs will be enabled if programmed. See
the "User I/O" section on page 2-13 for more details.
Special Functions
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
User I/O
The RTSX-SU family features a flexible I/O structure that supports 3.3 V LVTTL, 5 V TTL, 5 V CMOS,
and 3.3 V and 5 V PCI. All I/O standards are hot-swap compliant, cold-sparing capable, and 5V tolerant
(except for 3.3 V PCI).
Each I/O module has an available power-up resistor of approximately 50 kΩ that can configure the I/O to
a known state during power-up. Just slightly before VCCA reaches 2.5 V, the resistors are disabled so
the I/Os will behave normally.
Note: Care must be exercised when using JTAG (HIGHZ command) to tristate all I/Os because the pull-
ups and pull-downs will be enabled if programmed.
For more information about the power-up resistors, refer to Microsemi’s application note Microsemi SX-A
and RTSX-SU Devices in Hot-Swap and Cold-Sparing Applications.
RTSX-SU inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device.
If the input voltage is greater than VCCI and a fast push-pull device is NOT used, the high-resistance
pull-up of the driver and the internal circuitry of the RTSX-SU I/O may create a voltage divider (when a
user I/O is configured as an input, the associated output buffer is tristated). This voltage divider could pull
the input voltage below specification for some devices connected to the driver. A logic ‘1’ may not be
correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 5 V
to provide the logic ‘1’ input, and VCCI is set to 3.3 V on the RTSX-SU device, the input signal may be
pulled down by the RTSX-SU input.
Hot Swapping
RTSX-SU I/Os can be configured to be hot swappable in compliance with the Compact PCI Specification.
However, 3.3 V PCI I/Os are not hot swappable. When the RTSX-SU FPGA is plugged into an
electrically-active system, designers should wait for the device to complete its power-up initialization
before expecting valid levels on the outputs. Refer to Microsemi’s application note, SX-A and RTSX-S
Devices in Hot-Swap and Cold-Sparing Applications for more information on hot swapping.
Customizing the I/O
Each user I/O on an RTSX-SU device can be configured as an input, an output, a tristate output, or a
bidirectional pin. Mixed I/O standards are allowed and can be set on a pin-by-pin basis. High or low slew
rates can be set on individual output buffers (except for PCI which defaults to high slew), as well as the
power-up configuration (either pull-up or pull-down).
The user selects the desired I/O by setting the I/O properties in PinEditor, Microsemi’s graphical pin-
placement and I/O properties editor. See the PinEditor online help for more information.
Revision 8
2-13
Detailed Specifications
Unused I/Os
All unused user I/Os are automatically tristated by Microsemi’s Designer software. Although termination
is not required, it is recommended that the user tie off all unused I/Os to GND externally. If the I/O clamp
diode is disabled, then unused I/Os are 5 V tolerant, otherwise unused I/Os are tolerant to VCCI.
Using the Weak Pull-Up and Pull-Down Circuits
Each RTSX-SU I/O comes with a weak pull-up (25-35 Kohm range) and pull-down circuit
(45-55 Kohm range). I/O macros are provided for various standards (TTL, CMOS) and can be
instantiated if a pull-up/pull-down is required. The resistance values depend on VCCI,
temperature, drive strength selection, and process. For board-level considerations and
accurate modelling, use the corresponding IBIS models, located on the Microsemi SoC
Products Group website at http://www.microsemi.com/soc/download/ibis/milaero.aspx.
I/O Macros
There are nine I/O macros available to the user for RTSX-SU:
•
•
•
•
•
•
•
•
•
CLKBUF/CLKBUFI: Clock Buffer, noninverting and inverting
CLKBIBUF/CLKBIBUFI: Bidirectional Clock Buffer, noninverting and inverting
QCLKBUF/QCLKBUFI: Quad Clock Buffer, noninverting and inverting
QCLKBIBUF/QCLKBIBUFI: Quad Bidirectional Clock Buffer, noninverting and inverting
HCLKBUF: Hardwired Clock Buffer
INBUF: Input Buffer
OUTBUF: Output Buffer
TRIBUF: Tristate Buffer
BIBUF: Bidirectional Buffer
Table 2-11 • User I/O Features
Function
Description
Input Buffer Threshold • 5 V: CMOS, PCI, TTL
Selections
•
•
•
•
3.3 V: PCI, LVTTL
5 V: CMOS, PCI, TTL
3.3 V: PCI, LVTTL
Flexible Output Driver
Selectable on an individual I/O basis
Output Buffer
Hot-Swap Capability
•
I/Os on an unpowered device does not sink the current (Power supplies
are at 0 V)
•
Can be used for cold sparing
Individually selectable slew rate, high or low slew (The default is high slew
rate). The slew rate selection only affects the falling edge of an output. There
is no change on the rising edge of the output or any inputs
Power-Up
Individually selectable pull-ups and pull-downs during power-up (default is to
power-up in tristate mode)
Enables deterministic power-up of a device
VCCA and VCCI can be powered in any order
2-14
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
I/O Module Timing Characteristics
E
D
TRIBUFF
PAD To AC test loads (shown below)
VCC
50% 50%
VOH
VCC
VCC
GND
D
E
GND
10%
E
50%
50%
VCC
GND
90%
50% 50%
VOH
VMEAS
VOL
VMEAS
Pad
Pad
VMEAS
VPad
VMEAS
VOL
GND
tDLH
tDHL
tENZL tENLZ
tENZH
tENHZ
Figure 2-4 • Output Timing Model and Waveforms
VCCI
V
0 V
Pad
V
MEAS
MEAS
VCC
Y
PAD
INBUF
50%
Y
GND
50%
tINYH
tINYL
Figure 2-5 • Input Timing Model and Waveforms
Load 2
(Used to measure enable delays)
Load 3
(Used to measure disable delays)
Load 1
(Used to measure
propagation delay)
GND
GND
VCC
VCC
To the output
under test
R to VCC for t
R to VCC for t
35 pF
PZL
PLZ
R to GND for t
R = 1 kΩ
R to GND for t
R = 1 kΩ
PZH
PHZ
To the output
under test
To the output
under test
35 pF
5 pF
Figure 2-6 • AC Test Loads
Revision 8
2-15
Detailed Specifications
5 V TTL and 3.3 V LVTTL
Table 2-12 • 5 V TTL and 3.3 V LVTTL Electrical Specifications
Military
Symbol
Parameter
Min.
Max.
Units
VOH
VCCI = Min.
VI = VIH or VIL
(IOH = –1mA)
(IOH = –8mA)
(IOL= 1mA)
0.9 VCCI
V
VCCI = Min.
VI = VIH or VIL
2.4
V
V
V
VOL
VCCI = Min.
VI = VIH or VIL
0.1 VCCI
0.4
VCCI = Min.
(IOL= 12mA)
VI = VIH or VIL
VIL1
VIH
Input Low Voltage
Input High Voltage
–0.5
2.0
0.8
V
V
IIL / IIH
Input Leakage Current, VIN = VCCI or GND
(VCCI ≤ 5.25 V)
(VCCI ≤ 5.5 V)
–20
–70
20
70
µA
µA
IOZ
Tristate Output Leakage Current, VOUT = VCCI or (VCCI ≤ 5.25 V)
–20
–70
20
70
µA
µA
GND
(VCCI ≤ 5.5 V)
2
tR, tF
CIN
Input Transition Time
Input Pin Capacitance3
CLK Pin Capacitance3
10
20
20
ns
pF
pF
V
CCLK
VMEAS
Trip point for Input buffers and Measuring point for
Output buffers
1.5
IV Curve4 Can be derived from the IBIS model on the web.
Notes:
1. For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns. Current during the
transition must not exceed 95 mA.
2. If t or t exceeds the limit of 10 ns, Microsemi can guarantee reliability but not functionality.
R
F
3. Absolute maximum pin capacitance, which includes package and I/O input capacitance.
4. The IBIS model can be found at www.microsemi.com/soc/techdocs/models/ibis.html.
2-16
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Timing Characteristics
Table 2-13 • RTSX32SU 5 V TTL and 3.3 V LVTTL I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Min. Max.
Parameter
Description
Min.
Max.
Units
5 V TTL Output Module Timing (VCCI = 4.5 V)
tINYH
tINYL
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
3.1
3.6
ns
tDHL
Data-to-Pad High to Low
3.8
4.4
ns
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENZHS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
9.8
11.5
4.4
ns
3.8
ns
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
9.8
11.5
3.6
ns
3.1
ns
Enable-to-Pad, Low to Z
3.1
3.6
ns
Enable-to-Pad, High to Z
3.8
4.4
ns
Enable-to-Pad, H to Z – low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
9.8
11.5
0.046
0.038
0.064
ns
2
dTLH
0.036
0.029
0.049
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
3.3 V LVTTL Output Module Timing (VCCI = 3.0 V)
tINYH
tINYL
Input Data Pad-to-Y High
0.8
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
4.1
4.8
ns
tDHL
Data-to-Pad High to Low
3.7
4.4
ns
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENZHS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to L
13.2
3.7
15.6
4.4
ns
ns
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to H
13.2
4.1
15.6
4.8
ns
ns
Enable-to-Pad, L to Z
4.1
4.8
ns
Enable-to-Pad, H to Z
3.7
4.4
ns
Enable-to-Pad, H to Z – low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
13.2
0.064
0.031
0.069
15.6
0.081
0.040
0.088
ns
2
dTLH
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
Revision 8
2-17
Detailed Specifications
Table 2-14 • RTSX72SU 5 V TTL and 3.3 V LVTTL I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter
Description
Units
5 V TTL Output Module Timing (VCCI = 4.5 V)
tINYH
tINYL
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
3.2
3.7
ns
tDHL
Data-to-Pad High to Low
4.0
4.7
ns
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENHZS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
10.3
4.0
12.1
4.7
ns
ns
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
10.3
3.2
12.1
3.7
ns
ns
Enable-to-Pad, Low to Z
3.2
3.7
ns
Enable-to-Pad, High to Z
4.0
4.7
ns
Enable-to-Pad, High to Z – low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
10.3
0.036
0.029
0.049
12.1
0.046
0.038
0.064
ns
2
dTLH
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
3.3 V LVTTL Output Module Timing (VCCI = 3.0 V)
tINYH
tINYL
Input Data Pad-to-Y High
1.0
2.2
1.2
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
4.0
4.6
tDHL
Data-to-Pad High to Low
3.6
4.2
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENHZS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to L
12.7
3.6
14.9
4.2
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to H
12.7
4.0
14.9
4.6
Enable-to-Pad, L to Z
4.0
4.6
Enable-to-Pad, H to Z
3.6
4.2
Enable-to-Pad, High to Z – low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
12.7
0.064
0.031
0.069
14.9
0.081
0.04
0.088
2
dTLH
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
2-18
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
5 V CMOS
Table 2-15 • 5 V CMOS Electrical Specifications
Military
Symbol
Parameter
Min.
Max.
Units
VOH
VCCI = MIN,
(IOH = –20 µA) VCCI – 0.1
V
VI = VCCI or GND
VOL
VCCI = MIN,
VI = VCCI or GND
(IOL= ±20 µA)
0.1
V
VIL1
VIH
Input Low Voltage, VOUT = VOL (maximum)
Input High Voltage, VOUT = VOH (minimum)
Input Leakage Current, VIN = VCCI or GND
– 0.5
0.3 VCC
V
V
0.7 VCC
I
IL /IIH
(VCCI ≤ 5.25 V)
(VCCI ≤ 5.5 V)
–20
–70
20
70
µA
µA
IOZ
Tristate Output Leakage Current, VOUT = VCCI or GND (VCCI ≤ 5.25 V)
(VCCI ≤ 5.5 V)
–20
–70
20
70
µA
µA
tR, tF
CIN
Input Transition Time
Input Pin Capacitance2
CLK Pin Capacitance2
10
20
20
ns
pF
pF
V
CCLK
VMEAS Trip point for Input buffers and Measuring point for
Output buffers
2.5
IV
Can be derived from the IBIS model on the web.
Curve2
Notes:
1. For AC signals, the input signal may undershoot during transitions –1.2 V for no longer than 11 ns. Current during the
transition must not exceed 95 mA.
2. The IBIS model can be found at www.microsemi.com/soc/techdocs/models/ibis.html.
Revision 8
2-19
Detailed Specifications
Timing Characteristics
Table 2-16 • RTSX32SU 5 V CMOS I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter
Description
Units
5 V CMOS Output Module Timing
tINYH
tINYL
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
3.4
4.0
ns
tDHL
Data-to-Pad High to Low
3.6
4.2
ns
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENHZS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
8.7
10.3
4.0
ns
3.4
ns
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
8.7
10.3
4.2
ns
3.6
ns
Enable-to-Pad, Low to Z
3.6
4.2
ns
Enable-to-Pad, High to Z
3.4
4.0
ns
Enable-to-Pad, High to Z — low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
8.7
10.3
10.21
0.038
0.064
ns
2
dTLH
8.68
0.029
0.049
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
2-20
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Table 2-17 • RTSX72SU 5 V CMOS I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Min. Max.
Parameter
Description
Min.
Max.
Units
5 V CMOS Output Module Timing
tINYH
tINYL
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
tDLH
Data-to-Pad Low to High
3.6
4.2
ns
tDHL
Data-to-Pad High to Low
3.8
4.5
ns
tDHLS
tENZL
tDENZLS
tENZH
tENLZ
tENHZ
tENZHS
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
9.2
10.8
4.2
ns
3.6
ns
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
9.2
10.8
4.5
ns
3.8
ns
Enable-to-Pad, Low to Z
3.8
4.5
ns
Enable-to-Pad, High to Z
3.6
4.2
ns
Enable-to-Pad, High to Z – low slew
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
9.2
10.8
0.046
0.038
0.064
ns
2
dTLH
0.036
0.029
0.049
ns/pF
ns/pF
ns/pF
2
dTHL
2
dTHLS
Delta Delay vs. Load High to Low – low
slew
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1* VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
Revision 8
2-21
Detailed Specifications
5 V PCI
The RTSX-SU family supports 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 2-18 • 5 V PCI DC Specifications
Symbol
VCCA
VCCI
VIH
Parameter
Condition
Min.
2.25
4.5
Max.
2.75
Units
V
Supply Voltage for Array
Supply Voltage for I/Os
Input High Voltage1
5.5
V
2.0
VCCI + 0.5
0.8
V
VIL
Input Low Voltage1
–0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
VIN = 2.75
VIN = 0.5
70
µA
µA
V
IIL
–70
VOH
VOL
CIN
IOUT = –2 mA
IOUT = 3 mA, 6 mA
2.4
5
Output Low Voltage2
Input Pin Capacitance3
CLK Pin Capacitance
0.55
10
V
pF
pF
V
CCLK
12
VMEAS Trip Point for Input Buffers and Measuring Point for
Output Buffers
1.5
Notes:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter
include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63:32],
C/BE[7:4]#, PAR64, REQ64#, and ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-
only devices, which could be up to 16 pF in order to accommodate PGA packaging. This mean that components for
expansion boards need to use alternatives to ceramic PGA packaging (i.e., PBGA,PQFP, SGA, etc.).
4. For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns. Current during the
transition must not exceed 95 mA.
200.0
I
Max. Specification
OL
I
OL
150.0
100.0
50.0
I
Min. Specification
OL
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
I
5
5.5
6
–50.0
–100.0
–150.0
–200.0
I
Min. Specification
OH
Max. Specification
OH
I
OH
Voltage Out (V)
Figure 2-7 • 5 V PCI V/I Curve for RTSX-SU
2-22
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Equation A
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
for VCCI > VOUT > 3.1 V
Equation B
IOL = 78.5 * VOUT * (4.4 – VOUT)
for 0 V < VOUT < 0.71 V
Table 2-19 • 5 V PCI AC Specifications
Symbol
Parameter
Condition
Min.
–44
Max.
Units
mA
IOH(AC)
0 < VOUT < 1.4 1
Switching Current High 1.4 < VOUT < 2.4 1, 2
3.1 < VOUT < VCCI 1, 3
(–44 + (VOUT – 1.4)/0.024)
mA
"Equation A"
–142
(Test Point)
VOUT = 3.1 3
mA
mA
mA
IOL(AC)
VOUT = 2.2 1
Switching Current Low 2.2 > VOUT > 0.55 1
0.71 > VOUT > 0 1, 3
95
(VOUT/0.023)
"Equation B"
206
(Test Point)
VOUT = 0.71
mA
mA
ICL
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN + 1)/0.015
slewR
slewF
Notes:
Output Rise Slew Rate 0.4 V to 2.4 V load4
Output Fall Slew Rate 2.4 V to 0.4 V load4
1
1
5
5
V/ns
V/ns
1. Refer to the V/I curves in Figure 2-7 on page 2-22. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does
not apply to CLK and RST#, which are system outputs. The “Switching Current High” specification is not relevant to
SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point
rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional
N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these
maximums (A and B) are provided with the respective curves in Figure 2-7 on page 2-22. The equation defined
maximum should be met by the design. In order to facilitate component testing, a maximum current test point is defined
for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load is optional; i.e., the designer may elect to
meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification (Figure 2-8). However,
adherence to both the maximum and minimum parameters is now required (the maximum is no longer simply a
guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there
may be components in the market that have faster edge rates; therefore, motherboard designers must bear in mind that
rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for
this. Rise slew rate does not apply to open drain outputs.
Pin
Output
Buffer
50 pF
Figure 2-8 • 5 V PCI Output Loading
Revision 8
2-23
Detailed Specifications
Timing Characteristics
Table 2-20 • RTSX32SU 5 V PCI I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ= 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter
Description
Units
5 V PCI Output Module Timing
tINYH
tINYL
tDLH
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
3.4
4.0
ns
tDHL
4.1
4.8
ns
tENZL
tENZH
tENLZ
tENHZ
4.1
4.8
ns
3.4
4.0
ns
3.4
4.0
ns
4.1
4.8
ns
2
dTLH
0.036
0.029
0.046
0.038
ns/pF
ns/pF
2
dTHL
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
2-24
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Table 2-21 • RTSX72SU 5 V PCI I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ= 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Min. Max.
Parameter
Description
Min.
Max.
Units
5 V PCI Output Module Timing
tINYH
tINYL
tDLH
Input Data Pad-to-Y High
0.7
1.1
0.9
1.3
ns
ns
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
3.5
4.1
ns
tDHL
4.3
5.1
ns
tENZL
tENZH
tENLZ
tENHZ
4.3
5.1
ns
3.5
4.1
ns
3.5
4.1
ns
4.3
5.1
ns
2
dTLH
0.036
0.029
0.046
0.038
ns/pF
ns/pF
2
dTHL
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
Revision 8
2-25
Detailed Specifications
3.3 V PCI
The RTSX-SU family supports 3.3 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 2-22 • 3.3 V PCI DC Specifications
Symbol
VCCA
VCCI
VIH
Parameter
Supply Voltage for Array
Condition
Min.
2.25
3.0
Max.
2.75
3.6
Units
V
Supply Voltage for I/Os
Input High Voltage
V
0.5 VCCI VCCI + 0.5
V
VIL
Input Low Voltage
–0.5
0.3 VCCI
V
IIPU
Input Pull-up Voltage1
0.7 VCCI
V
IIL/IIH
VOH
VOL
Input Leakage Current2
0 < VIN < VCCI
IOUT = –500 µA
IOUT = 1500 µA
±20
µA
V
Output High Voltage
0.9 VCCI
Output Low Voltage
0.1 VCCI
V
CIN
Input Pin Capacitance3
10
12
pF
pF
V
CCLK
VMEAS
CLK Pin Capacitance
5
Trip point for Input buffers
Output buffer measuring point - rising edge
Output buffer measuring point - falling edge
0.4 * VCCI
0.285 * VCCI
0.615 * VCCI
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to
pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting
minimum current at this input VIN.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to motherboard-
only devices, which could be up to 16 pF, in order to accommodate PGA packaging. This means that components for
expansion boards would need to use alternatives to ceramic PGA packaging.
4. For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns. Current during the
transition must not exceed 95 mA.
5. For AC signals, the input signal may overshoot during transitions to VCCI + 1.2 V for no longer than 11 ns. Current
during the transition must not exceed 95 mA.
150.0
I
Max. Specification
OL
I
OL
100.0
50.0
I
Min. Specification
OL
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
–50.0
–100.0
–150.0
I
Min. Specification
OH
I
Max. Specification
I
OH
OH
Voltage Out (V)
Figure 2-9 • 3.3 V PCI V/I Curve for the RTSX-SU Family
2-26
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Equation C
IOH = (98.0/VCCI) * (VOUT – VCCI) * (VOUT + 0.4 VCCI)
for VCCI > VOUT > 0.7 VCCI
Equation D
IOL = (256/VCCI) * VOUT * (VCCI – VOUT)
for 0 V < VOUT < 0.18 VCCI
Table 2-23 • 3.3 V PCI AC Specifications
Symbol Parameter Condition
Min.
Max.
Units
mA
IOH(AC) Switching Current 0 < VOUT ≤ 0.3 VCCI 1
–12 VCCI
High
0.3 VCCI ≤ VOUT < 0.9 VCCI 1 (–17.1 + (VCCI – VOUT))
0.7 VCCI < VOUT < VCCI 1, 2
mA
"Equation C"
–32 VCCI
(Test Point)
VOUT = 0.7 VCC 2
mA
mA
mA
IOL(AC) Switching Current VCCI > VOUT ≥ 0.6 VCCI 1
16 VCCI
Low
0.6 VCCI > VOUT > 0.1 VCCI 1
(26.7 VOUT)
0.18 VCCI > VOUT > 0 1, 2
"Equation D"
38 VCCI
(Test Point)
VOUT = 0.18 VCC 2
mA
mA
ICL
Low Clamp Current –3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
ICH
High Clamp Current VCCI + 4 > VIN ≥ VCCI + 1
Output Rise Slew 0.2 VCCI to 0.6 VCCI load 3
Rate
25 + (VIN – VCCI – 1)/0.015
1
mA
slewR
4
4
V/ns
slewF
Output Fall Slew 0.6 VCCI to 0.2 VCCI load 3
Rate
1
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-9 on page 2-26. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does
not apply to CLK and RST#, which are system outputs. The “Switching Current High” specification is not relevant to
SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these
maximums (C and D) are provided with the respective curves in Figure 2-9 on page 2-26. The equation defined
maximum should be met by the design. In order to facilitate component testing, a maximum current test point is defined
for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load is optional (Figure 2-10); i.e., the designer
may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification.
However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a
guideline). Rise slew rate does not apply to open drain outputs.
Pin
1/2 in. max.
Pin
1/2 in. max.
Output
Buffer
Output
Buffer
10 pF
VCC
1 k/25 Ω
1 k/25 Ω
10 pF
Figure 2-10 • 3.3 V PCI Output Loading
Revision 8
2-27
Detailed Specifications
Timing Characteristics
Table 2-24 • RTSX32SU 3.3 V PCI I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std.’Speed
Min. Max.
Parameter
Description
Units
3.3 V PCI Output Module Timing
tINYH
tINYL
tDLH
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
0.8
0.9
0.9
1.1
ns
ns
3.0
3.5
ns
tDHL
3.0
3.5
ns
tENZL
tENZH
tENLZ
tENHZ
3.0
3.5
ns
3.0
3.5
ns
3.0
3.5
ns
3.0
3.5
ns
2
dTLH
0.067
0.031
0.085
0.040
ns/pF
ns/pF
2
dTHL
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * VCCI - 0.9 * VCCI)/ (C
* d
|d
|d
)
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
2-28
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Table 2-25 • RTSX72SU 3.3 V PCI I/O Module
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Min. Max.
Parameter
Description
Min.
Max.
Units
3.3 V PCI Output Module Timing
tINYH
tINYL
tDLH
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
0.7
0.9
0.8
1.1
ns
ns
2.8
3.3
ns
tDHL
2.8
3.3
ns
tENZL
tENZH
tENLZ
tENHZ
2.8
3.3
ns
2.8
3.3
ns
2.8
3.3
ns
2.8
3.3
ns
2
dTLH
0.067
0.031
0.085
0.040
ns/pF
ns/pF
2
dTHL
Notes:
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following
equation:
Slew Rate [V/ns] = ±(0.1 * V
- 0.9 * V )/ (C
* d
|d
|d
)
CCI
CCI
load
TLH THL THLS
where C
is the load capacitance driven by the I/O in pF;
load
d
|d
|d
is the worst case delta value from the datasheet in ns/pF.
TLH THL THLS
Revision 8
2-29
Detailed Specifications
Module Specifications
C-Cell
Introduction
The C-cell is one of the two logic module types in the RTSX-SU architecture. It is the combinatorial logic
resource in the device. The RTSX-SU architecture uses the same C-cell configuration as found in the SX
and SX-A families.
The C-cell features the following (Figure 2-11):
•
Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of
these inputs. C-cell inputs (A0, A1, B0, B1) can be tied to one of the either the routed or quad
clocks (CLKA/B or QCLKA/B/C/D).
•
•
Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell.
A hardwired connection (direct connect) to the associated R-cell with a signal propagation time of
less than 0.1 ns.
This layout of the C-cell enables the implementation of over 4,000 functions of up to five bits. For
example, two C-cells can be used together to implement a four-input XOR function in a single cell delay.
The C-cell configuration is handled automatically for the user with Microsemi's extensive macro library
(refer to the Antifuse Macro Library Guide for a complete listing of available RTSX-SU macros).
D0
D1
Y
D2
D3
Sa
Sb
DB
A0 B0
A1 B1
Figure 2-11 • C-Cell
VCC
GND
S, A or B
50% 50%
VCC
S
A
B
Y
50%
50%
Y
GND
tPD
tPD
VCC
50%
Y
GND
tPD
50%
tPD
Figure 2-12 • C-Cell Timing Model and Waveforms
2-30
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Timing Characteristics
Table 2-26 • C-Cell
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V
TJ= 125°C, Radiation Level = 0 krad (Si)
–1’Speed
Std. Speed
Paramet
er
Description
Min. Max.
Min. Max.
Units
C-cell Propagation Delays
tPD Internal Array Module
1.2
1.4
ns
Note: For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1
tSUD, whichever is appropriate.
+
R-Cell
Introduction
The R-cell, the sequential logic resource of RTSX-SU devices, is the second logic module type in the
RTSX-SU family architecture. The RTSX-SU R-cell is an SEU-enhanced version of the SX and SX-A R-
cell (Figure 2-13).
The main features of the R-cell include the following:
•
Direct connection to the adjacent C-cell through the hardwired connection DCIN. DCIN is driven
by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a
connection with less than 0.1 ns of routing delay.
•
The R-cell can be used as a standalone flip-flop. It can be driven by any other C-cell or I/O
modules through the regular routing structure (using DIN as a routable data input). This gives the
option of using it as a 2:1 MUXed flip-flop as well.
•
•
Independent active-low asynchronous clear (CLRB).
Independent active-low asynchronous preset (PSETB). If both CLRB and PSETB are Low, CLRB
has higher priority.
•
Clock can be driven by any of the following (CKP input selects clock polarity):
–
–
–
–
The high-performance, hardwired, fast clock (HCLK)
One of the two routed clocks (CLKA/B)
One of the four quad clocks (QCLKA/B/C/D) in the case of the RTSX72SU
User signals
•
•
S0, S1, PSETB, and CLRB can be driven by CLKA/B, QCLKA/B/C/D (for the RTSX72SU) or user
signals.
Routed Data Input and S1 can be driven by user signals.
Revision 8
2-31
Detailed Specifications
As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for
the user through Microsemi's extensive macro library (see the Antifuse Macro Library Guide for a
complete listing of available RTSX-SU macros).
Routed
Data Input
S1
S0
PSETB
Direct
Connect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CLRB
CKS
CKP
Figure 2-13 • R-Cell
SEU-Hardened D Flip-Flop
In order to meet the stringent SEU requirements of a LET threshold greater than 40MeV-cm2/gm, the
internal design of the R-cell was modified without changing the functionality of the cell.
Figure 2-14 is a simplified representation of how the D flip-flop in the R-cell is implemented in the SX-A
architecture. The flip-flop consists of a master and a slave latch gated by opposite edges of the clock.
Each latch is constructed by feeding back the output to the input stage. The potential problem in a space
environment is that either of the latches can change state when hit by a particle with enough energy.
To achieve the SEU requirements, the D flip-flop in the RTSX-SU R-cell is enhanced (Figure 2-15). Both
the master and slave latches are each implemented with three latches. The asynchronous self-correcting
feedback paths of each of the three latches is voted with the outputs of the other two latches. If one of the
three latches is struck by an ion and starts to change state, the voting with the other two latches prevents
the change from feeding back and permanently latching. Care was taken in the layout to ensure that a
single ion strike could not affect more than one latch. Figure 2-16 shows a simplified schematic of the
test circuitry that has been added to test the functionality of all the components of the flip-flop. The inputs
to each of the three latches are independently controllable so the voting circuitry in the asynchronous
self-correcting feedback paths can be tested exhaustively. This testing is performed on an
unprogrammed array during wafer sort, final test, and post-burn-in test. This test circuitry cannot be used
to test the flip-flops once the device has been programmed.
Q
D
CLK
CLK
Figure 2-14 • SX-A R-Cell Implementation of a D Flip-Flop
2-32
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Q
D
CLK
CLK
Voter
Gate
CLK
CLK
CLK
CLK
CLK
CLK
Figure 2-15 • RTSX-SU R-Cell Implementation of D Flip-Flop Using Voter Gate Logic
Q
D
Tst1
Tst2
Tst3
Voter
Gate
CLK
Test
Circuitry
Figure 2-16 • R-Cell Implementation – Test Circuitry
Revision 8
2-33
Detailed Specifications
PRE
CLR
D
Q
CLK
(Positive edge triggered)
tHD
D
tHPWH
tRPWH
tSUD
tHP
CLK
tRCO
tHPWL
tRPWL
Q
tPRESET
tCLR
tWASYN
CLR
PRESET
Figure 2-17 • R-Cell Timing Models and Waveforms
Timing Characteristics
Table 2-27 • R-Cell
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter
Description
Units
R-Cell Propagation Delays
tRCO
Sequential Clock-to-Q
1.0
0.8
1.1
0.8
0.0
2.8
0.7
0.7
1.2
1.0
1.3
1.0
0.0
3.3
0.8
0.8
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
tPRESET
tSUD
tHD
tWASYN
tRECASYN Asynchronous Recovery Time
tHASYN Asynchronous Hold Time
2-34
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Routing Specifications
Routing Resources
The routing structure found in RTSX-SU devices enables any logic module to be connected to any other
logic module in the device while retaining high performance. There are multiple paths and routing
resources that can be used to route one logic module to another, both within a SuperCluster and
elsewhere on the chip.
There are three primary types of routing within the RTSX-SU architecture: DirectConnect, FastConnect,
and Vertical and Horizontal Routing.
DirectConnect
DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 1-3
and Figure 1-4 on page 1-5). This connection can be made from the Y output of the C-cell to the
DirectConnect input of the R-cell by configuring of the S0 line of the R-cell. This provides a connection
that does not require an antifuse and has a delay of less than 0.1 ns.
FastConnect
For high-speed routing of logic signals, FastConnects can be used to build a short distance connection
using a single antifuse (Figure 1-3 and Figure 1-4 on page 1-5). FastConnects provide a maximum delay
of 0.4 ns. The outputs of each logic module connect directly to the output tracks within a SuperCluster.
Signals on the output tracks can then be routed through a single antifuse connection to drive the inputs of
logic modules either within one SuperCluster or in the SuperCluster immediately below.
Horizontal and Vertical Routing
In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented
routing resources known as segmented routing and high-drive routing. Microsemi’s segmented routing
structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact
combination of track lengths and antifuses within each path is chosen by the 100-percent-automatic
place-and-route software to minimize signal propagation delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for the initial design performance
evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are
determined by net property assignment prior to placement and routing. Up to six percent of the nets in a
design may be designated as critical, while 90 percent of the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple
rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This
increases capacitance and resistance results in longer net delays for macros connected to long tracks.
Typically up to six percent of nets in a fully utilized device require long tracks. Long tracks can cause a
delay from 4.0 ns to 8.4 ns. This additional delay is represented statistically in higher fanout routing
delays in the "Timing Characteristics" section on page 2-36.
Revision 8
2-35
Detailed Specifications
Timing Characteristics
Table 2-28 • RTSX32SU
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter Description
Predicted Routing Delays
Units
tDC
FO = 1 Routing Delay, DirectConnect
0.1
0.4
0.8
1.0
1.4
1.5
2.9
4.0
0.1
0.4
0.9
1.2
1.6
1.8
3.4
4.7
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO = 1 Routing Delay, FastConnect
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
Note: Routing delays are for typical designs across worst-case operating conditions. These parameters
should be used for estimating device performance. Post-route timing analysis or simulation is
required to determine actual worst-case performance.
Table 2-29 • RTSX72SU
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Min. Max.
Std. Speed
Min. Max.
Parameter Description
Predicted Routing Delays
Units
tDC
FO = 1 Routing Delay, DirectConnect
0.1
0.4
0.9
1.2
1.8
1.9
3.7
5.1
0.1
0.4
1.0
1.4
2.0
2.3
4.3
6.0
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO = 1 Routing Delay, FastConnect
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
Note: Routing delays are for typical designs across worst-case operating conditions. These parameters
should be used for estimating device performance. Post-route timing analysis or simulation is
required to determine actual worst-case performance.
2-36
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Global Resources
One of the most important aspects of any FPGA architecture is its global resource or clock structure. The
RTSX-SU family provides flexible and easy-to-use global resources without the limitations normally
found in other FPGA architectures.
The RTSX-SU architecture contains three types of global resources, the HCLK (hardwired clock) and
CLK (routed clock) and in the RTSX72SU, QCLK (quadrant clock). Each RTSX-SU device is provided
with one HCLK and two CLKs. The RTSX72SU has an additional four QCLKs.
Hardwired Clock
The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all R-cells in the
device with no antifuse in the path. The HCLK is available everywhere on the chip.
Upon power-up of the RTSX-SU device, four clock pulses must be detected on HCLK before the clock
signal will be propagated to registers in the device.
Routed Clocks
The routed clocks (CLKA and CLKB) are low-skew networks that can drive the clock inputs of all R-cells
in the device (logically equivalent to the HCLK). CLK has the added flexibility in that it can drive the S0
(Enable), S1, PSETB, and CLRB inputs of R-cells as well as any of the inputs of any C-cell in the device.
This allows CLKs to be used not only as clocks but also for other global signals or high fanout nets. Both
CLKs are available everywhere on the chip.
If CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as Low or High
on the board. They must not be left floating (except in RTSX72SU, where these clocks can be configured
as regular I/Os).
Revision 8
2-37
Detailed Specifications
Quadrant Clocks
The RTSX72SU device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD) to the user,
which can be sourced from external pins or from internal logic signals within the device. Each of these
clocks can individually drive up to one full quadrant of the chip, or they can be grouped together to drive
multiple quadrants (Figure 2-18). If QCLKs are not used as quadrant clocks, they can behave as regular
I/Os. See Microsemi’s application note Using A54SX72A and RT54SX72S Quadrant Clocks for more
information.
4 QCLKBUFS
4
Quadrant 2
Quadrant 3
5:1
5:1
QCLKINT
(to array)
QCLKINT
(to array)
4
Quadrant 0
Quadrant 1
5:1
5:1
QCLKINT
(to array)
QCLKINT
(to array)
Figure 2-18 • RTSX-SU QCLK Structure
2-38
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Timing Characteristics
Table 2-30 • RTSX32SU at VCCI = 3.0 V
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Network
tHCKH
tHCKL
tHPWH
tHPWL
tHCKSW
tHP
Pad to R-Cell Input Low to High
Pad to R-Cell Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.9
3.9
4.6
4.6
ns
ns
2.1
2.1
2.5
2.5
ns
ns
1.6
1.9
ns
Minimum Period
4.2
5.0
ns
fHMAX
Maximum Frequency
238
200
MHz
Routed Array Clock Networks
tRCKH
tRCHKL
tRCKH
tRCKL
Pad to R-cell Input High to Low (Light Load))
4.2
3.9
5.0
4.3
5.6
4.9
4.9
4.6
5.9
5.1
6.5
5.7
ns
ns
Pad to R-cell Input Low to High (Light Load))
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
tRCKH
tRCKL
ns
ns
tRPWH
tRPWL
tRCKSW
tRCKSW
tRCKSW
tRP
2.1
2.1
2.5
2.5
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
2.8
2.8
2.8
3.3
3.3
3.3
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
4.2
5.0
ns
fRMAX
Maximum Frequency
238
200
MHz
Revision 8
2-39
Detailed Specifications
Table 2-31 • RTSX32SU at VCCI = 4.5 V
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Network
tHCKH
tHCKL
tHPWH
tHPWL
tHCKSW
tHP
Pad to R-Cell Input Low to High
Pad to R-Cell Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.9
3.9
4.6
4.6
ns
ns
2.1
2.1
2.5
2.5
ns
ns
1.6
1.9
ns
Minimum Period
4.2
5.0
ns
fHMAX
Maximum Frequency
238
200
MHz
Routed Array Clock Networks
tRCKH
tRCHKL
tRCKH
tRCKL
Pad to R-cell Input High to Low (Light Load))
3.9
3.7
4.7
4.1
5.3
4.7
4.6
4.4
5.6
4.9
6.2
5.5
ns
ns
Pad to R-cell Input Low to High (Light Load))
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
tRCKH
tRCKL
ns
ns
tRPWH
tRPWL
tRCKSW
tRCKSW
tRCKSW
tRP
2.1
2.1
2.5
2.5
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
2.8
2.8
2.8
3.3
3.3
3.3
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
4.2
5.0
ns
fRMAX
Maximum Frequency
238
200
MHz
2-40
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Table 2-32 • RTSX72SU at VCCI = 3.0 V
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Network
tHCKH
tHCKL
tHPWH
tHPWL
tHCKSW
tHP
Pad to R-cell Input Low to High
Pad to R-cell Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
3.2
3.5
3.8
4.1
ns
ns
2.7
2.7
3.2
3.2
ns
ns
2.7
3.1
ns
Minimum Period
5.4
6.4
ns
fHMAX
Maximum Frequency
185
156
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRCKSW
tRCKSW
tRP
Pad to R-cell Input Low to High (Light Load))
5.7
6.5
5.7
6.5
5.7
6.5
6.7
7.7
6.7
7.7
6.7
7.7
ns
ns
Pad to R-cell Input High to Low (Light Load)
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
ns
ns
2.7
2.7
3.2
3.2
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
5.1
4.9
4.9
6.0
5.8
5.8
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
5.4
6.4
ns
fRMAX
Maximum Frequency
185
156
MHz
Quadrant Array Clock Networks
tQCKH
tQCKL
tQCKH
tQCKL
tQCKH
tQCKL
tQPWH
tQPWL
tQCKSW
tQCKSW
tQCKSW
tQP
Pad to R-cell Input Low to High (Light Load)
3.6
3.6
3.7
3.9
4.0
4.1
4.2
4.2
4.3
4.5
4.7
4.8
ns
ns
Pad to R-cell Input High to Low (Light Load)
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
ns
ns
2.7
2.7
3.2
3.2
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
0.6
1.0
1.0
0.7
1.1
1.1
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
5.4
6.4
ns
fQMAX
Maximum Frequency
185
156
MHz
Revision 8
2-41
Detailed Specifications
Table 2-33 • RTSX72SU at VCCI = 4.5 V
Worst-Case Military Conditions VCCA = 2.25 V, VCCI = 4.5 V, TJ = 125°C
Radiation Level = 0 krad (Si)
–1 Speed
Std. Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Network
tHCKH
tHCKL
tHPWH
tHPWL
tHCKSW
tHP
Pad to R-cell Input Low to High
Pad to R-cell Input High to Low
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
4.1
4.1
4.8
4.8
ns
ns
2.8
2.8
3.3
3.3
ns
ns
3.2
3.7
ns
Minimum Period
5.6
6.6
ns
fHMAX
Maximum Frequency
179
152
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
tRPWH
tRPWL
tRCKSW
tRCKSW
tRCKSW
tQP
Pad to R-cell Input Low to High (Light Load))
6.8
8.2
6.8
8.2
6.8
8.2
8.0
9.7
8.0
9.7
8.0
9.7
ns
ns
Pad to R-cell Input High to Low (Light Load)
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
ns
ns
2.8
2.8
3.3
3.3
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
7.0
6.8
6.8
8.2
8.0
8.0
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
5.6
6.6
ns
fQMAX
Maximum Frequency
179
152
MHz
Quadrant Array Clock Networks
tQCKH
tQCKL
tQCKH
tQCKL
tQCKH
tQCKL
tQPWH
tQPWL
tQCKSW
tQCKSW
tQCKSW
tQP
Pad to R-cell Input Low to High (Light Load))
3.9
4.2
4.2
4.5
4.5
5.0
4.6
4.9
4.9
5.3
5.3
5.9
ns
ns
Pad to R-cell Input High to Low (Light Load)
Pad to R-cell Input Low to High (50% Load)
Pad to R-cell Input High to Low (50% Load)
Pad to R-cell Input Low to High (100% Load)
Pad to R-cell Input High to Low (100% Load)
Minimum Pulse Width High
ns
ns
ns
ns
2.8
2.8
3.3
3.3
ns
Minimum Pulse Width Low
ns
Maximum Skew (Light Load)
0.7
1.3
1.4
0.8
1.5
1.6
ns
Maximum Skew (50% Load)
ns
Maximum Skew (100% Load)
ns
Minimum Period
5.6
6.6
ns
fQMAX
Maximum Frequency
179
152
MHz
2-42
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Global Resource Access Macros
The user can configure which global resource is used in the design as well as how each global resource
is driven through the use of the following macros:
•
•
HCLKBUF – used to drive the hardwired clock (HCLK) in both devices from an external pin
CLKBUF and CLKBUFI – noninverting and inverting inputs used to drive either routed clock
(CLKA or CLKB) in both devices from external pins
•
•
•
•
CLKINT and CLKINTI – noninverting and inverting inputs used to drive either routed clock (CLKA
or CLKB) in both devices from internal logic
QCLKBUF and QCLKBUFI – noninverting and inverting inputs used to drive quadrant routed
clocks (QCLKA/B/C/D) in the RTSX72SU from external pins
QCLKINT and QCLKINTI – noninverting and inverting inputs used to drive quadrant routed clocks
(QCLKA/B/C/D) in the RTSX72SU from internal logic
QCLKBIBUF and QCLUKBIBUFI – noninverting and inverting inputs used to drive quadrant
routed clocks (QCLKA/B/C/D) in the RTSX72SU alternatively from either external pins or internal
logic
Figure 2-19, Figure 2-20, and Figure 2-21 illustrate the various global-resource access macros.
Constant Load
Clock Network
HCLKBUF
Figure 2-19 • Hardwired Clock Buffer
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 2-20 • Routed Clock Buffers in RTSX32SU
Revision 8
2-43
Detailed Specifications
OE
From Internal Logic
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
QCLKBUF
QCLKBUFI
QCLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
Figure 2-21 • Routed and Quadrant Clock Buffers in RTSX72SU
2-44
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Other Architectural Features
JTAG Interface
All RTSX-SU devices are IEEE 1149.1 compliant and offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through
special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by
two available modes: dedicated and flexible (Table 2-34). Note that TRST and TMS cannot be employed
as user I/Os in either mode.
Table 2-34 • Boundary Scan Pin Functionality
Dedicated Test Mode
Flexible Mode
TCK, TDI, TDO are dedicated BST pins
No need for pull-up resistor for TMS
TCK, TDI, TDO are flexible and may be used as user I/Os
Use a pull-up resistor of 10 kΩ on TMS
Dedicated Mode
In dedicated mode, all JTAG pins are reserved for BST; users cannot employ them as regular I/Os. An
internal pull-up resistor (on the order of 17 kΩ to 22 kΩ3) is automatically enabled on both TMS and TDI
pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification.
To enter dedicated mode, users need to reserve the JTAG pins in Microsemi’s Designer software during
device selection. To reserve the JTAG pins, users can check the Reserve JTAG box in the Device
Selection Wizard in the Designer software (Figure 2-22).
Figure 2-22 • Device Selection Wizard
Flexible Mode
In flexible mode, TDI, TCK, and TDO may be employed as either user I/Os or as JTAG input pins. The
internal resistors on the TMS and TDI pins are not present in flexible JTAG mode.
To enter the flexible mode, users need to clear the Reserve JTAG box in the Device Selection Wizard in
Designer software. TDI, TCK, and TDO pins may function as user I/Os or BST pins in flexible mode. This
functionality is controlled by the BST TAP controller. The TAP controller receives two control inputs: TMS
and TCK. Upon power-up, the TAP controller enters the Test-Logic-Reset state. In this state, TDI, TCK,
and TDO function as user I/Os. The TDI, TCK, and TDO are transformed from user I/Os into BST pins
when a rising edge on TCK is detected while TMS is at logic Low. To return to the Test-Logic-Reset state,
in the absences of TRST assertion, TMS must be held High for at least five TCK cycles. An external, 10
kΩ pull-up resistor tied to VCCI should be placed on the TMS pin to pull it High by default.
Table 2-35 describes the different configurations of the BST pins and their functionality in different
modes.
Table 2-35 • JTAG Pin Configurations and Functions
Mode
Designer Reserve JTAG Selection
TAP Controller State
Any
Dedicated (JTAG)
Flexible (User I/O)
Flexible (JTAG)
Checked
Unchecked
Unchecked
Test-Logic-Reset
Other
3. On a given device, the value of the internal pull-up resistor varies within 1 kW between the TMS and TDI pins.
Revision 8
2-45
Detailed Specifications
TRST Pin
The TRST pin functions as a dedicated boundary scan reset pin. An internal pull-up resistor is
permanently enabled on the TRST pin. Additionally, the TRST pin must be grounded for flight
applications. This will prevent single event upsets (SEU) in the TAP controller from inadvertently placing
the device into JTAG mode.
Probing Capabilities
RTSX-SU devices also provide internal probing capability that is accessed with the JTAG pins.
Silicon Explorer II Probe Interface
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Designer
software, allows users to examine any of the internal nets of the device while it is operating in a prototype
or a production system. The user can probe two nodes at a time without changing the placement or
routing of the design and without using any additional device resources. Highlighted nets in Designer’s
ChipEditor can be accessed using Silicon Explorer II in order to observe their real time values.
Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the
debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals
out to external pins, which is necessary when using programmable logic devices from other suppliers. By
eliminating multiple place-and-route cycles, the integrity of the design is maintained throughout the
debug process.
Both members of the RTSX-SU family have two external pads: PRA and PRB. These can be used to
bring out two probe signals from the device. To disallow probing, the SFUS security fuse in the silicon
signature has to be programmed. Table 2-36 shows the possible device configuration options and their
effects on probing.
During probing, the Silicon Explorer II Diagnostic Hardware is used to control the TDI, TCK, TMS, and
TDO pins to select the desired nets for debugging. The user simply assigns the selected internal nets in
the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is
activated when the BST pins are in JTAG mode and the TRST pin is driven High. If the TRST pin is held
Low, the TAP controller will remain in the Test-Logic-Reset state, so no probing can be performed. Silicon
Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin High or
allow the internal pull-up resistor to pull TRST High.
Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the
circuit board are achieved using a nine-pin D-Sub connector (Figure 1-5 on page 1-8). Once the design
has been placed-and-routed and the RTSX-SU device has been programmed, Silicon Explorer II can be
connected and the Silicon Explorer software can be launched.
Silicon Explorer II comes with an additional optional PC-hosted tool that emulates an 18-channel logic
analyzer. Two channels are used to monitor two internal nodes, and 16 channels are available to probe
external signals. The software included with the tool provides the user with an intuitive interface that
allows for easy viewing and editing of signal waveforms.
Table 2-36 • Device Configuration Options for Probe Capability
JTAG Mode TRST Security Fuse Programmed
PRA and PRB1
User I/O2
TDI, TCK, and TDO1
Probing Unavailable
User I/O2
Dedicated
Flexible
Dedicated
Flexible
–
Low
Low
High
High
–
No
No
No
No
Yes
User I/O2
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit I/O
Probe Circuit I/O
Probe Circuit Secured Probe Circuit Secured
Notes:
1. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports during probing. Since
these pins are active during probing, input signals will not pass through these pins and may cause
contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are
automatically tristated by the Designer software.
2-46
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Security Fuses
Microsemi antifuse FPGAs, with FuseLock technology, offer the highest level of design security available
in a programmable logic device. Since antifuse FPGAs are live at power-up, there is no bitstream that
can be intercepted, and no bitstream or programming data is ever downloaded to the device, thus
making device cloning virtually impossible. In addition, special security fuses are hidden throughout the
fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the
device by attempting to exploit either the programming or probing interfaces. Both invasive and
noninvasive attacks against an RTSX-SU device that access or bypass these security fuses will destroy
access to the rest of the device. Refer to the Understanding Actel Antifuse Device Security white paper
for more information.
Look for this symbol to ensure your valuable IP is protected with the highest level of security available in
the industry (Figure 2-23).
®
FuseLock
Figure 2-23 • FuseLock Logo
To ensure maximum security in RTSX-SU devices, it is recommended that the user program the device
security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent
internal probing, and the programming interface is also disabled. All JTAG public instructions are still
accessible by the user. For more information, refer to the Implementation of Security in Actel Antifuse
FPGAs application note.
Programming
Device programming is supported through the Silicon Sculptor series programmers. These programmers
are single-site, robust and compact device-programmers for the PC. Multiple Silicon Sculptor
programmers can be daisy-chained and controlled from a single PC host. The number of programmers
that can be daisy chained depends on the programmer model. With standalone software for the PC,
Silicon Sculptor programmers are designed to allow concurrent programming of multiple units from the
same PC when daisy-chained.
Silicon Sculptor programmers program devices independently to achieve the fastest programming times
possible. Each fuse is verified by Silicon Sculptor programmers to ensure correct programming.
Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming
was completed properly.
Not only do they test programmed and nonprogrammed fuses, Silicon Sculptor programmers also
provide a self-test to extensively test their own hardware.
Programming an RTSX-SU device using a Silicon Sculptor programmer is similar to programming any
other antifuse device. The procedure is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers volume programming services either
through distribution partners or via our In-House Programming Center. For more details on programming
RTSX-SU devices, refer to the Silicon Sculptor Software v5.0 for Silicon Sculptor II and Silicon Sculptor 3
Programmer User’s Guide. Find more information on the Microsemi SoC Products Group website:
http://www.microsemi.com/soc/products/hardware/program_debug/ss/default.aspx#docs.
Revision 8
2-47
3 – Package Pin Assignments
CQ84
Pin 1 indicator
may be in a different
shape for different
devices.
84
64
1
63
21
22
43
42
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/default.aspx.
Revision 8
3-1
Package Pin Assignments
CQ84
CQ84
CQ84
Pin Number RTSX32SU Function
Pin Number RTSX32SU Function
Pin Number RTSX32SU Function
1
I/O
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
GND
I/O
73
74
75
76
77
78
79
80
81
82
83
84
CLKB
PRA, I/O
I/O
2
3
TMS
I/O
TDO, I/O
I/O
4
I/O
5
VCCI
GND
I/O
I/O
I/O
6
I/O
GND
VCCA
I/O
7
I/O
8
I/O
I/O
9
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I/O
VCCA
VCCI
GND
I/O
TCK, I/O
TDI, I/O
I/O
TRST
I/O
I/O
I/O
I/O
VCCA
GND
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
I/O
I/O
I/O
VCCA
GND
I/O
I/O
GND
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
HCLK
I/O
VCCI
GND
I/O
I/O
I/O
VCCA
CLKA
3-2
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CQ208
1
2
3
4
156
155
154
153
Pin 1
Ceramic
Tie Bar
208-Pin CQFP
49
50
51
52
108
107
106
105
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/default.aspx.
Revision 8
3-3
Package Pin Assignments
CQ208
CQ208
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
Pin Number
38
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
2
39
3
40
VCCI
VCCA
I/O
VCCI
VCCA
I/O
4
I/O
I/O
41
5
I/O
I/O
42
6
I/O
I/O
43
I/O
I/O
7
I/O
I/O
44
I/O
I/O
8
I/O
I/O
45
I/O
I/O
9
I/O
I/O
46
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I/O
I/O
47
I/O
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
48
I/O
I/O
49
I/O
I/O
50
I/O
I/O
I/O
I/O
51
I/O
I/O
I/O
I/O
52
GND
I/O
GND
I/O
I/O
I/O
53
I/O
I/O
54
I/O
I/O
I/O
GND
VCCA
I/O
55
I/O
I/O
I/O
56
I/O
I/O
I/O
57
I/O
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
60
VCCI
I/O
VCCI
I/O
I/O
I/O
61
NC
I/O
62
I/O
I/O
GND
VCCA
GND
I/O
GND
VCCA
GND
I/O
63
I/O
I/O
64
I/O
I/O
65
NC
I/O
I/O
66
I/O
TRST
I/O
TRST
I/O
67
I/O
I/O
68
I/O
I/O
I/O
I/O
69
I/O
I/O
I/O
I/O
70
I/O
I/O
I/O
I/O
71
I/O
I/O
I/O
I/O
72
I/O
I/O
I/O
I/O
73
I/O
I/O
I/O
I/O
74
I/O
QCLKA, I/O
3-4
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CQ208
CQ208
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
75
Pin Number
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
I/O
PRB, I/O
GND
VCCA
GND
NC
I/O
PRB, I/O
GND
VCCA
GND
NC
I/O
I/O
I/O
I/O
76
77
VCCA
VCCI
I/O
VCCA
VCCI
GND
VCCA
I/O
78
79
80
I/O
81
I/O
I/O
I/O
82
HCLK
I/O
HCLK
VCCI
QCLKB, I/O
I/O
I/O
I/O
83
I/O
I/O
84
I/O
I/O
I/O
85
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
89
I/O
I/O
I/O
I/O
90
I/O
I/O
I/O
I/O
91
I/O
I/O
I/O
I/O
92
I/O
I/O
GND
VCCA
GND
NC
GND
VCCA
GND
I/O
93
I/O
I/O
94
I/O
I/O
95
I/O
I/O
96
I/O
I/O
I/O
I/O
97
I/O
I/O
I/O
I/O
98
VCCI
I/O
VCCI
I/O
I/O
I/O
99
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCI
Revision 8
3-5
Package Pin Assignments
CQ208
CQ208
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
Pin Number
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
I/O
I/O
I/O
PRA, I/O
I/O
PRA, I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKC, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKD, I/O
I/O
I/O
CLKA
CLKB
NC
GND
VCCA
GND
CLKA, I/O
CLKB, I/O
NC
GND
VCCA
GND
3-6
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CQ256
1
2
3
4
192
191
190
189
Pin 1
Ceramic
Tie Bar
256-Pin CQFP
61
62
63
64
132
131
130
129
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/default.aspx.
Revision 8
3-7
Package Pin Assignments
CQ256
CQ256
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
Pin Number
38
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
39
3
40
I/O
4
I/O
I/O
41
I/O
5
I/O
I/O
42
I/O
6
I/O
I/O
43
I/O
7
I/O
I/O
44
I/O
8
I/O
I/O
45
I/O
9
I/O
I/O
46
VCCA
VCCI
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I/O
I/O
47
TMS
I/O
TMS
I/O
48
49
I/O
I/O
I/O
50
I/O
I/O
I/O
51
I/O
I/O
I/O
52
I/O
I/O
I/O
53
I/O
I/O
VCCI
I/O
54
I/O
I/O
55
I/O
I/O
I/O
56
GND
I/O
I/O
I/O
57
I/O
I/O
58
I/O
I/O
I/O
59
GND
I/O
I/O
I/O
60
I/O
I/O
61
I/O
I/O
I/O
62
I/O
I/O
I/O
63
I/O
I/O
I/O
64
I/O
VCCI
GND
VCCA
GND
I/O
VCCI
GND
VCCA
GND
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
I/O
I/O
70
I/O
TRST
I/O
TRST
I/O
71
I/O
72
I/O
I/O
VCCA
GND
73
VCCI
I/O
I/O
74
3-8
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CQ256
CQ256
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
75
Pin Number
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
76
77
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
I/O
79
I/O
I/O
I/O
I/O
80
I/O
I/O
I/O
I/O
81
I/O
I/O
I/O
I/O
82
I/O
I/O
I/O
I/O
83
I/O
I/O
I/O
VCCI
I/O
84
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
89
I/O
QCLKA, I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
TDO, I/O
I/O
TDO, I/O
I/O
90
PRB, I/O
GND
VCCI
GND
VCCA
I/O
91
GND
I/O
GND
I/O
92
93
I/O
I/O
94
I/O
I/O
95
I/O
I/O
96
HCLK
I/O
HCLK
I/O
I/O
I/O
97
I/O
I/O
98
I/O
QCLKB, I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
VCCI
GND
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
Revision 8
3-9
Package Pin Assignments
CQ256
CQ256
RTSX32SU
Function
RTSX72SU
Function
RTSX32SU
Function
RTSX72SU
Function
Pin Number
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
Pin Number
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
NC
GND
VCCI
I/O
GND
NC
I/O
I/O
I/O
I/O
GND
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
I/O
I/O
212
213
214
215
216
217
218
219
220
221
222
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QCLKD, I/O
CLKA, I/O
CLKB, I/O
VCCI
GND
I/O
I/O
CLKA
CLKB
VCCI
GND
I/O
VCCI
I/O
I/O
I/O
I/O
3-10
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CQ256
RTSX32SU
Function
RTSX72SU
Function
Pin Number
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
NC
GND
PRA, I/O
I/O
NC
GND
PRA, I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
QCLKC, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
Revision 8
3-11
Package Pin Assignments
CC256
Top View
A1 Index Corner
256
193
192
Extenral Wire-Bond Number
1
64
129
65
128
Bottom View
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/default.aspx.
3-12
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
A1
Pin Number
C3
1
GND
TCK, I/O
I/O
65
252
249
245
239
230
226
218
210
201
197
211
178
195
12
GND
I/O
A2
256
255
251
243
238
232
228
227
221
216
209
203
200
2
C4
A3
C5
I/O
A4
I/O
C6
I/O
A5
I/O
C7
I/O
A6
I/O
C8
I/O
A7
I/O
C9
CLKA
I/O
A8
I/O
C10
C11
C12
C13
C14
C15
C16
D1
A9
CLKB
I/O
I/O
A10
A11
A12
A13
A14
A15
A16
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
13
D2
8
I/O
242
22
D3
10
I/O
B2
GND
I/O
D4
7
I/O
B3
254
253
248
241
234
33
D5
250
244
237
229
217
208
206
199
205
173
190
188
16
I/O
B4
I/O
D6
I/O
B5
I/O
D7
I/O
B6
I/O
D8
PRA, I/O
I/O
B7
I/O
D9
B8
VCCA
I/O
D10
D11
D12
D13
D14
D15
D16
E1
I/O
B9
222
220
212
207
202
198
32
I/O
B10
B11
B12
B13
B14
B15
B16
C1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
196
6
E2
15
I/O
I/O
E3
9
I/O
C2
4
TDI,I/O
E4
11
I/O
Note: *This table was sorted by the pin number.
Note: *This table was sorted by the pin number.
Revision 8
3-13
Package Pin Assignments
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
E5
Pin Number
G7
5
I/O
I/O
43
54
GND
GND
GND
GND
VCCI
I/O
E6
240
233
231
223
219
213
167
183
189
187
186
17
G8
E7
I/O
G9
67
E8
I/O
G10
G11
G12
G13
G14
G15
G16
H1
77
E9
I/O
87
E10
E11
E12
E13
E14
E15
E16
F1
I/O
169
180
176
179
175
29
I/O
GND
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
H2
31
I/O
I/O
H3
160
35
VCCA
TRST
I/O
F2
18
I/O
H4
F3
20
I/O
H5
37
F4
14
TMS
I/O
H6
108
86
VCCI
GND
GND
GND
GND
VCCI
I/O
F5
19
H7
F6
28
I/O
H8
96
F7
3
VCCI
VCCI
VCCI
VCCI
I/O
H9
107
118
128
165
170
168
166
174
30
F8
23
H10
H11
H12
H13
H14
H15
H16
J1
F9
44
F10
F11
F12
F13
F14
F15
F16
G1
55
157
97
I/O
VCCA
I/O
I/O
177
185
184
181
24
I/O
I/O
I/O
I/O
I/O
I/O
J2
38
I/O
I/O
J3
40
I/O
G2
25
I/O
J4
41
I/O
G3
27
I/O
J5
39
I/O
G4
26
I/O
J6
139
127
140
VCCI
GND
GND
G5
21
I/O
J7
G6
66
VCCI
J8
Note: *This table was sorted by the pin number.
Note: *This table was sorted by the pin number.
3-14
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
J9
Pin Number
L11
L12
L13
L14
L15
L16
M1
151
161
150
159
163
164
162
158
34
GND
GND
VCCI
I/O
103
149
146
148
145
147
42
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
J10
J11
J12
J13
J14
J15
J16
K1
I/O
I/O
I/O
I/O
M2
53
I/O
M3
61
K2
45
I/O
M4
60
K3
47
I/O
M5
72
K4
50
VCCA
I/O
M6
81
K5
48
M7
89
K6
171
172
182
192
204
191
153
155
156
152
154
36
VCCI
GND
GND
GND
GND
VCCI
I/O
M8
95
K7
M9
101
105
114
111
141
142
137
144
49
K8
M10
M11
M12
M13
M14
M15
M16
N1
K9
K10
K11
K12
K13
K14
K15
K16
L1
I/O
I/O
I/O
I/O
N2
57
I/O
N3
63
L2
46
I/O
N4
79
L3
51
I/O
N5
70
L4
58
I/O
N6
76
L5
52
I/O
N7
83
L6
91
I/O
N8
99
L7
194
214
235
246
VCCI
VCCI
VCCI
VCCI
N9
109
117
112
124
L8
N10
N11
N12
L9
L10
Note: *This table was sorted by the pin number.
Note: *This table was sorted by the pin number.
Revision 8
3-15
Package Pin Assignments
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
N13
N14
N15
N16
P1
Pin Number
R15
R16
T1
121
133
135
136
59
I/O
I/O
225
193
236
69
GND
GND
GND
I/O
I/O
I/O
T2
I/O
T3
71
I/O
P2
138
56
GND
I/O
T4
75
I/O
P3
T5
80
I/O
P4
74
I/O
T6
84
I/O
P5
64
I/O
T7
88
I/O
P6
82
I/O
T8
93
I/O
P7
90
I/O
T9
224
102
110
116
122
125
129
247
VCCA
I/O
P8
94
I/O
T10
T11
T12
T13
T14
T15
T16
P9
104
113
119
123
143
131
132
134
62
I/O
I/O
P10
P11
P12
P13
P14
P15
P16
R1
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
TDO,I/O
GND
I/O
Note: *This table was sorted by the pin number.
I/O
I/O
R2
215
68
GND
I/O
R3
R4
73
I/O
R5
78
I/O
R6
85
I/O
R7
92
I/O
R8
98
I/O
R9
100
106
115
120
126
130
HCLK
I/O
R10
R11
R12
R13
R14
I/O
I/O
I/O
I/O
Note: *This table was sorted by the pin number.
3-16
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
A1
Pin Number
H4
L1
1
GND
GND
VCCI
TDI,I/O
I/O
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
TRST
I/O
A15
F7
2
3
H5
J2
I/O
C2
E5
4
I/O
5
J5
I/O
C1
D4
D2
E3
6
I/O
J3
I/O
7
I/O
J4
I/O
8
I/O
M1
G7
F9
I/O
9
I/O
GND
VCCI
I/O
D3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O
E4
I/O
K2
D1
I/O
L2
I/O
A16
F4
GND
TMS
I/O
K3
I/O
K5
I/O
E2
N1
K4
I/O
E1
I/O
VCCA
I/O
F1
I/O
L3
F2
I/O
L5
I/O
F5
I/O
M2
G8
F10
P3
I/O
F3
I/O
GND
VCCI
I/O
G5
B2
I/O
GND
VCCI
I/O
F8
N2
L4
I/O
G1
G2
G4
G3
F6
I/O
I/O
P1
I/O
I/O
M4
M3
R1
N3
P5
I/O
I/O
I/O
I/O
I/O
H1
I/O
I/O
J1
I/O
I/O
H2
I/O
C3
G6
G9
R3
GND
VCCI
GND
I/O
B15
B8
GND
VCCA
I/O
K1
Note: *This table was sorted by the wire-bond number.
Note: *This table was sorted by the wire-bond number.
Revision 8
3-17
Package Pin Assignments
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
T2
Pin Number
L11
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
I/O
I/O
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
I/O
I/O
N5
P9
T3
I/O
M10
R10
H9
I/O
M5
R4
I/O
I/O
I/O
GND
VCCI
I/O
P4
I/O
H6
T4
I/O
N9
N6
I/O
T11
I/O
G10
R5
GND
I/O
M12
N11
P10
M11
R11
T12
N10
H10
P11
R12
N13
T13
P12
N12
T14
R13
J7
I/O
I/O
N4
I/O
I/O
T5
I/O
I/O
M6
P6
I/O
I/O
I/O
I/O
N7
I/O
I/O
T6
I/O
GND
I/O
R6
I/O
H7
GND
VCCI
I/O
I/O
G11
T7
I/O
I/O
M7
P7
I/O
I/O
I/O
I/O
L6
I/O
I/O
R7
I/O
I/O
T8
I/O
GND
VCCI
TDO,I/O
I/O
P8
I/O
H11
T15
R14
P14
P15
N14
P16
N15
N16
M8
H8
PRB, I/O
GND
VCCA
I/O
F12
R8
I/O
I/O
N8
I/O
I/O
R9
HCLK
I/O
I/O
M9
T10
I/O
I/O
I/O
Note: *This table was sorted by the wire-bond number.
Note: *This table was sorted by the wire-bond number.
3-18
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
M15
P2
Pin Number
K6
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
I/O
GND
VCCI
GND
I/O
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
VCCI
GND
I/O
K7
J6
D14
H16
G16
G14
F13
C15
G15
G13
F16
K8
J8
I/O
M13
M14
P13
M16
L15
L13
L16
L14
L12
J11
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
VCCA
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
E13
F15
F14
E16
E15
D16
E14
D15
K11
K9
VCCI
GND
I/O
I/O
J9
I/O
K15
K12
K16
K13
K14
F11
J16
J12
H3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
GND
VCCI
I/O
I/O
I/O
R16
L7
VCCA
GND
I/O
J10
J15
J13
J14
H12
H15
E12
H14
G12
H13
C16
B16
C13
B14
D12
A14
C12
B13
A13
K10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
Note: *This table was sorted by the wire-bond number.
Note: *This table was sorted by the wire-bond number.
Revision 8
3-19
Package Pin Assignments
CC256*
CC256*
External Wire-
Bond Number
RTSX32SU
Function
External Wire-
Bond Number
RTSX32SU
Function
Pin Number
D13
D11
B12
D10
A12
C11
C14
B11
E11
L8
Pin Number
C7
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
I/O
I/O
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
E6
I/O
B6
I/O
I/O
B1
I/O
I/O
A5
I/O
I/O
D6
I/O
I/O
C6
I/O
I/O
L10
T16
B5
VCCI
GND
I/O
I/O
VCCI
GND
I/O
R2
C5
I/O
A11
D9
D5
I/O
I/O
A4
I/O
C10
E10
B10
A10
B9
I/O
C4
I/O
I/O
B4
I/O
I/O
B3
I/O
I/O
A3
I/O
I/O
A2
TCK, I/O
E9
I/O
Note: *This table was sorted by the wire-bond number.
T9
VCCA
GND
CLKA
CLKB
I/O
R15
C9
A9
A8
D8
PRA, I/O
I/O
C8
E8
I/O
A7
I/O
E7
I/O
B7
I/O
L9
VCCI
GND
I/O
T1
D7
A6
I/O
Note: *This table was sorted by the wire-bond number.
3-20
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CG624
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/solutions/package/default.aspx.
Revision 8
3-21
Package Pin Assignments
CG624
CG624
RTSX72SU
CG624
RTSX72SU
RTSX72SU
Pin Number
A2
Function
Pin Number
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C1
Function
Pin Number
C22
C23
C24
C25
D1
Function
NC
I/O
I/O
A3
NC
I/O
GND
VCCI
NC
A4
NC
CLKB, I/O
I/O
A5
I/O
A6
I/O
I/O
GND
GND
TDI, I/O
GND
I/O
A7
I/O
I/O
D2
A8
I/O
I/O
D3
A9
I/O
I/O
D4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
I/O
I/O
D5
I/O
I/O
D6
I/O
I/O
GND
VCCI
GND
NC
D7
I/O
GND
I/O
D8
I/O
D9
I/O
I/O
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E1
I/O
I/O
NC
I/O
I/O
C2
VCCI
GND
I/O
I/O
I/O
C3
I/O
I/O
C4
QCLKD, I/O
I/O
I/O
C5
I/O
I/O
C6
I/O
I/O
GND
NC
C7
I/O
I/O
C8
I/O
I/O
NC
C9
I/O
I/O
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
I/O
I/O
NC
QCLKC, I/O
I/O
I/O
B2
GND
GND
VCCI
GND
I/O
VCCI
GND
GND
GND
I/O
B3
PRA, I/O
CLKA, I/O
I/O
B4
B5
B6
I/O
B7
I/O
I/O
E2
I/O
B8
VCCI
GND
I/O
I/O
E3
I/O
B9
I/O
E4
I/O
B10
B11
I/O
E5
TCK, I/O
I/O
I/O
I/O
E6
3-22
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CG624
RTSX72SU
CG624
RTSX72SU
CG624
RTSX72SU
Pin Number
E7
Function
Pin Number
F17
F18
F19
F20
F21
F22
F23
F24
F25
G1
Function
Pin Number
H2
Function
I/O
I/O
I/O
E8
I/O
I/O
H3
I/O
E9
I/O
I/O
H4
I/O
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
F1
I/O
I/O
H5
I/O
I/O
I/O
H6
I/O
VCCA
GND
I/O
I/O
H7
I/O
I/O
H8
VCCI
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCI
I/O
I/O
H9
I/O
I/O
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
J1
I/O
I/O
I/O
G2
I/O
I/O
G3
TMS
I/O
I/O
G4
I/O
G5
I/O
I/O
G6
I/O
I/O
G7
VCCI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
VCCI
I/O
I/O
G8
I/O
G9
I/O
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
H1
I/O
I/O
I/O
F2
VCCI
I/O
I/O
F3
I/O
F4
I/O
GND
I/O
F5
I/O
F6
NC
NC
I/O
I/O
F7
J2
I/O
F8
J3
I/O
F9
NC
NC
NC
NC
I/O
J4
I/O
F10
F11
F12
F13
F14
F15
F16
J5
I/O
I/O
J6
I/O
I/O
J7
NC
NC
VCCI
NC
NC
I/O
J8
I/O
I/O
J9
NC
GND
I/O
J10
J11
I/O
Revision 8
3-23
Package Pin Assignments
CG624
CG624
RTSX72SU
CG624
RTSX72SU
RTSX72SU
Pin Number
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
K1
Function
Pin Number
K22
K23
K24
K25
L1
Function
Pin Number
M7
Function
NC
I/O
NC
NC
I/O
M8
NC
NC
I/O
M9
NC
NC
I/O
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
N1
GND
GND
GND
GND
GND
GND
GND
NC
NC
I/O
VCCI
NC
L2
I/O
L3
I/O
NC
L4
I/O
I/O
L5
I/O
VCCA
I/O
L6
I/O
L7
NC
I/O
L8
NC
NC
I/O
L9
NC
NC
I/O
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M1
GND
GND
GND
GND
GND
GND
GND
NC
I/O
I/O
GND
I/O
K2
GND
I/O
K3
I/O
K4
I/O
GND
I/O
K5
I/O
K6
GND
NC
I/O
K7
N2
I/O
K8
NC
NC
N3
I/O
K9
NC
NC
N4
I/O
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
GND
GND
GND
GND
GND
GND
GND
NC
I/O
N5
VCCA
I/O
I/O
N6
I/O
N7
VCCA
NC
I/O
N8
I/O
N9
NC
I/O
N10
N11
N12
N13
N14
N15
N16
GND
GND
GND
GND
GND
GND
GND
I/O
M2
I/O
NC
M3
I/O
NC
M4
I/O
I/O
M5
GND
I/O
I/O
M6
3-24
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CG624
RTSX72SU
CG624
RTSX72SU
CG624
RTSX72SU
Pin Number
N17
N18
N19
N20
N21
N22
N23
N24
N25
P1
Function
Pin Number
R2
Function
Pin Number
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
U1
Function
GND
GND
GND
GND
GND
NC
NC
I/O
NC
R3
I/O
VCCA
I/O
R4
TRST
I/O
R5
VCCA
I/O
R6
GND
NC
R7
I/O
R8
NC
NC
VCCI
I/O
R9
NC
NC
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T1
GND
GND
GND
GND
GND
GND
GND
NC
GND
I/O
I/O
P2
I/O
I/O
P3
I/O
I/O
P4
I/O
I/O
P5
I/O
I/O
P6
I/O
I/O
P7
NC
U2
I/O
P8
NC
NC
U3
I/O
P9
NC
NC
U4
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
R1
GND
GND
GND
GND
GND
GND
GND
NC
I/O
U5
I/O
I/O
U6
I/O
I/O
U7
I/O
I/O
U8
NC
I/O
U9
VCCI
NC
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
I/O
NC
T2
I/O
NC
NC
T3
I/O
NC
NC
T4
I/O
NC
I/O
T5
I/O
NC
GND
I/O
T6
I/O
NC
T7
I/O
VCCI
NC
I/O
T8
NC
I/O
T9
NC
NC
I/O
T10
T11
GND
GND
I/O
I/O
I/O
Revision 8
3-25
Package Pin Assignments
CG624
CG624
RTSX72SU
CG624
RTSX72SU
RTSX72SU
Pin Number
U22
U23
U24
U25
V1
Function
Pin Number
W7
Function
VCCI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O
Pin Number
Y17
Function
I/O
I/O
I/O
W8
Y18
I/O
I/O
W9
Y19
I/O
I/O
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y1
Y20
I/O
I/O
Y21
I/O
V2
I/O
Y22
I/O
V3
I/O
Y23
I/O
V4
VCCA
I/O
Y24
GND
I/O
V5
Y25
V6
I/O
AA1
GND
GND
I/O
V7
GND
VCCI
NC
AA2
V8
AA3
V9
VCCI
I/O
AA4
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
W1
NC
AA5
GND
I/O
NC
I/O
AA6
NC
I/O
AA7
I/O
NC
I/O
AA8
I/O
NC
I/O
AA9
I/O
NC
I/O
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AB1
I/O
NC
I/O
I/O
NC
Y2
I/O
I/O
VCCI
I/O
Y3
I/O
VCCA
GND
I/O
Y4
I/O
I/O
Y5
I/O
I/O
Y6
I/O
I/O
VCCA
I/O
Y7
I/O
I/O
Y8
I/O
I/O
I/O
Y9
I/O
I/O
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
I/O
I/O
I/O
NC
GND
I/O
GND
I/O
W2
VCCI
I/O
W3
I/O
W4
I/O
NC
GND
I/O
I/O
W5
I/O
GND
NC
W6
I/O
3-26
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
CG624
RTSX72SU
CG624
RTSX72SU
CG624
RTSX72SU
Pin Number
AB2
Function
VCCI
I/O
Pin Number
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD1
Function
PRB, I/O
I/O
Pin Number
AD22
AD23
AD24
AD25
AE1
Function
GND
VCCI
GND
NC
AB3
AB4
GND
I/O
HCLK
I/O
AB5
AB6
I/O
I/O
NC
AB7
I/O
I/O
AE2
NC
AB8
I/O
I/O
AE3
NC
AB9
I/O
I/O
AE4
GND
I/O
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AC1
I/O
I/O
AE5
I/O
I/O
AE6
I/O
QCLKA, I/O
I/O
I/O
AE7
I/O
GND
I/O
AE8
I/O
I/O
AE9
I/O
I/O
NC
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
I/O
I/O
NC
I/O
I/O
AD2
GND
VCCI
GND
I/O
I/O
I/O
AD3
I/O
I/O
AD4
QCLKB, I/O
I/O
I/O
AD5
TDO, I/O
VCCI
I/O
AD6
I/O
I/O
AD7
I/O
I/O
AD8
I/O
I/O
VCCI
NC
AD9
I/O
I/O
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
VCCI
I/O
I/O
NC
I/O
AC2
I/O
I/O
GND
NC
AC3
GND
I/O
I/O
AC4
I/O
NC
AC5
I/O
I/O
NC
AC6
I/O
GND
I/O
AC7
I/O
AC8
I/O
I/O
AC9
I/O
I/O
AC10
AC11
I/O
I/O
I/O
I/O
Revision 8
3-27
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the document.
Revision
Changes
Page
Revision 8
(January 2012)
The "Designed for Space" section bullet regarding single event latch-up immunity was
revised to "Single Event Latch-Up (SEL) Immunity to LETTH > 104 MeVcm2/mg" (SAR
33213).
i
The "Features" section and "Security Fuses" section were revised to clarify that i, 2-47
although no existing security measures can give an absolute guarantee, Microsemi
FPGAs implement the best security available in the industry (SAR 34672).
Package names used throughout the document the were revised to match standards i, 3-1
given in Package Mechanical Drawings (SAR 34783).
Notes stating that All CCGA PROTOs will be offered in Six Sigma Columns were
removed from the "Ordering Information" section and "Temperature Grade and
Application Offering" section (SAR 36171).
ii, iii
vi
A note was added to the "EV Flow (Class V Flow Equivalent Processing)" table
regarding an enhancement to the Au ball bonding process control (SAR 36172).
References to Silicon Sculptor II were changed to Silicon Sculptor series programmers 1-6,
(SAR 36473).
2-47
The following note was added to Table 2-3 • Absolute Maximum Conditions1 (SAR
32303):
2-2
For AC signals, the 5 V non-PCI input signals may overshoot during transitions to VCCI
+ 1.2 V for no longer than 11 ns. The 3.3V non-PCI input signals may overshoot during
transitions to 6.0 V for no longer than 11 ns. Current during the transition must not
exceed 95 mA. Refer to PCI specifications for the PCI input overshoot limit.
EQ 2 was changed from PDC = (ICC) * VCCA + (ICC) * VCCI to PDC = ICCA * VCCA +
ICCI * VCCI (SAR 35679).
The "Hot Swapping" section was revised. Table 2-3 • Time at which I/Os Become Active 2-13,
by Ramp Rate was deleted. The information from this table is in the Microsemi SX-A
and RTSX-SU Devices in Hot-Swap and Cold-Sparing Applications application note
(SAR 35624).
2-1
The equation for slew rate, which first appears in the note for Table 2-13 • RTSX32SU 2-18
5 V TTL and 3.3 V LVTTL I/O Module, was revised by adding "±." It is negative for falling
edges and positive for rising edges. The equation was revised in each place it occurs in
the datasheet (SAR 30955).
Revision 7
(October 2010)
The range for VCCA DC core supply voltage in Table 2-3 • Absolute Maximum
Conditions1 was erroneously changed in Revision 6 of the datasheet from "–0.3 to 3.0"
to "0.3 to 3.0." It has now been changed back to the correct value of "–0.3 to 3.0."
2-2
Revision 6
(May 2010)
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "RTSX-SU
Device Status" table indicates the status for each device in the family.
N/A
The "Processing Flows" section and "Prototyping Options" section are new.
i
The "Ordering Information" table was updated to add the EV and PROTO application
(temperature range) ordering codes.
ii
Revision 8
4-1
Datasheet Information
Revision
Changes
Page
Revision 6
(continued)
A note was added to the "Ordering Information" table and "Temperature Grade and
Application Offering" table to explain that PROTO refers to RTSX-SU prototype units.
All CCGA PROTOs will be offered in Six Sigma Columns.
ii
The note for the "Ceramic Device Resources" table regarding availability of the 256-pin
CCLG package for military temperature only was deleted.
iii
iii
EV and PROTO were added to the "Temperature Grade and Application Offering" table.
The B and E codes were also added for the CG256 package for RTSX32SU.
The "Speed Grade and Temperature Grade Matrix" table was replaced.
iii
A note regarding performing CCGA tests at LGA level was added to Table 2 • MIL-STD-
883 Class B Product Flow* for RTSX32SU and RTSX72SU and Table 3 • Extended
Flow for RTSX32SU and RTSX72SU1,2.
iv, v
Table 4 • EV Flow (Class V Equivalent Flow Processing) for RTSX32SU and
RTSX72SU1, 2, 3 is new.
vi
The "Low-Cost Prototyping Solution" section was expanded to include prototyping with
RTSX-SU PROTO units.
1-7
2-1
2-2
2-2
A note was added to Table 2-2 • Characteristics for All I/O Configurations, giving
information about power-up resistor pull.
Table 2-3 • Absolute Maximum Conditions1 was revised. The TJ and VO parameters
and some notes were added.
Temperature range and the ICC standby current parameter were added to Table 2-4 •
Recommended Operating Conditions (SAR 62430).
Table 2-5 • RTSX-SU Standby Current is new.
2-3
2-4
The "AC Power Dissipation" section was revised, including the addition of two formulas
for power dissipation for the RTSX72SU device. Additional parameters were added to
Table 2-6 • Fixed Power Parameters. The definition of CL given in relation to EQ 6 was
changed to "output load capacitance in pF" (SAR 69980).
A note was added to the "User I/O" section to exercise care when using JTAG to tristate 2-13
all I/Os (SAR 79515).
The "Using the Weak Pull-Up and Pull-Down Circuits" section is new (SAR 79515).
2-14
The minimum value for VIL (– 0.5 V) was added to Table 2-12 • 5 V TTL and 3.3 V 2-16,
LVTTL Electrical Specifications and Table 2-15 • 5 V CMOS Electrical Specifications 2-19
(SAR 41193). The second table note, regarding overshoot for AC signals, was
deleted (SAR 68437).
Values in the following tables were revised (SAR 68197). The tENHZS parameter was 2-17,
added where applicable.
2-18,
2-20,
2-21
Table 2-13 • RTSX32SU 5 V TTL and 3.3 V LVTTL I/O Module
Table 2-14 • RTSX72SU 5 V TTL and 3.3 V LVTTL I/O Module,
Table 2-16 • RTSX32SU 5 V CMOS I/O Module
Table 2-17 • RTSX72SU 5 V CMOS I/O Module
A note regarding undershoot for AC signals was added to Table 2-18 • 5 V PCI DC 2-22
Specifications (SAR 68437).
Values in the following tables were revised (SAR 68197).
Table 2-20 • RTSX32SU 5 V PCI I/O Module
Table 2-21 • RTSX72SU 5 V PCI I/O Module
2-24
4-2
Revision 8
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Revision
Changes
Page
Revision 6
(continued)
Notes regarding undershoot and overshoot for AC signals were added to Table 2-22 • 2-26
3.3 V PCI DC Specifications (SAR 68437).
Values in the following tables were revised (SAR 68197).
Table 2-24 • RTSX32SU 3.3 V PCI I/O Module
Table 2-25 • RTSX72SU 3.3 V PCI I/O Module
2-28
The note in the "CQ208" table stating that pin 65 is a no connect on commercial
A54SX32S PQ208 was deleted (SAR 52216).
3-4
v2.2
(March 2006)
The notes in Table 2-12 • 5 V TTL and 3.3 V LVTTL Electrical Specifications were 2-16
updated.
The notes in Table 2-15 • 5 V CMOS Electrical Specifications were updated.
Figure 1-5 • Probe Setup was updated and a note was added.
2-19
1-8
v2.1
Table 2-12 • 5 V TTL and 3.3 V LVTTL Electrical Specifications was updated to include 2-16
Notes 2 and 3.
Table 2-15 • 5 V CMOS Electrical Specifications was updated to include Notes 1 and 2.
Footnote 1 and Footnote 2 in the "Pin Descriptions" section were updated.
2-19
2-11,
2-12
v2.0
The "RTSX-SU Product Profile" table was updated to include the CQ84.
The "Ceramic Device Resources" table was updated to include CQ84.
The "Temperature Grade and Application Offering" table was updated to include CQ84.
i
iii
iii
Table 2-3 • Time at which I/Os Become Active by Ramp Rate was updated. The
2-1
0.25V/ms was changed to 0.25V/μs and 0.025V/ms was changed to 0.025V/µs.
Table 2-7 • Package Thermal Characteristics was updated to include the CQ84.
2-8
Table 2-13 • RTSX32SU 5 V TTL and 3.3 V LVTTL I/O Module through Table 2-17 • 2-17 to
RTSX72SU 5 V CMOS I/O Module, Table 2-20 • RTSX32SU 5 V PCI I/O Module, 2-24,
Table 2-21 • RTSX72SU 5 V PCI I/O Module, Table 2-24 • RTSX32SU 3.3 V PCI I/O 2-28
Module, and Table 2-25 • RTSX72SU 3.3 V PCI I/O Module were updated to include
Note 2.
The headings in Table 2-34 • Boundary Scan Pin Functionality were updated to
Dedicated Test Mode and Flexible Mode.
2-8
v2.0
The "CQ84" section, which includes the package figure and the pin table, is new.
3-1
(continued)
Advance v0.3
Advance v0.2
In Table 2-15 • 5 V CMOS Electrical Specifications, the IOH = –20μA and IOL = ±20 µA.
2-19
2-9
Table 2-8 • Temperature and Voltage Derating Factors was updated.
The following tables were updated:
2-17
through
2-42
Table 2-13 • RTSX32SU 5 V TTL and 3.3 V LVTTL I/O Module
Table 2-14 • RTSX72SU 5 V TTL and 3.3 V LVTTL I/O Module
Table 2-16 • RTSX32SU 5 V CMOS I/O Module,
Table 2-17 • RTSX72SU 5 V CMOS I/O Module
Table 2-20 • RTSX32SU 5 V PCI I/O Module
Table 2-21 • RTSX72SU 5 V PCI I/O Module
Table 2-24 • RTSX32SU 3.3 V PCI I/O Module
Table 2-25 • RTSX72SU 3.3 V PCI I/O Module
Table 2-27 • R-Cell through Table 2-33 • RTSX72SU at VCCI = 4.5 V
Revision 8
4-3
Datasheet Information
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has
been fully characterized from silicon devices. The data provided for a given device, as highlighted in the
"RTSX-SU Device Status" table, is designated as "Product Brief," "Advance," "Production," or "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advance
This datasheet version contains initial estimated information based on simulation, other products,
devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the
general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more
detailed information and for specifications that do not differ between the two families.
Export Administration Regulations (EAR) or International
Traffic in Arms Regulations (ITAR)
The product described in this datasheet could be subject to either the Export Administration Regulations
(EAR) or in some cases the International Traffic in Arms Regulations (ITAR). They could require an
approved export license prior to export from the United States. An export includes release of product or
disclosure of technology to a foreign national inside or outside the United States.
4-4
Revision 8
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