TRU050-TBCGA-25M2480000 概述
Phase Locked Loop, CDIP16, SMD-16
TRU050-TBCGA-25M2480000 数据手册
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Complete VCXO based Phase-Locked Loop
Features
•
•
•
•
•
•
•
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Output Frequencies to 65.536 MHz
5.0 V or 3.3Vdc Operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS Outputs
0/70°or –40/85°C Temperature Range
Ceramic SMD Package
RoHS/Lead Free Compliant Versions
The TRU050, VCXO based PLL
Description
Applications
•
•
•
•
Frequency Translation
The VI TRU050 is a user-configurable crystal-based
PLL integrated circuit. It includes a digital phase
detector, op-amp, VCXO and additional integrated
functions for use in digital synchronization
applications. Loop filter software is available as well
SPICE models for circuit simulation.
Clock Smoothing
NRZ Clock Recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low Jitter PLL’s
•
Figure 1. TRU050 Block Diagram
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
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TRU050, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Output Frequency (ordering option)
Out 1, 5V option
Out 1, 3.3V option
Supply Voltage 1
+5
1.000
1.000
65.636
51.840
MHz
MHz
VDD
4.5
3.0
5.0
3.3
5.5
3.6
65
V
V
mA
+3.3
Supply Current
IDD
Output Logic Levels
Output Logic High2
Output Logic Low2
Output Transition Times
Rise Time2
VOH
VOL
2.5
V
V
0.5
tR
tF
5
5
ns
ns
Fall Time2
Input Logic Levels
Output Logic High2
Output Logic Low2
Loss of Signal Indication
Output Logic High2
Output Logic Low2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle3
Out 1
Out 2
RCLK
Absolute Pull Range, ordering option
VIH
VIL
2.0
2.5
V
V
0.5
0.5
VOH
VOL
V
V
ppm
ppm
75
75
SYM1
SYM2
RCLK
APR
40/60
45/55
40/60
%
%
%
ppm
50
80
over operating temp, aging, power supply
variations
100
0.5
0.3
Test Conditions for APR (+5V option)
Test Conditions for APR (+3.3V option)
Gain Transfer
VC
VC
4.5
3.0
V
V
Positive
Phase Detector Gain
+5V option
+3.3V Option
Operating temperature, ordering option
0.53
0.35
rad/V
rad/V
°C
0/70 or –40/85
Control Voltage Leakage Current IVCXO
1. A good quality 0.01uF in parrallel with a 0.1 uf capacitor should be located as close to pin 16 to ground as possible.
uA
1
2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which these parameters are
tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.
TF
TR
IDD
650Ω
80
%
16
1
1.4V
+
-
VDD
.
1µF
.01µF
3
20
%
IC
VC
On Time
15pF
1.8k
+
-
Period
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RDATA and RCLK
Test Conditions (25 5°C)
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TRU050, VCXO Based PLL
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional
operation is not implied at these or any other conditions in excess of conditions represented in the operational
sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect
device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Symbol
VDD
Ratings
7
-55/125
Unit
Vdc
°C
°C/sec
V
Tstorage
TPEAK / tP
Soldering Temperature/Duration
Clock and Data Input Range
260 / 40
Gnd-0.5 to VDD +0.5
CLKIN, DATAIN
Reliability
The TRU050 is capable of meeting the following qualification tests.
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
MIL-STD-883, Method 1014, 100% Tested
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the the TRU050, proper precautions should be taken
when handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD
susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit
parameters used to define the model.
Table 4. ESD Ratings
Model
Minimum
1500V
1000V
Human Body Model
Charged Device Model
MIL-STD 3015
JESD 22-C101
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TRU050, VCXO Based PLL
Phase Detector
TRU050 Theory of Operation
The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.
DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about a
50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN
and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by
more than a few hundred millivolts.
The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to produce
a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a block
diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does not
have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be centered
in the middle of the DATAIN signal, see figure 6.
The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3
volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ
signals, but 0.25 could be used as a starting point for data density.
The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant
ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications
such as 8kHz frequency translation, see figures 8 and 9.
Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so
under normal locked conditions and input frequencies >1MHz, PHO will be about VDD/2 and will not vary
signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary according
to the input frequency offset, but PHO will remain relatively constant.
Data In
(pin 7)
D
20 kΩ
Q1
Clock In
(pin 9)
30 kΩ
D
PHO
(pin 6)
Q2
Gain = 2 / 3
Gain = 5 V / 2π
Figure 4. Simplified Phase Detector Block Diagram
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TRU050, VCXO Based PLL
Vd
VDD
0
−π
+π
Relative
Phase (θe
VDD/2
)
0V
Gain Slope = VDD/ 2
π
Figure 5. Open Loop Phase Detector Transfer Curve
Recovered Clock and Data Alignment Outputs
The TRU050 is designed to recover an imbedded clock from an NRZ data signal and retime it with a data
pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and the
outputs are taken off Pin 11, RCLK, and Pin 12, RDATA. Under locked conditions, the falling edge of RCLK is
centered in the RDATA pattern. Also, there is a 1.5 clock cyle delay between DATAIN and RDATA. Figure 6
shows the relationship between the DATAIN, CLKIN, RDATA and RCLK.
Data In
Data1
Clock In
Recovered
Data1
Recovered Clock
Figure 6. Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomidated by using a TRU050 at twice the
baud rate.
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is
normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected
DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the TRU050’s
LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 1) is switched to an internal
voltage which centers OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS automatically closes the op
amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage equal to the +op
amp voltage (pin 4), usually VDD/2.
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TRU050, VCXO Based PLL
VCXO and Absolute Pull Range (APR) Specification
The TRU050’s VCXO is a varactor tuned crystal oscillator, which produces an output frequency proportional
to the control voltage (pin 1). The frequency deviation of the TRU050 VCXO is specified in terms of Absolute
Pull Range (APR). APR provides the user with a guaranteed specification for minimum available frequency
deviation over all operating conditions. Operating conditions include operating temperature range, power
supply variation, and differences in output loading and changes due to aging.
A TRU050 VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all operating
conditions. The fourth character of the product code in Table 6 specifies absolute Pull Range (APR). Please
see Vectron’s web site, www.vectron.com, for the APR Application Note.
APR is tested at 0.5 and 4.5 volts for a 5 volt option and 0.3 and 3.0 volts for the 3.3 volt option.
VCXO Aging
Quartz stabilized oscillators typically exhibit a small shift in output frequency during aging. The major factors,
which lead to this shift, are changes in the mechanical stress on the crystal and mass-loading of foreign
material on the crystal.
As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the
package to the crystal mounting arrangement can lead to frequency variations. VI has minimized these two
effects through the use of a miniature AT-Cut strip resonator crystal, which allows a superior mounting
arrangement, and results in minimal relaxation and almost negligible environmental stress transfer.
VI has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing outgassing by
limiting the number of internal components through the use of ASIC technology. Mass-loading on the crystal
generally results in a frequency decrease and is typically due to outgassing of material within a hermetic
package or from contamination by external material in a less than hermetic package.
Under normal operating conditions with an operating temperature of 40°C, the TRU050 will typically exhibit 2
ppm aging in the first year of operation. The device will then typically exhibit 1 ppm aging the following year
with a logarithmic decline each year thereafter.
Divide-By Feature
The lowest available VCXO OUT 1 frequency is 12.000MHz. To achieve lower frequencies, such as 1.544 or
2.048 MHz, OUT1 is divided by a 2n counter , where n=1 to 8 and is the OUT2 frequency. This results in a
divide by 2,4,8…256 option and is wire-bonded at the factory, so it is user selectable upon ordering only. To
achieve 1.544 or 2.048MHz, a TRU050 at 24.704 with a divide by 16 or a TRU050 16.384 with a divide-by 8
would be used. Additional external divide-by circuits can be used to further lower or change the input
frequency range.
A disabled Out2 is available.
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TRU050, VCXO Based PLL
Loop Filter
A PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input
frequency. While there will be some phase error, theory states there is no frequency error. The loop filter
design will dictate many key parameters such as jitter reduction, stability, lock range and acquisition time. Be
advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are
based on ideal systems. Such equations may not be accurate for real systems due to nonlinearities, DC
offsets, noise and don’t take into account the limited VCXO bandwidth. This section deals with some real
world design examples. Also, there is loop filter software on the Vectron web site, plus experienced
applications engineers are eager to assist in this process. Common TRU050 PLL applications are shown in
figures 7 and 8 (frequency translation), 9 (clock recovery) and 10 (clock smoothing).
Of primary concern to the designer is selecting a loop filter that insures lock-in, stability and provides adequete
filtering of the input signal. A good starting point for the the loop filter bandwidth is 100ppm times the DATAIN
frequency. An example would be translating an 8kHz signal to 44. 736MHz – DS3 – which is = 100 ppm x kHz
= 8Hz . So for 8kHz inputs, ~ 8 Hz loop bandwidth may be reasonable and figures 7 and 8 show and 8kHz to
DS3 and 8kHz to 19.440 MHz frequency translation designs.
It’s fairly easy to set a low loop bandwidth for large frequency translations such as 8kHz to 44.736MHz, but
becomes more difficult for clock smoothing applications such as 19.440MHz in and 19.440MHz output. In this
example, 100ppm x 19.440MHz is about 2kHz and may be too high to reject kow frequency jitter. A good way
to resolve this is to lower the input frequency such as dividing the input frequency down. The loop filter
bandwidth becomes lower since 100ppm * DATAIN is lowered. Figure 10 shows an example of how to design
a low loop bandwith on a relatively high input signal and still maintain a wide lock range. The “100ppm *
DATAIN frequency” loop filter bandwidth can then be tailored to the application, since lower bandwidthds are
desriable to clean up and or translate clock signals and higher bandwidths may be needed for clock recovery
of NRZ signals.
There is no known accurate formula for calculating acquisition time and so the best way to provide realisitc
figures is to measure the lock time for a TRU050. Aquistion time was measured to be 3 to 5 seconds by
measuring the control voltage in an 8kHz to 34.368 MHz frequency translation application - similar to the
application in figure 7 and 8, to sub 10 milliseconds for NRZ data patterns such as figure 9. It may be tempting
reduce the damping factor to 0.7 or 1.0 in order to increase aquisition time; but, it degrades stability and will
not signifigantly decrease lock time. This is due to the fact that most VCXO’s have a 10kHz bandwidth so
setting a 100kHz loop bandwidth is impossible. A damping factor of 4 is fairly conservative and allows for
excellent stability.
Some general quidelines for selecting loop filter include: Values should be less than 1Megohm and at least
10Kohm between the PHO and OPN, the capacitor should be low leakage and a polarized capacitor is
acceptable, the R/C’s should be located physically close to the TRU050 . Also, the loop filter software
available on the web site was written for 5 volt operation, a simple way to calculate values for 3.3 volt
operation is to times the data density by 0.66 (3.3V / 5V).
SPICE models are another design aid. In most cases a new PLL TRU050 design is calculated by using the
software and verified with SPICE models, and depending on the circumstances evaluated in the applications
lab. The simple active pi model is in figure 7. Loop filter values can be modified to suit the system
requirements and application. There are many excellent references on designing PLL’s, such as “Phase-
Locked Loops, Theory, Design and Applications”, by Roland E Best McGraw-Hill; however, there is loop filter
software on the Vectron web site, plus experienced applications engineers eager to assist in this process.
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
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TRU050, VCXO Based PLL
Figure 7. SPICE Model
Vi Ri
1
E1 R2 C1
3
E2 R1 C2
Rf
Cf E3 R5 C4
E4 R6 C5 E5
10 11
E6
2
4
5
6
7
8
9
*****TRU050 ac Loop model
vi 1 0 ac 1
ri 1 0 1K
*****Phase Detector
e1 2 0 1 0 1 (for closed loop response use: e1 2 0 1 12 1)
r2 2 3 30K
c1 2 0 60p
*****Phase Detector Gain=0.53 x Data Density (Data Density=1 for clocks) for 5 volt
operation and = 0.35 * Data Density for 3.3 volt operation
e2 4 0 3 0 .35
*****Loop filter
r1 4 5 60K
c2 5 0 10p
rf 5 6 90K
cf 6 7 1.0u
e3 7 0 5 0 –10000
***** VCXO, Input Bandwidth=50kHz
r5 7 8 160K
c4 8 0 20p
*****VCXO Gain x 2pi (Example, use OUT1 x 100ppm x 2 x pi)
e4 9 0 8 0 12214
*****1/S model
r6 9 10 1000
c5 10 11 0.001
e5 11 0 10 0 –1e6
****Divide by N
e6 12 0 11 0 1
r8 12 0 1K
The bold numbers are user selectable R/C, data density, VCXO frequency and divide-
by values, and are from figure 11.
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TRU050, VCXO Based PLL
Layout Considerations
To achieve stable, low noise performance good analog layout techniques should be incorporated and a partial
list includes:
The TRU050 should be treated more like an analog device and the power supply should be well decoupled
with good quality RF 0.01 uf and 0.1uf capacitors. In some cases, a pi filter such as a large capacitor (10uF)
to ground, a series ferrite bead or inductor, and 0.01 uf and 100 pf capacitor to ground to decouple the
device supply is used.
The traces for the OUT1, OUT2, RCLK and RDATA ouputs should be kept as short as possible. It is common
practice to use a series resistor – 50 to 100 ohms – in order to reduce reflections if these traces are more than
a couple of inches long. Also OUT1, OUT2 RCLK and RDATA should not be routed directly underneath the
device.
The op-amp loop filter components should be kept as close to the device as possible and the feedback
capacitor should be located close the op-amp input terminal. The loop filter capacitor(s) should be low leakage
and polarized capacitors are allowed keeping this is mind.
Unused outputs should be left floating and it is not required to load or terminate them (such as an PECL or
ECL output). Loading unused outputs will only increase current consumption.
Typical Application Circuits
10K 0.1uF 10K 2.2uF 330K 20K 0.1uF
pin 6
pin 2
pin 3
pin 1
pin 15
8 kHz (Pin 7)
44.736 MHz
∅
TRU050
pin 4
10K
16kHz (Pin 9)
10K , 2.2uF
The above loop has a 11 Hz bandwidth.
Figure 8. 8kHz to DS3 Frequency Translation
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TRU050, VCXO Based PLL
20K 0.1uF 20K 2.2uF 600K 20K 0.1uF
pin 6
pin 2
pin 3
pin 1
pin 15
8 kHz (Pin 7)
19.440MHz
∅
TRU050
pin 4
10K
16kHz (Pin 9)
10K , 2.2uF
÷ 1215
The above loop has a 10 Hz bandwidth.
Figure 9. 8kHz to 19.44MHz Frequency Translation
10K
0.01uF 130K
pin 6
pin 2
pin 3
pin 1
44.736 Mb/s (Pin 7)
Pin 15
44.736 MHz
∅
Disabled
TRU050
pin 4
10K
(Pin 9)
10K, 2.2uF
The above loop has a 4.5 kHz bandwidth.
Figure 10. DS3 NRZ Clock Recovery
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TRU050, VCXO Based PLL
60K
1.0uF 90K 10K
19.440MHz
pin 6
pin 2
pin 3
pin 1
Pin 15
Pin 13
19.440 MHz
÷16
∅
2.430 MHz
TRU050
Pin 9
pin 4
10K, 2.2uF , 10K
The above loop has a 125 Hz bandwidth.
Figure 11. 19.440 Clock Smoothing
Table 5. Reflow Profile (IPC/JEDEC J-STD-020C)
Symbol
Parameter
PreHeat Time
Value
60 sec Min, 180 sec Max
t S
3 oC/sec Max
60 sec Min, 150 sec Max
480 sec Max
Ramp Up
R UP
t L
Time Above 217 oC
Time To Peak Temperature
Time At 260 oC
t AMB-P
t P
20 sec Min, 40 sec Max
6 oC/sec Max
Ramp Down
R DN
t L
t P
The device has been qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-Free
small body requirements. The temperatures refer to
the topside of the package, measured on the
package body surface. The TRU050 device is
hermetically sealed so an aqueous wash is not an
issue.
260
R UP
217
200
R DN
150
t S
t AMB-P
25
Time (sec)
Figure 12. Suggested IR profile
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TRU050, VCXO Based PLL
Figure 13. Tape and Reel Diagram
Table 6. Tape and Reel Information
Tape Dimensions (mm)
Reel Dimensions (mm)
Dimension
Tolerance
TRU050
A
B
C
D
E
F
G
H
I
J
K
L
Typ
# Per
Reel
Typ Typ Typ Typ
32 14.2 1.5
Typ
16
Min
Min
Typ
Min Typ Max
4
1.78 21 13.0 100
5
33.1 330
200
Package Outline Diagrams
Figure 14. “Gull Wing Lead” Package
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TRU050, VCXO Based PLL
Figure 15. “Thru Hole Lead” Package
Table 7. Pin Functions
Symbol
Pin
Function
1
VC
OPN
VCXO Control Voltage
Op-Amp Negative Input
Op-Amp Output
2
3
OPOUT
OPP
LOSIN
4
Op-Amp Positive Input
INPUT (Used with LOS)
5
Logic 0, VCXO control voltage is enabled.
Logic 1, VCXO control voltage (pin 1) is disabled and OUT1 and OUT2 are within
+/-75 ppm of center frequency
Has Internal pull-down resistor
Phase detector output
6
7
PHO
DATAIN
GND
Phase detector Input signal (TTL switching thresholds)
Cover and Electrical Ground
8
9
10
CLKIN
LOS
Phase detector Clock signal (TTL switching thresholds)
OUTPUT (Used with LOSIN)
Logic 1 if there are no transitions detected at DATAIN after 256 clock cycles at
CLKIN. As soon as a transition occurs at DATAIN, LOS is set to logic low.
Recovered Clock
11
12
13
14
RCLK
RDATA
Output 2
HIZ
Recovered Data
Divided-down VCXO Output, or No Output
INPUT
Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state.
Logic 1, OUT1, OUT2, RCLK, RDATA are active.
Has Internal pull-up resistor
15
16
Output 1
VDD
VCXO Output
Power Supply Voltage (3.3 V 10% or 5.0 V 10%)
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TRU050, VCXO Based PLL
Ordering information
Table 8. Standard OUT1 Frequencies
12.0000000
18.4320000
28.0000000
41.2416000
65.5360000
12.2880000
19.4400000
30.7200000
41.9430000
12.6240000
20.0000000
32.0000000
44.7360000
13.8240000
20.4800000
32.7680000
47.4570000
16.0000000
22.1184000
33.3300000
49.1520000
16.1280000
22.5790000
34.3680000
49.4080000
16.3840000
24.5760000
35.3280000
50.0000000
16.7770000
25.0000000
38.8800000
51.8400000
16.8960000
25.2480000
40.0000000
61.4400000
17.9200000
27.0000000
40.9600000
62.2080000
* Other frequencies may be available upon request
Table 9. Part Number Builder
TRU050 - G A L G A - xxMxxxxxxx
Frequency (See Above)
Lead Style
1M00000000 - 65M5360000
T: Thru hole*
G: Gull Wing*
S: Solder Dipped Gull Wing**
Power Supply
A = 5.0 V
B = 3.3 V
Divide by
A = 2
B = 4
C = 8
D = 16
E = 32
F = 64
G = 128
H = 256
K = Disabled
Absolute Pull Range
C: ± 20 ppm
F: ± 32 ppm
G: ± 50 ppm (Standard)
N: ± 80 ppm
H: ± 100 ppm
Temperature Range
C 0 to 70°C
L: -40 to 85°C
* Parts are RoHS6/6 without exemption.
* * Leads are hot solder-dipped with 63/37 SnPb eutectic solder. Parts are RoHS 5/6 and compliant with exemption 7(b).
Contact Information:
USA: Vectron International • 267 Lowell Rd. Hudson, Unit 102, NH 03051
Tel: 1-88-VECTRON-1 • Fax: 1-888-FAX-VECTRON
EUROPE: Landstrasse, D-74924, Neckarbischofsheim, Germany
Tel: 49 (0) 7268 8010 • Fax: 49 (0) 7268 801281
ASIA: Vectron International • 68 Yin Cheng Road(C), 22nd Floor, One LuJiaZui
Pudong, Shanghai 200120, China
Tel: 86 21 6194 6886 • Fax: 86 21 6194 6699
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is
assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 14 of 14
Tel: 1-88-VECTRON-1 • Web: www.vectron.com
Rev: 4/12/2016
TRU050-TBCGA-25M2480000 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
TRU050-TBCGA-30M7200000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-32M7680000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-35M3280000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-38M8800000 | MICROSEMI | Phase Locked Loop, CDIP16 | 获取价格 | |
TRU050-TBCGA-40M0000000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-49M4080000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-50M0000000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-51M8400000 | MICROSEMI | Phase Locked Loop, CDIP16, SMD-16 | 获取价格 | |
TRU050-TBCGA-61M4400000 | MICROSEMI | Phase Locked Loop, CDIP16 | 获取价格 | |
TRU050-TBCGA-65M0000000 | VECTRON | Complete VCXO based Phase-Locked Loop | 获取价格 |
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