VCC6-QAF-77M7600

更新时间:2024-10-29 23:38:38
品牌:MICROSEMI
描述:LVPECL Output Clock Oscillator, 77.76MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6

VCC6-QAF-77M7600 概述

LVPECL Output Clock Oscillator, 77.76MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6

VCC6-QAF-77M7600 数据手册

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VCC6  
LVPECL, LVDS Crystal Oscillator Data Sheet  
VCC6  
Description  
Vectron’s VCC6 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off either 2.5 or 3.3 volt supply,  
hermetically sealed 5x7 ceramic package.  
Features  
Applications  
• Ultra Low Jitter Performance, Fundamental or 3rd OT Crystal Design  
• Output Frequencies to 350.000MHz  
• 0.3 ps typical RMS jitter, 12k-20MHz  
• Differential Output  
• Enable/Disable  
• -10/70°C or -40/85°C Operation  
• Ethernet, GbE, Synchronous Ethernet  
• Fiber Channel  
• Enterprise Servers  
• Telecom  
• Clock source for A/D’s, D/A’s  
• Driving FPGA’s  
• Test and Measurement  
• PON  
• Hermetically Sealed 5x7 Ceramic Package  
• Product is compliant to RoHS directive  
and fully compatible with lead free assembly  
• Medical  
• COTS  
Block Diagram  
Complementary  
Output  
Output  
VDD  
Crystal  
Oscillator  
E/D or NC  
E/D or NC  
Gnd  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page1  
Performance Specifications  
Table 1. Electrical Performance, LVPECL Option  
Parameter  
Symbol  
Min  
Typical  
Maximum  
Units  
Supply  
Voltage1  
VDD  
IDD  
3.135  
2.375  
3.3  
2.5  
3.465  
2.625  
V
V
Current (No Load)  
50  
98  
mA  
Frequency  
Nominal Frequency2  
Stability2,3 (Ordering Options)  
fN  
10  
350.000  
MHz  
ppm  
20, 25, 50, 100  
Outputs  
Output Logic Levels4, -10/70°C  
Output Logic High  
Output Logic Low  
VOH  
VOL  
VDD-1.025  
VDD-0.880  
VDD-1.620  
V
V
V
DD-1.810  
Output Logic Levels4, -40/85°C  
Output Logic High  
Output Logic Low  
VOH  
VOL  
VDD-1.085  
VDD-1.830  
VDD-0.880  
VDD-1.555  
V
V
Output Rise and Fall Time4  
tR/tF  
600  
ps  
Load  
50 ohms into VDD-1.3V  
Duty Cycle5  
45  
50  
55  
%
Jitter (12 kHz - 20 MHz BW)155.52MHz6  
Period Jitter7  
RMS  
фJ  
фJ  
0.3  
0.7  
ps  
2.3  
20  
2.4  
0
ps  
ps  
ps  
ps  
P/P  
Random Jitter  
Deterministic Jitter  
Enable/Disable  
Output Enabled8  
Output Disabled  
VIH  
VIL  
0.7*VDD  
V
V
0.3*VDD  
200  
Enable/Disable Time  
tD  
ns  
Enable/Disable Leakage Current  
200  
uA  
Enable Pull-Up Resistor  
Output Enabled  
Output Disabled  
33  
1
KOhm  
MOhm  
Start-Up Time  
tSU  
10  
ms  
°C  
Operating Temp. (Ordering Option)  
Package Size  
TOP  
-10/70 or -40/85  
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2  
mm  
1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.  
2. See Standard Frequencies and Ordering Information for more information.  
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.  
4. Figure 1 defines the test circuit and Figure 2 defines these parameters.  
5. Duty Cycle is defined as the On/Time Period.  
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series.  
7. Measured using a Wavecrest SIA3300C, 90K samples.  
8. Outputs will be Enabled if Enable/Disable is left open.  
tR  
tF  
VDD -1.3V  
VOH  
1
2
3
6
5
4
50%  
VOL  
NC  
NC  
On Time  
50 ȍ  
Figure 1.  
50 ȍ  
-1.3V  
Period  
Figure 2.  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page2  
Performance Specifications  
Table 2. Electrical Performance, LVDS Option  
Parameter  
Symbol  
Min  
Typical  
Maximum  
Units  
Supply  
Voltage1  
VDD  
IDD  
3.135  
2.375  
3.3  
2.5  
3.465  
2.625  
V
V
Current (No Load)  
60  
mA  
Frequency  
Nominal Frequency2  
Stability2,3, (Ordering Options)  
fN  
10  
350.000  
MHz  
ppm  
20, 25, 50, 100  
Outputs  
Output Logic Levels4  
Output Logic High  
Output Logic Low  
VOH  
VOL  
1.43  
1.10  
1.6  
V
V
0.9  
Differential Output  
Differential Output Error  
Offset Voltage  
247  
330  
454  
50  
mV  
mV  
V
1.125  
1.25  
1.375  
50  
Offset Voltage Error  
Output Leakage Current  
Output Rise and Fall Time4  
Load  
mV  
uA  
ps  
10  
tR/tF  
600  
100 ohms differential  
Duty Cycle5  
45  
50  
55  
%
Jitter (12 kHz - 20 MHz BW)155.52MHz6  
Period Jitter7  
RMS  
фJ  
фJ  
0.3  
0.7  
ps  
2.5  
22  
2.6  
0
ps  
ps  
ps  
ps  
P/P  
Random Jitter  
Deterministic Jitter  
Enable/Disable  
Output Enabled8  
Output Disabled  
VIH  
VIL  
0.7*VDD  
V
V
0.3*VDD  
200  
Enable/Disable Time  
tD  
ns  
Enable/Disable Leakage Current  
200  
uA  
Enable Pull-Up Resistor  
Output Enabled  
Output Disabled  
33  
1
KOhm  
MOhm  
Start-Up Time  
tSU  
10  
ms  
°C  
Operating Temp. (Ordering Option)  
Package Size  
TOP  
-10/70 or -40/85  
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2  
mm  
1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.  
2. See Standard Frequencies and Ordering Information for more information.  
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.  
4. Figure 2 defines these parameters and Figure 3 defines the test circuit.  
5. Duty Cycle is defined as the On/Time Period.  
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series.  
7. Measured using a LeCroy 8600, 25K samples.  
Out  
Out  
8. Outputs will be Enabled if Enable/Disable is left open.  
50  
50  
6
1
5
2
4
0.01 uF  
3
DC  
Figure 3.  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page3  
Package and Pinout  
Table 3. Pinout  
Pin #  
Symbol  
Function  
1
2
3
4
5
6
E/D or NC  
E/D or NC  
GND  
Enable Disable or No Connection  
Enable Disable or No Connection  
Electrical and Lid Ground  
Output Frequency  
The Enable/Disable function is set at the factory on either pin 1  
or pin 2 and is an ordering option  
fO  
CfO  
Complementary Output Frequency  
Supply Voltage  
VDD  
7.0 0.15  
7.49 0.15  
6
5
4
6
5
4
Part Number  
Frequency  
Date Code  
Part Number  
Frequency  
Date Code  
5.0 0.15  
5.08 0.15  
1
2
3
1
2
3
1.6 max  
2.16 max  
1.397  
1.27  
1.397  
1.27  
1
6
2
3
4
1
6
2
3
4
Bottom View  
5
3.57  
Bottom View  
5
3.57  
Dimensions are in mm  
2.54  
2.54  
5.08  
5.08  
Figure 4. Package A Outline Drawing  
Figure 5. Optional Package Outline Drawing  
The VCC6 can be supplied in one of two package options and  
Figure 4 shows the primary package used. The pad layout and  
dimesnions are identical and a reel would include only 1 of the  
two options  
1.96  
1.78  
3.66  
2.54  
5.08  
Figure 6. Pad Layout  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page4  
LVPECL Application Diagrams  
Figure 7. Standard PECL Output Configuration Figure 8. Single Resistor Termination Scheme  
Figure 9. Pull-Up Pull Down Termination  
Resistor values are typically 120 to 240 ohms  
for 3.3V operation.  
Resistor values are typically 82 to 120 ohms  
for 2.5V operation.  
Resistor values are typically for 3.3V operation  
For 2.5V operation, the resistor to ground is 62  
ohms and the resistor to supply is 240 ohms  
The VCC6 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes on  
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme as  
shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.  
LVDS Application Diagrams  
VCC  
LVDS  
Driver  
LVDS  
Receiver  
LVDS  
Driver  
Receiver  
100ȍ  
100ȍ  
OUT+  
OUT-  
Figure 11. LVDS to LVDS Connection, Internal 100ohm  
Some LVDS structures have an internal 100 ohm resistor on the  
input and do not need additional components.  
Figure 12. LVDS to LVDS Connection  
External 100ohm and AC blocking caps  
Some input structures may not have an internal 100 ohm  
resistor on the input and will need an external 100ohm  
resistor for impedance matching. Also, the input may have  
an internal DC bias which may not be compatible with  
LVDS levels, AC blocking capacitors can be used.  
Figure 10 Standard LVDS  
Output Configuration  
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-  
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching  
into account. Load matching and power supply noise are the main contributors to jitter related problems.  
Environmental and IR Compliance  
Table 4. Environmental Compliance  
Parameter  
Mechanical Shock  
Mechanical Vibration  
Temperature Cycle  
Solderability  
Condition  
MIL-STD-883 Method 2002  
MIL-STD-883 Method 2007  
MIL-STD-883 Method 1010  
MIL-STD-883 Method 2003  
MIL-STD-883 Method 1014  
MIL-STD-883 Method 2015  
MSL1  
Fine and Groossss LLeeaakk  
Resistance to Solvents  
Moisture Sensitivity Level  
Contact Pads  
Gold over Nickel  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page5  
IR Compliance  
Suggested IR Profile  
tL  
tP  
Devices are built using lead free epoxy and can be subjected to  
standard lead free IR reflow conditions shown in Table 5. Contact  
pads are gold over nickel and lower maximum temperatures can also  
be used, such as 220C.  
260  
RUP  
217  
200  
RDN  
Table 5. Reflow Profile  
Parameter  
PreHeat Time  
Symbol  
ts  
Value  
150  
25  
200 sec Max  
3°C/sec Max  
150 sec Max  
480 sec Max  
10 sec Max  
60 sec Max  
6°C/sec Max  
tS  
tAMB-P  
Ramp Up  
RUP  
Time above 217°C  
Time to Peak Temperature  
Time att 226600°°CC  
tL  
tAMB-P  
tP  
ility  
Time at 240°C  
tP2  
Ramp dowwnn  
RDN  
Time (sec)  
Maximum Ratings, Tape & Reel  
Absolute Maximum Ratings and Handling Precautions  
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other  
excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended  
periods may adversely affect device reliability.  
Although ESD protection circuitry has been designed into the VCC6, proper precautions should be taken when handling and mounting,  
VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.  
ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for  
the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.  
Table 6. Maximum Ratings  
Parameter  
Symbol  
TSTORE  
Rating  
-55/125  
Unit  
°C  
Storage Temperature  
Supply Voltage  
-0.5 to 5.0  
-0.5 to VDD+0.5  
1500  
V
Enable Disable Voltage  
ESD, Human Body Model  
ESD, Charged Device Model  
V
V
1000  
Table 7. Tape and Reel Information  
Tape Dimensions (mm)  
Reel Dimensions (mm)  
W
F
Do  
1.5  
Po  
4
P1  
8
A
B
2
C
D
N
W1  
17  
W2  
21  
#/Reel  
250  
16  
7.5  
180  
13  
21  
55  
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com  
Page6  
Table 8. Standard Frequencies (MHz)  
19.4400  
43.7500  
71.5000  
84.0000  
114.2850  
136.0000  
156.2500  
166.0000  
173.4380  
195.3125  
25.0000  
27.1200  
53.1250  
74.2500  
90.0000  
124.4160  
142.5408  
156.2740  
166.6286  
176.0950  
210.000  
33.0000  
56.0000  
33.3330  
61.4400  
35.0000  
62.2080  
35.5000  
62.5000  
38.8800  
66.0000  
40.0000  
68.0000  
40.6800  
70.0000  
50.0000  
74.1758  
75.0000  
75.4000  
77.7600  
78.1250  
80.0000  
81.2500  
83.3330  
86.0000  
95.0000  
100.0000  
125.0093  
148.7500  
159.3750  
167.3317  
177.3437  
212.5000  
105.0000  
128.0000  
150.0000  
160.0000  
167.4100  
180.0000  
225.0000  
106.2500  
130.0000  
153.6000  
161.1328  
168.2009  
187.0177  
250.0000  
110.0000  
130.5882  
153.8500  
162.3250  
168.6997  
187.5000  
260.000  
112.0000  
133.0000  
155.5200  
164.3555  
172.6423  
190.0000  
312.500  
112.5000  
135.0000  
156.1734  
165.0000  
173.3708  
192.4560  
120.0000  
140.0000  
156.2539  
166.5600  
175.0000  
200.0000  
125.0000  
143.0000  
156.2930  
166.6667  
176.8382  
212.4840  
Ordering Information  
VCC6 - X X X - XXMXXXXXX  
Frequency in MHz  
Product  
XO, 5x7 Package  
Stability/Temp Range  
Output and Voltage  
Q: +3.3 Vdc 5%, LVPECL  
R: +3.3 Vdc 5%, LVPECL  
L: +3.3 Vdc 5%, LVDS  
V: +2.5 Vdc 5%, LVDS  
A: 100 ppm over -10/70°C  
B: 50 ppm over -10/70°C  
C: 100 ppm over -40/85°C  
D: 50 ppm over -40/85°C  
E: 25ppm over -10/70°C  
F: 25ppm over -40/85°C  
Enable/Disable  
A: E/D is on Pin 2  
C: E/D is on Pin 1  
G: 20ppm over -10/70°C, excludes aging  
*Note: not all combination of options are available.  
Other specifications may be available upon request.  
20ppm Options  
VCC6-107-frequency  
LVPECL +3.3V,  
20ppm over -10/70°C  
20ppm over -10/70°C  
20ppm over -10/70°C  
20ppm over -10/70°C  
VCC6-109-frequency  
VCC6-110-frequency  
VCC6-111-frequency  
LVDS  
LVPECL +2.5V  
LVDS +2.5V  
+3.3V  
For Additional Information, Please Contact  
USA:  
Europe:  
Asia:  
Vectron International  
267 Lowell Road  
Hudson, NH 03051  
Tel: 1.888.328.7661  
Vectron International  
Vectron International  
Landstrasse, D-74924  
Neckarbischofsheim, Germany  
Tel: +49 (0) 3328.4784.17  
1F-2F, No 8 Workshop, No 308 Fenju Road  
WaiGaoQiao Free Trade Zone  
Pudong, Shanghai, China 200131  
Tel: 86.21.5048.0777  
Fax: 1.888.329.8328  
Fax: +49 (0) 3328.4784.30  
Fax: 86.21.5048.1881  
Disclaimer  
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application.  
No rights under any patent accompany the sale of any such product(s) or information.  
Rev: 01/29/2010  

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