VSC8221HH [MICROSEMI]
Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs;
| 型号： | VSC8221HH |
| 厂家： | 
Microsemi |
| 描述： | Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs 局域网（LAN）标准 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总138页 (文件大小：1143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VSC8221
Data Sheet
Single Port 10/100/1000BASE-T PHY with1.25 Gbps SerDes for SFPs/GBICs
1 GENERAL DESCRIPTION
Ideally suited for Ethernet Switches with SGMii/SerDes MAC
interfaces, Media Converter applications, and SFP/GBiC
modules, the industry-leading, low-power VSC8221 from
Microsemi integrates a high-performance 1.25Gbps SerDes
or to 100BASE-FX (over its copper media interface). in SGMii
mode, the VSC8221 provides a fully compliant, 4-pin or 6-pin
interface to MACs. The 1000BASE-X SerDes and SGMii
interfaces offer either automatic or user-controlled auto-
negotiation priority resolution between the 1000BASE-X and
1000BASE-T auto-negotiation processes. A single chip
copper-to-optics Media Converter can be easily implemented
by simultaneous use of the SerDes and Cat-5 media
interfaces.
and
a triple speed (10/100/1000BASE-T) transceiver,
providing unmatched tolerance to noise and cable plant
imperfections.
Consuming approximately 700mW and eliminating the need
for external power supply regulators, the device requires only
a single 3.3V power supply. To further minimize system
complexity and cost, the VSC8221's twisted pair interface
features fully integrated line terminations, exceptionally low
EMi, and robust Cable Sourced ESD (CESD) performance.
To minimize power consumption, the VSC8221 offers several
programmable power management modes. The device also
supports the comprehensive VeriPHY® Cable Diagnostics
feature from Microsemi, offering the system manufacturer
and iT administrator a complete suite of cable plant
diagnostics to simplify the manufacture, installation, and
management of Gigabit-over-copper networks.
The VSC8221 offers direct connectivity to SGMii or SerDes
interfaces. in 1000BASE-X SerDes mode, the VSC8221 may
be used to connect a MAC to copper media (MAC to Cat-5)
2 FEATURES AND BENEFITS
Features
Benefits
•
Very low power consumption
•
•
Reduces power supply costs
Fully compliant with SFP MSA’s power dissipation
specification of less than 1W maximum per module
•
•
Single 3.3V power supply with on-chip regulator
SGMii & SerDes interfaces
•
Eliminates external regulators, reducing system costs
•
•
Connects to serial MACs or optical modules
Supports triple-speed copper SFP/GBiC modules
•
Patented line driver with integrated line side termination
resistors
•
•
•
May allow use of SimpliPHY’d Magnetics with up to 50%
cost savings versus competition
Saves over 12 external components per port and
reduces PCB area and cost by 50%
Can enable a superior, FCC Class B capable EMi
solution for copper SFPs
•
Over 150m of Cat-5 reach with the industry’s highest
noise tolerance
•
Ensures trouble-free deployment in real world Ethernet
networks
•
•
Several flexible power management modes
•
•
Reduces power consumption and system cost
Small footprint 9mm x 9mm, 100-TFBGA package
Suitable for Gigabit switch ports, SFPs/GBiCs, and
media converters
3 APPLICATIONS
Triple-speed SFP/GBiC modules
•
•
Media converters
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Microsemi Corporation One Enterprise, Aliso Viejo, CA 92656 USA
sales.support@microsemi.com www.microsemi.com
VSC8221
Data Sheet
4 APPLICATIONS DIAGRAMS
4.1 SFP/GBiC Serial interface (SGMii or 802.3z SerDes) to Cat-5
3.3 V
Quad
Transformer
Module
SGMII
or
802.3z SerDes
Cat-5 UTP
10/100/1000BASE-T
SerDes I/F
GBIC/SFP
Interface
RJ-45
VSC8221
Optional I/F for
Configuration
Optional
EEPROM
4.2 Media Converter (1000BASE-X to Cat-5)
3.3 V
Quad
Transformer
Module
CAT-5 UTP
1000BASE-T
1000BASE-LX
1000BASE-SX
Optical Module
Single Mode Fiber
Multimode Fiber
SerDes I/F
RJ-45
VSC8221
Optional I/F for
Configuration
Optional EEPROM
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Data Sheet
5 DEVICE BLOCK DIAGRAM
The diagram below depicts the primary functional blocks and pins for the VSC8221 iC.
TDP
TXVPA
TXVNA
TBI
TDN
802.3z
SerDes
OR
SGMII
PCS
PMA (DSP Data Pump)
TX FIR
MDI (Analog Front End)
RDP
RDN
PCS
ENCODER
HYBRID
SCLKP
SCLKN
DAC
TXVPB
TXVNB
PAM-5 SYMBOL
MAPPER,
SCRAMBLER
TBI
NC1
NC3
NC2
EC
TXVPC
TXVNC
CMODE[3:0]
RESET
Control
TXDIS/SRESET
PCS
DECODER
TRELLIS
DECODER
FFE
ADC
VGA
TXVPD
TXVND
+
X4
PAM-5 SYMBOL
DE-MAPPER,
DESCRAMBLER
TIMING RECOVERY
CLKOUTMICRO
PLL,
OSCILLATOR
MODDEF0/CLKOUTMAC
XTAL2
XTAL1REFCLK
TDI
TDO
TMS
TCK
TEST
MANAGER
+ JTAG
AUTO-NEGOTIATION
REFFILT
BIASING,
SWITCHING
REGULATOR
TRST
REFREXT
REGEN
REGOUT
EEPROM and SERIAL
MANAGEMENT
INTERFACE
MII
MODDEF1/MDC
MODDEF2/MDIO
REGISTERS
RXLOS/SIGDET
LED0
LED1
LED2
LED
INTERFACE
PLLMODE/EECLK
EEDAT
Figure 1. VSC8221 Block Diagram
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6 RELEVANT SPECIFICATIONS & DOCUMENTATION
The VSC8221 conforms to the following specifications. Please refer to these documents for additional information.
Table 1. Specifications and Documentation
Specification - Revision
Description
Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and
Physical Layer Specifications. iEEE 802.3-2002 consolidates and supersedes the following
specifications:
iEEE 802.3-2002
802.3ab (1000BASE-T), 802.3z (1000BASE-X), 802.3u (Fast Ethernet), with references to
ANSi X3T12 TP-PMD standard (ANSi X3.263 TP-PMD)
Test Access Port and Boundary Scan Architecture1.
includes iEEE Standard 1149.1a-1993 and iEEE Standard 1149.1b-1994
iEEE 1149.1-1990
JEDEC EiA/JESD8-5
JEDEC JESD22-A114-B
JEDEC JESD22-A115-A
2.5V±0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and
interface Standard for Nonterminated Digital integrated Circuits
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
Revision of JESD22-A114-A
Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)
Revision of EiA/JESD22-A115
JEDEC EiA/JESD78
MiL-STD-883E
Cisco SGMii v1.7
PiCMG 2.16
iC Latch-Up Test Standard
Miltary Test Method Standard for Microcircuits
Cisco SGMii specification
iP Backplane for CompactPCi
Advanced TCA™ Base
PiCMG 3.0
iP Backplane specification for CompactPCi v3.0
Cisco Systems inLine Power Detection:
http://www.cisco.com/en/US/products/hw/phones/ps379/prod-
ucts_tech_note09186a00801189b5.shtml
Cisco inLine Power Detection
Algorithm
Small Form-factor Pluggable
(SFP) Transceiver MultiSource
Agreement
Specification for pluggable fiber optic transceivers. Describes module data access protocol
and interface
1
Often referred to as the “JTAG” test standard.
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Data Sheet
7 DATA SHEET CONVENTIONS
Conventions used throughout this data sheet are specified in the following table.
Table 2. Data Sheet Conventions
Convention
Syntax
Examples
Description
RegisterNumber.Bit
or
RegisterNumber.BitRange
Register
number
23.10
23.12:10
Register 23 (address 17h), bit 10
Register 23 (address 17h), bits 12, 11, and 10
Extended
Page Regis-
ter Number1
RegisterNumberE.Bit
or
RegiesterNumberE.BitRange
23E.10
23E.12:10
Extended Register 23 (address 17h), bit 10
Extended Register 23 (address 17h), bits 12, 11, and 10
Signal name
(active high)
SiGNALNAME2
SiGNALNAME2
PLLMODE
RESET
Signal name for PLLMODE
Signal name
(active low)
Active low reset signal
Signal bus
name
BUSNAME[MSB:LSB]2
RXD[4:2]
Receive Data bus, bits 4, 3, and 2
1
2
For more information about Mii Extended Page Registers, refer to Section 22: "PHY Register Set Conventions" on page 63.
All signal names are in all CAPiTAL LETTERS.
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Data Sheet
Contents
1
2
3
4
General Description .........................................................................................................................................................1
Features and Benefits .....................................................................................................................................................1
Applications .....................................................................................................................................................................1
Applications Diagrams ....................................................................................................................................................2
4.1 SFP/GBiC Serial interface (SGMii or 802.3z SerDes) to Cat-5 ............................................................ 2
4.2 Media Converter (1000BASE-X to Cat-5) ............................................................................................. 2
5
6
7
8
Device Block Diagram .....................................................................................................................................................3
Relevant Specifications & Documentation ..................................................................................................................4
Data Sheet Conventions .................................................................................................................................................5
Package Pin Assignments & Signal Descriptions .................................................................................................. 14
8.1 Package Ball Diagram ........................................................................................................................ 14
8.2 Ball Locations and Signal Names ....................................................................................................... 15
8.3 Signal Type Descriptions .................................................................................................................... 15
8.4 Detailed Pin Descriptions ................................................................................................................... 16
9
System Schematics ...................................................................................................................................................... 27
9.1 System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY Operating Mode . 27
9.2 System Schematic - 100Mbps Fiber Media implementation .............................................................. 28
10
Twisted Pair interface ................................................................................................................................................... 29
10.1 Twisted Pair Auto-Negotiation (iEEE802.3 Clause 28) ...................................................................... 29
10.2 Twisted Pair Auto MDi/MDi-X Function .............................................................................................. 29
10.3 Auto MDi/MDi-X in Forced 10/100 Link Speeds ................................................................................. 30
10.4 Forcing the PHY into MDi or MDi-X mode in 10/100/1000 Link Speeds ............................................ 31
10.5 Twisted Pair Link Speed Downshift .................................................................................................... 31
10.6 100Mbps Fiber Support Over Copper Media interface ....................................................................... 31
10.6.1
Register Settings ...................................................................................................................................31
11
12
Transformerless Operation for PiCMG 2.16 and 3.0 iP-based Backplanes ........................................................ 32
Dual Mode Serial Management interface (SMi) ........................................................................................................ 33
12.1 PHY Register Access with SMi in MSA mode .................................................................................... 33
12.1.1
12.1.2
12.1.3
12.1.4
Write Operation - Random Write ..........................................................................................................35
Write Operation - Sequential Write .......................................................................................................36
Read Operation - Random Read .........................................................................................................37
Read Operation - Sequential Read ......................................................................................................38
12.2 PHY Register Access with SMi in iEEE Mode .................................................................................... 38
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12.3 SMi interrupt ....................................................................................................................................... 40
13
14
LED interface ................................................................................................................................................................. 41
13.1 Serial LED Output ............................................................................................................................... 43
Test Mode interface (JTAG) ......................................................................................................................................... 44
14.1 Supported instructions and instruction Codes .................................................................................... 45
14.2 Boundary-Scan Register Cell Order ................................................................................................... 46
15
16
17
Enhanced ActiPHY Power Management ................................................................................................................... 47
15.1 Operation in Enhanced ActiPHY Mode .............................................................................................. 47
15.2 Low-Power State ................................................................................................................................ 48
15.3 LP Wake-Up State .............................................................................................................................. 48
15.4 Normal Operating State ...................................................................................................................... 48
Ethernet in-line Powered Device Support ................................................................................................................ 49
16.1 Cisco in-Line Powered Device Detection Mode ................................................................................. 49
16.2 in-Line Power Ethernet Switch Diagram ............................................................................................. 49
16.3 in-Line Powered Device Detection (Cisco Method) ............................................................................ 50
16.4 iEEE 802.3af (DTE Power via MDi) .................................................................................................... 50
Advanced Test Modes .................................................................................................................................................. 51
17.1 Ethernet Packet Generator (EPG) ...................................................................................................... 51
17.2 CRC Counter ...................................................................................................................................... 51
17.3 Far-End Loopback .............................................................................................................................. 51
17.4 Near-End Loopback ............................................................................................................................ 52
17.5 Connector Loopback .......................................................................................................................... 52
18
19
Hardware Configuration Using CMODE pins ........................................................................................................... 53
18.1 Setting the CMODE Configuration Bits ............................................................................................... 53
18.2 CMODE Bit Descriptions .................................................................................................................... 54
18.3 Procedure for Selecting CMODE Pin Pull-Up/Pull-Down Resistor Values ......................................... 56
EEPROM interface ........................................................................................................................................................ 57
19.1 Programming Multiple VSC8221s Using the Same EEPROM ........................................................... 57
20
21
22
PHY Startup and initialization ..................................................................................................................................... 61
PHY Operating Modes .................................................................................................................................................. 62
PHY Register Set Conventions ................................................................................................................................... 63
22.1 PHY Register Set Structure ................................................................................................................ 63
22.2 PHY Register Set Nomenclature ........................................................................................................ 64
22.3 PHY Register Bit types ....................................................................................................................... 64
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23
PHY Register Set ........................................................................................................................................................... 65
23.1 PHY Register Names and Addresses ................................................................................................ 65
23.2 Mii Register Descriptions .................................................................................................................... 67
23.2.1
23.2.2
23.2.3
23.2.4
23.2.5
23.2.6
23.2.7
23.2.8
23.2.9
Register 0 (00h) – Mode Control Register ...........................................................................................67
Register 1 (01h) – Mode Status Register ............................................................................................69
Register 2 (02h) – PHY identifier Register #1 ....................................................................................70
Register 3 (03h) – PHY identifier Register #2 .....................................................................................71
Register 4 (04h) – Auto-Negotiation Advertisement Register ............................................................71
Register 5 (05h) – Auto-Negotiation Link Partner Ability Register ....................................................72
Register 6 (06h) – Auto-Negotiation Expansion Register ..................................................................73
Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register ...................................................74
Register 8 (08h) – Auto-Negotiation Link Partner Next-Page Receive Register ..............................75
23.2.10 Register 9 (09h) – 1000BASE-T Control Register .............................................................................76
23.2.11 Register 10 (0Ah) – 1000BASE-T Status Register #1 .......................................................................78
23.2.12 Register 11 (0Bh) – Reserved Register ...............................................................................................79
23.2.13 Register 12 (0Ch) – Reserved Register ...............................................................................................80
23.2.14 Register 13 (0Dh) – Reserved Register ...............................................................................................80
23.2.15 Register 14 (0Eh) – Reserved Register ...............................................................................................80
23.2.16 Register 15 (0Fh) – 1000BASE-T Status Register #2 .......................................................................80
23.2.17 Register 16 (10h) – Reserved ..............................................................................................................81
23.2.18 Register 17 (11h) – Reserved ..............................................................................................................81
23.2.19 Register 18 (12h) – Bypass Control Register ......................................................................................81
23.2.20 Register 19 (13h) – Reserved .............................................................................................................. 83
23.2.21 Register 20 (14h) – Reserved ..............................................................................................................84
23.2.22 Register 21 (15h) – Reserved ..............................................................................................................84
23.2.23 Register 22 (16h) – Control & Status Register ....................................................................................84
23.2.24 Register 23 (17h) – PHY Control Register #1 .....................................................................................86
23.2.25 Register 24 (18h) – PHY Control Register #2 .....................................................................................87
23.2.26 Register 25 (19h) – interrupt Mask Register ........................................................................................88
23.2.27 Register 26 (1Ah) – interrupt Status Register ......................................................................................90
23.2.28 Register 27 (1Bh) – LED Control Register ..........................................................................................92
23.2.29 Register 28 (1Ch) – Auxiliary Control and Status Register ................................................................94
23.2.30 Register 29 (1Dh) – Reserved ..............................................................................................................96
23.2.31 Register 30 (1Eh) - MAC interface Clause 37 Auto-Negotiation Control and Status .......................96
23.2.32 Register 31 (1Fh) – Extended Page Access .......................................................................................98
23.3 Extended Mii Registers ....................................................................................................................... 98
23.3.1
23.3.2
23.3.3
23.3.4
23.3.5
23.3.6
23.3.7
23.3.8
23.3.9
Register 16E (10h) - Reserved .............................................................................................................98
Register 17E (11h) - Serdes Control Register .....................................................................................98
Register 18E (12h) - Reserved .............................................................................................................99
Register 19E (13h) - SerDes Control # 2 .............................................................................................99
Register 20E (14h) - Extended PHY Control Register #3 ................................................................100
Register 21E (15h) - EEPROM interface Status and Control Register ...........................................101
Register 22E (16h) - EEPROM Data Read/Write Register ..............................................................102
Register 23E (17h) - Extended PHY Control Register #4 ................................................................103
Register 24E (18h) - Reserved ...........................................................................................................103
23.3.10 Register 25E (19h) - Reserved ...........................................................................................................104
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23.3.11 Register 26E (1Ah) - Reserved ..........................................................................................................104
23.3.12 Register 27E (1Bh) - Reserved ..........................................................................................................104
23.3.13 Register 28E (1Ch) - Reserved ..........................................................................................................104
23.3.14 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1 ..................... 105
23.3.15 Register 30E (1Eh) - 1000BASE-T Ethernet Packet Generator Register #2 .................................106
24
Electrical Specifications ............................................................................................................................................ 107
24.1 Absolute Maximum Ratings .............................................................................................................. 107
24.2 Recommended Operating Conditions .............................................................................................. 107
24.3 Thermal Application Data ................................................................................................................. 108
24.4 Package Thermal Specifications - 100 TFBGA ................................................................................ 109
24.5 Current and Power Consumption Estimates .................................................................................... 109
25
26
DC Specifications ....................................................................................................................................................... 114
25.1 Digital Pins (VDDiO = 3.3 V) ............................................................................................................. 114
25.2 Digital Pins (VDDiO = 2.5 V) ............................................................................................................. 114
25.3 LED Output Pins (LED[2:0]) ............................................................................................................. 115
Clocking Specifications ............................................................................................................................................. 116
26.1 Reference Clock Option ................................................................................................................... 116
26.2 Crystal Option ................................................................................................................................... 116
27
28
SerDes Specifications ................................................................................................................................................ 117
System Timing Specifications .................................................................................................................................. 118
28.1 JTAG Timing ..................................................................................................................................... 118
28.2 SMi Timing ........................................................................................................................................ 119
28.3 MDiNT Timing ................................................................................................................................... 120
28.4 Serial LED_CLK and LED_DATA Timing ......................................................................................... 120
28.5 REFCLK Timing ................................................................................................................................ 121
28.6 CLKOUT and CLKOUTMiCRO Timing ............................................................................................. 122
28.7 Reset Timing .................................................................................................................................... 123
29
Packaging Specifications .......................................................................................................................................... 124
29.1 100-Ball 9 × 9mm TFBGA Mechanical Specification ........................................................................ 124
29.2 Package Moisture Sensitivity ............................................................................................................ 124
30
31
Ordering information .................................................................................................................................................. 125
30.1 Devices ............................................................................................................................................. 125
Design Guidelines ....................................................................................................................................................... 126
31.1 Required PHY Register Write Sequence .......................................................................................... 126
31.2 interoperability with intel 82547Ei Gigabit Ethernet MAC+PHY iC ................................................... 126
31.3 SerDes Jitter ..................................................................................................................................... 126
31.4 SGMii 100BASE-TX Corruption of Packets with Odd Preambles .................................................... 127
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31.5 SGMii 100BASE-TX Corruption of Packets with no ESDs ............................................................... 127
31.6 Software Reset Time ........................................................................................................................ 128
31.7 Reducing EMi ................................................................................................................................... 128
31.8 Clause 40 Auto MDi/MDi-X interoperability Testing ......................................................................... 129
31.9 10BASE-T HDX issue with iXiA Test Suite ....................................................................................... 129
31.10 100BASE-FX initialization Script ...................................................................................................... 129
32
33
Product Support .......................................................................................................................................................... 133
32.1 Available Documents and Application Notes .................................................................................... 133
Document History and Notices ................................................................................................................................ 134
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Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
VSC8221 Block Diagram........................................................................................................................................ 3
100 Ball TFBGA Package Ball Diagram ............................................................................................................. 14
Signal Type Descriptions ..................................................................................................................................... 15
System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY Operating Mode ............ 27
System Schematic - 100Mbps Fiber Media implementation............................................................................. 28
Twisted Pair interface........................................................................................................................................... 29
Data Validity [D] .................................................................................................................................................... 34
Start [S] and Stop [T] Definition ........................................................................................................................... 34
Acknowledge (by Receiver) [A] ........................................................................................................................... 34
Figure 10. Acknowledge (by Host) [H] .................................................................................................................................. 34
Figure 11. No Acknowledge (by Host) [N] ............................................................................................................................ 35
Figure 12. MDiO Read Frame............................................................................................................................................... 39
Figure 13. MDiO Write Frame ............................................................................................................................................... 40
Figure 14. Logical Representation of MDiNT Pin................................................................................................................. 40
Figure 15. Test Access Port and Boundary Scan Architecture............................................................................................ 44
Figure 16. Enhanced ActiPHY State Diagram...................................................................................................................... 47
Figure 17. in-line Powered Ethernet Switch Diagram.......................................................................................................... 49
Figure 18. Far-end Loopback Block Diagram ...................................................................................................................... 51
Figure 19. Near-end Loopback Block Diagram.................................................................................................................... 52
Figure 20. Connector Loopback............................................................................................................................................ 52
Figure 21. EEPROM interface Connections......................................................................................................................... 58
Figure 22. PHY Startup and initialization Sequence ............................................................................................................ 61
Figure 23. Extended Page Register Diagram ...................................................................................................................... 63
Figure 24. JTAG interface AC Timing................................................................................................................................... 118
Figure 25. SMi AC Timing..................................................................................................................................................... 119
Figure 26. LED_CLK and LED_DATA Output AC Timing.................................................................................................. 120
Figure 27. REFCLK AC Timing ........................................................................................................................................... 121
Figure 28. CLKOUT AC Timing........................................................................................................................................... 122
Figure 29. CLKOUTMiCRO AC Timing .............................................................................................................................. 122
Figure 30. RESET AC Timing.............................................................................................................................................. 123
Figure 31. 100-Ball 9 × 9mm TFBGA Mechanical Specification....................................................................................... 124
Figure 32. SGMii Rx Path from the PHY to the MAC ........................................................................................................ 127
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Data Sheet
Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Specifications and Documentation ........................................................................................................ 4
Data Sheet Conventions ........................................................................................................................ 5
Signal Type Descriptions ..................................................................................................................... 15
Configuration and Control Signals ......................................................................................................16
System Clock interface Signals (SCi) ................................................................................................. 17
Regulator Control and Analog Bias Signals ....................................................................................... 18
JTAG Access Port ................................................................................................................................ 19
Serial Management interface Signals ................................................................................................. 20
EEPROM interface Signals ................................................................................................................. 21
Table 10. LED interface Signals ........................................................................................................................... 22
Table 11. Serial MAC interface Signals ............................................................................................................... 22
Table 12. Twisted Pair interface Signals ............................................................................................................. 24
Table 13. Power Supply and Ground Connections ............................................................................................ 25
Table 14. No Connects ......................................................................................................................................... 25
Table 15. Power Supply and Associated Functional Signals ............................................................................. 26
Table 16. MDi Wiring Pair Combinations ............................................................................................................ 30
Table 17. SMi Pin Descriptions - MSA Mode ......................................................................................................33
Table 18. SMi Pin Descriptions - iEEE Mode ......................................................................................................38
Table 19. SMi Frame Format ............................................................................................................................... 39
Table 20. LED Function Assignments ................................................................................................................. 41
Table 21. Parallel LED Functions ........................................................................................................................ 41
Table 22. LED Output Options ............................................................................................................................. 43
Table 23. JTAG Device identification Register Description ................................................................................ 44
Table 24. JTAG interface instruction Codes ........................................................................................................ 45
Table 25. CMODE Pull-up/Pull-down Resistor Values ....................................................................................... 53
Table 26. CMODE Bit to PHY Operating Condition Parameter Mapping ......................................................... 54
Table 27. PHY Operating Condition Parameter Description .............................................................................. 54
Table 28. Configuration EEPROM Data Format ................................................................................................ 58
Table 29. PHY Operating Modes ......................................................................................................................... 62
Table 30. Register Set Nomenclature ................................................................................................................. 64
Table 31. PHY Register Bit Types ....................................................................................................................... 64
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Table 32. PHY Register Names and Addresses ................................................................................................. 65
Table 33. PHY Operating Modes ......................................................................................................................... 86
Table 34. Absolute Maximum Ratings ...............................................................................................................107
Table 35. Recommended Operating Conditions ..............................................................................................107
Table 36. Thermal Application Data ...................................................................................................................108
Table 37. Thermal Resistances .........................................................................................................................108
Table 38. Thermal Specifications - 100-Ball TFBGA 9 × 9mm package .........................................................109
Table 39. VDDiO at 3.3 V, SerDes-Cat-5, SCLK Disabled ..............................................................................109
Table 40. VDDiO at 3.3 V, SGMii-Cat-5 (1000 Mbps), SCLK Disabled .......................................................... 110
Table 41. VDDiO at 3.3 V, SGMii-Cat-5 (100 Mbps), SCLK Disabled ............................................................ 110
Table 42. VDDiO at 3.3 V, SGMii-Cat-5 (10 Mbps), SCLK Disabled ................................................................111
Table 43. VDDiO at 3.3 V SerDes-Cat-5, SCLK Enabled .................................................................................111
Table 44. VDDiO at 3.3 V SerDes-Cat-5, SFP Mode On ................................................................................. 112
Table 45. VDDiO at 3.3V SGMii-100BASE-FX, SFP Mode Off ....................................................................... 112
Table 46. VDDiO at 3.3 V SerDes-Cat-5, SFP Mode On, Regulator On ........................................................ 112
Table 47. Digital Pins Specifications (VDDiO = 3.3 V) ..................................................................................... 114
Table 48. Digital Pins Specifications (VDDiO = 2.5 V) ..................................................................................... 114
Table 49. LED Output Pins Specification .......................................................................................................... 115
Table 50. Reference Clock Option Specifications ............................................................................................ 116
Table 51. Crystal Option Specifications ............................................................................................................. 116
Table 52. SerDes Specifications ........................................................................................................................ 117
Table 53. JTAG Timing Specifications ............................................................................................................... 118
Table 54. SMi Timing Specifications .................................................................................................................. 119
Table 55. MDiNT Timing Specifications .............................................................................................................120
Table 56. Serial LED_CLK and LED_DATA Timing Specifications .................................................................120
Table 57. REFCLK Timing Specifications .........................................................................................................121
Table 58. CLKOUT and CLKOUTMiCRO Timing Specifications ....................................................................122
Table 59. RESET AC Timing Specification .......................................................................................................123
Table 60. Part Number for the VSC8221 ..........................................................................................................125
Table 61. Software Reset Times ........................................................................................................................128
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8 PACKAGE PIN ASSIGNMENTS & SIGNAL DESCRIPTIONS
8.1 Package Ball Diagram
The following package ball diagram shows the view from the top of the package with the underlying BGA ball positions
superimposed:
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
0.8 mm Ball Pitch (9 x 9 mm body size)
(Top View)
Figure 2. 100 Ball TFBGA Package Ball Diagram
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8.2 Ball Locations and Signal Names
1
2
3
4
5
6
7
8
9
10
MODDEF0/
CLKOUT
RESET
LED1
LED2
CMODE0
TXVPD
TXVPC
TXVPB
TXVPA
XTAL2
A
B
C
D
E
F
A
RXLOS/
SiGDET
XTAL1/
B
TDO
TCK
NC
LED0
TDi
CMODE3
CMODE1
CMODE2
VSS
TXVND
VSS
TXVNC
VSS
TXVNB
VDD33A
VSS
TXVNA
VDDREG
VDD33A
VDD12A
REFCLK
VDDiOC-
TRL
NC
NC
NC
NC
NC
REGEN
C
TMS
VSS
VSS
VSS
VSS
VSS
VSS
REGOUT
D
NC
TRST
VDD12
VDD12
VSS
VSS
VSS
VSS
REFREXT
E
EECLK/
PLLMODE
NC
VSS
VSS
VSS
VDD12
REFFiLT
F
TXDiS/
SRESET
NC
VSS
VSS
VSS
EEDAT
MDiNT
VDD12
G
G
CLKOUTMi-
CRO/OSC-
VDDiOMi-
CRO
NC
NC
NC
NC
NC
NC
VDDiO
NC
NC
NC
VSS
NC
VDD12
SCLKP
H
H
DiS
MODDEF2/
MDiO
MODDEF1/
SCLKN
J
J
MDC
NC
NC
NC
NC
NC
NC
RDN
RDP
TDP
TDN
K
1
2
3
4
5
6
7
8
9
10
Figure 3. Signal Type Descriptions
8.3 Signal Type Descriptions
Table 3. Signal Type Descriptions
Symbol
Signal Type
Description
i
Digital input
Standard digital input signal. No internal pull-up or pull-down.
Standard digital input. includes on-chip 100k pull-up to VDDiO,
iPU
Digital input with Pull-up
Digital input with Pull-up
VDDiOMiCRO,VDDiOCTRL or the VDD33A supply. Refer to Section 15: “Power
Supply and Associated Functional Signals” for details.
Standard digital input. includes on-chip 100k pull-up to
VDDiO,VDDiOMiCRO,VDDiOCTRL or the TXVDD supply. Refer to
Section 15: “Power Supply and Associated Functional Signals” for details. This
input pin is 5v tolerant.
iPU5V
iPD
Digital input with Pull-down Standard digital input. includes on-chip 100k pull-down to GND.
Standard digital input. includes on-chip 100k pull-down to GND. This input pin is 5V
iPD5V
Digital input with Pull-down
tolerant.
SerDes differential input pair with 100Ω or 150Ω differential terminations. Pins
Differential input Pair
iDiFF
should be AC-coupled with external 0.01µF capacitors.
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Table 3. Signal Type Descriptions (continued)
Symbol
Signal Type
Description
O
Digital Output
Standard digital output signal.
50Ω integrated (on-chip) source series terminated, digital output signal. Used
impedance Controlled Output primarily for timing-sensitive, 125MHz clock output pins, in addition to high speed
manufacturing test mode pins.
OZC
SerDes differential output pair, with on-chip 100Ω or 150Ω differential terminations.
Differential Output Pair
ODiFF
i/O
Pins should be AC-coupled with external 0.01µF capacitors.
Digital Bidirectional
Digital Bidirectional
Tristate-able, digital input and output signal.
Tristate-able, digital input and output signal. includes on-chip 100k pull-up to
VDDiO,VDDiOMiCRO,VDDiOCTRL or the VDD33A supply. Refer to
Section 15: “Power Supply and Associated Functional Signals” for details.
iPU/O
Tristate-able, digital input and output signal. includes on-chip 100k pull-down to
GND.
i
PD/O
OD
Digital Bidirectional
Open drain digital output signal. Must be pulled to VDDiOMiCRO through an
external pull-up resistor.
Digital Open Drain Output
Analog Differential
Analog Bias
ADiFF
ABiAS
iA
Analog differential signal pair for twisted pair interface.
Analog bias or reference signal. Must be tied to external resistor and/or capacitor
bias network, as shown in Section 9: “System Schematics”.
Analog input
Analog input for sensing variable voltage levels.
Open source digital output signal. Must be pulled to GND through an external pull-
down resistor.
OS
Open Source
P
G
Power Supply
GND
Power supply connection. Must be connected to specified power supply plane.
Ground Connection. Must be connected to ground.
NC
No Connect
No connect signal. Must be left floating.
8.4 Detailed Pin Descriptions
Table 4. Configuration and Control Signals
100 TFBGA
Signal Name
Type
Description
Ball
Hardware Chip Mode Select.
CMODE3
CMODE2
CMODE1
CMODE0
The CMODE inputs are used for hardware configuration of the various operating
modes of the PHY. Each pin has multiple settings, each of which is established by
an external 1% resistor tied to GND or VDD33A. See “Hardware Configuration
Using CMODE pins,” page 53 for details on configuring the PHY with the CMODE
pins.
iA
B4,C5,B5,A5
Hardware Chip Reset.
RESET is an active low input. When asserted, it powers down all of the internal
reference voltages and the PLLs. it resets all internal logic, including the DSPs and
the Mii Management Registers.
A2
RESET
i
Hardware reset is distinct from soft reset which only resets the port to accept new
configuration based on register settings.
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Table 4. Configuration and Control Signals (continued)
100 TFBGA
Signal Name
Type
Description
Transmit Disable or Software Reset.
Ball
When asserted, it places the PHY in a low power state, which includes disabling the
SerDes interface. Although the device is powered down, non-volatile Serial
Management interface registers retain their values.
TXDiS/
SRESET
iPU
G8
TXDiS and SRESET are simply two names for the same function. The assertion
state (active high or low respectively) of this input pin is determined by the value of
Mii Register 21E.15 'SFP MODE' set at startup using Hardware Configuration or
using the EEPROM interface. Refer to “Hardware Configuration Using CMODE
pins,” page 53 and “EEPROM interface,” page 57 for details on configuration at
startup.
Table 5. System Clock interface Signals (SCi)
100
TFBGA
BALL
Signal Name
Type
Description
XTAL1 - Crystal Oscillator input.
Enabled by pulling OSCDiS (internal Oscillator Disabled) high, a 25MHz parallel
resonant crystal, with a +/- 50ppm frequency tolerance, should be connected
across XTAL1 and XTAL2. 33pf capacitors should be connected from XTAL1 and
XTAL2 to ground when using AT cut-type crystal rated for a parallel capacitance
of 20pf. PLLMODE should be left floating (or pulled low) on reset when a 25MHz
crystal is used.
XTAL1/
REFCLK
B10
i
REFCLK - PHY Reference Clock input.
The reference input clock can either be a 25MHz (PLLMODE is low) or 125MHz
(PLLMODE is high) reference clock, with a +/-100ppm frequency tolerance. See
EECLK / PLLMODE pin description for more details.
Crystal Output.
25MHz parallel resonant crystal oscillator output. 33pF capacitors should be
connected from both XTAL1 and XTAL2 to ground when using AT cut-type crystal
rated for a parallel capacitance of 20pf. PLLMODE should be left floating (or tied
low) on reset when using the 25MHz crystal.
A10
XTAL2
O
This output can be left floating if driving XTAL1/REFCLK with a reference clock.
CLKOUTMiCRO - Clock Output.
This is a 4MHz (default) or a 125MHz output clock depending on the value of Mii
Register 20E.8. The voltage levels of the clock are based on the VDDiOMiCRO
power supply.
CLKOUTMi-
CRO/ OSCDiS
iPU/O
H10
OSCDiS - Active Low on-chip Oscillator Disable input.
This input is sampled during the device power-up sequence or on assertion of
RESET. When sampled high, the PHY enables the internal on-chip oscillator
allowing operation with a 25MHz crystal. When sampled low, the PHY’s oscillator
is turned off and the PHY must be supplied with an external 25MHz or 125MHz
clock on the REFCLK pin.
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Table 5. System Clock interface Signals (SCi) (continued)
100
TFBGA
BALL
Signal Name
Type
Description
The functionality of this signal pin depends on the value for Mii Register 21E.15
‘SFP Mode’ which is set at startup. Refer to “Hardware Configuration Using
CMODE pins,” page 53, and “EEPROM interface,” page 57 for details on
configuration at startup.
MODDEF0 – Active Low PHY Ready indicator Output (valid in SFP Mode,
when Mii Register 21E.15 = 1).
This output is driven high immediately on PHY power-up or reset. This signal is
asserted low after the PHY startup sequence has completed and the PHY has
enabled access to the EEPROM connected to the EEPROM interface through the
Serial Management interface. The minimum time this signal is high before being
driven low is 10ms. The maximum time depends on the startup information stored
in the EEPROM. Refer to “PHY Startup and initialization,” page 61 and “EEPROM
interface,” page 57 for details.
MODDEF0/
CLKOUT
A1
O
CLKOUT – 125MHz Clock Output
(valid in iEEE Mode, when Mii Register 21E.15 = 0).
The PHY drives a 125MHz clock output after the PHY startup sequence has
completed. This clock can be disabled by clearing Mii Register 18.0. The voltage
levels of this clock are determined by the VDDiO power supply.
Table 6. Regulator Control and Analog Bias Signals
100 TFBGA
Signal Name
REFREXT
REFFiLT
Type
ABiAS
ABiAS
Description
BALL
REFREXT - Reference External Resistor.
Bias pin connects through external 2kΩ (1%) resistor to analog ground.
E10
REFFiLT - Reference Filter.
Filter internal reference through external 0.1µF (10%) capacitor to analog ground.
F10
C10
REGEN- Regulator Enable.
Tie to VDD33A (3.3v) to enable the internal 1.2v regulator for normal chip
operation.
ABiAS
REGEN
REGOUT - Regulator Supply Output.
This is the output of the on-chip switching regulator, which generates the primary
1.2v power supply voltage VDD12. REGOUT must be connected to an off-chip
“LC” filter. See Section 9: “System Schematics” for more information.
ABiAS
D10
REGOUT
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Table 7. JTAG Access Port
100 TFBGA
Signal Name
BALL
Type
Description
JTAG Test Data Serial input Data.
Serial test pattern data is scanned into the device on this input pin, which is
sampled with respect to the rising edge of TCK.
iPU5V
C3
B2
D3
TDi
This pin should be tied high to VDDiOCTRL in designs that do not require JTAG
functionality.
JTAG Test Data Serial Output Data.
Serial test data from the PHY is driven out of the device on the falling edge of
TCK. This pin should be left floating during normal chip operation.
OZC
TDO
TMS
JTAG Test Mode Select.
This input pin, sampled on the rising edge of TCK, controls the TAP (Test Access
Port) controller’s 16-state, instruction state machine.
iPU5V
This pin should be tied high to VDDiOCTRL in designs that do not require JTAG
functionality.
JTAG Test Clock.
This input pin is the master clock source used to control all JTAG test logic in the
device.
iPU5V
C2
TCK
This pin should be pulled down with a 2kΩ pull-down resistor in designs that
require JTAG functionality.
This pin should be tied low in designs that do not require JTAG functionality.
JTAG Reset.
This active low input pin serves as an asynchronous reset to the JTAG TAP
controller’s state machine. As required by the JTAG standard, this pin includes an
integrated on-chip pull-up (to VDDiOCTRL) resistor. Because of the internal
pull-up, if the JTAG controller on the printed circuit board does not utilize the
TRST signal, then the device will still function correctly when the TRST pin is left
unconnected on the board.
iPU5V
E3
TRST
if the JTAG port of the PHY is not used on the printed circuit board, then this pin
should be pulled down with a 2kΩ pull-down resistor or a falling edge must be
provided to this pin after PHY power up.
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Table 8. Serial Management interface Signals
100 TFBGA
Signal Name
Type
Description
BALL
The Functionality of this pin is determined by the value of Mii Register 21E.15
‘SFP MODE’ set at startup using CMODE Hardware Configuration or via the
EEPROM interface.
MODDEF1 - Serial MSA Clock (valid in SFP Mode, when Mii Register 21E.15
= 1).
MODDEF1 is the clock input of the two-wire serial interface for accessing the
PHY’s registers or the EEPROM connected to the EEPROM interface using the
protocol specified in the MSA specification. Although typically operated at
100kHz, MODDEF1 can be operated at a maximum of 1MHz.
MODDEF1/
MDC
J10
i
MDC - Management Data Clock (valid in iEEE Mode, when Mii Register
21E.15 = 0).
MDC is the clock input of the two wire serial interface for accessing the PHY’s
registers or the EEPROM connected to the EEPROM interface using the Serial
Management interface protocol specified in the iEEE 802.3 specification.
Although typically operated at less than 100kHz due to frequency limitations of
the EEPROM used with the PHY, the PHY registers can be accessed at a
maximum frequency of 1MHz.
The Functionality of this pin is determined by the value of Mii Register 21E.15
‘SFP MODE’ set at startup using CMODE Hardware Configuration or via the
EEPROM interface.
MODDEF2 - Serial i/O Data (valid in SFP Mode, when Mii Register 21E.15 =
1).
MODDEF2 is the data line of the two-wire serial interface for accessing the PHY’s
registers or the EEPROM connected to the EEPROM interface using the protocol
specified in the MSA specification. This pin normally requires a 1.5kΩ to 4.7kΩ
pull-up resistor to VDDiOMiCRO at the Station Manager. The value of the pull-up
resistor depends on the MODDEF1 frequency and the capacitive load on the
MODDEF2 line.
MODDEF2/
MDiO
J9
i/O
MDiO - Serial i/OP Data (valid in iEEE Mode, when Mii Register 21E.15 = 0).
MDiO is the data line of the two-wire serial interface for accessing the PHY’s
registers or the EEPROM connected to the EEPROM interface using the Serial
Management interface protocol specified in the iEEE 802.3 specification. This pin
normally requires a 1.5kΩ to 4.7kΩ pull-up resistor to VDDiOMiCRO at the
Station Manager. The value of the pull-up resistor depends on the MDC
frequency and the capacitive load on the MDiO line.
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Table 8. Serial Management interface Signals (continued)
100 TFBGA
Signal Name
Type
Description
BALL
Management Data interrupt
MDiNT is asserted whenever there is a change in the operating status of the
device. This open drain signal indicates a change in the PHY's link operating
conditions for which a Station Manager must interrogate to determine further
information. See Mii Register 25 and Mii Register 26 for more information.
The assertion polarity of MDiNT is determined by the presence of a pull-up or
pulldown on the MDiNT pin.
H9
MDiNT
OD
if the MDiNT pin is pulled up to VDDiOMiCRO using a 4.7kΩ το 10kΩ resistor, it
becomes an active low signal.
if the MDiNT pin is pulled down using a 4.7kΩ το 10kΩ resistor, then it becomes
an active high signal.
Table 9. EEPROM interface Signals
100 TFBGA
Signal Name
Type
Description
BALL
EECLK - EEPROM Clock Output.
This output is the clock line of the two-wire, MSA compliant, serial EEPROM
interface. This pin should be connected to the SCL input pin of the AT24 series of
Atmel EEPROMs. Refer to “EEPROM interface,” page 57 for details.
PLLMODE - PLL Mode Select input.
EECLK/
PLLMODE
OZC/iPD
F9
PLLMODE is sampled during the device power-up sequence or on reset. When
PLLMODE is high, the PHY expects a 125MHz clock input as the PHY's
reference clock.
When low (default), a reference clock of 25MHz is expected at the REFCLK pin
from either an external crystal or a clock reference. This pin is internally pulled
down with a 100kΩ resistor.
EEPROM Serial i/O Data.
This bidirectional signal is the data line of the two wire, MSA compliant, serial
EEPROM interface. This pin should be connected to the SDA pin of the AT24
series of Atmel EEPROMs. Refer to “EEPROM interface,” page 57 for details.
The PHY determines that an external EEPROM is present by monitoring the
EEDAT pin at power-up or when RESET is de-asserted. if EEDAT has a 4.7kΩ -
10kΩ external pull-up (to VDDiOMiCRO) resistor, it assumes an EEPROM is
present. The EEDAT pin can be left floating or grounded to indicate no EEPROM.
OZC/iPD
G9
EEDAT
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Table 10. LED interface Signals
100
TFBGA
BALL
Signal Name
Type
Description
LED - Direct-Drive LED Outputs.
After reset, these pins serve as the direct drive, low EMi, LED driver output pins.
All LEDs pins are active-low and driven at a 3.3V logic-high through the VDD33A
analog power supply. The function of each LED can be set using hardware
configuration or via Mii Register 27. Refer “Hardware Configuration Using
CMODE pins,” page 53 and Mii Register 27 for details.
LED2
LED1
LED0
OZC
A4,A3,B3
Table 11. Serial MAC interface Signals
100
TFBGA
BALL
Signal
Name
Type
Description
Transmitter Data Differential input Pair.
TDP
TDN
Differential 1.25Gbaud receiver inputs with register selectable on-chip 100Ω or 150Ω
differential termination. The TDP and TDN signals should be AC-coupled with external
0.01µF series capacitors. See Section 9: “System Schematics” for further information.
iDiFF
K9,K10
K8,K7
Receiver Data Differential Output Pair.
Differential 1.25 Gbaud transmitter outputs. External 0.01µF AC coupling capacitors
should be located on the PHY side. The register selectable 100Ω or 150Ω differential
termination should be placed near the MAC side. For more information, see Section 9.1,
“System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY
Operating Mode” on page 9-27. For more information on adjusting the output swing of
these pins, see “Register 17E (11h) - Serdes Control Register,” page 98.
RDP
RDN
ODiFF
SGMii Clock Differential Output Pair.
This signal pair is a differential 625MHz SGMii clock for the SGMii data in accordance
with Cisco’s SGMii specification. These pins should be AC-coupled with external 0.01µF
series capacitors or left unconnected when not used. For more information, see Section
9.1, “System Schematic - SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY
Operating Mode” on page 9-27. For more information on adjusting the output swing of
these pins, see “Register 17E (11h) - Serdes Control Register,” page 98.
SCLKP
SCLKN
ODiFF
J7,J8
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Table 11. Serial MAC interface Signals (continued)
100
TFBGA
BALL
Signal
Name
Type
Description
The functionality of this signal pin depends on the value of Mii Register 21E.15 ‘SFP
Mode’ which is set at startup. Refer to “Hardware Configuration Using CMODE pins,”
page 53 and “EEPROM interface,” page 57 for details on configuration at startup.
RXLOS - Receiver Loss of Signal Output (valid in SFP Mode, when Mii Register
21E.15 = 1).
This active high signal is asserted when the Cat-5 link goes down. The pulse width of the
RXLOS signal is configurable. Refer to Mii Register 30.1:0 for details.
SiGDET - SerDes Signal Detect (i/O) (valid in iEEE Mode, when Mii Register 21E.15
= 0).
SiGDET can be configured as an input or output and can be configured to function as
active low or active high at startup using hardware configuration or the EEPROM
interface. Refer to “Hardware Configuration Using CMODE pins,” page 53 or “EEPROM
interface,” page 57 for details on configuration at startup.
RXLOS/
SiGDET
B1
i/O
SiGDET as input:
When used as an input, the SiGDET signal is meant to be connected to the signal detect
output of the fiber optic transceiver. if SiGDET is high, this indicates receive activity on the
fiber optic transceiver.
if SiGDET is not used as an input, the PHY internally generates the signal detect function,
from the incoming data on the TDP and TDN signal pins.
SiGDET as Output:
For Serial MAC to CAT5 Media PHY Operating modes, SiGDET is asserted if a valid
CAT5 link has been established.
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Table 12. Twisted Pair interface Signals
100
TFBGA
BALL
Signal
Name
Type
Description
TX/RX Channel “A” Positive Signal.
Positive differential signal connected to the positive primary side of the transformer. This
signal forms the positive signal of the “A” data channel. in all three speeds, this signal
generates the secondary side signal, normally connected to RJ-45 pin 1. in 100BASE-FX
mode, it is connected instead to the positive SFP transmit data signal (SFP_TD+). See
Section 9: “System Schematics” for details.
ADiFF
A9
B9
TXVPA
TX/RX Channel “A” Negative Signal.
Negative differential signal connected to the negative primary side of the transformer.
This signal forms the negative signal of the “A” data channel. in all three speeds, this
signal generates the secondary side signal, normally connected to RJ-45 pin 2. in
100BASE-FX mode, it is connected instead to the negative SFP transmit data signal
ADiFF
TXVNA
(SFP_TD–). See Section 9: “System Schematics” for details.
TX/RX Channel “B” Positive Signal.
Positive differential signal connected to the positive primary side of the transformer. This
signal forms the positive signal of the “B” data channel. in all three speeds, this signal
generates the secondary side signal, normally connected to RJ-45 pin 3. in 100BASE-FX
mode, it is connected instead to the positive SFP receive data signal (SFP_RD+). See
Section 9: “System Schematics” for details.
ADiFF
A8
B8
TXVPB
TXVNB
TX/RX Channel “B” Negative Signal.
Negative differential signal connected to the negative primary side of the transformer.
This signal forms the negative signal of the “B” data channel. in all three speeds, this
signal generates the secondary side signal, normally connected to RJ-45 pin 6. in
100BASE-FX mode, it is connected instead to the negative SFP receive data signal
(SFP_RD–). See Section 9: “System Schematics” for details.
ADiFF
TX/RX Channel “C” Positive Signal.
Positive differential signal connected to the positive primary side of the transformer. This
signal forms the positive signal of the “C” data channel. in 1000Mb mode, this signal
generates the secondary side signal, normally connected to RJ-45 pin 4 (not used in 10M/
100M modes). See Section 9: “System Schematics” for details.
ADiFF
ADiFF
ADiFF
ADiFF
A7
B7
A6
B6
TXVPC
TXVNC
TXVPD
TXVND
TX/RX Channel “C” Negative Signal.
Negative differential signal connected to the negative primary side of the transformer.
This signal forms the negative signal of the “C” data channel. in 1000Mb mode, this signal
generates the secondary side signal, normally connected to RJ-45 pin 5 (not used in the
10M/100M modes). See Section 9: “System Schematics” for details.
TX/RX Channel “D” Positive Signal.
Positive differential signal connected to the positive primary side of the transformer. This
signal forms the positive signal of the “D” data channel. in 1000Mb mode, this signal
generates the secondary side signal, normally connected to RJ-45 pin 7 (not used in the
10M/100M modes). See Section 9: “System Schematics” for details.
TX/RX Channel “D” Negative Signal.
Negative differential signal connected to the negative primary side of the transformer.
This signal forms the negative signal of the “D” data channel. in 1000Mb mode, this signal
generates the secondary side signal, normally connected to RJ-45 pin 8 (not used in the
10M/100M modes). See Section 9: “System Schematics” for details.
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Table 13. Power Supply and Ground Connections
100
TFBGA
BALL
Nominal
Supply
Voltage
(V)
Supply
Name
Recommended PCB
Power Plane
Type
Description
Digital i/O Power Supply Pins
3.3V or
2.5V
Power for the RXLOS/SiGDET and
MODDEF0/CLKOUT pins
VDDiO1
H4
V+iO
V+iO
V+iO
P
P
P
3.3V or
2.5V
VDDiOMiCRO1
H8
Power for SMi and EEPROM interface
Power for JTAG i/O
3.3V or
2.5V
VDDiOCTRL1
C4
Digital Core Power Supply Pins
G10,F3,G3,
VDD12
Power for internal digital logic, PLL and
SerDes/SGMii i/O Power
V+12
P
P
1.2V
F8,H7
Analog Power Pins
Power for MDi, CMODE, PLL, and LED
blocks
C8,D9
VDD33A
V+33A
3.3V
C9
E9
VDDREG
VDD12A
V+33REG
V+12A
P
P
3.3V
1.2V
Power for on-chip switching regulator
Power for internal PLL and ADC
Ground Pins
D4,D5,D6,
D7,E4,E5,
E6,E7,F4,
F5,F6,F7,
G4,G5,G6,
G7,C6,C7,
D8,E8,H6
VSS
GND
G
0V
Ground for all blocks
1
The i/O power supplies on the PHY are separated on the chip itself to facilitate support for different VDDiO supply voltages. These VDDiO
supplies can be run independently at 2.5V OR 3.3V i/O.
Table 14. No Connects
100 TFBGA
Signal Name
Type
Description
BALL
C1,D1,E1,
F1,G1,H1,
J1,K1,D2,
E2,F2,G2,
H2,J2,K2,
H3,J3,K3,
J4,K4,H5,
J5,K5,J6,K6
NC
NC
No Connect - must be left floating
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Table 15. Power Supply and Associated Functional Signals
Power Sup-
Nominal Voltages
ply Pins
Associated Functional Pins
RXLOS/SiGDET, MODDEF0/CLKOUT
VDDiO
3.3V or 2.5V
3.3V or 2.5V
VDDiO-
MiCRO
EECLK/PLLMODE, EEDAT, TXDiS/SRESET, MDiNT, MODDEF1/MDC,
MODDEF2/MDiO, CLKOUTMiCRO/OSCDiS
VDDiOC-
TRL
3.3V or 2.5V
3.3V
RESET, TDO, TDi, TMS, TCK, TRST
LED[2:0], CMODE[3:0], TXVND, TXVPD, TXVNC, TXVPC, TXVNB, TXVPB, TXVNA,
TXVPA, XTAL2, XTAL1/REFCLK, REFFiLT, REFREXT
VDD33A
VDDREG
VDD12
3.3v
1.2V
1.2V
REGOUT
RDP, RDN, TDP, TDN, SCLKP, SCLKN
VDD12A
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9 SYSTEM SCHEMATICS
9.1 System Schematic − SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY Operating Mode
4.7-5.6µH
….
100
or
100
or
100
or
150
150
150
10k
4.7k
100
or
150
100
or
150
4.7k
Figure 4. System Schematic − SGMii/802.3z SerDes MAC to 1000Mbps CAT5 Media PHY Operating Mode
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9.2 System Schematic − 100Mbps Fiber Media implementation
VDD33
VDD33
LINK100/ACTIVITY
LEDn
11
12
13
14
15
16
17
18
19
20
1
2
Veet
Tfault
Veer
RD-
PHY_TXVNB
PHY_TXVPB
SFP_RD-
SFP_RD+
TXVNB
TXVPB
SFP_TXFAULT
SFP_TXDIS
SFP_SDA
3
Tdis
RD+
Veer
Vccr
Vcct
Veet
TD+
TD-
4
MOD_DEF2
MOD_DEF1
MOD_DEF0
Rate Select
LOS
5
SFP_SCL
6
SFP_PRESENT
7
PHY_TXVPA
PHY_TXVNA
SFP_TD+
SFP_TD-
8
TXVPA
TXVNA
SFP_RX_LOS
9
Veer
10
Veer
Veet
SFP Connector
VDD33
1uH
10uF
100nF
11
12
13
14
15
16
17
18
19
20
1
2
GND1
GND2
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
3
10uF
100nF
GND3
4
TXVPC
TXVNC
GND4
GND5
5
6
TXVPD
TXVND
GND6
7
1uH
GND7
GND8
8
100nF
9
GND9
10
GND10
SFP Cage
VSC8211/VSC8221
Figure 5. System Schematic − 100Mbps Fiber Media implementation
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10 TWISTED PAIR INTERFACE
The twisted pair interface on the VSC8221 is fully compliant with the iEEE802.3-2000 specification for CAT-5 media. All passive
components necessary to connect the PHY to an external 1:1 transformer have been integrated into the VSC8221. The
connection of the twisted pair interface is shown in the following figure:
VSC8221
*
TXVPA
0.1µF
J1
RJ-45
A+
A-
TXVNA
1
2
TXVPB
0.1µF
3
6
B+
B-
TXVNB
TXVPC
4
5
0.1µF
C+
C-
TXVNC
TXVPD
7
8
D+
D-
0.1µF
S1
S2
TXVND
75
75
75
75
PHY Port
1000pF, 2kV
* SimpliPHY’d magnetics may be used.
For information, refer to the SimpliPHY’d Magnetics
application note.
Figure 6. Twisted Pair interface
Unlike other Gigabit PHYs, which do not integrate the line terminations in the PHY, the VSC8221’s twisted pair interface is
compatible with a wide variety of standard magnetics and RJ-45 modules from common module vendors. Depending upon the
application (the number of ports, EMi performance requirements such as FCC Class A or B, the type and quality of the
equipment shielding, and other EMi design practices, for example), the twisted pair interface may be used with standard (12- or
8-core) magnetics as well as SimpliPHY’d (4-core) magnetics modules available from many module vendors. in addition, this
interface is also used to provide support for 100Mbps fiber module connection. For more information on the suitability of using
SimpliPHY’d magentics for a particular design, see the Magnetics Guide, available from the Microsemi Web site.
10.1 Twisted Pair Auto-Negotiation (iEEE802.3 Clause 28)
The VSC8221 supports twisted pair auto-negotiation, as defined in iEEE 802.3-2002 clause 28. (However, auto-negotiation is
not defined by iEEE for the 100BASE-FX mode and is therefore not supported.) This process evaluates the advertised
capabilities of the local PHY and its link partner to determine the best possible operating mode. in particular, auto-negotiation
can determine speed, duplex, and MASTER/SLAVE modes for 1000BASE-T. Auto-negotiation also allows the local MAC to
communicate with the Link Partner MAC (via optional “Next-Pages”) to set attributes that may not be defined in the standard. if
the link partner does not support auto-negotiation, the VSC8221 will automatically use parallel-detect to select the appropriate
link speed.
Clause 28 twisted-pair auto-negotiation can be disabled by clearing Mii Register 0.12 – Auto-Negotiation Enable. if auto-
negotiation is disabled, the operating speed and duplex mode of the VSC8221 is determined by the state of Mii Register 0.13,
0.6 – Forced Speed Selection and Mii Register 0.8 – Duplex Mode.
10.2 Twisted Pair Auto MDi/MDi-X Function
For trouble-free configuration and management of Ethernet links, the VSC8221 includes robust Automatic Crossover Detection
functionality for all three speeds on the twisted pair interface (10BASE-T, 100BASE-TX, and 1000BASE-T) – fully compliant with
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the iEEE standard. in addition, the VSC8221 detects and corrects polarity errors on all MDi pairs, beyond what is required by the
standard. Both the Automatic MDi/MDi-X and Polarity Correction functions are enabled by default. However, complete user
control of these two features is contained in Mii Register bits 18.5:4. Status bits for each of these functions are indicated in Mii
Register 28 (1Ch) – Auxiliary Control and Status Register.
The VSC8221’s Automatic MDi/MDi-X algorithm will successfully detect, correct, and operate with any of the MDi wiring pair
combinations listed in the following table:
Table 16. MDi Wiring Pair Combinations
RJ-45 Connections
Comments
1,2
3,6
4,5
7,8
Normal MDi mode
Normal DTE/NiC mode
No crossovers
A
B
C
D
MDi-X mode
B
A
A
B
C
D
D
C
Normal for switches & repeaters
Crossover on A and B pairs only
MDi Pair
Connection
Combinations
Accepted by
VSC8221
Normal MDi mode
Normal for DTEs (NiCs)
No crossovers
Pair swap on C and D pairs
Normal MDi-X mode
Normal switch/repeater mode
Crossovers assumed
B
A
D
C
Crossover on A and B pairs
Pair swap on C and D pairs
10.3 Auto MDi/MDi-X in Forced 10/100 Link Speeds
The VSC8221 includes the ability to perform Auto MDi/MDi-X even when auto-negotiation is disabled (Mii Register 0.12 = 0)
and the link is forced into 10/100 link speeds. in order to enable this feature, additional Mii register write settings are also
needed in the following order:
To enable Auto MDi/MDi-X in forced 10/100 link speeds:
•
•
•
•
•
Write Mii Register 31 = 0x52b5
Write Mii Register 18 = 0x0012
Write Mii Register 17 = 0x2803
Write Mii Register 16 = 0x87fa
Write Mii Register 31 = 0x0000
To disable Auto MDi/MDi-X in forced 10/100 link speeds:
•
•
•
•
•
Write Mii Register 31 = 0x52b5
Write Mii Register 18 = 0x0012
Write Mii Register 17 = 0x3003
Write Mii Register 16 = 0x87fa
Write Mii Register 31 = 0x0000
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10.4 Forcing the PHY into MDi or MDi-X mode in 10/100/1000 Link Speeds
if the Auto-MDi/MDi-X feature is disabled by setting Mii Register 18.5, or by disabling auto-negotiation, the PHY’s default
behavior is to establish a link in MDi mode. To force the PHY into MDi-X mode:
•
•
•
Write Mii Register 31 = 0x2A30
Write Mii Register 5 = 0x1038
Write Mii Register 31 = 0x0000
To force the PHY into MDi mode:
•
•
•
Write Mii Register 31 = 0x2A30
Write Mii Register 5 = 0x1030
Write Mii Register 31 = 0x0000
To disable the forcing of MDi/MDi-X mode:
•
•
•
Write Mii Register 31 = 0x2A30
Write Mii Register 5 = 0x1020
Write Mii Register 31 = 0x0000
10.5 Twisted Pair Link Speed Downshift
in addition to automatic crossover detection, the VSC8221 supports an automatic link speed “downshift” option for operation in
cabling environments incompatible with 1000BASE-T. When this feature is enabled, the VSC8221 will automatically change its
auto-negotiation advertisement to 100BASE-TX after a set number of failed attempts at 1000BASE-T. This is especially useful
in setting up networks using older cable installations which may include only pairs A and B and not pairs C and D. The link
speed downshift feature is configured and monitored through Mii Register 20E (14h) - Extended PHY Control Register #3.
10.6 100Mbps Fiber Support Over Copper Media interface
The VSC8221 supports 100BASE-FX over its copper media interface by using pairs A and B, which provide TX and RX
differential connections, respectively. if the fiber module does not have internal AC coupling capacitors, then they are required
between the PHY and fiber module. The value should be 0.1µF.
The RXLOS/SiGDET signal is not used in this mode.
A separate 1000BASE-X fiber module may be connected to the PHY through the 1000BASE-X SerDes pins.
10.6.1 Register Settings
The PHY can be brought into the 100BASE-FX operation mode using the following configuring sequence:
1. initialize the PHY into the specific MAC-to-copper operating mode for the MAC interface type required (register 23).
2. Disable auto-negotiation and force the 100BASE-T FDX mode (register 0).
3. Run the 100BASE-FX initialization script; for more information, see Section 31.10: "100BASE-FX initialization
Script".
4. Configure other settings, such as LEDs.
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11 TRANSFORMERLESS OPERATION FOR PICMG 2.16 AND 3.0 IP-BASED BACKPLANES
The twisted pair interface supports capacitively coupled links, such as those specified by the PiCMG 2.16 and 3.0
specifications. With proper AC coupling, the typical category-5 magnetic isolation can be replaced with capacitors. Refer to
Microsemi Application Note #3 (AN003 - Transformerless Ethernet Concept and Applications) for more information. See MII
Register Bit 24.12 for more information.
By enabling the PiCMG Miser mode, power consumption can be reduced to under 500mW.
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12 DUAL MODE SERIAL MANAGEMENT INTERFACE (SMI)
The Serial Management interface provides access to the PHY registers for device configuration and Status information. it also
provides access to the EEPROM connected to the EEDAT and EECLK pins (EEPROM interface) of the PHY. For details on
EEPROM access through the SMi interface, refer to Section 19 on page 57.
The MODDEF1/MDC, MODDEF2/MDiO, and MDiNT pins comprise the SMi interface.
By writing to Mii Register 21E.15 at startup (Refer to Section 18 on page 53 and Section 19 on page 57 for details), the SMi of
the PHY can be set to operate in one of the following two modes:
1. MSA
2. iEEE
12.1 PHY Register Access with SMi in MSA mode
in this mode, the PHY registers are accessed using the standard MSA compliant protocol. This protocol is generally used for
reading and writing to Atmel’s AT24 series compatible EEPROMs.
in this mode, the SMi pins function as follows:
Table 17. SMi Pin Descriptions - MSA Mode
Pin Name
Description
MODDEF1
Clock input. Connect to the SCL pin of the AT24 series of EEPROMs.
Bidirectional Data. Connect to the SDA pin of the AT24 series of EEPROMs. This
pin should be pulled high on the board using a 4.7kΩ to 10kΩ pullup resistor.
MODDEF2
MDiNT
interrupt Signal.
According to the protocol described in the MSA specification, the following conditions are defined:
• Start [S]: A high to low transition on the MODDEF2 pin when MODDEF1 is high.
• Data [D]: A transition on the MODDEF2 pin when MODDEF1 is low. A low to high transition is '1' and a high to low
transition is '0'.
• Stop [T]: A low to high transition on the MODDEF2 pin when MODDEF1 is high.
• Acknowledge (By Receiver) [A]: A low driven by the PHY/Receiver after 8 Data states. The transition on MODDEF2
takes place when MODDEF1 is low. The host does not drive the MODDEF2 Data line in this condition.
• Acknowledge (By Host) [H]: A low driven by the host after 8 Data states. The transition on MODDEF2 takes place when
MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition.
• No Acknowledge (By Host) [N]: A high driven by the host after 8 Data states. The transition on MODDEF2 takes place
when MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition
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MODDEF2
MODDEF1
Data
Change
Data Stable
Data Stable
Figure 7. Data Validity [D]
MODDEF2
MODDEF1
START [S]
STOP [T]
Figure 8. Start [S] and Stop [T] Definition
1
8
9
MODDEF1
MODDEF2
(Driven by Receiver)
START
ACKNOWLEDGE
Figure 9. Acknowledge (by Receiver) [A]
1
8
9
MODDEF1
MODDEF2
(Driven by Host)
START
ACKNOWLEDGE
Figure 10. Acknowledge (by Host) [H]
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1
8
9
MODDEF1
MODDEF2
(Driven by Host)
START
ACKNOWLEDGE
Figure 11. No Acknowledge (by Host) [N]
12.1.1 Write Operation - Random Write
S
S
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
A
A
0
0
0
0
0
0
R4 R3 R2 R1 R0
A
A
M7 M6 M5 M4 M3 M2 M1 M0
A
A
T
T
R4 R3 R2 R1 R0
L7 L6 L5 L4 L3 L2 L1 L0
From Host to PHY/Receiver
From PHY/Receiver to Host
• R4..R0 are the 5 bits of the Register address R.
• M7..M0 are bits of the Upper byte of the 16 bit Register data
• L7..L0 are bits of the Upper byte of the 16 bit Register data
The PHY register is written only after the host performs the lower data byte write operation.
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12.1.2 Write Operation - Sequential Write
MSB for Register R
S
1
0
1
0
1
1
0
0
A
0
0
0
R4 R3 R2 R1 R0
A
M7 M6 M5 M4 M3 M2 M1 M0
A
LSB for Register R
MSB for Register R+1
L7 L6 L5 L4 L3 L2 L1 L0
A
A
A
M7 M6 M5 M4 M3 M2 M1 M0
A
LSB for Register R+1
MSB for Register R+n
L7 L6 L5 L4 L3 L2 L1 L0
M7 M6 M5 M4 M3 M2 M1 M0
A
LSB for Register R+n
L7 L6 L5 L4 L3 L2 L1 L0
T
From Host to PHY/Receiver
From PHY/Receiver to Host
• R4..R0 are the 5 bits of the Register address R.
• M7..M0 are bits of the Upper byte of the 16 bit Register data
• L7..L0 are bits of the Upper byte of the 16 bit Register data
The PHY register is written only after the host performs the lower data byte write operation.
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12.1.3 Read Operation - Random Read
S
S
S
S
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
A
A
A
A
0
0
0
R4 R3 R2 R1 R0
A
M7 M6 M5 M4 M3 M2 M1 M0
N
T
0
0
0
R4 R3 R2 R1 R0
A
L7 L6 L5 L4 L3 L2 L1 L0
N
T
From Host to PHY/Receiver
From PHY/Receiver to Host
• R4..R0 are the 5 bits of the Register address
• M7..M0 are bits of the Upper byte of the 16 bit Register data
• L7..L0 are bits of the Lower byte of the 16 bit Register data
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12.1.4 Read Operation - Sequential Read
S
1
0
1
0
1
1
0
0
0
1
A
A
0
0
0
R4 R3 R2 R1 R0
A
MSB for Register R
S
1
0
1
0
1
1
M7 M6 M5 M4 M3 M2 M1 M0
MSB for Register R+1
H
LSB for Register R
L7 L6 L5 L4 L3 L2 L1 L0
H
H
N
M7 M6 M5 M4 M3 M2 M1 M0 H
LSB for Register R+1
LSB for Register R+n
L7 L6 L5 L4 L3 L2 L1 L0
M7 M6 M5 M4 M3 M2 M1 M0 H
LSB for Register R+n
L7 L6 L5 L4 L3 L2 L1 L0
T
From Host to PHY/Receiver
From PHY/Receiver to Host
• R4..R0 are the 5 bits of the Register address
• M7..M0 are bits of the Upper byte of the 16 bit Register data
• L7..L0 are bits of the Lower byte of the 16 bit Register data
12.2 PHY Register Access with SMi in iEEE Mode
in iEEE mode, the SMi is fully compliant with the iEEE 802.3-2000 Mii interface specifications.
in iEEE mode, the SMi pins function as follows:
Table 18. SMi Pin Descriptions - iEEE Mode
Pin Name
Description
MDC
Clock input, 0 – 12.5 Mhz.
Bidirectional Data. This pin should be pulled high on the board using a 4.7kΩ to
10kΩ resistor.
MDiO
Active Low or Active High open drain interrupt output.
MDiNT
As many as 32 PHYs (32 distinct PHY Addresses) can share a common iEEE SMi signal pair (MDC, MDiO).
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Data is transferred over the iEEE SMi using 32-bit frames with an optional and arbitrary length preamble. The iEEE SMi frame
format is described in the following table.
Table 19. SMi Frame Format
Direction
Start of
Frame
PHY
Address
Register
Address
Turn-
Around
from
Preamble
Op Code
Data
idle
VSC8221
# of
bits
1+
2
2
5
5
2
16
?
Output
input
Z’s
1’s
Z’s
1’s
ZZ
01
ZZ
01
ZZ
10
ZZ
01
Z’s
Z’s
Z0
ZZ
ZZ
10
data
Z’s
Z’s
Z’s
Z’s
Z’s
Read
Write
addr
Z’s
addr
Z’s
Output
input
Z’s
addr
addr
data
• idle: During idle, the MDiO node goes to a high-impedance state. This allows an external pull-up resistor to pull the MDiO
node up to a logical “1” state. Since idle mode should not contain any transitions on MDiO, the number of bits is
undefined during idle.
• Preamble: For the VSC8221, the preamble is optional. By default, preambles are not expected or required. The preamble
is a string of “1”s. if it exists, the preamble must be at least one bit, but otherwise may be arbitrarily long. See Mii Register
1.6 for more information.
• Start of Frame: A “01” pattern indicates the start of frame. if these bits are anything other than “01”, all following bits are
ignored until the next “preamble:0” pattern is detected.
• Operation Code: A “10” pattern indicates a read. A “01” pattern indicates a write. if these bits are anything other than “01”
or “10”, all following bits are ignored until the next “preamble:0” pattern is detected.
• PHY Address: The next five bits are the PHY address. The PHY responds to a message frame only when the received
PHY address matches its physical address. The PHY's address is indicated by the CMODE1[2] and CMODE0[3:0] bits.
• Register Address: The next five bits are the register address.
• Turn-Around: The next two bits are “turn-around” (TA) bits. They are used to avoid contention when a read operation is
performed on the MDiO. During read operations, the VSC8221 will drive the second TA bit, which is a logical “0”.
• Data: The next sixteen bits are data bits. When data is being read from the PHY, data is valid at the output of the PHY
from one rising edge of MDC to the next rising edge of MDC. When data is being written to the PHY, data must be valid
around the rising edge of MDC.
• idle: The sequence is repeated.
The following two figures diagram iEEE SMi read and iEEE SMi write operations.
Station Manager Drives MDIO
PHY Drives MDIO
MDC
MDIO
Z
Z
1
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Z
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Data from PHY
Z
Z
Idle Preamble SFD
(optional)
Read
PHY Address
Register Address
to PHY
TA
Idle
Figure 12. MDiO Read Frame
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Station Manager Drives MDIO (PHY tristates MDIO during entire sequence)
MDC
MDIO
Z
Z
1
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Data from PHY
Z
Z
Idle Preamble SFD
(optional)
Write
PHY Address
Register Address
to PHY
TA
Idle
Figure 13. MDiO Write Frame
12.3 SMi interrupt
The SMi includes an output signal MDiNT for signaling the Station Manager when certain events occur in the PHY. The MDiNT
pin can be configured for active-low or active-high operation by tying the pin to either a pull-up resistor to VDDiOMiCRO or to a
pull-down resistor to GND.
VDDIOMICRO
VSC8221
4.7k-10k External
Pull-up
at Station Manager
MDINT
MDINT
(to Station Manager)
Interrupt Enable (Register 25.15)
Interrupt Status (Register 26.15)
PHY
4.7k-10k External
Pull-down
at Station Manager
Figure 14. Logical Representation of MDiNT Pin
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13 LED INTERFACE
The PHY has dedicated pins LED[2:0] to drive 3 LEDs directly. For power savings, all LED outputs can be configured to pulse at
5kHz with a 20% duty cycle. All LED outputs are active-low and driven with 3.3V from the VDD33A power supply when
deasserted.
Because the 100BASE-FX mode uses 100BASE-T resources, its indications are those of the 100BASE-T mode.
Four different functions have been assigned to each LED pin. Selection is done through CMODE hardware configuration (see
Section 18 on page 53) or through Mii Register 27 (1Bh) – LED Control Register. The functions are assigned according to the
following table:
Table 20. LED Function Assignments
LED Configuration Bits
Value
11
LED Function Selection
TX1
10
01
00
11
Link/Activity
LED Pin 2 Config [1:0]
Duplex/Collision2
Link10/Activity
Link100/1000/Activity1
Link/Activity
10
01
00
11
LED Pin 1 Config [1:0]
Link10/100/Activity2
Link100/Activity
RX1
10
01
00
Fault
LED Pin 0 Config [1:0]
Link/Act (with serial output on LED pins 1 and 2)2
Link1000/Activity
1
When using Enable Force LED in Mii Register 20E.13, this setting is “Force on”. For more information, see Section 23.3.5 on page 100.
When using Enable Force LED in Mii Register 20E.13, this setting is “Force Off”. For more information, see Section 23.3.5 on page 100.
2
LED functions are summarized in the following table:
Table 21. Parallel LED Functions
Function Name
State
Description
No link in 1000BASE-T or 1000BASE-X
1
0
Link1000/Activity1
Valid 1000BASE-T link or 1000BASE-X link
Valid 1000BASE-T link and activity present (optional)
No link in 100BASE-Tx
Pulse-stretch/Blink2
1
0
Link100/Activity1
Valid 100BASE-Tx link
Pulse-stretch/Blink2
(optional) Valid 100BASE-Tx link and activity present
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Table 21. Parallel LED Functions (continued)
Function Name
State
Description
1
0
No link in 10BASE-T
Valid 10BASE-T link
Link10/Activity1
Pulse-stretch/Blink2
(optional) Valid 10BASE-T link and activity present
No link in 10BASE-T or 100BASE-Tx
1
0
Link10/100/Activi-
ty1
Valid 10BASE-T link or valid 100BASE-Tx link
Pulse-stretch/Blink2
(optional) Valid 10BASE-T link or valid 100BASE-Tx link and activity present
No link in 100BASE-Tx or 1000BASE-T
Valid 100BASE-Tx link or valid 1000BASE-T link
(optional) Valid 100BASE-Tx link or valid 1000BASE-T link and activity present
No link in any speed
1
0
Link100/1000/
Activity1
Pulse-stretch/Blink2
1
0
Link/Act3
Valid link in any speed
Pulse-stretch/Blink2
1
Valid link in any speed and activity present
No collisions detected
Collision
Activity
Fiber
Pulse-stretch/blink2
1
Collisions detected
No activity
Pulse-stretch/blink2
Activity present
1
0
1
0
**
1
0
No valid 1000BASE-X link established
Fiber media detected on SerDes interface and valid 1000BASE-X link established
No iEEE Clause 37/28 auto-negotiation fault
iEEE Clause 37/28 auto-negotiation fault
See serial interface specification
Fault
Serial
Link established in half-duplex mode, or no link established
Link established in full-duplex mode
(optional) Link established in half duplex mode and collisions present
No activity on Rx side
Duplex/Collision4
Pulse-stretch/Blink2
1
Rx
Tx
1
Pulse-stretch/blink2
1
Activity present on Rx side
No activity on Tx side
Pulse-stretch/blink2
Activity present on Tx side
The “Linkxxx” functions are combined with “Activity” by default. To use the LED as a dedicated “Linkxxx,” LED Mii register bit 27.1 must be set.
Function can either blink or be pulse-stretched when active. See Table 22 below.
2
3
4
The “Link” functions are combined with “Activity” by default. To use the LED as a dedicated “Link,” LED Mii Register bit 27.2 must be set.
The “Duplex” function is combined with “Collision” by default. To use the LED as a dedicated “Duplex,” LED Mii register bit 27.0 must be set.
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in addition to function selection, several options are available for the LED outputs through the use of Mii register 27.5:0. These
are summarized below:
Table 22. LED Output Options
Mii
LED Option Bits
LED Function Selection
Reg Bits
0 = 5 Hz blink rate/200 ms pulse-stretch
1 = 10 Hz blink rate/100 ms pulse-stretch
5
LED Pulse-stretch Rate/ Blink Rate
1 = Enable 5 kHz, 20% duty cycle LED pulsing for power
4
3
LED Pulsing Enable
savings
0 = LED pulsing disabled
1 = Collision, Activity, Rx and Tx functions will flash at a rate
selected by Blink/Pulse-Stretch Rate bits
0 = Collision, Activity, Rx and Tx functions will blink at a rate
selected by Blink/Pulse-Stretch Rate bits
LED Pulse-Stretch / Blink Select
1 = Link function indicates link status only
0 = Link/Activity function will blink or flash when activity is pres-
ent. Blink/flash behavior is selected by Pulse-Stretch
Enable and Blink/Pulse-Stretch Rate bits.
2
1
Link/Activity Behaviour
1 = Link function indicates link status only
0 = All link functions will blink or flash when activity is present.
Blink/flash behavior is selected by Pulse-Stretch Enable
and Blink/Pulse-Stretch Rate bits.
LED Linkxxxx/Activity1 Behavior
LED Duplex/Collision Behavior
1 = Duplex function indicates duplex status only
0 = Duplex function will blink or flash when collision is present
0
1
Linkxxxx/Activity stands for Link10/Activity,Link100/Activity,Link1000/Activity,Link10/100/Activity and Link100/1000/Activity. its
definition does not include the Link/Activity function.
13.1 Serial LED Output
A serial output option is available which allows access to all LED signals through two pins. This option is selected by setting
LED Pin 0 configuration bits to 01 on the PHY. in this mode, LED pins 1 and 2 function as serial data and clock. LED function
outputs for the PHY are clocked out on the rising edge of data clock. The clock rate is approximately 1MHz.
The serial bitstream outputs each LED signal as described by the numbered list below.The individual signals shall be clocked
out in the following order:
1. Link1000/Act
2. Link/Act
3. Link100/Act
4. Act
5. Link10/Act
6. Dup/Col
7. Tx
8. Col
9. Rx
10. Fault
11. Fiber/Copper
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14 TEST MODE INTERFACE (JTAG)
The PHY supports the Test Access Port and Boundary Scan Architecture iEEE 1149.1 standards. The device includes an iEEE
1149.1 compliant test interface, often referred to as a “JTAG TAP interface”. iEEE 1149.1 defined test logic provides the
following standardized test methodologies:
• Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or
other substrate.
• Testing the integrated circuit itself during iC and systems manufacture.
• Observing or modifying circuit activity during the component’s normal operation.
The JTAG Test interface logic on the PHY, accessed through a Test Access Port (TAP) interface, consists of a boundary- scan
register and other logic control blocks. The TAP controller includes all iEEE-required signals (TMS, TCK, TDi, and TDO), in
addition to the optional asynchronous reset signal TRST.
The following figure diagrams the TAP and Boundary Scan Architecture.
Boundary-Scan
Register
Device Identification
Register
Bypass Register
Mux,
DFF
TDO
control
Instruction Register,
Instruction Decode,
Control
TDI
control
TMS
TRSTz
TCK
select
Test Access Port
Controller
tdoenable
Figure 15. Test Access Port and Boundary Scan Architecture
The PHY also includes the optional Device identification Register, shown in the following table, which allows the manufacturer,
part number, and version number of the device to be determined through the TAP Controller. See Chapter 11 of the iEEE
1149.1-1990 specifications for more details. Also, note that some of the information in the identification register is duplicated in
the iEEE-specified bit fields in Mii Register 3 (PHY identifier Register #2).
Table 23. JTAG Device identification Register Description
Device Version Number Part Number
Microsemi’s
Manufacturer identity
Description
Bit Field
LSB
(or Revision Code)
(or Model Number)
31 - 28
27 - 12
11 - 1
0
1
Binary Value 0001
1000 0010 0010 0001
001 1001 1000
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14.1 Supported instructions and instruction Codes
After a TAP reset, the Device identification Register is serially connected between TDi and TDO by default. The TAP instruction
Register is loaded either from a shift register (when a new instruction is shifted in), or, if there is no new instruction in the shift
register, a hard-wired default value of 0110 (iDCODE) is loaded. Using this method, there is always a valid code in the
instruction register, and the problem of toggling instruction bits during a shift is avoided. Unused codes are mapped to the
BYPASS instruction.
The VSC8221 supports the instruction codes listed in the following table and described below.
Table 24. JTAG interface instruction Codes
instruction
EXTEST
Code
0000
0001
0110
0010
0011
0111
Selected Register
Register Width
Specification
Boundary-Scan Register
Boundary-Scan Register
Device identification Register
Bypass Register
72
72
32
1
Mandatory iEEE 1149.1
Mandatory iEEE 1149.1
Optional iEEE 1149.1
Optional iEEE 1149.1
Optional iEEE 1149.1
Mandatory iEEE 1149.1
SAMPLE/PRELOAD
iDCODE
CLAMP
HiGHZ
Bypass Register
1
BYPASS
Bypass Register
1
0100, 1000,
1001, 1010,
1011, 1100,
1101,1110,
1111
Reserved
EXTEST
The mandatory EXTEST instruction allows testing of off-chip circuitry and board-level interconnections by sampling input pins
and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which have to be updated with
valid values (with the PRELOAD instruction) prior to the EXTEST instruction.1
SAMPLE/PRELOAD
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of inputs and outputs during normal system operation to be
taken and examined. it also allows data values to be loaded into the boundary-scan cells prior to the selection of other
boundary-scan test instructions.
iDCODE
The optional iDCODE instruction provides the version number (bits 31:28), part number (bits 27:12), and Microsemi’s
manufacturer identity (bits 11:1) to be serially read from the PHY.
CLAMP
The optional CLAMP instruction allows the state of the signals driven from the component pins to be determined from the
Boundary-Scan Register while the Bypass Register is selected as the serial path between TDi and TDO. While the CLAMP
instruction is selected, the signals driven from the component pins will not change.1
HiGHZ
The optional HiGHZ instruction places the component in a state in which all of its system logic outputs are placed in a high
impedance state. in this state, an in-circuit test system may drive signals onto the connections normally driven by a component
output without incurring a risk of damage to the component. This makes it possible to use a board where not all of the
components are compatible with the iEEE 1149.1 standard.1
1Following the use of this instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied.
Therefore, the on-chip system logic may need to be reset on return to normal (i.e., non-test) operation.
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BYPASS
The Bypass Register contains a single shift-register stage and is used to provide a minimum-length serial path (one TCK clock
period) between TDi and TDO to bypass the device when no test operation is required.
14.2 Boundary-Scan Register Cell Order
All inputs and outputs are observed in the Boundary-Scan Register cells. All outputs are additionally driven by the contents of
Boundary-Scan Register cells. Bidirectional pins have all three related Boundary-Scan Register cells: the input, the output, and
the control. The full boundary scan cell order is available from Microsemi Semiconductor in *.BSD file format.
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15 ENHANCED ACTIPHY POWER MANAGEMENT
in addition to the iEEE-specified power-down control bit (Mii Register 0.11), the VSC8221 implements an Enhanced ActiPHY™
power management mode. This mode enables support for power-sensitive applications by utilizing a signal-detect function that
monitors the media interface for the absence of a link to determine when to automatically power-down the PHY. The Station
Manager is in control of this mode. The PHY then ‘wakes up’ at a programmable interval and attempts to ‘wake-up’ the link
partner PHY by sending a fast link pulse (FLP) on the Media interface.
The Enhanced ActiPHY™ power management mode can be set at startup (Refer to Section 18 on page 53 and Section 19 on
page 57 for details) or at any time during normal operation by writing to Mii Register 28.6.
15.1 Operation in Enhanced ActiPHY Mode
There are three PHY operating states when Enhanced ActiPHYTM mode is enabled:
• Low power state
• LP Wake up state
• Normal operating state (link up state)
The PHY switches between the low power state and LP wake up state at a programmable rate (sleep timer) until signal energy
has been detected on the media interface pins. When signal energy is detected, the PHY enters the normal operating state.
When the PHY is in the normal operating state and link is lost, the PHY returns to the low power state after the link status
timeout timer has expired. After reset, the PHY enters the low power state.
When auto-negotiation is enabled in the PHY, the ActiPHYTM state machine will operate as described above. if auto-negotiation
is disabled and the link is forced to 10BT or 100BTX mode while the PHY is in the low power state, the PHY continues to
transition between the low power and LP wakeup states until signal energy is detected on the media pins. At that time, the PHY
transitions to the normal operating state and stays in that state even when the link is dropped. if auto-negotiation is disabled
while the PHY is in the normal operation state, the PHY stays in that state when the link is dropped and does not transition back
to the low power state.
Low Power State
Signal Energy Detect on
Media (CAT5 or Fiber)
FLP Sent
Sleep timer Expires
Timeout timer expires after
link has been dropped and
auto-negotiation is enabled.
LP Wake-up State
Normal Operation
Figure 16. Enhanced ActiPHY State Diagram
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15.2 Low-Power State
in the low-power state, all major digital blocks are powered down. However the following functionality is provided:
• SMi interface (MDC/MODDEF1, MDiO/MODDEF2, MDiNT)
• CLKOUT and CLKOUTMiCRO
in this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of the low power state and
transitions to the Normal operating state when signal energy is detected on the media. This happens when the PHY is
connected to one of the following:
• Auto-negotiation capable link partner
• Auto-negotiation incapable (blind/forced) 100BTX only link partner
• Auto-negotiation incapable (blind/forced) 10BT only link partner
• Another PHY in enhanced ActiPHY LP wakeup state
in the absence of signal energy on the media pins, the PHY will transition from the low power state to the LP Wake up state
periodically based on the programmable sleep timer. Two register bits (Mii Register bits 28.1:0) are provided to program the
value of the sleep timer. The sleep timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec), or 2'b11 (4sec). The
default value is 2 seconds. The actual sleep time duration is randomized by -80ms to +60ms to prevent two PHYs in Enhanced
ActiPHY mode from entering a lock-up state.
15.3 LP Wake-Up State
in this state, the PHY attempts to wake up the link partner. One complete FLP (Fast link Pulse) is sent on both pairs A and B of
the CAT5 media. in this state, the following functionality is provided:
• SMi interface (MDC/MODDEF1, MDiO/MODDEF2, MDiNT)
• CLKOUT and CLKOUTMiCRO
After sending signal energy on the relevant media, the PHY returns to the Low power state.
15.4 Normal Operating State
in this state, the PHY establishes a link with a link partner. When the media is unplugged or the link partner is powered down,
the PHY waits for the duration programmed through a link status timeout timer and then enters the low power state. The Link
Status Timeout timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec) or 2'b11 (4sec). The default value for this
timer is 2 seconds.
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16 ETHERNET IN-LINE POWERED DEVICE SUPPORT
16.1 Cisco in-Line Powered Device Detection Mode
Used to detect in-line powered devices and devices that derive power from CAT-5 cable for their operation in Ethernet network
applications, the VSC8221 device's in-line powered device detection mode can be part of a system that allows iP-phones and
other devices to receive power from an Ethernet cable, similar to office digital phones receiving power from a PBX (Private
Branch Exchange) office switch via the phone cable. This can eliminate the need for an iP-Phone to have an external power
supply, since the Ethernet cable provides power. it also enables the in-line powered device to remain active during a power
outage (assuming the Ethernet switch is connected to an uninterrupted power supply, battery, back-up power generator, etc.).
This mode is disabled by default and must be enabled in order to perform in-line powered device detection. Please refer to http:/
/www.cisco.com/en/US/products/hw/phones/ps379/products_tech_note09186a00801189b5.shtml for additional information.
16.2 in-Line Power Ethernet Switch Diagram
Processor
Gigabit Switch/MAC
MAC
Interface
Control
SMI
VSC8221
10/100/
IN-LINE
POWER
SUPPLY
UNIT
1000BT PHY
X-former
RJ-45
I/F
CAT-5
Figure 17. in-line Powered Ethernet Switch Diagram
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16.3 in-Line Powered Device Detection (Cisco Method)
This section describes the flow process an Ethernet switch must perform in order to process in-line power requests made by a
link partner (LP) capable of receiving in-line power.
1. The in-line powered device detection mode is enabled by setting Mii Register bit 23E.10 = 1 and ensuring that the
Auto-Negotiation Enable Bit is set (Mii Register 0.12 = 1). An interrupt can also be asserted on the MDiNT pin when in-
line power is needed. This is set by Mii Register 25.9 = 1 and ensuring Mii Register 25.15 = 1 in order to enable the
MDiNT pin.
2. The PHY will then start sending a special Fast Link Pulse (FLP) signal to the LP. Mii Register 23E.9:8 will equal 00
during the search for devices needing in-line power.
3. The PHY monitors for the special FLP signal looped back by the LP. An LP device capable of receiving in-line power
will loopback the special FLP pulses when it is in a powered-down state. This is reported when Mii Register 23E.9:8 =
01. if enabled, an interrupt on the MDiNT pin will also be asserted. This can be verified as an in-line power detection
interrupt by reading Mii Register 26.9 = 1, which will subsequently be cleared and the interrupt de-asserted after the
read. if an LP device does not loopback the special FLP after a specific time, then Mii Register 23E.9:8 = 10.
4. if the PHY reports that the LP needs in-line power, then the Ethernet switch needs to enable in-line power to this port
external of the PHY.
5. The PHY automatically disables in-line powered device detection after Event #3 above and now changes to the normal
Auto-negotiation process. A link is then auto-negotiated and established when the link status register is set (Mii Regis-
ter bit 1.2 = 1).
6. in a link down event (Mii Register bit 1.2 = 0), the in-line power should be disabled to the in-line powered device exter-
nal of the PHY. The PHY will disable the normal auto-negotiation process and re-enable in-line powered device detec-
tion mode.
16.4 iEEE 802.3af (DTE Power via MDi)
The VSC8221 is fully compatible with switch designs used in systems that supply power to DTE (Data Terminal Equipment) by
means of a MDi (Media Dependent interface, or twisted pair cable), as specified by iEEE 802.3af standard (Clause 33).
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17 ADVANCED TEST MODES
17.1 Ethernet Packet Generator (EPG)
For system-level debugging and in-system production testing, the VSC8221 includes an Ethernet packet generator. This can be
used to isolate problems between the MAC and PHY and between a local PHY and remote link partner. it is intended for use
with lab testing equipment or in-system test equipment only, and should not be used when the VSC8221 is connected to a live
network.
To use the EPG, it must be enabled by writing a “1” to Mii Register 29E.15. This effectively disables all MAC-interface transmit
pins and selects the EPG as the source for all data transmitted onto the VSC8221 media interface. For this reason, packet loss
will occur if the EPG is enabled during transmission of packets from MAC to PHY. The MAC receive pins will still be active when
the EPG is enabled, however. if it is necessary to disable the MAC receive pins as well, this can be done by writing a “1” to MII
Register bit 0.10.
When a “1” is written to MII Register Bit 29E.14, the VSC8221 will begin transmitting iEEE802.3 layer-2 compliant packets with
a data pattern of repeating 16-bit words as specified in MII Register 30E. The source and destination addresses for each
packet, packet size, interpacket gap, FCS state and transmit duration can all be controlled through Mii Register 29E. Note that if
MII Register Bit 29E.13 is cleared, MII Register Bit 29E.14 will be cleared automatically after 30,000,000 packets have been
transmitted.
17.2 CRC Counter
When the EPG is enabled, a bad-CRC counter is also available for all incoming packets. This counter is available in MII
Register Bits 23E.7:0 - CRC Counter and is automatically cleared when read.
17.3 Far-End Loopback
Far-end loopback mode, when enabled (Mii Register bit 23.3 = 1), forces incoming data from a link partner on the media
interface to be retransmitted back to the link partner on the media interface as shown in the figure below. in addition, the
incoming data will also appear on the receive data pins (RDP/RDN) of the MAC interface. Data present on the transmit pins of
the MAC interface are ignored in this mode. For more information, please refer to MII Register 23 (Extended PHY Control
Register #1).
Link Partner
VSC8221
RX
RDP/RDN
TDP/TDN
CAT-5 or Fiber
Serial
MAC
TX
Figure 18. Far-end Loopback Block Diagram
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17.4 Near-End Loopback
When Near-end loopback is set (Mii Register bit 0.14 = 1), the Transmit Data (TDP/TDN) on the MAC interface is looped back
onto the Receive Data (RDP/RDN) pins to the MAC as shown in the figure below. in this mode, the CAT-5 media link is dropped.
Link Partner
VSC8221
RX
CAT-5 or Fiber
RDP/RDN
TDP/TDN
Serial
MAC
TX
Figure 19. Near-end Loopback Block Diagram
17.5 Connector Loopback
Connector Loopback allows for the twisted pair interface to be looped back externally. in this mode the PHY must be connected
to a loopback connector or a loopback cable. For this loopback, pair A should be connected to the corresponding wire of pair B
using a 100Ω resistor, and each wire of pair C should be connected to the corresponding wire of pair D using a 100Ω resistor.
This loopback will work in all speeds selected for the interface.
VSC8221
A
B
RDP/RDN
TDP/TDN
Serial
MAC
C
D
Figure 20. Connector Loopback
The auto-negotiation, speed, and duplex can be configured using Mii registers 0,4 and 9. For 1000BT connector loopback only
the following additional writes are required in the specific order.
1. Master/Slave configuration forced to Master (Mii Register Bits 9.12:11 = 11)
2. Enable 1000BT connector loopback (Mii Register 24.0 = 1)
3. Disable pair swap correction (Mii Register Bit 18.5=1)
4. Disable auto-negotiation and force 1000BT link (Mii Register Bit 0.12=0, Mii Register Bit 0.6=1, and Mii Register Bit 0.12=0)
and force either full or half duplex (Mii Register Bit 0.8=0 or 1).
This loopback is also available in the 100BASE-FX mode.
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18 HARDWARE CONFIGURATION USING CMODE PINS
Each of the four CMODE pins (CMODE[3:0]) are used to latch a four bit value at PHY reset. A total of sixteen CMODE
configuration bits are set at reset. Each CMODE bit represents the default value of a particular PHY register bit and therefore
sets a default PHY operating condition at startup.
18.1 Setting the CMODE Configuration Bits
The CMODE bits are set by connecting each CMODE pin to either VDD33A or VSS (ground) through an external 1% resistor.
The four bit value latched by the PHY on each CMODE pin depends upon the value of the resistor used to pull-up or pull-down
the CMODE pin. CMODE resistor values and connections are defined in the following table:
Table 25. CMODE Pull-up/Pull-down Resistor Values
CMODE
CMODE
CMODE
CMODE
CMODE
Tied to
bit 3 value
bit 2 value
bit 1 value
bit 0 value
Resistor Value
VDD33A or GND
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
GND
GND
GND
GND
2.26k
4.02k
5.90k
0
1
0
8.25k
GND
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
12.1k
16.9k
22.6k
0
GND
GND
GND
VDD33A
VDD33A
VDD33A
VDD33A
VDD33A
VDD33A
VDD33A
VDD33A
2.26k
4.02k
5.90k
8.25k
12.1k
16.9k
22.6k
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18.2 CMODE Bit Descriptions
The following table outlines the mapping of each CMODE bit to a PHY operating condition parameter. Each of the PHY
operating condition parameters is described in detail in Table 27: “PHY Operating Condition Parameter Description”.
Table 26. CMODE Bit to PHY Operating Condition Parameter Mapping
CMODE Pin Name
‘CMODE Bit’ to ‘PHY Operating Condition Parameter’ Mapping
Bit 3
Bit 2
Bit 1
Bit 0
CMODE0
CMODE1
PHY Address[3]
PHY Address[2]
PHY Address[1]
PHY Address[0]
SerDes Line imped-
ance
SFP Mode Disable
PHY Address[4]
SiGDET pin direction
PHY Operating
Mode[3]
PHY Operating
Mode[2]
PHY Operating
Mode[1]
PHY Operating
Mode[0]
CMODE2
CMODE3
Auto-negotiation
Advertisement Con-
trol[1]
LED Control[1]
SQE Enable
Reserved
Each of the PHY Operating Condition Parameters mentioned in Table 26 above is described in detail in Table 27.
Table 27. PHY Operating Condition Parameter Description
PHY Operating
Condition Parame-
ter Name
CMODE Pin Name and
Value
Description
Bit Position
31-0
Sets the PHY Address used to access PHY Registers when the
PHY’s SMi is in iEEE mode. The value latched is reflected in
Extended Mii Register 23.15:11.
CMODE1[2],
CMODE0[3:0]
PHY Address[4:0]
These CMODE bits set the default PHY Operating Mode by setting the
default values of Mii Register 23.15:12,2:1.
0000
802.3z SerDes to CAT5 Media, Clause 37 auto-negotiation
auto-sense enabled.
0100
0101
1010
1110
1111
802.3z SerDes to CAT5 Media, Clause 37 disabled.
SGMii to CAT5 Media, SCLK enabled.
PHY Operating
Mode[3:0]
CMODE2[3:0]
802.3z SerDes to CAT5 Media, Media Connector Mode.
802.3z SerDes to CAT5 Media, Clause 37 enabled.
SGMii to CAT5 Media, SCLK disabled.
This sets the default behavior of LED pins LED[2:0] by setting the startup
values of MII Register Bit Register 27 (1Bh) – LED Control Register.
0
LED[2:0] = {Link10/Activity, Link100/Activity, Link1000/Activity}
(Mii Reg 27 = 0000h)
LED Control[1]
CMODE3[3]
1
LED[2:0] = {Link/Activity, Link/Activity, Fault}
(Mii Reg 27 = AA80h)
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Table 27. PHY Operating Condition Parameter Description (continued)
PHY Operating
Condition Parame-
ter Name
CMODE Pin Name and
Value
Description
Bit Position
These CMODE bits set the default auto-negotiation advertisement
defaults by setting the defaults of Mii Registers 4 and 9.
Auto-negotiation
Advertisement
Control[1]
CMODE3[0]
0
1
10/100/1000BASE-T HDX, FDX
10/100BASE-T HDX, FDX
This CMODE bit sets the default value of Mii Register 21E.15 .
This sets Mii Register 21E.15 = 1.
0
Sets the following PHY defaults:
• TXDiS/SRESET is active high i.e. behaves like TXDiS.
• MODDEF0/CLKOUT pin functions like MODDEF0 i.e this pin
is asserted low by the PHY once the EEPROM inter-
face is released for access through the SMi interface.
• RXLOS/SiGDET pins functions like the RXLOS.
• The SMi interface is set in MSA mode.
SFP Mode Disable
CMODE1[3]
This sets Mii Register 21E.15 = 0.
1
Sets the following PHY defaults:
• TXDiS/SRESET is active low i.e. behaves like SRESET.
• MODDEF0/CLKOUT pin functions like CLKOUT i.e this pin
drive out a 125Mhz clock.
• RXLOS/SiGDET pin functions like the SiGDET.
• The SMi interface is set in iEEE mode
The value of this bit is valid in non-SFP mode when CMODE bit
CMODE1[3] is 1. This CMODE bit set the direction of the SiGDET pin by
setting the default value of Extended Mii Register 19E.1
SiGDET pin direction CMODE1[1]
0
1
input
Output
Sets the internal end termination resistance value of the Serial MAC/
Media interface input pins.
SerDes Line
CMODE1[0]
impedance
0
1
50 Ω
75Ω
Sets the default value of Mii Register 22.12.
SQE Enable
CMODE3[2]
0
1
SQE Disabled (Mii Register 22.12=1)
SQE Enabled (Mii Register 22.12=0)
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18.3 Procedure for Selecting CMODE Pin Pull-Up/Pull-Down Resistor Values
1. Using the descriptions in Table 27 column D (“Description”), choose the desired PHY operating condition parameter
values from column C (“Value”).
2. Using Table 27 Column B (“CMODE Pin Name and Bit Position”) and the chosen PHY operating condition parameter
values, enter the value of each CMODE bit in Table 26: “CMODE Bit to PHY Operating Condition Parameter Mapping”.
3. Choose the value of each CMODE pull-up or pull-down resistor from Table 25: “CMODE Pull-up/Pull-down Resistor
Values” based on the CMODE Bit values in Table 26.
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19 EEPROM INTERFACE
The EEPROM interface consists of the EEDAT and EECLK pins of the PHY. if this interface is used, these pins should connect
to the SDA and SCL pins respectively of a serial EEPROM that is compatible with the AT24xxx series of ATMEL EEPROMs.
The EEPROM interface on the VSC8221 serves the following purposes:
• it provides the PHY with the ability to self configure its internal registers.
• The system manager can access the EEPROM to obtain information pertaining to the system/module configuration.
• A single EEPROM can be shared among multiple PHYs for their custom configuration.
The PHY detects the EEPROM based on the presence of a pullup on the EEDAT pin. it is initialized using the configuration
EEPROM (if present) under the following conditions:
• RESET deassertion.
• TXDiS/SRESET deassertion and Extended Mii Register 21E.14 is set.
• S/W reset (Mii Register 0.15) is asserted and Extended Mii Register 21E.14 is set.
if an EEPROM is present, the start-up control block looks for a “Microsemi Header” (value:16’hBDBD’) at address 0 and 1 of the
EEPROM. The address is incremented by 256 until the Microsemi Header is found. if the Microsemi Header is not found, or no
EEPROM is connected, the VSC8221 bypasses the EEPROM read step.
Once the Microsemi header is located, the EEPROM interface block of the PHY searches for its PHY address in bit position 7:3
in the subsequent EEPROM location. Once the PHY address is located, the 11 bit EEPROM address location for the start of the
configuration script is read. At this point, the PHY begins reading from this 11 bit EEPROM address and initializes its Register
values based on the EEPROM configuration script contents. Refer to Table 28: “Configuration EEPROM Data Format” for
details on the configuration EEPROM data format.
The total number of EEPROM bytes needed for a configuration script is equal to:
((Number of Register writes) * 3 + 2 (BDBD) + 2 (PHY address and Configuration Script Address) + 2 (Length of configuration
script)).
Data is read from the EEPROM sequentially (at 50 Khz, or 50 kbits/s) until all PHY registers are set. Once all of the PHY
registers are set, the PHY enters the ‘NORMAL STATE’. For more information, see Section 20 on page 61.
if the PHY is in the ‘NORMAL STATE’ state, the user can access the EEPROM connected to the EEPROM interface through the
SMi. if the SMi is in iEEE mode, the EEPROM can be accessed via the SMi using Extended Mii Registers 21E and 22E. if the
SMi is in MSA mode, the EEPROM can be accessed directly via the SMi i.e. the PHY behaves as if the MODDEF2 and
MODDEEF1 pins of the SMi are directly connected to the EEDAT and EECLK pins of the PHY.1
One exception is the memory portion with device/page address ‘110’. This is reserved for the PHY Register access when the
PHY’s SMi is set in MSA mode.
if an EEPROM is present, but the EEPROM does not acknowledge (according to the ATMEL EEPROM protocol), the VSC8221
waits for an acknowledgement for approximately 3 seconds. if there is no acknowledgement within 3 seconds, the VSC8221 will
abort and continue into normal operation.
19.1 Programming Multiple VSC8221s Using the Same EEPROM
To prevent contention on the 2 wire bus when multiple PHYs use the same EEPROM for initialization, the EEPROM start-up
block of each VSC8221 monitors the bus for (PHY Address[4:0] + 1) * 9 + 92 clock cycles for no bus activity and only then
attempts to access the EEPROM bus. PhyAddress[4:0] is chosen because these are the PHY Address bits that are unique to
each VSC8221 (that is, VSC8221 with lowest PHY Address gets priority in this bus).
1EEPROM memory with device address ‘110’ cannot be accessed directly when the SMi is in MSA mode. This device address is reserved for
PHY Register access in MSA mode. To access an EEPROM with device address ‘110’ in MSA mode, Extended Mii Registers 21E and 22E
should be used.
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.
REFCLK
Source
RESET
Source
VSC8221
(1)
VSC8221
(2)
SCL
SDA
EEPROM
Figure 21. EEPROM interface Connections
NOTE: The same clock must be used for each VSC8221's REFCLK input. in addition, the RESET pin for each VSC8221 must
be driven from the same source to ensure that the reference clock modes within each device are correctly set.
This prevents using the CLKOUT or CLKOUTMiCRO output from one VSC8221 to drive the clock input of another VSC8221, if
the devices are sharing the same EEPROM.
Table 28. Configuration EEPROM Data Format
Address
-------------
-------------
-------------
-------------
O+7
Contents
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
Data to be written (LSB)
O+6
Data to be written (MSB)
O+5
RegAddress b
O+4
Data to be written (LSB)
O+3
Data to be written (MSB)
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Table 28. Configuration EEPROM Data Format (continued)
Address
O+2
Contents
RegAddress a
O+1
Number of PHY Register writes *3[7:0]
Number of PHY Register writes *3[15:8]
{bpage_ad-
dr3,s_addr3} = O
-------------
-------------
-------------
-------------
M+7
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
Data to be written (LSB)
M+6
Data to be written (MSB)
M+5
RegAddress b
M+4
Data to be written (LSB)
M+3
Data to be written (MSB)
M+2
RegAddress a
M+1
Number of PHY Register writes *3[7:0]
{bpage_ad-
dr2,s_addr2} = M
Number of PHY Register writes *3[15:8]
-------------
N+7
----------------------------------------------------
Data to be written (LSB)
Data to be written (MSB)
RegAddress b
N+6
N+5
N+4
Data to be written (LSB)
Data to be written (MSB)
RegAddress a
N+3
N+2
N+1
Number of PHY Register writes *3[7:0]
{bpage_ad-
dr1,s_addr1} = N
Number of PHY Register writes *3[15:8]
-------------
7,263,519,..
6,262,518,..
5,261,517,..
4,260,516,..
3,259,515,..
----------------------------------------------------
Starting address for initializing PHY3 s_addr3
{PHY Address 1[4:0], 3’bpage_addr3}
Starting address for initializing PHY2 s_addr2
{PHY Address 2[4:0], 3’bpage_addr2}
Starting address for initializing PHY1 s_addr1
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Table 28. Configuration EEPROM Data Format (continued)
Address
2,258,514,..
1,257,513..
0,256,512...
Contents
{PHY Address 1[4:0], 3’bpage_addr1}
8’hBD
8’hBD
Using the EEPROM Data Format of Table 28 enables multiple PHYs to be initialized in a similar way by reading the same
locations from the EEPROM. if the PHYs have to be initialized differently, then the 'Address pointers' will differ for each PHY,
along with different PHY configuration data values.
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20 PHY STARTUP AND INITIALIZATION
The PHY Startup and initialization sequence is detailed in the flowchart below.
A
Start - 3.3v supply is up
B
N
Drive out CLKOUT and CLKOUTMICRO if
enabled during Initialzation.
C
If RESETz=1
Y
N
Y
If REGEN=1
N
N
Is external 1.2v
supply up
1. Turn on on-chip
Is TXDIS/SRESETz deasserted
(The assertion polarity is based on
setting of Extended MII register
21E.15, which can be initialized
using Hardware or EEPROM
Initialization)
regulator and wait for
1.2v supply to come up.
Is REFCLK
input present
Y
Y
Latch EEDAT,PLLMODE,OSCDISz and MDINTz
polarity using internally generated rising edge
Y
1.Perfom Hardware Initialization - i.e. overwrite
default PHY Register values based on resister
values on CMODE[3:0]
2.Store startup CMODE initialization values
3. Set Internal variable SR=0.
If SR=1
Y
If EEDAT=1
If MII Register 22.9 ‘Sticky Reset Enable’=0
(On RESETz deassertion this bit will be set to 1)
Y
Perform EEPROM Initialization - i.e. overwrite
default PHY Register values using configuration
EEPROM data
Y
N
1.Perfom Initialization - i.e. overwrite
default PHY Register values based on stored
CMODE values.
N
A
N
If Extended MII Register 21E.14 ‘Reread
EEPROM on s/w reset’=1
(On RESETz deassertion this bit will be set to 0)
Y
NORMAL STATE
Start - 3.3v supply is up
If EEDAT=1
N
N
Y
Is TXDIS/
SRESETz
asserted
If RESETz=0
N
N
Perform EEPROM Initialization - i.e. overwrite
default PHY Register values using configuration
EEPROM data
Y
B
Y
SR=1
NORMAL STATE
C
1. Enter Normal Operating Mode
2. Release SMI for user access.
Figure 22. PHY Startup and initialization Sequence
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21 PHY OPERATING MODES
The PHY Operating Mode is set according to the value of Mii Register 23.15:12,23.2:1. For more information, see Section 18 on
page 53 and Section 19 on page 57 for details on PHY Operating Mode configuration at startup. The following table summarizes
the PHY operating modes.
Table 29. PHY Operating Modes
Mii
Operating
Mode
Category
Register CMODE2
23.15:12,
23.2:1
MAC
interface
Media
interface
Other Settings
[3:0]
802.3z Ser-
Des
1111, 00
1110, 01
1110, 10
1110, 00
0100
CAT5
Clause 37 disabled
802.3z Ser-
Des
1110
1010
0000
CAT5
CAT5
CAT5
Clause 37 enabled
802.3z Ser-
Des
Clause 37 enabled, Media Convertor Mode
With Clause 37 Auto-Negotiation Detection
Serial MAC
PHY Oper-
ating Modes
802.3z Ser-
Des
1010, 01 1111
1000, 01 0101
SGMii
SGMii
CAT5
CAT5
625Mhz SCLK Clock Disabled
625MHz SCLK Clock Enabled
Modified Clause 37 auto-negotiation disabled,
625MHz SCLK Clock Enabled
1001, 00
1011, 00
SGMii
SGMii
CAT5
CAT5
Modified Clause 37 auto-negotiation disabled,
625MHz SCLK Clock Disabled
Note: For more information about VSC8221 operating modes, see Designing a Copper SFP using the VSC8221 application
note available on the Microsemi Web site.
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22 PHY REGISTER SET CONVENTIONS
The user can control the PHY's features, operating modes, etc. by setting the PHY Registers to the desired values. The PHY
provides access to its Registers using the Serial Management interface. For details on PHY Register access, refer to Section 12
on page 33.
22.1 PHY Register Set Structure
The register access protocol, as defined by the iEEE 802.3 specification, reserves 5 bits for register addressing. This limits the
register space to 32, 16 bit wide registers. Of these, registers addressed 0 through 15 are defined by the iEEE 802.3
specification and registers addressed 16 through 31 are vendor specific. To provide extensive feature control of the PHY, the
vendor specific registers addressed 16 through 31 have been divided into two Page views, called PAGE0 and PAGE1, enabling
access to 32 vendor specific registers instead of 16.
PAGE0 is the default page view. To switch to PAGE1 write 0001 to PHY Register 31. To switch to PAGE0 write 0000h to PHY
Register 31.
Normal Page
Registers
0
1
2
3
.
.
.
.
.
.
.
Extended Page
Registers
15
16
16E
17
17E
18
18E
19
19E
.
.
.
.
.
.
.
.
.
.
.
.
.
.
30
30E
0000
0001
31
Figure 23. Extended Page Register Diagram
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22.2 PHY Register Set Nomenclature
Table 30. Register Set Nomenclature
Register Address
Page View
- NA-
Naming Convention
Mii Register
0-15
16-31
PAGE0
Mii Register
Extended Page Mii Register (Referred to with
an ‘E’ after the register number e.g. 20E.15 is
Page 1 Register 20 bit 15)
16-31
PAGE1
22.3 PHY Register Bit types
PHY Register bit types are defined in the table below:
Table 31. PHY Register Bit Types
Register Bit Type
Description
R/W
RO
Read and Write, effective immediately
Read Only (must be written ‘0’, unless specified otherwise)
Read Only, Self Clears after Read
Latched High, Clears after Read
Latched Low, Clears after Read
Self-Cleared
RO SC
LH
LL
SC
Read and Write, effective after s/w reset. This register will read the new value only
after s/w reset.
RWSW
“Sticky” refers to the behavior of the register bit(s) after a software reset. if an “S” appears in the sticky column, the
corresponding bit(s) will retain their values after a software reset, as long as Mii Register bit 22.9 - Sticky Reset Enable is set.
if an “SS” appears in the sticky column, the corresponding bit(s) will retain their values after a software reset, regardless of the
state of Mii Register bit 22.9 - Sticky Reset Enable.
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23 PHY REGISTER SET
23.1 PHY Register Names and Addresses
Table 32. PHY Register Names and Addresses
Register Name
Register Address
Register Number
(hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Mode Control
0
Mode Status
1
PHY identifier Register # 1
PHY identifier Register # 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next-Page Transmit
Auto-Negotiation Link Partner Next Page Receive
1000BASE-T Control
1000BASE-T Status Register # 1
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Reserved
Reserved
Reserved
1000BASE-T Status Register #2
Reserved
Reserved
Bypass Control
12
13
14
15
16
17
18
19
1A
1B
1C
Reserved
Reserved
Reserved
Control & Status
PHY Control # 1
PHY Control # 2
interrupt Mask
interrupt Status
LED Control
Auxiliary Control & Status
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Table 32. PHY Register Names and Addresses (continued)
Register Address
Register Name
Register Number
(hex)
1D
1E
1F
10
Reserved
29
MAC interface Clause 37 Auto-negotiation Control & Status
30
Extended Page Access
Reserved
31
16E
17E
18E
19E
20E
21E
22E
23E
24E
25E
26E
27E
28E
29E
30E
SerDes Control #2
11
Reserved
12
SerDes Control Register # 2
Extended PHY Control # 3
EEPROM interface Status and Control
EEPROM Data Read/Write
Extended PHY Control # 4
Reserved
13
14
15
16
17
18
Reserved
19
Reserved
1A
1B
1C
1D
1E
Reserved
Reserved
1000BASE-T Ethernet Packet Generator (EPG) # 1
1000BASE-T Ethernet Packet Generator (EPG) # 2
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23.2 Mii Register Descriptions
23.2.1 Register 0 (00h) – Mode Control Register
Register 0 (00h) – Mode Control Register
Bit
Name
Access States
Reset Value
Sticky
1 = Reset asserted
0 = Reset de-asserted
1 = Loopback on
Software Reset1
15
R/W SC
R/W
0
14
Near End Loopback
0
0 = Loopback off
00 = 10Mbps
01 = 100Mbps
10 = 1000Mbps
6, 13 Forced Speed Selection
R/W
10
11 = Reserved
1 = Auto-negotiation enabled
0 = Auto-negotiation disabled
1 = Power-down
12
11
10
9
Auto-Negotiation Enable
R/W
1
0
0
0
Power-Down2
isolate
R/W
0 = Power-up
1 = Disable MAC outputs
0 = Normal Operation
1 = Restart Mii
0 = Normal operation
1 = Full duplex
R/W
Restart Auto-Negotiation
Duplex Mode
R/W SC
8
R/W
RO
0
0 = Half duplex
7
Reserved
0
MSB for Speed Selection
(see bit 13 above)
Reserved
6
See “Forced Speed Selection” Above
1
5:0
000000
1
2
in MSA mode, when this bit is set, the PHY does not return the correct values for the subsequent register read operations. in order to read the correct PHY register
values, the station manager must provide 70 clock cycles on the MODDEF1/MDC pin or perform two byte read operations on any eeprom address other than in
page ‘110’ immediately following s/w reset.
The status of the Link Status bit, Mii Register 1.2, remains unchanged when this bit is set.
0.15 – Software Reset
Writing a “1” to bit 0.15 initiates a software reset. Once Software Reset is asserted, the PHY is returned to normal operating
mode and is ready for the next SMi transaction, so Software Reset always reads back “0”. Software Reset restores all SMi
registers to their default states, except for registers marked with an “S” or “SS” in the sticky column.
0.14 – Near End Loopback
When Near End Loopback is asserted, the Transmit Data (TXD) on the MAC interface is looped back as Receive Data (RXD). in
loopback mode, no signal is transmitted over the network media. The loopback mechanism works in all (10/100/1000) modes of
operation. The operating mode is determined by bits 0.13 and 0.6 (forced speed selection).
0.13, 0.6 – Forced Speed Selection
These bits determine the 10/100/1000 speed when auto-negotiation is disabled by clearing control bit 0.12. These bits are
ignored if control bit 0.12 is set. These bits also determine the operating mode when Near End Loopback (0.14) is set to “1”.
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0.12 – Auto-Negotiation Enable
After a power-up or reset, the PHY automatically activates the auto-negotiation state machine, setting bit 0.12 to a “1”. if a “0” is
written to bit 0.12, the auto-negotiation process is disabled and the present contents of the PHY’s SMi register bits determine
the operating characteristics. Note that auto-negotiation is always required in 1000BASE-T mode.
0.11 – Power-Down
Power-Down functions the same as Software Reset, except that it is not self-clearing, and that R/W SMi bits are not restored to
their default states by Power-Down. The RGMii pins (except for SMi pins MDC, MDiO, and MDiNT#) are electrically isolated
during power-down. After Power-Down is released (i.e., set to “0”), the PHY will be ready for normal operation before the next
SMi transaction. if auto-negotiation is enabled, the PHY will begin auto-negotiation immediately upon exiting Power-Down.
0.10 – isolate1
When isolate is asserted (i.e., set to “1”), all Serial MAC outputs (except for MDiO) will be high impedance. Operation of the
PHY is otherwise unaffected. For example, if isolate is asserted while CAT5 auto-negotiation is under way, auto-negotiation will
continue unaffected.
0.9 – Restart Auto-Negotiation
When restart auto-negotiation is asserted (i.e., set to “1”), the auto-negotiation state machine will restart the auto-negotiation
process, even if it is in the midst of an auto-negotiation process. This control bit is self-clearing, meaning that it will always return
a “0” when read.
0.8 – Duplex Mode
Bit 0.8 determines the duplex mode of the VSC8221 when auto-negotiation is disabled. Changes to the state of Duplex Mode
while auto-negotiation is enabled are ignored.
0.7 – Reserved
0.5:0 – Reserved
1When set, while the PHY’s SerDes side auto-negotiation function is enabled, the PHY will drop the CAT5 link. Also, setting of this bit does not
disable the output clock on the SCLKP and SCLKN pins.
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23.2.2 Register 1 (01h) – Mode Status Register
Register 1 (01h) – Mode Status Register
Bit
15
14
13
12
11
10
9
Name
Access States
Reset Value Sticky
100BASE-T4 Capability
100BASE-X FDX Capability
100BASE-X HDX Capability
10BASE-T FDX Capability
10BASE-T HDX Capability
100BASE-T2 FDX Capability
100BASE-T2 HDX Capability
Extended Status Enable
Reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
1 = 100BASE-T4 capable
0
1
1
1
1
0
0
1 = 100BASE-X FDX capable
1 = 100BASE-X HDX capable
1 = 10BASE-T FDX capable
1 = 10BASE-T HDX capable
1 = 100BASE-T2 FDX capable
1 = 100BASE-T2 HDX capable
8
7
1 = Extended status information present in R15 1
0
1 = MF preamble may be suppressed
0 = MF preamble always required
1 = Auto-negotiation complete
0 = Auto-negotiation not complete
6
5
Preamble Suppression Capability RO
1
Auto-Negotiation Complete
RO
0
1 = Far-end fault detected
0 = No fault detected
1 = Auto-negotiation capable
1 = Link is up
0 = Link is down
4
3
2
Remote Fault
RO LH
RO
0
Auto-Negotiation Capability
Link Status1
1
0
RO LL
1 = Jabber condition detected
0 = No jabber condition detected
1 = Extended register capable
1
0
Jabber Detect
RO LH
RO
0
1
Extended Capability
1
The status of this bit remains unchanged when the PHY is put in Power Down mode by setting Mii Register 0.11 or by asserting the TXDiS/SRESET pin.
1.15 – 100BASE-T4 Capability
The VSC8221 is not 100BASE-T4 capable, so this bit is hard-wired to “0”.
1.14 – 100BASE-X FDX Capability
The VSC8221 is 100BASE-X FDX capable, so this bit is hard-wired to “1”.
1.13 – 100BASE-X HDX Capability
The VSC8221 is 100BASE-X HDX capable, so this bit is hard-wired to “1”.
1.12 – 10BASE-T FDX Capability
The VSC8221 is 10BASE-T FDX capable, so this bit is hard-wired to “1”.
1.11 – 10BASE-T HDX Capability
The VSC8221 is 10BASE-T HDX capable, so this bit is hard-wired to “1”.
1.10 – 100BASE-T2 FDX Capability
The VSC8221 is not 100BASE-T2 FDX capable, so this bit is hard-wired to “0”.
1.9 – 100BASE-T2 HDX Capability
The VSC8221 is not 100BASE-T2 HDX capable, so this bit is hard-wired to “0”.
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1.8 – Extended Status Enable
The VSC8221 is extended status capable, so this bit is hard-wired to “1”.
1.7 – Reserved
1.6 – Preamble Suppression Capability
The VSC8221 accepts management frames on the SMi without preambles, so preamble suppression capability is hard-wired to
“1”. The management frame preamble may be as short as 1 bit.
1.5 – Auto-Negotiation Complete
When this bit is a “1”, the contents of Registers 4, 5, 6, 10 and 28 are valid.
1.4 – Remote Fault
Bit 1.4 will be set to “1” if the Link Partner signals a far-end fault. The bit is cleared automatically upon a read if the far-end fault
condition has been removed.
1.3 – Auto-Negotiation Capability
The VSC8221 is auto-negotiation capable, so this bit is hard-wired to “1”. Note that this bit will read a “1” even if auto-negotiation
is disabled via bit 0.12.
1.2 – Link Status
This bit will return a “1” when the VSC8221 link state machine has reached the “link pass” state, meaning that a valid link has
been established. if the link is subsequently lost, the Link Status will revert to a “0” state. it will remain a “0” until Link Status is
read while the link state machine is in the “link pass” state.
1.1 – Jabber Detect
Note that Jabber Detect is required for 10BASE-T mode only. Jabber Detect will be set to “1” when the jabber condition is
detected. Jabber Detect will be cleared automatically when this register is read.
1.0 – Extended Capability
The VSC8221 has extended register capability, so this bit is hard-wired to “1”.
23.2.3 Register 2 (02h) – PHY identifier Register #1
Register 2 (02h) – PHY identifier Register #1
Bit
Name
Access States
Reset Value
0000000000001111
or
Sticky
OUi most significant bits
(Microsemi OUi bits 3:18)
15:0 Organizationally Unique identifier RO
(000Fh)
2.15:0 – PHY identifier Register #1
Microsemi has been assigned an OUi from the iEEE of 0003F1h. Per iEEE requirements, only OUi bits 3 to 18 are used in this
register.
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23.2.4 Register 3 (03h) – PHY identifier Register #2
Register 3 (03h) – PHY identifier Register #2
Bit
Name
Access States
Reset Value
110001
Sticky
OUi least significant bits
15:10 Organizationally Unique identifier RO
(Microsemi OUi bits 19:24)
Vendor’s model number (iC)
Vendor’s revision number (iC)
9:4
3:0
Vendor Model Number
Vendor Revision Number
RO
RO
010101 = VSC8221
0001 = Silicon Revision C
3.15:10 – OUi
Microsemi has been assigned an OUi from the iEEE of 0003F1h. Per iEEE requirements, only OUi bits 19 to 24 are used in this
register.
3.9:4 - Vendor Model Number
The Model no. of this iC is ‘010101’.
3.3:0 - Vendor Revision Number
The current Revision Number of this iC is ‘0001’.
23.2.5 Register 4 (04h) – Auto-Negotiation Advertisement Register
Register 4 (04h) – Auto-Negotiation Advertisement Register
Bit
15
14
13
12
11
10
9
Name
Access States
Reset Value
0
0
0
Sticky
Next-Page Transmission Request R/W
Reserved
Transmit Remote Fault
Reserved
Advertise Asymmetric Pause
Advertise Symmetric Pause
1 = Next-Page transmission request
RO
R/W
RO
1 = Transmit remote fault
0
R/W
R/W
1 = Advertise Asymmetric Pause capable
1 = Advertise Symmetric Pause capable
1 = 100BASE-T4 capable
CMODE
CMODE
0
Advertise 100BASE-T4 Capability R/W
8
7
6
5
Advertise 100BASE-TX FDX
Advertise 100BASE-TX HDX
Advertise 10BASE-T FDX
Advertise 10BASE-T HDX
Advertise Selector Field
R/W
R/W
R/W
R/W
R/W
1 = 100BASE-TX FDX capable
1 = 100BASE-TX HDX capable
1 = 10BASE-T FDX capable
CMODE
CMODE
CMODE
CMODE
00001
1 = 10BASE-T HDX capable
4:0
This register controls the advertised abilities of the local (not remote) PHY. The state of this register is latched when the auto-
negotiation state machine enters the ABiLiTY_DETECT state. Thus, any writes to this register prior to completion of auto-
negotiation as indicated by Mii Register bit 1.5 should be followed by a re-negotiation for the new values to be properly used for
auto-negotiation. Once auto-negotiation has completed, this register value may be read via the SMi to determine the highest
common denominator technology.
4.15 – Auto-Negotiation Additional Next-Page Transmission Request
The VSC8221 supports additional Next-Page transmission through Mii Register bit 4.15. See description of Mii Register bit 18.1
for more details on Next-Page exchanges.
4.14, 4.12 – Reserved
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4.13 – Transmit Remote Fault
This bit is used by the local MAC to communicate a fault condition to the link partner during auto-negotiation. This bit does not
have any effect on the local PHY operation. This bit is automatically cleared following a successful negotiation with the Link
Partner. Note that iEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit.
This discrepancy is handled in Mii Extended register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 - Remote Fault
Mapping OR.
4.11 – Advertise Asymmetric Pause Capability
This bit is used by the local MAC to communicate Asymmetric Pause Capability to the link partner during auto-negotiation. This
has no effect on PHY operation. Changing this bit in Clause-28 view will also change bit 4.8 in Clause-37 view.
4.10 – Advertise Symmetric Pause Capability
This bit is used by the local MAC to communicate Symmetric Pause Capability to the link partner during auto-negotiation. This
has no effect on PHY operation. Changing this bit in Clause-28 view will also change bit 4.9 in Clause-37 view.
4.9:5 – Advertise Capability
Bits 4.9:5 allow the user to customize the ability information transmitted to the Link Partner during auto-negotiation. By writing a
“1” to any of these bits, the corresponding ability will be advertised to the Link Partner. Writing a “0” to any bit causes the
corresponding ability to be suppressed from transmission. The state of these bits has no other effect on the operation of the
local PHY. Resetting the chip restores the default bit values. Note that the default values of these bits indicate the true ability of
the VSC8221. These bits are not available for read or write in Clause-37 view.
4.4:0 – Advertise Selector Field
Since the VSC8221 is a member of the 802.3 class of PHYs, the Advertise Selector Field defaults to “00001”. These bits are
R/W because the Ethernet standard requires them to be R/W. Changing the value of these bits has no effect on PHY operation.
23.2.6 Register 5 (05h) – Auto-Negotiation Link Partner Ability Register
Register 5 (05h) – Auto-Negotiation Link Partner Ability Register
Bit Name
Access States
Reset Value Sticky
15 LP Next-Page Transmit Request
14 LP Acknowledge
13 LP Remote Fault
12 Reserved
11 LP Asymmetric Pause Capability
10 LP Symmetric Pause Capability
RO
RO
RO
RO
RO
RO
1 = LP NP transmit request
1 = LP acknowledge
1 = LP remote fault
0
0
0
0
1 = LP Advertise Asymmetric Pause capable 0
1 = LP Advertise Symmetric Pause capable
1 = LP Advertise 100BASE-T4 capable
1 = LP 100BASE-TX FDX capable
1 = LP 100BASE-TX HDX capable
1 = LP 10BASE-T FDX capable
0
0
0
0
0
0
9
8
7
6
5
LP Advertise 100BASE-T4 Capability RO
LP Advertise 100BASE-TX FDX
LP Advertise 100BASE-TX HDX
LP Advertise 10BASE-T FDX
LP Advertise 100BASE-T HDX
RO
RO
RO
RO
RO
1 = LP 100BASE-T HDX capable
LP Advertise Selector Field
4:0 LP Advertise Selector Field
00000
5.15 – LP Next-Page Transmit Request
Bit 5.15 returns a “1” when the Link Partner implements the Next-Page function and has Next-Page information it wants to
transmit. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) or the Page Received bit (6.1) is set.
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5.14 – LP Acknowledge
Bit 5.14 returns a “1” when the Link Partner signals that it has successfully received the Link Code Word from the local PHY. The
local PHY uses this bit for proper Link Code Word exchange, as defined in Clause 28 of iEEE 802.3.
5.13 – LP Remote Fault
Bit 5.13 returns a “1” when the Link Partner signals that a remote fault (from its perspective) has occurred. The local PHY does
not otherwise use this bit. Note that iEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single
remote fault bit. This difference is handled in Extended Mii register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 -
Remote Fault Mapping OR. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.
5.12 – Reserved
5.11 – LP Asymmetric Pause Capability
The LP Asymmetric Pause Capability bit indicates whether the Link Partner has asymmetric pause capability. The state of this
bit is valid when the Auto-Negotiation Complete bit (1.5) is set.
5.10 – LP Symmetric Pause Capability
The LP Symmetric Pause Capability bit indicates whether the Link Partner supports symmetric pause frame capability. This bit
is used by the Link Partner’s MAC to communicate symmetric pause capability to the local MAC. it has no effect on PHY
operation. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.
5.9:5 – LP Advertise Capability
Bits 5.9:5 reflect the abilities of the Link Partner. A “1” on any of these bits indicates that the Link Partner advertises capability of
performing the corresponding mode of operation. These bits are not available for read in Clause-37 view, but remain valid for
CAT-5 copper media and can be viewed by switching to Clause-28 view.
5.4:0 – LP Advertise Selector Field
Bits 5.4:0 indicate the state of the Link Partner’s Selector Field. The local PHY does not otherwise use these bits.
23.2.7 Register 6 (06h) – Auto-Negotiation Expansion Register
Register 6 (06h) – Auto-Negotiation Expansion Register
Bit
Name
Access
RO
States
Reset Value
00000000000
Sticky
15:5 Reserved
4
3
2
1
0
Parallel Detection Fault
LP Next-Page Able
Local PHY Next-Page Able
Page Received
LP Auto-Negotiation Able
RO LH
RO
RO
RO LH
RO
1 = Parallel detection fault
1 = LP Next-Page capable
1 = Next-Page capable
1 = New page has been received
1 = LP auto-negotiation capable
0
0
1
0
0
6.15:5 – Reserved
6.4 – Parallel Detection Fault
Parallel Detection Fault returns a “1” when a parallel detection fault occurs in the local auto-negotiation state machine. Once
set, this bit is automatically cleared when (and only when) Register 6 is read.
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6.3 – LP Next-Page Able
LP Next-Page Able returns a “1” when the Link Partner has Next-Page capabilities. This bit is used in the auto-negotiation state
machines, as defined in Clause 28 of iEEE 802.3. The state of this bit is valid when either the Auto-Negotiation Complete bit
(1.5) or the Page Received bit (6.1) is set.
6.2 – Local PHY Next-Page Able
Since the VSC8221 is next-page capable during Clause-28 auto-negotiation, this bit is hard-wired to “1”.
6.1 – Page Received
Page Received is set to “1” when a new Link Code Word is received from the Link Partner, validated, and acknowledged. Page
Received is automatically cleared when (and only when) Register 6 is read via the SMi.
6.0 – LP Auto-Negotiation Able
LP Auto-Negotiation Able is set to “1” if the Link Partner advertises auto-negotiation capability. The state of this bit is valid when
the Auto-Negotiation Complete bit (1.5) or the Page Received bit (6.1) is set.
23.2.8 Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register
Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register
Bit
15
14
13
Name
Access States
Reset Value
Sticky
1 = More pages follow
0 = Last page
Next Page
Reserved
Message Page
R/W
RO
0
0
1
1 = Message page
0 = Unformatted page
R/W
1 = Will comply with request
0 = Cannot comply with request
1 = Previous transmitted LCW == 0
0 = Previous transmitted LCW == 1
12
11
Acknowledge2
Toggle
R/W
0
RO
0
10:0 Message/Unformatted Code
R/W
00000000001
7.15 – Next Page
The Next Page bit indicates whether this is the last Next-Page to be transmitted. By default, this bit is set to “0”, indicating that
this is the last page.
7.14 – Reserved
7.13 – Message Page
The Message Page bit indicates whether this page is a message page or an unformatted page. This bit does not otherwise
affect the operation of the local PHY. By default, this bit is set to “1”, indicating that this is a message page.
7.12 – Acknowledge2
The Acknowledge2 bit indicates if the local MAC reports that it is able to act on the information (or perform the task) indicated in
the previous message. The local PHY does not interpret or act on changes in the state of this bit.
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7.11 – Toggle
The Toggle bit is used by the arbitration function in the local PHY to ensure synchronization with the Link Partner during Next-
Page exchanges. The Toggle bit is automatically set to the opposite state of the Toggle bit in the previously exchanged Link
Code Word.
7.10:0 – Message/Unformatted Code
The Message/Unformatted Code bits indicate the message code being transmitted to the Link Partner. The local PHY passes
the message code to the Link Partner without interpreting or reacting to it. By default, this code is set to “000 0000 0001”,
indicating a null message.
23.2.9 Register 8 (08h) – Auto-Negotiation Link Partner Next-Page Receive Register
Register 8 (08h) – Auto-Negotiation Link Partner Next-Page Receive Register
Bit
15
14
13
12
11
Name
Access States
1 = More pages follow
Reset Value
Sticky
LP Next Page
LP Acknowledge
LP Message Page
LP Acknowledge2
LP Toggle
RO
RO
RO
RO
RO
RO
0
0 = Last page
1 = LP acknowledge
1 = Message page
0 = Unformatted page
1 = LP will comply with request
1 = Previous transmitted LCW == 0
0 = Previous transmitted LCW == 1
0
0
0
0
10:0 LP Message/Unformatted Code
00000000000
SMi Register 8 contains the Link Partner’s Next-Page register contents. The contents of this register are only valid when the
Page Received bit (6.1) is set.
8.15 – LP Next Page
This bit indicates if more pages follow from the Link Partner.
8.14 – LP Acknowledge
This bit returns a “1” when the Link Partner signals that it has received the Link Code Word from the local PHY. The local PHY
uses this bit for proper Link Code Word exchange, as defined in Clause 28 of iEEE 802.3.
8.13 – LP Message Page
The Message Page bit indicates if the page received from the Link Partner is a message page or an unformatted page.
8.12 – LP Acknowledge2
The Acknowledge2 bit indicates whether the Link Partner MAC reports that it is able to act on the information (or perform the
task) indicated in the message. The local PHY does not interpret or act on changes in the state of this bit.
8.11 – LP Toggle
The Toggle bit is used by the arbitration function in the local PHY to ensure synchronization with the Link Partner during Next-
Page exchanges. in the Link Partner, the Toggle bit is automatically set to the opposite state of the Toggle bit in the previously
exchanged Link Code Word from the Link Partner.
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8.10:0 – LP Message/Unformatted Code
The Message/Unformatted Code bits indicate the message code being transmitted by the Link Partner.
23.2.10 Register 9 (09h) – 1000BASE-T Control Register
Register 9 (09h) – 1000BASE-T Control Register
Acces
Bit
Name
States
Reset Value Sticky
s
15:13 Transmitter Test Mode
R/W
Described below, per iEEE 802.3, 40.6.1.1.2
1 = Enable MASTER/SLAVE Manual Configu-
ration value
0 = Disable MASTER/SLAVE Manual Configu-
ration value
000
MASTER/SLAVE Manual
12
R/W
0
Configuration Enable
1 = Configure PHY as MASTER during MAS-
TER/SLAVE negotiation, only when bit 9.12 is
set to logical one.
0 = Configure PHY as SLAVE during MASTER/
SLAVE negotiation, only when bit 9.12 is set to
logical one.
MASTER/SLAVE Manual
Configuration Value
11
R/W
R/W
0
0
1 = Multi-port device
0 = Single-port device
10
Port Type
9
8
7:0
1000BASE-T FDX Capability
1000BASE-T HDX Capability
Reserved
R/W
R/W
R/W
1 = PHY is 1000BASE-T FDX capable
1 = PHY is 1000BASE-T HDX capable
CMODE
CMODE
00000000
9.15:13 – Transmitter/Receiver Test Mode1
This test is valid only in 1000BASE-T mode. Refer to iEEE 802.3-2002, section 40.6.1.1.2 for more information.
Bit 1
Bit 2
Bit 3
Test Mode
(9.15) (9.14) (9.13)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal operation
Test Mode 1 – Transmit waveform test
Test Mode 2 – Transmit jitter test in MASTER mode
Test Mode 3 – Transmit jitter test in SLAVE mode
Test Mode 4 – Transmitter distortion test
Reserved; operation not defined
Reserved; operation not defined
Reserved; operation not defined
• Test Mode 1: The PHY repeatedly transmits the following sequence of data symbols from all four transmitters: {{"+2"
followed by 127 "0" symbols}, {"-2" followed by 127 "0" symbols}, {"+1" followed by 127 "0" symbols}, {"-1" followed by
127 "0" symbols}, {128 "+2" symbols, 128 "-2" symbols, 128 "+2" symbols, 128 "-2" symbols}, {1024 "0" symbols}}. The
transmitter should use a 125.00 MHz ± 0.01% clock and should operate in MASTER timing mode.
1The state of this register is internally latched when the auto-negotiation state machine enters the ABiLiTY_DETECT state. Changes to the
states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.
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• Test Mode 2: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should
use a 125.00 MHz ± 0.01% clock in the MASTER timing mode.
• Test Mode 3: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should
use a 125.00 MHz ± 0.01% clock and should operate in SLAVE timing mode.
• Test Mode 4: The PHY transmits the sequence of symbols generated by the following scrambler generator polynomial,
bit generation, and level mappings:
The maximum-length shift register used to generate the sequences defined by this polynomial is updated once per
symbol interval (8ns). The bits stored in the shift register delay line at a particular time n are denoted by Scrn[10:0]. At
each symbol period, the shift register is advanced by one bit, and one new bit represented by Scrn[0] is generated. Bits
Scrn[8] and Scrn[10] are exclusive-OR'd together to generate the next Scrn[0] bit. The bit sequences, x0n, x1n, and x2n,
generated from combinations of the scrambler bits as shown in the following equations, shall be used to generate the
quinary symbols, sn, as shown in the following table. The transmitter should use a 125.00 MHz ± 0.01% clock and should
operate in MASTER timing mode.
x2n
x1n
x0n
Quinary Symbol, sn
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
-1
0
1
-2
-1
9.12 – MASTER/SLAVE Manual Configuration Enable1
When this bit is set to “0” (default), the MASTER/SLAVE designation of the local PHY is determined using the arbitration
protocol established in the iEEE Ethernet standard. When this bit is set to “1”, the MASTER/SLAVE designation of the local PHY
is set by bit 9.11. Note that MASTER/SLAVE configuration is valid only in 1000BASE-T mode.
9.11 – MASTER/SLAVE Configuration Value1
This bit is ignored when bit 9.12 is set to “0”. However, if bit 9.12 is set to “1”, bit 9.11 determines the MASTER/SLAVE
designation of the local PHY. if bit 9.12 is set to “1” and bit 9.11 set to “0” (default), the local PHY is forced to be a SLAVE. if bit
9.12 is set to “1” and bit 9.11 set to “1”, the local PHY is forced to be a MASTER. Note that MASTER/SLAVE configuration is
valid only in 1000BASE-T mode.
9.10 – Port Type1
Since the VSC8221 is a single port physical layer transceiver, bit 9.10 is set to “0” by default. When set to “0”, this bit indicates a
preference for operation as a SLAVE. if the Link Partner does not indicate the same preference, the local PHY will operate as a
SLAVE, and the Link Partner will be a MASTER. Otherwise, the normal MASTER/SLAVE assignment protocol is used.
1The state of this register is internally latched when the auto-negotiation state machine enters the ABiLiTY_DETECT state. Changes to the
states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.
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9.9 – 1000BASE-T FDX1
Since the VSC8221 is 1000BASE-T FDX capable, this bit is “1” by default. if bit 9.9 is written to be “0”, the auto-negotiation state
machine for the local PHY will be blocked from advertising 1000BASE-T FDX. Note that the Link Partner will be notified of the
state of bit 9.9 during auto-negotiation. After auto-negotiation is complete, changing the state of this bit has no effect unless
auto-negotiation is manually restarted.
9.8 – 1000BASE-T HDX1
Since the VSC8221 is 1000BASE-T HDX capable, this bit is “1” by default. if bit 9.8 is written to be “0”, the auto-negotiation state
machine for the local PHY will be blocked from advertising 1000BASE-T HDX. Note that the Link Partner will be notified of the
state of bit 9.8 during auto-negotiation. After auto-negotiation is complete, changing the state of this bit has no effect unless
auto-negotiation is manually restarted.
9.7:0 – Reserved
23.2.11 Register 10 (0Ah) – 1000BASE-T Status Register #1
Register 10 (0Ah) – 1000BASE-T Status Register #1
Bit Name
Access
States
Reset Value Sticky
1 = MASTER/SLAVE configuration fault detected
RO LH SC 0 = No MASTER/SLAVE configuration fault
detected
MASTER/SLAVE Configuration
Fault
15
14
0
MASTER/SLAVE Configuration
Resolution
1 = Local PHY configuration resolved to MASTER
0 = Local PHY configuration resolved to SLAVE
1 = Local receiver OK
(loc_rcvr_status == OK)
0 = Local receiver not OK
(loc_rcvr_status == NOT_OK)
1 = Remote receiver OK
(rem_rcvr_status == OK)
0 = Remote receiver not OK
RO
1
0
13 Local Receiver Status
12 Remote Receiver Status
RO
RO
0
(rem_rcvr_status == NOT_OK)
1 = LP 1000BASE-T FDX capable
11 LP 1000BASE-T FDX Capability RO
10 LP 1000BASE-T HDX Capability RO
0
0
0 = LP not 1000BASE-T FDX capable
1 = LP is 1000BASE-T HDX capable
0 = LP is not 1000BASE-T HDX capable
9:8 Reserved
RO
00
7:0 idle Error Count
RO SC
00000000
10.15 – MASTER/SLAVE Configuration Fault2
This bit indicates whether a MASTER/SLAVE configuration fault has been detected by the local PHY. A configuration fault
occurs if both the local and remote PHYs are forced to the same MASTER/SLAVE state, or if no resolution is reached after
seven retries. When such a fault has been detected, this bit is set to “1”, but the PHY continues to renegotiate until the
MASTER/SLAVE configuration is resolved. Once set, this bit is automatically cleared when (and only when) Register 10 is read
via the SMi.
1The state of this register is internally latched when the auto-negotiation state machine enters the ABiLiTY_DETECT state. Changes to the
states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode.
2This bit is valid only when the Page Received bit (6.1) is set to a “1” and if Mii Register bit 9.9 or 9.8 is set.
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10.14 – MASTER/SLAVE Configuration Resolution1
By default, the MASTER/SLAVE configuration is determined as part of the auto-negotiation process. However, the MASTER/
SLAVE status can optionally be manually forced via bits in Mii Register 9. Bit 10.14 indicates the final MASTER/SLAVE
configuration status for the local PHY. This bit can change state only as a result of the reset or subsequent restart of the auto-
negotiation process. This bit is only valid when the Auto-Negotiation Complete bit (1.5) is set.
10.13 – Local Receiver Status1
Bit 10.13 indicates the state of the loc_rcvr_status flag within the PMA receive function within the local PHY.
10.12 – Remote Receiver Status1
Bit 10.12 indicates the state of the rem_rcvr_status flag within the PMA receive function within the local PHY.
10.11 – LP 1000BASE-T FDX Capability1
Bit 10.11 is set to “1” if the Link Partner PHY advertises 1000BASE-T FDX capability. Otherwise, this bit is set to “0”. The state
of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.
10.10 – LP 1000BASE-T HDX Capability1
Bit 10.10 is set to “1” if the Link Partner PHY advertises 1000BASE-T HDX capability. Otherwise, this bit is set to “0”. The state
of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set.
10.9:8 – Reserved
10.7:0 – idle Error Count1
Bits 10.7:0 indicate the idle Error count, where 10.7 is the most significant bit. These bits contain a cumulative count of the
errors detected when the receiver is receiving idles and PMA_TXMODE.indicate is equal to SEND_N (indicating that both the
local and remote receiver status have been detected to be OK). The counter is incremented every symbol period that
rx_error_status in the PMA receive function is equal to ERROR. Bits 10.7:0 are reset to all “0”s when the error count is read by
the management function, or upon execution of the PCS reset function, and they are saturated to all “1”s in case of overflow.
23.2.12 Register 11 (0Bh) – Reserved Register
Register 11 (0Bh) – Reserved Register
Bit
Name
Access States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
11.15:0 – Reserved
1This bit is valid only when the Page Received bit (6.1) is set to a “1” and if Mii Register bit 9.9 or 9.8 is set.
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23.2.13 Register 12 (0Ch) – Reserved Register
Register 12 (0Ch) – Reserved Register
Bit
Name
Access States
RO
Reset Value
00000000 00000000
Sticky
Sticky
Sticky
Sticky
15:0 Reserved
12.15:0 – Reserved
23.2.14 Register 13 (0Dh) – Reserved Register
Register 13 (0Dh) – Reserved Register
Bit
Name
Access
States
Reset Value
00000000 00000000
15:0 Reserved
RO
13.15:0 – Reserved
23.2.15 Register 14 (0Eh) – Reserved Register
Register 14 (0Eh) – Reserved Register
Bit
Name
Access
States
Reset Value
00000000 00000000
15:0 Reserved
RO
14.15:0 – Reserved
23.2.16 Register 15 (0Fh) – 1000BASE-T Status Register #2
Register 15 (0Fh) – 1000BASE-T Status Register #2
Bit
Name
Access States
Reset Value
1 = PHY is 1000BASE-X FDX capable
0 = PHY is not 1000BASE-X FDX capable
15
1000BASE-X FDX Capability
RO
RO
RO
0
1 = PHY is 1000BASE-X HDX capable
0 = PHY is not 1000BASE-X HDX capable
1 = PHY is 1000BASE-T FDX capable
0 = PHY is not 1000BASE-T FDX capable
1 = PHY is 1000BASE-T HDX capable
0 = PHY is not 1000BASE-T HDX capable
14
13
12
1000BASE-X HDX Capability
1000BASE-T FDX Capability
1000BASE-T HDX Capability
0
1
RO
RO
1
11:0 Reserved
0000 00000000
15.15 – 1000BASE-X FDX Capability
The VSC8221 is not 1000BASE-X capable, so this bit is hard-wired to “0”.
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15.14 – 1000BASE-X HDX Capability
The VSC8221 is not 1000BASE-X capable, so this bit is hard-wired to “0”.
15.13 – 1000BASE-T FDX Capability
The VSC8221 is 1000BASE-T FDX capable, so this bit is hard-wired to “1”.
15.12 – 1000BASE-T HDX Capability
The VSC8221 is 1000BASE-T HDX capable, so this bit is hard-wired to “1”.
15.11:0 – Reserved
23.2.17 Register 16 (10h) – Reserved
Register 16 (10h) – Reserved Register
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
16.15:0 – Reserved
23.2.18 Register 17 (11h) – Reserved
Register 17 (11h) – Reserved Register
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
17.15:0 – Reserved
23.2.19 Register 18 (12h) – Bypass Control Register
Register 18 (12h) – Bypass Control Register
Reset
Value
0
Bit
15
14
Name
Access States
Sticky
Reserved
RO
1 = Bypass 4B5B encoder/decoder
0 = Enable 4B5B encoder/decoder
1 = Bypass scrambler
Bypass 4B5B Encoder/Decoder
R/W
R/W
0
0
13
Bypass Scrambler
0 = Enable scrambler
1 = Bypass descrambler
0 = Enable descrambler
12
Bypass Descrambler
Reserved
R/W
RO
0
11:9
000
1 = Enable internal TXCLK test output on CLK-
OUTMiCRO pin
0 = Disable internal TXCLK test output on CLK-
OUTMiCRO pin
8
Transmitter Test Clock Enable
R/W
0
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Register 18 (12h) – Bypass Control Register
Reset
Value
01
Bit
7:6
5
Name
Access States
Sticky
Reserved
Disable Automatic Pair Swap Cor-
rection
RO
1=Disable
0=Enable
1=Disable
0=Enable
R/W
R/W
0
0
4
Disable Polarity inversion
1 = Do not ignore advertised ability
0 = ignore advertised ability
3
2
Parallel-Detect Control
Reserved
R/W
RO
1
0
S
1 = Disable automatic 1000BASE-T Next-Page
exchanges
0 = Enable automatic 1000BASE-T Next-Page
exchanges
1 = Enable output clock pins CLKOUT
0 = Disable output clock pins CLKOUT
Disable Automatic 1000BASE-T
Next-Page Exchange
1
0
R/W
R/W
0
1
S
S
CLKOUT Output Enable
18.15 – Reserved
18.14 – Bypass 4B5B Encoder/Decoder 1
When bit 18.14 is set to “1”, the 5B codes (TXER and TXD[3:0]) will be passed from the Mii interface directly to the scrambler,
bypassing the 4B5B encoder. Note that in this mode, J/K and T/R code insertion will not be performed. The receiver will pass
descrambled/aligned 5B codes directly to the Mii interface (RXER and RXD[3:0]), bypassing the 4B5B decoder. Carrier sense
(CRS) is still asserted when a valid frame is detected.
18.13 – Bypass Scrambler2
When bit 18.13 is set to “1”, the scrambler is disabled.
18.12 – Bypass Descrambler2
When bit 18.12 is set to “1”, the descrambler is disabled.
18.11:9 – Reserved
18.8 – Transmitter Test Clock Enable
When a “1” is written to bit 18.8, the CLKOUTMiCRO output pin becomes a test pin for the transmit clock “TXCLK”. This
capability is intended to enable measurement of transmitter timing jitter, as specified in iEEE Standard 802.3-2002, section
40.6.1.2.5. When in iEEE-specified transmitter test modes 2 or 3 (see iEEE 802.3-2002, section 40.6.1.1.2 and Mii Register bits
9.15:13), the peak-to-peak jitter of the zero-crossings of the differential signal output at the MDi, relative to the corresponding
edge of TXCLK, is measured. The corresponding edge of TXCLK is the edge of the transmit test clock, in polarity and time, that
generates the zero-crossing transition being measured.
While transmitter test mode clock TXCLK is intended only for characterization test purposes, CLKOUTMiCRO is intended to
serve as a general purpose system or MAC reference clock.
18.7:6 – Reserved
1This bit applies only in 100BASE-TX mode.
2This bit applies only in 100BASE-TX and 1000BASE-T modes.
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18.5 - Disable Automatic Pair Swap Correction
When set to ‘1’, the automatic pair swap correction feature of the PHY is disabled.
18.4 - Disable Polarity inversion
When set to ‘1’, the automatic polarity inversion feature of the PHY is disabled.
18.3 – Parallel-Detect Control
When bit 18.3 is “1”, Mii Register 4, bits [8:5], are taken into account when attempting to parallel-detect. This is the default
behavior expected by the standard. Setting 18.3 to a “0” will result in auto-negotiation ignoring the advertised abilities, as
specified in Mii Register 4, during parallel detection of a non-auto-negotiating 10BASE-T or 100BASE-TX PHY.
18.2 – Reserved
18.1 – Disable Automatic 1000BASE-T Next-Page Exchanges
Bit 18.1 is used to control the automatic exchange of 1000BASE-T Next-Pages defined in iEEE 802.3-2002 (Annex 40C). When
this bit is set, the automatic exchange of these pages is disabled, and the control is returned to the user through the SMi after
the base page has been exchanged. You then have the complete responsibility to both of the following:
• Send the correct sequence of Next-Pages to the Link Partner.
• Determine common capabilities and force the device into the correct configuration following successful exchange of
pages.
When bit 18.1 is reset to “0”, the 1000BASE-T related Next-Pages are automatically exchanged without user intervention. if the
Next Page bit 4.15 was set by the user in the Auto-Negotiation Advertisement register at the time the auto-negotiation was
restarted, control is returned to the user for additional Next-Pages following the 1000BASE-T Next-Page exchange.
if both bit 18.1 and Mii Register bit 4.15 are reset when an auto-negotiation sequence is initiated, all Next-Page exchange is
automatic, including sourcing of null pages. No user notification is provided until either auto-negotiation completes or fails. See
the description of Mii Register bit 4.15 for more details on standard Next-Page exchanges.
18.0 – CLKOUT Output Enable
When bit 18.0 is set to “1”, the VSC8221 provides a 125MHz clock on the CLKOUT output pin. The electrical specification for
this clock corresponds to the current settings for VDDiO. This clock is for use by the MAC, system manager CPU, or control
logic. By default, this pin is enabled, which enables the clock output independent of the status of any link, unless the hardware
reset is active (which also powers down the PLL). When disabled, the clock pins are normally driven low.
23.2.20 Register 19 (13h) – Reserved
Register 19 (13h) – Reserved
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
19.15:0 - Reserved
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23.2.21 Register 20 (14h) – Reserved
Register 20 (14h) – Reserved
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
20.15:0 – Reserved
23.2.22 Register 21 (15h) – Reserved
Register 21 (15h) – Reserved
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
21.15:0 – Reserved
23.2.23 Register 22 (16h) – Control & Status Register
Register 22 (16h) – Control & Status Register
Name Access States
Disable Link integrity State Machine R/W
Reset
Value
Bit
Sticky
1 = Disable link integrity test
0 = Enable link integrity test
1 = Disable jabber detect
0 = Enable jabber detect
15
0
S
S
14
13
12
Disable jabber Detect
Reserved
R/W
RO
0
0
1=Disable SQE Transmit
0=Enable SQQ Transmit
SQE Disable Mode
R/W
CMODE
S
S
00 = Normal squelch
01 = Low squelch
10 = High squelch
11 = Reserved
11:10 10BASE-T Squelch Control
R/W
R/W
00
1 = All bits marked as sticky will retain their
values during software reset
0 = All bits marked as sticky will be changed to
default values during software reset
1 = EOF error detected since last read
0 = EOF error not detected since last read
1 = 10BASE-T link disconnected
0 = 10BASE-T link connected
1 = 10BASE-T link active
9
Sticky Reset Enable
1
SS
8
7
EOF Error
RO SC
RO SC
0
0
10BASE-T Disconnect State
6
10BASE-T Link Status
Reserved
RO
RO
0
0 = 10BASE-T link inactive
5:0
000000
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22.15 – Disable Link-integrity State Machine1
When bit 22.15 is set to “0”, the VSC8221 link integrity state machine runs automatically. When bit 22.15 is set to “1”, the link
integrity state machine is bypassed and the PHY is forced into link pass status.
22.14 – Disable Jabber Detect1
When bit 22.14 is set to “0”, the VSC8221 automatically shuts off the transmitter when a transmission request exceeds the
iEEE-specified time limit. When bit 22.14 is set to “1”, transmission requests are allowed to be arbitrarily long without shutting
down the transmitter.
22.13 – Reserved
22.12 – SQE Disable Mode2
When bit 22.12 is set to “1”, SQE (Signal Quality Error) pulses are not sent. Note that this control bit applies in 10BASE-T HDX
mode only.
22.11:10 – 10BASE-T Squelch Control2
When bits 22.11:10 are set to “00”, the VSC8221 uses the squelch threshold levels prescribed by the iEEE’s 10BASE-T
specification. When bits 22.11:10 are set to “01”, the squelch level is decreased, which may improve the bit error rate
performance on long loops. When bits 22.11:10 are set to “10”, the squelch level is increased, which may improve the bit error
rate in high-noise environments.
22.9 - Sticky Reset Enable
When bit 22.9 is set, all Mii register bits that are marked with an “S” in the “sticky” column will retain their values during a
software reset. When cleared, all Mii register bits that are marked with an “S” in the “sticky” column will be changed to their
default values during a software reset. Note that bits marked with an “SS” retain their values across software reset regardless of
the setting of bit 22.9.
22.8 – EOF Error2
When bit 22.8 returns a “1”, a defective EOF (End-of-Frame) sequence has been received since the last time this bit was read.
This bit is automatically set to “0” when it is read.
22.7 – 10BASE-T Disconnect State
Bit 22.7 is set to “1” if the 10BASE-T connection has been broken by the carrier integrity monitor since the last read of this bit.
Otherwise, this bit is set to “0”.
22.6 – 10BASE-T Link Status
Bit 22.6 is set to “1” if the 10BASE-T link is active. Otherwise, this bit is set to “0”.
22.5:0 – Reserved
1This bit applies only in 10BASE-T mode.
2This bit applies only in 10BASE-T HDX mode.
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23.2.24 Register 23 (17h) – PHY Control Register #1
Register 23 (17h) – PHY Control Register #1
Reset
Value
Bit
Name
Access States
Sticky
15:12 MAC/Media interface Mode Select RWSW See Table 33 below
CMODE
Reserved1
Far End (Media-Side) Loopback
Enable
11:4
3
RO
1010 0010
1 = Far End (Media side) loopback is enabled
0 = Far End (Media side) loopback is disabled
R/W
0
2:1
MAC/Media interface Mode Select RWSW See Table 33 below
1 = EEPROM is detected on EEPROM interface
CMODE
0
EEPROM Status
RO
0 = EEPROM is not detected on EEPROM inter- 0
face
1
Writes to Mii Register 23 must preserve the value of bits 11:4, i.e., all writes to Mii Register 23 must be in the format xA2xh.
23.15:12, 2:1– MAC/Media interface Mode Select
Bits 23.15:12 and 23.2:1 are used to select the MAC interface modes and media interface modes. The reset value for these bits
is dependent upon the state of the MAC interface bits in the CMODE hardware configuration. All combinations of these bits not
indicated below are reserved:
Table 33. PHY Operating Modes
Mii
Operating
Mode
Category
Register CMODE2
23.15:12,
23.2:1
MAC
interface
Media interface
Other Settings
[3:0]
802.3z Ser-
Des
1111,00
1110, 01
1110,10
1110,00
0100
CAT5
Clause 37 disabled
802.3z Ser-
Des
1110
1010
0000
CAT5
CAT5
CAT5
Clause 37 enabled
802.3z Ser-
Des
Clause 37 enabled, Media Convertor Mode
With Clause 37 Auto-Negotiation Detection
Serial MAC
PHY Oper-
ating Modes
802.3z Ser-
Des
1010,01
1000,01
1111
SGMii
SGMii
CAT5
CAT5
625Mhz SCLK Clock Disabled
625MHz SCLK Clock Enabled
0101
Modified Clause 37 Auto-Negotiation disabled,
625MHz SCLK Clock Enabled
1001,00
1011,00
SGMii
SGMii
CAT5
CAT5
Modified Clause 37 Auto-Negotiation disabled,
625MHz SCLK Clock Disabled
Note: For more information about VSC8221 operating modes, see Designing a Copper SFP using the VSC8221 application
note available on the Microsemi Web site.
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23.11:4 – Reserved
Writes to Mii Register 23 must preserve the value of bits 11:4, i.e., all writes to Mii Register 23 must be in the format xA2xh.
23.3 – Far End (Media-Side) Loopback Enable
When bit 23.3 is set to “1”, all incoming data from the link partner on the media interface is retransmitted back to the link partner
on the media interface. in addition, the incoming data will also appear on the RDP/RDN pins of the MAC interface. Any data
present on the TDP/TDN pins of the MAC interface is ignored by the VSC8221 when bit 23.3 is set. in order to avoid loss of
data, bit 23.3 should not be set while the VSC8221 is receiving data on the media interface. Bit 23.3 applies to all operating
modes of the VSC8221. When bit 23.3 is cleared, the VSC8221 resumes normal operation. This bit is cleared by default. Refer
to Section 17.3 on page 51.
23.0 – EEPROM Status
When bit 23.0 is set to “1”, an EEPROM has been detected on the external EEPROM interface. When cleared, bit 23.0 indicates
that no EEPROM has been detected.
23.2.25 Register 24 (18h) – PHY Control Register #2
Register 24 (18h) – PHY Control Register #2
Reset
Value
Bit
Name
Access States
Sticky
Reserved1
15:13
12
RO
111
S
S
1 = PiCMG miser mode is enabled
0 = PiCMG miser mode is disabled
Enable PiCMG Miser Mode2
R/W
RO
0
11:10 Reserved
00
000 to 010 = Reserved
011 = Jumbo packet mode
100 = iEEE mode
101 to 111 = Reserved
000 to 010 = Reserved
011 = Jumbo packet mode
100 = iEEE mode
9:7
6:4
TX FiFO Depth Control
R/W
R/W
100
100
S
S
RX FiFO Depth Control
101 to 111 = Reserved
3:1
0
Reserved
RO
000
0
1 = Active (See Section 17.3 on page 51 for
details)
Connector Loopback
R/W
0 = Disable
1
2
These bits must always be written to as ‘111’.
See Section 11 on page 32 for more information.
24.15:13 – Reserved
These bits must always be written to as ‘111’.
24.12 - Enable PiCMG Miser Mode1
Setting bit 24.12 turns off some portions of the PHY's DSP block and reduces the PHY's Operating power. This bit can be set in
order to reduce power consumption in applications where the signal to noise ratio on the CAT-5 media is high, such as ethernet
over the backplane or where the cable length is short (<10m).
1See Section 11 on page 32 for more information.
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24.11:10 - Reserved
24.9:7 – TX FiFO Depth Control1
Bits 24.9:7 control symbol buffering for the transmit synchronization FiFO used in all 1000BT modes. An internal FiFO is used to
synchronize the clock domains between the MAC transmit clock and the PHY’s clock (e.g., REFCLK), used to transmit symbols
on the local PHY’s twisted pair interface.
The iEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (iPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (iPG). When using jumbo packet
mode, a larger iPG is recommended due to the possible compression of the iPG at the output of the FiFO.
24.6:4 – RX FiFO Depth Control1
Used in 1000BT , bits 24.6:4 control symbol buffering as determined by the receive synchronization FiFO. An internal FiFO is
used to synchronize the clock domains between the MAC receive clock and the PHY’s clock (e.g., REFCLK), used to receive
symbols on the local PHY’s twisted pair interface.
The iEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (iPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (iPG). When using jumbo packet
mode, a larger iPG is recommended due to the possible compression of the iPG at the output of the FiFO.
24.3:1 – Reserved
24.0 - Connector Loopback
See Section 17.3 on page 51 for details.
23.2.26 Register 25 (19h) – interrupt Mask Register
Register 25 (19h) – interrupt Mask Register
Reset
Value
Bit
Name
Access States
Sticky
1 = Enable interrupt pin
0 = Disable interrupt pin
15
14
13
12
11
interrupt Pin Enable
Reserved
R/W
RO
0
0
0
0
0
S
1 = Enable Link State/ Energy Detect interrupt
0 = Disable Link State/ Energy Detect interrupt
Link State-Change interrupt Mask
R/W
RO
S
S
S
Reserved
Auto-Negotiation Error interrupt
Mask
1 = Enable Auto-Negotiation Error interrupt
0 = Disable Auto-Negotiation Error interrupt
1 = Enable Auto-Negotiation-Done/ interlock Done
interrupt
0 = Disable Auto-Negotiation-Done/ interlock
Done interrupt
1 = Enable inline Powered Device Detected inter-
rupt
0 = Disable inline Powered Device Detected inter-
rupt
R/W
Auto-Negotiation-Done / interlock
Done interrupt Mask
10
9
R/W
R/W
0
0
inline Powered Device Detected
interrupt Mask
S
1 = Enable Symbol Error interrupt
0 = Disable Symbol Error interrupt
1 = Enable Lock-Lost interrupt
0 = Disable Lock-Lost interrupt
8
7
Symbol Error interrupt Mask
R/W
R/W
0
0
S
S
Descrambler Lock-Lost interrupt
Mask
1The TX and RX FiFOs are not used for 10BASE-T and 100BASE-TX.
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Register 25 (19h) – interrupt Mask Register
Reset
Value
Bit
Name
Access States
Sticky
1 = Enable TX FiFO interrupt
6
TX FiFO interrupt Mask
R/W
0
S
S
0 = Disable TX FiFO interrupt
1 = Enable RX FiFO interrupt
0 = Disable RX FiFO interrupt
5
4
3
RX FiFO interrupt Mask
Reserved
R/W
RO
0
0
0
1 = Enable False Carrier interrupt
0 = Disable False Carrier interrupt
1 = Enable Cable impairment Detect interrupt
0 = Disable Cable impairment Detect interrupt
1 = Enable MASTER/SLAVE interrupt
0 = Disable MASTER/SLAVE interrupt
1 = Enable RX_ER interrupt
False Carrier interrupt Mask
R/W
S
S
S
S
Cable impairment Detect interrupt
Mask
MASTER/SLAVE Resolution Error
interrupt Mask
2
1
0
R/W
R/W
R/W
0
0
0
RXER interrupt Enable
0 = Disable RX_ER interrupt
25.15 – interrupt Pin Enable
When bit 25.15 is set to “1”, the hardware interrupt is enabled, meaning that the state of the external interrupt pin (MDiNT) can
be influenced by the state of the interrupt Status bit (26.15). When bit 25.15 is set to “0”, the interrupt status bits (Register 26)
continue to be set in response to interrupts, but the interrupt hardware pin MDiNT on the VSC8221 will not be influenced by this
particular PHY.
25.14 – Reserved
25.13 – Link State-Change interrupt Mask
When bit 25.13 is set to “1”, the Link State-Change / Energy Detect interrupt is enabled.
25.12 – Reserved
25.11 – Auto-Negotiation Error interrupt Mask
When bit 25.11 is set to “1”, the Auto-Negotiation Error interrupt is enabled.
25.10 – Auto-Negotiation-Done / interlock Done interrupt Mask
When bit 25.10 is set to “1”, the Auto-Negotiation-Done interrupt is enabled.
25.9 – inline Powered Device Detected interrupt Mask
When bit 25.9 is set to “1”, the inline Powered Device Detected interrupt is enabled.
25.8 – Symbol Error interrupt Mask
When bit 25.8 is set to “1”, the Symbol Error interrupt is enabled.
25.7 – Descrambler Lock-Lost interrupt Mask
When bit 25.7 is set to “1”, the Descrambler Lock-Lost interrupt is enabled.
25.6 – TX FiFO interrupt Mask
When bit 25.6 is set to “1”, the TX FiFO interrupt is enabled.
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25.5 – RX FiFO interrupt Mask
When bit 25.5 is set to “1”, the RX FiFO interrupt is enabled.
25.4 – Reserved
25.3 – False Carrier interrupt Mask
When bit 25.3 is set to “1”, the False Carrier interrupt is enabled.
25.2 – Cable impairment Detect interrupt Mask1
When bit 25.2 is set to “1”, the Cable impairment Detect interrupt is enabled.
25.1 – MASTER/SLAVE Resolution Error interrupt Mask
When bit 25.1 is set to “1”, the MASTER/SLAVE Resolution Error interrupt is enabled.
25.0 – RXER interrupt Enable
When bit 25.0 is set to “1”, the RXER interrupt is enabled.
23.2.27 Register 26 (1Ah) – interrupt Status Register
Register 26 (1Ah) – interrupt Status Register
Reset
Value
Bit
Name
Access States
Sticky
1 = interrupt pending
0 = No interrupt pending
15
14
13
12
11
interrupt Status
Reserved
RO SC
RO
0
0
0
0
0
1 = Link State-Change/ Energy Detect interrupt
pending
Link State-Change interrupt Status RO SC
Reserved
Auto-Negotiation Error interrupt
Status
RO
RO SC 1 = Auto-Negotiation Error interrupt pending
Auto-Negotiation-Done / interlock
Done interrupt Status
inline Powered Device Detected
interrupt Status
Symbol Error interrupt Status
Descrambler Lock-Lost interrupt
Status
1 = Auto-Negotiation-Done/ interlock Done inter-
rupt pending
1 = inline Powered Device Detected interrupt
pending
10
RO SC
0
9
8
7
RO SC
0
0
0
RO SC 1 = Symbol Error interrupt pending
RO SC 1 = Lock-Lost interrupt pending
6
5
4
3
TX FiFO interrupt Status
RX FiFO interrupt Status
Reserved
False Carrier interrupt Status
Cable impairment Detect interrupt
Status
RO SC 1 = TX FiFO interrupt pending
RO SC 1 = RX FiFO interrupt pending
RO
0
0
0
0
RO SC 1 = False Carrier interrupt pending
2
1
0
RO SC 1 = Cable impairment Detect interrupt pending
RO SC 1 = MASTER/SLAVE Error interrupt pending
0
0
0
MASTER/SLAVE Resolution inter-
rupt Status
1 = RXER interrupt pending
RO
RXER interrupt Status
0 = No RXER interrupt pending
1This interrupt is vaild only when 10/100 speeds are advertised.
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26.15 – interrupt Status
When bit 26.15 is set to “1”, an unacknowledged interrupt is pending. The cause of the interrupt can be determined by reading
the interrupt status bits in this register. This bit is automatically cleared when read.
26.14 – Reserved
26.13 – Link State-Change interrupt Status
When the link status of the PHY changes, bit 26.13 is set to “1” if bit 25.13 is also set to “1”. This bit is automatically cleared
when read.
26.12 – Reserved
26.11 – Auto-Negotiation Error interrupt Status
When an error is detected by the Auto-Negotiation state machine, bit 26.11 is set to “1” if bit 25.11 is also set to “1”. This bit is
automatically cleared when read.
26.10 – Auto-Negotiation-Done / interlock Done interrupt Status
When the auto-negotiation state machine finishes a negotiation process, bit 26.10 is set to “1” if bit 25.10 is also set to “1”. This
bit is automatically cleared when read.
26.9 – inline Powered Device Detected interrupt Status
When a device requiring inline power over CAT-5 is detected, bit 26.9 is set to “1” if bit 25.9 is also set to “1”. This bit is
automatically cleared when read.
26.8 – Symbol Error interrupt Status
When a symbol error is detected by the descrambler, bit 26.8 is set to “1” if bit 25.8 is also set to “1”. This bit is automatically
cleared when read.
26.7 – Descrambler Lock-Lost interrupt Status
When the descrambler loses lock, bit 26.7 is set to “1” if bit 25.7 is also set to “1”. This bit is automatically cleared when read.
26.6 – TX FiFO interrupt Status
When the TX FiFO enters an underflow or overflow condition, bit 26.6 is set to “1” if bit 25.6 is also set to “1”. This bit is
automatically cleared when read.
26.5 – RX FiFO interrupt Status
When the RX FiFO enters an underflow or overflow condition, bit 26.5 is set to “1” if bit 25.5 is also set to “1”. This bit is
automatically cleared when read.
26.4 – Reserved
26.3 – False Carrier interrupt Status
When the PHY has detected a false carrier, bit 26.3 is set to “1” if bit 25.3 is also set to “1”. This bit is automatically cleared when
read,
26.2 – Cable impairment Detect interrupt Status
When the PHY has detected an impairment on the CAT-5 media, bit 26.3 is set to “1” if bit 25.3 is also set to “1”. This bit is
automatically cleared when read.
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26.1 – MASTER/SLAVE Resolution Error interrupt Status
When a MASTER/SLAVE resolution error is detected, bit 26.1 is set to “1” if bit 25.1 is also set to “1”. This bit is automatically
cleared when read.
26.0 – RXER interrupt Status
When an RXER condition occurs, bit 26.0 is set to “1” if bit 25.0 is also set to “1”.This bit is automatically cleared when read.
23.2.28 Register 27 (1Bh) – LED Control Register
Register 27 (1Bh) – LED Control Register
Reset
Value
Bit
Name
Access States
Sticky
15:12 Reserved
RO
CMODE
00 = Link10/Activity
011 = Duplex/Collision
10 = Link/Activity
11:10 LED Pin 2 Configuration
R/W
CMODE S
112 = Tx
00 = Link100/Activity
01 = Link10/100/Activity
10 = Link/Activity
11 = Link100/1000/Activity
00 = Link1000/Activity
01 = Link/Activity w/ Serial output on LED pins 1 and 2
10 = Fault
9:8
7:6
LED Pin 1 Configuration
LED Pin 0 Configuration
R/W
R/W
CMODE S
CMODE S
11 = Rx
LED Pulse-stretch Rate/ Blink
Rate
0 = 5 Hz blink rate/200 ms pulse-stretch
1 = 10 Hz blink rate/100 ms pulse-stretch
1 = Enable 5 kHz, 20% duty cycle LED pulsing for
power savings
5
4
R/W
R/W
0
0
S
S
LED Pulsing Enable
0 = LED pulsing disabled
1 = Collision, Activity, Rx and Tx functions will flash at
a rate selected by Blink/Pulse-Stretch Rate bits
0 = Collision, Activity, Rx and Tx functions will blink at
a rate selected by Blink/Pulse-Stretch Rate bits
1 = Link function indicates link status only
0 = Link/Activity function will blink or flash when
activity is present. Blink/flash behavior is selected
by Pulse-Stretch Enable and Blink/Pulse-Stretch
Rate bits.
3
2
LED Pulse-Stretch / Blink Select R/W
0
0
S
Link/Activity Behaviour
R/W
1 = Link function indicates link status only
0 = All link functions will blink or flash when activity is
present. Blink/flash behavior is selected by Pulse-
Stretch Enable and Blink/Pulse-Stretch Rate bits.
1 = Duplex function indicates duplex status only
0 = Duplex function will blink or flash when collision is
present
LED Linkxxxx/Activity3 Behavior
LED Duplex/Collision Behavior
1
0
R/W
R/W
0
0
S
S
1
2
3
This setting is ‘Force off’ when Mii Register 20E.13 is set.
This setting is ‘Force on’ when Mii Register 20E.13 is set.
Linkxxxx/Activity stands for Link10/Activity,Link100/Activity,Link1000/Activity,Link10/100/Activity and Link100/1000/Activity. its definition does not include the Link/
Activity function.
27.15:12 - Reserved
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27.11:6 – LED Pin Configuration
Each of the three LED pins on the VSC8221 can be configured for one of four functions. These functions are different for each
LED pin.1 Bits 27.11:6 are used to select the function for each LED pin. The reset value of these bits is set by the LED
configuration bits in the CMODE hardware configuration.
7.5 – LED Pulse-Stretch/Blink Rate
The Collision, Activity, Tx and Rx LED functions can be set to either blink at a constant rate or visibly flash through the use of
pulse-stretching. The blink rate and pulse-stretch length are set with this bit.
27.4 – LED Pulsing Enable
When bit 27.4 is set to “1”, all LED outputs are pulsed at a 5kHz rate with 20% duty cycle in order to save power.
27.3 – LED Pulse-Stretch / Blink Select
When bit 27.3 is set to “1”, Collision, Activity, Tx and Rx LED functions will be pulse-stretched. When bit 27.3 is cleared, these
LED functions will blink at a constant rate. Bit 27.5 are used to select the pulse-stretch / blink rate.
27.2 – LED Link/Activity Behavior
When bit 27.2 is set to “0”, the link status LED function will blink or flash when activity is present. Blink / flash behavior is
selected by bits 27.3 and 27.5.
27.1 – LED Linkxxxx/Activity Behavior
When bit 27.1 is set to “0”, all linkxxxx status LED functions (Link10, Link100, Link1000, Link10/100, Link100/1000) will blink or
flash when activity is present. Blink / flash behavior is selected by bits 27.3 and 27.5.
27.0 – LED Duplex/Collision Behavior
When bit 27.0 is set to “1”, the Duplex LED function indicates duplex status only. When bit 27.0 is cleared, the Duplex function
will blink or flash when collision is present. Blink / flash behavior is selected by bits 27.3 and 27.5.
1Note that if bits 27.7:6 are set to “01”, LED pins 1 and 2 are used as serial output pins and the values of bits 27.11:8 are ignored.
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23.2.29 Register 28 (1Ch) – Auxiliary Control and Status Register
Register 28 (1Ch) – Auxiliary Control and Status Register
Reset
Value
Bit
15
14
13
12
11
10
9
Name
Access States
1 = Auto-negotiation complete
Sticky
Auto-Negotiation Complete
Auto-Negotiation Disabled
MDi/MDi-X Crossover indication
CD Pair Swap
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0 = Auto-negotiation not complete
1 = Auto-negotiation was disabled
0 = Auto-negotiation is enabled
1 = MDi/MDi-X crossover detected
0 = MDi/MDi-X crossover not detected
1 = CD pairs are swapped
0 = CD pairs are not swapped
1 = Polarity swapped on pair A
0 = Polarity not swapped on pair A
1 = Polarity swapped on pair B
0 = Polarity not swapped on pair B
1 = Polarity swapped on pair C
0 = Polarity not swapped on pair C
1 = Polarity swapped on pair D
0 = Polarity not swapped on pair D
-
A Polarity inversion
B Polarity inversion
C Polarity inversion
8
7
D Polarity inversion
Reserved
RO
RO
0
--
1 = Enable enhanced ActiPHY power manage-
ment
0 = Disable enhanced ActiPHY power manage-
ment
1 = Full Duplex
0 = Half Duplex
6
5
Enhanced ActiPHY Mode Enable
FDX Status
R/W
RO
0
0
S
00 = Speed is 10BASE-T
01 = Speed is 100BASE-TX or 100BASE-FX
10 = Speed is 1000BASE-T
11 = Reserved
4:3
2
Speed Status
RO
RO
R/W
00
1
Reserved1
00=1 second
01=2 seconds
10-3 seconds
11=4 seconds
Enhanced ActiPHYTM Sleep Timer
1:0
01
1
This bit must always be set to ‘1’.
28.15 – Auto-Negotiation Complete
This bit is a copy of bit 1.5, duplicated here for convenience.
28.14 – Auto-Negotiation Disabled
When bit 28.14 is read as a “1”, this bit indicates that the auto-negotiation process has been disabled. This happens only when
register bit 0.12 is set to “0”.
28.13 – MDi/MDi-X Crossover indication
When bit 28.13 returns a “1”, the auto-negotiation state machine has determined that crossover does not exist in the signal path.
The crossover will therefore be performed internally to the PHY, as described by the MDi/MDi-X crossover specification.1
1This bit is valid only after descrambler lock has been achieved and as long as bit 18.5 is set to “0”.
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28.12 – CD Pair Swap1
When bit 28.12 returns a “1”, the PHY has determined that subchannel cable pairs C and D have been swapped between the
far-end transmitted and the receiver. When bit 28.12 returns a “1”, the PHY internally swaps pairs C and D (as long as bit 18.5 is
set to “0”).1
28.11 – A Polarity inversion
When bit 28.11 returns a “1”, the PHY has determined that the polarity of subchannel cable pair A has been inverted between
the far-end transmitter and the near-end receiver. When bit 28.11 returns a “1”, the PHY internally corrects the pair inversion.
Polarity-inversion correction runs in all three modes; as a result, the state of 28.11 is valid only when bit 1.5 is set to “1”.
28.10 – B Polarity inversion
When bit 28.10 returns a “1”, the PHY has determined that the polarity of subchannel cable pair B has been inverted between
the far-end transmitter and the near-end receiver. When bit 28.10 returns a “1”, the PHY internally corrects the pair inversion.
Polarity-inversion correction runs in all three modes; as a result, the state of 28.10 is valid only when bit 1.5 is set to “1”.
28.9 – C Polarity inversion2
When bit 28.9 returns a “1”, the PHY has determined that the polarity of subchannel cable pair C has been inverted between the
far-end transmitter and the near-end receiver. When bit 28.9 returns a “1”, the PHY internally corrects the pair inversion.
Polarity-inversion correction runs in all three modes; as a result, the state of 28.9 is valid only when bit 1.5 is set to “1”.
28.8 – D Polarity inversion1
When bit 28.8 returns a “1”, the PHY has determined that the polarity of subchannel cable pair D has been inverted between the
far-end transmitter and the near-end receiver. When bit 28.8 returns a “1”, the PHY internally corrects the pair inversion.
Polarity-inversion correction runs in all three modes; as a result, the state of 28.8 is valid only when bit 1.5 is set to “1”.
28.7 – Reserved
28.6 - Enable Enhanced ActiPHY Mode
When bit 28.6 is set to a “1”, the enhanced ActiPHY power management mode is set in the VSC8221. The reset value for this bit
is determined by the Enhanced ActiPHY bit in the CMODE hardware configuration.
28.5 – FDX Status
Bit 28.5 indicates the actual FDX/HDX operating mode of the PHY.
28.4:3 – Speed Status
Bits 27.4:3 indicate the actual operating speed of the PHY.
28.2 – Reserved
This bit must always be set to ‘1’.
28.1:0 - Enhanced ActiPHYTM Sleep Timer
This sets the time period the PHY stays in ‘Low Power’ State when Enhanced ActiPHYTM mode is enabled, before entering the
‘LP Wake-up State’. Refer to Section 15 on page 47 for details.
1This bit applies only in 1000BASE-T mode.
2This bit applies only in 1000BASE-T mode.
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23.2.30 Register 29 (1Dh) – Reserved
Register 29 (1Dh) – Reserved
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
29.15:0 - Reserved
23.2.31 Register 30 (1Eh) - MAC interface Clause 37 Auto-Negotiation Control and Status
Register 30 (1Eh) – MAC interface Clause 37 Auto-Negotiation Control and Status
Reset
Value
0
Bit
15
14
Name
Access States
Sticky
Reserved
RO
1 = Disable clause 37 auto-negotiation
0 = Enable clause 37 auto-negotiation
Correspond to remote fault bits sent by MAC
during clause 37 auto-negotiation
Corresponds to Asymmetric Pause bit sent by
MAC during clause 37 auto-negotiation
Corresponds to Symmetric Pause bit sent by
MAC during clause 37 auto-negotiation
1 = initiate restart of clause 37 auto-negotiation
0 = Normal operation
Clause 37 Auto-Negotiation Disable R/W
0
S
13:12 MAC Remote Fault
RO
RO
RO
00
0
11
10
9
MAC Asymmetric Pause
MAC Symmetric Pause
Clause 37 Restart Auto-Negotiaton
MAC Full Duplex
0
R/W
SC
0
Corresponds to Full Duplex Ability bit sent by
MAC during clause 37 auto-negotiation
Corresponds to Half Duplex Ability bit sent by
MAC during clause 37 auto-negotiation
8
RO
0
7
6
MAC Half Duplex
Reserved
RO
RO
0
0
1 = Clause 37 auto-negotiation has completed
successfully
0 = Clause 37 auto-negotiation has not completed
Clause 37 Auto-Negotiation Com-
plete
5
RO
0
4
3
Reserved
RO
RO
0
0
1 = Clause 37/28 auto-negotiation interlock could
not complete
Link interlock Fail
1 = Clause 37/28 auto-negotiation interlock com-
pleted
00 = 0ms (always stays low)
01 = 20ms
10 = 200ms
2
Link interlock Complete
RXLOS Pulse Delay1
RO
0
1:0
R/W
01
11 = 500ms
1
in SGMii to CAT-5, Modified Clause 37 Auto-negotiation-Enabled PHY Operating modes, the RXLOS signal is always driven, regardless of the settings of Mii
Register 30.1:0. For more information about PHY operating modes, see Table 33, “PHY Operating Modes,” on page 86.
30.15 – Reserved
30.14 - Clause 37 Auto-Negotiation Disable
When bit 30.14 is set to a “1”, the clause 37 auto-negotiation state machine is disabled in the VSC8221. Bit 30.14 is cleared by
default.
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30.13:12 - MAC Remote Fault
Bits 30.13:12 correspond to the Remote Fault bits sent to the VSC8221 by the MAC during the clause 37 auto-negotiation
process.
30.11 - MAC Asymmetric Pause
Bit 30.11 corresponds to the Asymmetric Pause bit sent to the VSC8221 by the MAC during the clause 37 auto-negotiation
process.
30.10 - MAC Symmetric Pause
Bit 30.10 corresponds to the Symmetric Pause bit sent to the VSC8221 by the MAC during the clause 37 auto-negotiation
process.
30.9 - Clause 37 Restart Auto-Negotiation
When bit 30.9 is set to a “1”, the clause 37 auto-negotiation process is restarted. This bit is self-clearing and always reads back
as “0”.
30.8 - MAC Full Duplex
Bit 30.8 corresponds to the Full Duplex Ability bit sent to the VSC8221 by the MAC during the clause 37 auto-negotiation
process.
30.7 - MAC Half Duplex
Bit 30.7 corresponds to the Half Duplex Ability bit sent to the VSC8221 by the MAC during the clause 37 auto-negotiation
process.
30.6 - Reserved
30.5 - Clause 37 Auto-Negotiation Complete
When bit 30.5 is set to a “1”, the clause 37 auto-negotiation has completed successfully.
30.4 - Reserved
30.3 - Link interlock Fail
Bit 30.3 is set to indicate a failure to complete interlock between Clause-37 auto-negotiation and Clause-28 auto-negotiation.
This bit is valid only in SerDes to CAT5 PHY operating modes.
30.2 - Link interlock Complete
Bit 30.2 is set to indicate a complete interlock between Clause-37 auto-negotiation and Clause-28 auto-negotiation. This bit is
valid only in SerDes to CAT5 PHY operating modes.
30.1:0 - RXLOS Pulse Delay
Bits 30.1:0 specify the RXLOS Pulse Delay. it sets the time the RXLOS/SiGDET signal pin is asserted when the CAT5 Media
Link is dropped. This bit is only valid when the ‘SFP Mode’ bit Extended Mii Register 21E.15 = “1”.
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23.2.32 Register 31 (1Fh) – Extended Page Access
Register 31 (1Fh) – Extended Page Access
1
Bit
Name
Access
States
Reset Value
Sticky
15:1 Reserved
RO
00000000 0000000
1 = Mii registers 16:30 will access extended
register set
0 = Mii registers 16:30 will access standard
register set
0
Extended Page Access R/W
0
1
This register will always read zero.
31.15:1 – Reserved
31.0 - Extended Page Access
in order to provide additional functionality beyond the iEEE802.3 specified 32 Mii registers, the VSC8221 contains an extended
register set which supports an additional 15 registers. When bit 31.0 is set to a “1”, Mii registers 16:30 will access the extended
set of registers. The state of bit 31.0 has no effect on Mii registers 0:15.
23.3 Extended Mii Registers
23.3.1 Register 16E (10h) - Reserved
Register 16E (10h) – Reserved
Bit
Name
Access States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
16E.15:0 – Reserved
23.3.2 Register 17E (11h) - Serdes Control Register
Register 17E (11h) – SerDes Control Register
Bit
Name
Access
States
Reset Value
Sticky
15:5 Reserved
RO
00000000 000
000=0.4mv(p-p)
001=0.6mv(p-p)
010=0.8mv(p-p)
011=1.0mv(p-p)
100=1.2mv(p-p)
101=1.4mv(p-p)
110/111=1.6mv(p-p)
1=Disable
RDP/RDN SCLKP/SCLKN
Output Swing Control
4:2
R/W
100
1
0
25mv Hysteresis Disable
CLKOUTMiCRO Enable
R/W
R/W
0
1
0=Enable
1=Enable
0=Disable
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17E.15:5 - Reserved
17E.4:2 - RDP/RDN SCLKP/SCLKN Output Swing Control
These bits set the output swing amplitude (peak-to-peak voltage) on the RDP/RDN SCLKP/SCKLN Output Swing output pins.
17E.1 - 25mv Hysteresis Disable
When set, this bit disables the 25mv Hysteresis built into the TDP/TDN and SDiP/SDiN high speed differential input pins.
17E.0 - CLKOUTMiCRO Enable
When set, the CLKOUTMiCRO clock output is enabled.
23.3.3 Register 18E (12h) - Reserved
Register 18E (12h) – Reserved
Bit
Name
Access
States
Reset Value
Sticky
15:0 Reserved
RO
00000001 11111111
18E.15:0 - Reserved
23.3.4 Register 19E (13h) - SerDes Control # 2
Register 19E (13h) – SerDes Control #2
Bit
Name
Access
States
Reset Value
Sticky
15:2 Reserved
RO
00000000 00000000
0 = input
1 = Output
0 = Active High
1 = Active Low
1
0
SiGDET Pin Direction
SiGDET Pin Polarity
R/W
R/W
CMODE
0
19E.15:2 - Reserved
19E.1 - SiGDET Pin Direction
This bit is valid in non-SFP modes i.e. when Mii Register 21E.15 is clear. in non-SFP mode, the RXLOS/SiGDET pin behaves
like the SiGDET pin. When set as an input, the assertion of the SiGDET pin enables the SerDes block in Serial MAC to CAT5
category of PHY operating modes. When set as an output in Serial MAC to CAT5 Media operating modes, the SiGDET pin is
asserted when the CAT5 Media link is up. in Fiber Media operating modes, the SiGDET output is asserted if the PHY sees valid
8B/10B encoded signals on the TDP/TDN pins.
19E.0 - SiGDET Pin Polarity
This bits sets the assertion polarity of the SiGDET pins. This bit is valid in both cases i.e when SiGDET is an input or an output.
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23.3.5 Register 20E (14h) - Extended PHY Control Register #3
Register 20E (14h) – Extended PHY Control Register #3
Reset
Value
Bit
Name
Access States
Sticky
0 = Enable
1 = Disable
15
14
13
12:9
8
Disable Byte Sync
Reserved
R/W
RO
0
S
0
1 = Enable LED force
0 = Disable LED force
Enable Force LED
R/W
0
S
S
Reserved1
1000
0
1 = 125MHz clock output on CLKOUTMiCRO
0 = 4MHz clock output on CLKOUTMiCRO
00 = No media selected
01 = Copper media selected
10 = Reserved
11 = Reserved
1=75 ohm impedance.
0=50 ohm impedance
1 = Enable auto link speed downshift
0 = Disable auto link speed downshift
00 = Downshift after 2 failed attempts
01 = Downshift after 3 failed attempts
10 = Downshift after 4 failed attempts
11 = Downshift after 5 failed attempts
0 = No downshift
CLKOUTMiCRO Frequency
R/W
RO
RO
7:6
Media Mode Status
0
Serial MAC interface Line imped-
ance
5
4
CMODE S
Enable Link Speed Auto-Downshift R/W
Link Speed Auto-Downshift Control R/W
Link Speed Auto-Downshift Status RO
0
S
S
3:2
01
1
0
0
0
1 = Downshift is required or has occurred
Reserved
RO
1
Writes to Extended Mii Register 20E must preserve the value of bits 12:9, i.e., all writes to Extended Mii Register 20E must be in the format xxx1000xxxxxxxxxb.
20E.15 Disable Byte Sync
When enabled, the PHY aligns the 10bit data to the boundary of the COMMA character.
20E.14 - Reserved
These bits must always be set to ‘”0”.
20E.13 - Enable LED force
When this bit is set, the LED configuration setting “01” becomes ‘Force off’ and the LED configuration setting “11” becomes
‘Force on’. Refer to Section 23.2.28: "Register 27 (1Bh) – LED Control Register" for details.
20E.12:9 Reserved
Writes to Extended Mii Register 20E must preserve the value of bits 12:9, i.e., all writes to Extended Mii Register 20E must be in
the format xxx1000xxxxxxxxxb.
20E.8 - CLKOUTMiCRO Frequency
The frequency of the CLKOUTMiCRO pin can be changed by using bit 20E.8.
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20E.7:6 - Media Mode Status
Bits 20E.7:6 reflect the media interface status.
20E.5 - SerDes Line impedance
The internal termination impedance of the high speed serial interface inside the VSC8221 can be selected using bit 20E.5. This
applies to the SerDes/SGMii pins on the device. The reset value of this bit is determined by the SerDes Line impedance bit in
the CMODE hardware configuration.
20E.4 - Enable Link Speed Auto-Downshift
When bit 20E.4 is set to a “1”, the VSC8221 will “downshift” the auto-negotiation advertisement to 100BASE-TX after the
number of failed 1000BASE-T auto-negotiation attempts specified in bits 20E.3:2. The reset value of this bit is determined by
the Link Speed Downshift bit in the CMODE hardware configuration.
20E.3:2 - Link Speed Auto-Downshift Control
Bits 20E.3:2 determine the number of unsuccessful 1000BASE-T auto-negotiation attempts that are required before the auto-
negotiation advertisement is “downshifted” to 100BASE-TX. These bits are valid only if bit 20E.4 is set.
20E.1 - Link Speed Auto-Downshift Status
When bit 20E.1 is set to a “1” and bit 20E.4 is set to a “1”, the current link speed is the result of a “downshift” to 100BASE-TX.
When bit 20E.1 is set to a “1” and bit 20E.4 is cleared, the current link requires a “downshift” in order to be established.
20E.0 - Reserved
23.3.6 Register 21E (15h) - EEPROM interface Status and Control Register
Register 21E (15h) - EEPROM interface Status and Control Register
Bit
Name
Access
States
Reset Value
Sticky
1 = SFP MODE
0 = iEEE MODE
15
SFP MODE
R/W
CMODE
SS
1 = Contents of EEPROM should be re-
read on software reset
0 = Contents of EEPROM should not be
re-read on software reset
Re-Read EEPROM on Software
Reset
14
R/W
0
SS
R/W
SC
13
12
11
EEPROM Access Enable
EEPROM Read/Write
EEPROM Ready1
1 = Execute read or write to EEPROM
0
1
1 = Read from EEPROM
0 = Write to EEPROM
1 = EEPROM is ready for read/write
0 = EEPROM is busy
R/W
RO
1
10:0 EEPROM Address
R/W
EEPROM address to read/write
000 00000000
1
After an EEPROM write operation, the station manager or controller must wait an additional 10 ms before performing the next EEPROM read or write operation.
This delay is needed for the EEPROM to complete its internal memory write process. Note that this additional wait is not needed after an EEPROM read operation.
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21E.15 - SFP MODE
SFP Mode (bit 15 =”1”) sets the following PHY defaults:
• TXDiS/SRESET is active high, i.e. behaves like TXDiS.
• MODDEF0/CLKOUT pin functions like MODDEF0, i.e this pin is asserted low by the PHY once the EEPROM interface is
released for access through the SMi interface.
• RXLOS/SiGDET pins functions like RXLOS.
• The SMi interface is set in MSA mode.
iEEE Mode (bit 15 = “0”) sets the following PHY defaults:
• TXDiS/SRESET is active low, i.e. behaves like SRESET.
• MODDEF0/CLKOUT pin functions like CLKOUT, i.e this pin drives out a 125MHz clock.
• RXLOS/SiGDET pin functions like SiGDET.
• The SMi interface is set in iEEE mode.
21E.14 - Re-Read EEPROM on Software Reset
When bit 21E.14 is set to a “1”, the contents of the EEPROM will be re-read and reloaded into the Mii registers upon software
reset.
21E.13 - EEPROM Access Enable
When bit 21E.13 is set to a “1”, the EEPROM address in bits 21E.10:0 is written to or read from, based on the state of bit
21E.12. The data to read/write resides in register 22E.
21E.12 - EEPROM Read/Write
When bit 21E.12 is set to a “1”, the VSC8221 will read from the EEPROM when bit 21E.13 is set. When bit 21E.12 is cleared,
the VSC8221 will write to the EEPROM when bit 21E.13 is set.
21E.11 - EEPROM Ready
When the VSC8221 is busy reading/writing to the EEPROM, bit 21E.11 will be cleared. Bit 21E.13 should not be set while bit
21E.11 is cleared.
21E.10:1 - EEPROM Address
These bits contain the EEPROM address that the VSC8221 will read from or write to when bit 21E.13 is set.
23.3.7 Register 22E (16h) - EEPROM Data Read/Write Register
Register 22E (16h) - EEPROM Data Read/Write Register
Reset
Bit
15:8 EEPROM Read Data
7:0 EEPROM Write Data
Name
Access States
Sticky
Value
RO
R/W
8-bit data read from EEPROM
8-bit data to write to EEPROM
00000000
00000000
22E.15:18 - EEPROM Read Data
After an EEPROM read has occurred by setting bits 21E.13 and 21E.12 to a “1”, the data read from the EEPROM is placed in
these bits.
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22E.7:0 - EEPROM Write Data
When an EEPROM write is initiated by setting bits 21E.13 to a “1” and clearing bit 21E.12, the data from these bits is written to
the EEPROM.
23.3.8 Register 23E (17h) - Extended PHY Control Register #4
Register 23E (17h) - Extended PHY Control Register #4
Bit
Name
Access States
Reset Value Sticky
15:11 PHY Address
RO
PHY address latched on reset
CMODE
Enable in-line Powered Device
Detection
1 = in-line powered device detection is enabled
0 = in-line powered device detection is disabled
00 = Searching for devices
10
R/W
0
S
01 = Device found which requires in-line power
10 = Device found which does not require in-
line power
in-line Powered Device Detection
Status
9:8
7:0
RO
00
11 = Reserved
CRC Counter
RO SC CRC counter for Ethernet packet generator
00000000
23E.15:11 - PHY Address
These bits contain the PHY address of the current PHY port. The reset value of these bits is determined by the PHY Address
bits in the CMODE hardware configuration.
23E.10 - Enable in-line Powered Device Detection
When bit 23E.10 is set to a “1”, the VSC8221 will search for devices requiring CAT-5 in-line power as part of the auto-
negotiation process.
23E.9:8 - in-line Powered Device Detection Status
Bits 23E.9:8 are used by the station manager to determine if a device which requires in-line power is connected to the
VSC8221.
23E.7:0 - CRC Counter
When the Ethernet Packet Generator is enabled by setting Mii Register 29.15, these bits count the number of packets received
that contain a CRC error. This counter will saturate at FFh and is cleared when read.
23.3.9 Register 24E (18h) - Reserved
Register 24E (18h) - Reserved Register
Bit
Name
Access States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
24E.15:0 - Reserved
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23.3.10 Register 25E (19h) - Reserved
Register 25E (19h) - Reserved Register
Bit
Name
Access States
Reset Value
Sticky
15:0 Reserved
RO
00000000 00000000
25E.15:0 - Reserved
23.3.11 Register 26E (1Ah) - Reserved
Register 26E (1Ah) - Reserved Register
Bit
Name
Access States
RO
Reset Value
00000000 00000000
Sticky
Sticky
Sticky
15:0 Reserved
26E.15:0 - Reserved
23.3.12 Register 27E (1Bh) - Reserved
Register 27E (1Bh) - Reserved Register
Bit
15:0
Name
Reserved
Access
States
Reset Value
00000000 00000000
RO
27E.15:0 - Reserved
23.3.13 Register 28E (1Ch) - Reserved
Register 28E (1Ch) - Reserved Register
Bit
Name
Access
States
Reset Value
15:0 Reserved
RO
00000000 00000000
28E.15:0 - Reserved
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23.3.14 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1
Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1
1
Reset
Value
Bit
15
14
13
Name
Access States
Sticky
1 = Enable EPG
EPG Enable
R/W
R/W
R/W
0
0 = Disable EPG
1 = Run EPG
EPG Run/Stop
Transmission Duration
0
0
0 = Stop EPG
1 = Continuous
0 = Send 30,000,000 packets and stop
00 = 125 bytes
01 = 64 bytes
10 = 1518 bytes
11 = 10,000 bytes (jumbo packet)
1 = 8,192 ns
0 = 96 ns
12:11 Packet Length
R/W
00
0
10
inter-packet Gap
R/W
9:6
5:2
Destination Address
Source Address
R/W
R/W
MSB’s lower nibble of the 6-byte destination address 0001
MSB’s lower nibble of the 6-byte source address
1 = Assert TXER
0 = Do not assert TXER
0000
1
0
TXER Control
R/W
R/W
0
1 = Generate packets with bad FCS
0 = Generate packets with good FCS
Bad FCS Generation
0
1
Refer to Section 17.1 on page 51 for more information.
29E.15 - EPG Enable
When bit 29E.15 is set to a “1”, the EPG is selected as the driving source for the PHY transmit signals, and the MAC transmit
pins are disabled. When bit 29E.15 is cleared, the MAC has full control of the PHY transmit signals.
29E.14 - EPG Run/Stop
Bit 29E.14 controls the beginning and end of packet transmission. When this bit is set to a “1”, the EPG begins the transmission
of packets. When this bit is cleared, the EPG ends the transmission of packets, after the current packet is transmitted. Bit
29E.14 is valid only if bit 29E.15 is set to a “1”.
29E.13 - Transmission Duration
When bit 29E.13 is set to a “1”, the EPG will continuously transmit packets as long as bit 29E.14 is set to a “1”. if bit 29E.13 is
cleared, the EPG will begin transmission of 30,000,000 packets when bit 29E.14 is set to a “1”, after which time, bit 29E.14 is
automatically cleared. if bit 29E.13 changes during packet transmission, the new value will not take effect until the EPG Run/
Stop bit (29E.14) has been cleared and set to a “1” again.
29E.12:11 - Packet Length
Bits 29E.12:11 select the length of the packets to be generated by the EPG. Note that when these bits are set to “11”, a 10,000-
byte “jumbo” packet is sent, which may not be compatible with all Ethernet equipment. if bits 29E.12:11 change during packet
transmission, the new values will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to a “1” again.
29E.10 - inter-packet Gap
Bit 29E.10 selects the inter-packet gap for packets generated by the EPG. if bit 29E.10 changes during packet transmission, the
new value will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to a “1” again.
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29E.9:6 - Destination Address
The 6-byte destination address for packets generated by the EPG is assigned one of 16 values in the range 0xF0 FF FF FF FF
FFh through 0xFF FF FF FF FF FFh. The most significant byte’s lower nibble bits of the destination address are selected by bits
29E.9:6. if bits 29E.9:6 change during packet transmission, the new values will not take effect until the EPG Run/Stop bit
(29E.14) has been cleared and set to a “1” again.
29E.5:2 - Source Address
The 6-byte source address for packets generated by the EPG is assigned one of 16 values in the range 0xF0 FF FF FF FF FFh
through 0xFF FF FF FF FF FFh. The most significant byte’s lower nibble bits of the source address are selected by bits 29E.5:2.
if bits 29E.5:2 change during packet transmission, the new values will not take effect until the EPG Run/Stop bit (29E.14) has
been cleared and set to a “1” again.
29E.1 - TXER Control
When bit 29E.1 is set to a “1”, all packets generated by the EPG will have the TXER signal asserted. When this bit is cleared,
TXER is not asserted. if bit 29E.1 changes during packet transmission, the new value will not take effect until the EPG Run/Stop
bit (29E.14) has been cleared and set to a “1” again.
29E.0 - Bad FCS Generation
When bit 29E.0 is set to a “1”, the EPG will generate packets containing an invalid Frame Check Sequence (FCS). When this bit
is cleared, the all EPG packets will contain a valid Frame Check Sequence. if bit 29E.0 changes during packet transmission, the
new value will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to a “1” again.
23.3.15 Register 30E (1Eh) - 1000BASE-T Ethernet Packet Generator Register #2
1
Register 30E (1Eh) - 1000BASE-T Ethernet Packet Generator Register #2
Bit
Name
Access
States
Reset Value
Sticky
15:0 EPG Packet Payload
R/W
Data for packets generated by EPG 00000000 00000000
1
Refer to Section 17.1 on page 51 for more information.
30E.15:0 - EPG Packet Payload
Each packet generated by the EPG contains a repeating sequence of bits 30E.15:0 as the data payload. if bits 30E.15:0 change
during packet transmission, the new values will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to
a “1” again.
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24 ELECTRICAL SPECIFICATIONS
24.1 Absolute Maximum Ratings
Stresses listed under the Absolute Maximum Ratings may be applied to devices one at a time without causing permanent
damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect
device reliability.
Table 34. Absolute Maximum Ratings
Symbol
Min
-65
Max
150
4.0
Unit
°C
V
Parameter Description & Conditions
Storage temperature range.
TStorage
VDD33A(Analog)
VDDREG
-0.5
-0.5
DC voltage on analog i/O supply pin.
DC voltage on Regulator supply pin.
4.0
V
VDDiO/VDDiO-
MiCRO/
-0.5
4.0
V
DC voltage on any digital i/O supply pin.
VDDiOCTRL
VDD(5V)
-0.5
-0.5
-0.5
-0.5
5.5
1.5
V
V
V
V
DC voltage on any 5 V-tolerant digital input pin.
DC voltage on any digital core supply pin.
DC voltage on any 1.2 V analog supply pin.
DC voltage on any non-supply pin.
VDD12
VDD12A
VPin(DC)
1.5
VDD + 0.5
ESD voltage on any pin, per event, according to the Human
Body Model.
VESD(HBM)
2
kV
CESD
2
kV
Cable-sourced ESD tolerance, per event, at 200 meters.
T = +85 °C, valid for all i/O signal pins.
iLATCHUP
-200
+200
mA
ELECTROSTATiC DiSCHARGE
This device can be damaged by ESD. Microsemi recommends that all integrated cir-
cuits be handled with appropriate precautions. Failure to observe proper handling
and installation procedures may adversely affect reliability of the device.
24.2 Recommended Operating Conditions
Table 35. Recommended Operating Conditions
Symbol
VDD33A
VDDREG
VDD12A
Min
3.0
Typ
3.3
3.3
1.2
Max
3.6
Unit
V
Parameter Description & Conditions
DC voltage on VDD33A pins
3.0
3.6
V
DC voltage on Regulator Supply pin
DC voltage on VDD12A pins
1.14
1.26
V
VDDiO/
VDDiOMiCRO/
VDDiOCTRL
DC voltage on VDDiO pins
Note: The on-chip i/O calibration is only valid
within these recommended operating conditions.
3.0
2.25
3.3
2.5
3.6
2.75
V
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Table 35. Recommended Operating Conditions (continued)
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
VDD12
1.14
1.2
1.26
V
DC voltage on VDD12 pins
Local reference clock (REFCLK) nominal
frequency. Refer to FTOL for minimum and
25
125
FREFCLK
MHz
ppm
maximum values.
Reference clock frequency offset tolerance over
specified temperature range
FTOL (REFCLK)
-100
+100
(25 MHz or 125 MHz)
CAT5 link partner frequency offset tolerance (for
any link speed)
FTOL (LiNK)
REXT
-1500
+1500
ppm
kΩ
µF
External reference circuit bias resistor
(1% tolerance).
2.00
0.1
External reference generator filter capacitor
(10% tolerance).
CREF_FiLT
Operating temperature. Lower limit of
specification is ambient temperature, and upper
limit is case temperature.
TOPER
0
100
°C
24.3 Thermal Application Data
Table 36. Thermal Application Data
Printed Circuit Board Conditions (JEDEC JESD51-9)
PCB Layers
4
PCB Dimensions (mm x mm)
101.6 × 114.3
1.6
PCB Thickness (mm)
Environment Conditions
Maximum operating junction temperature (ºC)
Ambient free-air operating temperature (ºC)
Worst Case Power Dissipation (W)
125
70
1
Table 37. Thermal Resistances
Symbol
Typ
Unit
Parameter Description & Conditions
40.8
°C/W
Junction-to-ambient thermal resistance
θ
θ
θ
JA (0 m/s airflow)
JA (1 m/s airflow)
JA (2 m/s airflow)
35.5
34.1
0.17
0.19
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance
Junction-to-ambient thermal resistance
Junction-to-top center of case thermal resistance
Junction-to-top center of case thermal resistance
ψ
JT (0 m/s airflow)
JT (1 m/s airflow)
ψ
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Table 37. Thermal Resistances (continued)
ψ
JT (2 m/s airflow)
0.24
28.6
13.6
°C/W
°C/W
°C/W
Junction-to-top center of case thermal resistance
Junction-to-board thermal resistance
Junction-to-case thermal resistance
θJB
θJC
24.4 Package Thermal Specifications - 100 TFBGA
Table 38. Thermal Specifications - 100-Ball TFBGA 9 × 9mm package
Symbol
Min
Typ
Max
70
Unit
°C
Parameter Description & Conditions
Ambient free-air operating temperature
Maximum operating junction temperature
TA
0
TJ
125
°C
θJC
13.6
0.17
°C/W
°C/W
Junction-to-case thermal resistance
Junction-to-top center of case thermal
resistance
ΨJT
24.5 Current and Power Consumption Estimates
Power supply current and power consumption information is provided below for PCB design targets.
VDDiO at 3.3 V, SerDes-Cat-5, FD,1518-byte random data packet,100% utilization, SCLK disabled, SFP mode off, regulator off
Table 39. VDDiO at 3.3 V, SerDes-Cat-5, SCLK Disabled
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
109
111
114
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
295
330
367
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
31
36
39
mA
731.64
841.8
968.76
mW
Power consumption
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VDDiO at 3.3 V, SGMii-Cat-5 (1000 Mbps), FD, 1518-byte random data packet,100% utilization, SCLK disabled, SFP mode off,
regulator off
Table 40. VDDiO at 3.3 V, SGMii-Cat-5 (1000 Mbps), SCLK Disabled
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
109
111
114
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
295
330
367
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
31
36
39
mA
731.64
841.8
968.76
mW
Power consumption
VDDiO at 3.3 V, SGMii-Cat-5 (100 Mbps), FD, 1518-byte random data packet, 100% utilization, SCLK disabled, SFP mode off,
regulator off
Table 41. VDDiO at 3.3 V, SGMii-Cat-5 (100 Mbps), SCLK Disabled
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
89
91
94
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
110
122
135
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
22
24
28
mA
450.48
511.8
590.58
mW
Power consumption
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VDDiO at 3.3 V, SGMii-Cat-5 (10 Mbps), FD, 1518-byte random data packet, 100% utilization, SCLK disabled, SFP mode off,
regulator off
Table 42. VDDiO at 3.3 V, SGMii-Cat-5 (10 Mbps), SCLK Disabled
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
146
151
155
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
53
56
61
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
22
25
28
mA
556.5
631.8
716.94
mW
Power consumption
VDDiO at 3.3 V SerDes-Cat-5, FD,1518-byte random data packet,100% utilization, SCLK enabled, SFP mode off, regulator off
Table 43. VDDiO at 3.3 V SerDes-Cat-5, SCLK Enabled
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
109
111
114
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
305
340
379
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
31
36
39
mA
743.04
853.8
983.88
mW
Power consumption
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VDDiO at 3.3 V, SerDes-Cat-5, FD,1518-byte random data packet,100% utilization, SCLK disabled, SFP mode on, regulator off
Table 44. VDDiO at 3.3 V SerDes-Cat-5, SFP Mode On
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
109
111
114
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
0.5
0.5
0.5
mA
iVDDiO
8
2
8
2
10
2
mA
mA
mA
Digital i/O supply current into VDDiO
iVDDiOMiCRO
iVDDiOCTRL
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
0.5
0.5
0.5
Digital 1.2 V core power supply current into
VDD12 pins
iVDD12
258
275
283
mA
Analog 1.2 V core power supply current into
VDD12A pins
iVDD12A
PD
31
36
39
mA
689.46
775.80
862.92
mW
Power consumption
VDDiO @ 3.3V, SGMii-100BASE-FX, FDX, 1518 Byte Random data packet, 100% Utilization, SFP Mode Off
Table 45. VDDiO at 3.3V SGMii-100BASE-FX, SFP Mode Off
Symbol
iVDD12
iVDD12A
Min
Typ
Max
Unit
Description
+
Power supply current into VDD12 and VDD12A
pins
145
mA
Analog 3.3V power supply current into
VDD33A pins
iVDD33A
96
mA
iVDDiOMAC
iVDDiOCTRL
iVDDiOMiCRO
+
Digital i/O supply current into VDDiOMAC,
VDDiOCTRL, and VDDiOMiCRO pins
+
19
mA
PD
554
mW
Power dissipation
VDDiO at 3.3 V, SerDes-Cat-5, FD,1518-byte random data packet, 100% utilization, SCLK disabled, SFP mode on, regulator on
Table 46. VDDiO at 3.3 V SerDes-Cat-5, SFP Mode On, Regulator On
Symbol
Min
Typ
Max
Unit
Description
Analog 3.3 V power supply current into
VDD33A pins
iVDD33A
109
111
114
mA
1.2 V regulator power supply current into the
VDDREG pins
iVDDREG
iVDDiO
149.5
8
139.5
8
129.5
10
mA
mA
Digital i/O supply current into VDDiO
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Table 46. VDDiO at 3.3 V SerDes-Cat-5, SFP Mode On, Regulator On (continued)
Symbol
Min
2
Typ
2
Max
2
Unit
mA
Description
iVDDiOMiCRO
Digital i/O supply current into VDDiOMiCRO
Digital i/O supply current into VDDiOCTRL
Power consumption
iVDDiOCTRL
PD
0.5
0.5
0.5
mA
807.0
861.3
921.6
mW
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25 DC SPECIFICATIONS
25.1 Digital Pins (VDDiO = 3.3 V)
The following specifications are valid only when TAmbient = 25 °C, VDDiO = 3.3 V, VDD12 = 1.2 V, VDD33A = 3.3 V, VSS = 0 V.
Table 47. Digital Pins Specifications (VDDiO = 3.3 V)
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Output high voltage.
VOH
2.4
VDDiO
V
VDDiO = MiN, iOH = -1.5 mA
Output low voltage.
VDDiO = MiN, iOL = 1.5 mA
VOL
GND
2.0
0.4
V
ViH
ViL
V
V
input high voltage.
0.8
10
10
input low voltage.
iiLeak
iOLeak
-10
-10
µA
µA
input leakage current.
Output leakage current.
25.2 Digital Pins (VDDiO = 2.5 V)
The following specifications are valid only when TAmbient = 25 °C, VDDiO = 2.5 V, VDD12 = 1.2 V, VDD33A = 3.3 V, VSS = 0 V.
Table 48. Digital Pins Specifications (VDDiO = 2.5 V)
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Output high voltage.
VOH
2.0
VDDiO
V
VDDiO = MiN, iOH = -1.0 mA
Output low voltage.
VDDiO = MiN, iOL = 1.0 mA
VOL
ViH
ViL
GND
1.7
0.4
V
V
V
input high voltage.
VDDiO = MiN
input low voltage.
VDDiO = MiN
0.7
iiLeak
-10
-10
10
10
µA
µA
input leakage current.
Output leakage current.
iOLeak
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25.3 LED Output Pins (LED[2:0])
The following specifications are valid over a voltage range of 2.3 V to 1.3 V applied to the LED[2:0] pins.1
Table 49. LED Output Pins Specification
Recommended1
Symbol
Max
Unit
Parameter Description
Current sinking capability of the LED drivers
isinking
40
8
mA
1
This recommendation is purely from a power savings view point.
1it is assumed that a typical LED will have a forward voltage drop of between 1v and 2v, thereby asserting a 1.3v (3.3v-2v) to 2.3v (3.3v-1v) sig-
nal across the LED.
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26 CLOCKING SPECIFICATIONS
26.1 Reference Clock Option
The following component specifications should be used to select a clock reference for use with the VSC8221. For more
information about clocking and frequency offset tolerance specifications when jumbo packet support is required, see the
application note Using Jumbo Packets with SimpliPHYs, available from the Microsemi Web site.
Table 50. Reference Clock Option Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Total frequency offset tolerance (25 MHz clock
option), including, initial offset, stability over
temperature.
FTOL-25MHZ
-100 ppm
25
+100 ppm
MHz
Rise and fall time (20% to 80%), 25 MHz clock
option.
TR1, TF1
4
ns
ns
%
Rise and fall time (20% to 80%), 125 MHz clock
option.
TR2, TF2
0.8
55
Duty cycle (25 MHz and 125 MHz clock
options).
DUTY
45
26.2 Crystal Option
The following component specifications should be used to select a crystal for use with the VSC8221. For more information
about clocking and frequency offset tolerance specifications when jumbo packet support is required, see the application note
Using Jumbo Packets with SimpliPHYs, available from the Microsemi Web site.
Table 51. Crystal Option Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Fundamental mode, AT-cut type, parallel
resonant crystal reference frequency.
FREF
25
MHz
Fundamental mode, AT-cut type, parallel
resonant crystal total frequency offset, including,
initial offset, stability over temperature, aging
and capacitive loading.
FTOL(TOTAL)
-50
18
+50
20
ppm
CL
pF
pF
Crystal parallel load capacitance.
Crystal external load capacitors to GND.1
Equivalent series resistance of crystal.
Crystal oscillator drive level.
CL-EXT
30
10
ESR
PD
30
Ω
0.5
mW
1
These values can depend on board parasitics.
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27 SERDES SPECIFICATIONS
All specifications valid for TAmbient = 0°C to 70°C.
Table 52. SerDes Specifications
Symbol
Min
100
350
Typ
Max
2400
1400
Unit
Parameter Description & Conditions
T_lock
500
uS
Frequency Lock Time
Peak to peak differential voltage (TDP-TDN)
Vidiff
mV
mV
terminated with a 100 Ω (differential) Load
Peak to peak differential voltage (RDP-RDN),
100 Ω (differential) termination in the module,
recommended voltage range is 500 mV to
1200 mV
Vodiff1
1200
Vicm
0.437 x VDD12 .45 x VDD12 0.464 x VDD12
V
V
input common mode voltage
Output common mode voltage
Vocm
0.4 x VDD12 .45 x VDD12
0.5 x VDD12
300
20%-80% Transition time.
Trise / Tfall of high speed output driver.
Tr_HS / Tf_HS
ps
Random jitter (1 sigma) as per 802.3 standard.
random jitter component at RDP, RDN in serial
MAC to CAT5 media category of PHY operating
modes.
RJ
18
38
ps RMS
With a K28.5+/K28.5- Pattern.
ps pk-pk Deterministic jitter at RDP, RDN in serial MAC to
CAT5 media category of PHY operating modes.
DJ
SerDes
Data Rate
1249.375
1250
1250.625
Mbps SerDes data rate. (+/- 500 ppm)
1
Vodiff is controlled by Extended Mii Register 17E.4:2. The default output swing is 1200mV. For more information, see <HyperLink>Section 23.3.2 on page 98.
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28 SYSTEM TIMING SPECIFICATIONS
28.1 JTAG Timing
The following specifications are valid only when the i/O power supply (VDDiOCTRL) is at either 3.3 V, ±5%, or 2.5 V, ±5%.
Table 53. JTAG Timing Specifications
Symbol
Min
100
45
Typ
Max
Unit
ns
Parameter Description & Conditions
TCK period.
TTCK-Period
TTCK-High
TTCK-Low
ns
TCK minimum pulse width high.
TCK minimum pulse width low.
(TMS or TDi) to TCK setup time.
(TMS or TDi) to TCK hold time.
TDO delay from TCK.
45
ns
TTDi/TMS-Setup
TTDi/TMS-Hold
TTDO-Delay
10
ns
10
ns
15
ns
TTDI/TMS-Setup
TTDI/TMS-Hold
TDI
TMS
TTCK-Period
TCK
TDO
TTCK-Low
TTCK-High
TTDO-Delay
Figure 24. JTAG interface AC Timing
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28.2 SMi Timing
The following specifications are valid only when the i/O power supply (VDDiOMiCRO) is at either 3.3 V, ±5%, or 2.5 V, ±5%.
Table 54. SMi Timing Specifications
Symbol
Min
0
Typ
2.5
50
Max
Unit
MHz
ns
Parameter Description & Conditions
MDC clock frequency.
FMDC
12.5
TMDC-High
TMDC-Low
20
20
MDC clock pulse width high.
MDC clock pulse width low.
50
ns
MDiO to MDC setup time when sourced by the
station manager.
TMDiO-Setup
TMDiO-Hold
10
10
ns
ns
MDiO to MDC hold time when sourced by the
station manager.
MDC to MDiO delay time from VSC8221.
Delay depends on the value of external pull-up
resistor on MDiO pin.
TMDiO-Delay
10
300
ns
Note: A 4.7k to 10k pullup is recommended on the MDiNT.
MDC
TMDIO-Setup
TMDIO-Hold
MDIO
(input)
Data
TMDC-Low
TMDC-High
MDC
FMDC
TMDIO-Delay
MDIO
(output)
Data
Figure 25. SMi AC Timing
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28.3 MDiNT Timing
The following specifications are valid only when the i/O power supply (VDDiOMiCRO) is at either 3.3 V, ±5%, or 2.5 V, ±5%.
Table 55. MDiNT Timing Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
MDiNT fall time, assuming a 2.2 kΩ external
pull-up resistor and a 50 pF total capacitive load.
tF
110
ns
28.4 Serial LED_CLK and LED_DATA Timing
The following specifications are valid only when the i/O power supply (VDD33A) is at 3.3V, ±5%.
Table 56. Serial LED_CLK and LED_DATA Timing Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
TLED_CLK
1
µs
LED_CLK output period.
LED_CLK pause between LED bit sequence
repeat (un-preambled mode).
TLED_CLK-Pause
TLED_DATA-Delay
25
ms
LED_DATA propagation delay from rising edge
of LED_CLK.
0.5
µs
TLED_CLK
TLED_CLK-Pause
LED_CLK
TLED_DATA-Delay
.......................
Bit 1 of 36
Bit 36 of 36
LED_DATA
Bit 1 of 36
Figure 26. LED_CLK and LED_DATA Output AC Timing
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28.5 REFCLK Timing
The following specifications are valid only when the VDD33A is at 3.3 V, ±5%.
Table 57. REFCLK Timing Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Reference clock period, PLLMODE = 0
(25 MHz reference).
TREFCLK25
40
ns
Reference clock period, PLLMODE = 1
(125 MHz reference).
TREFCLK125
FSTABiLiTY
TDUTY
8
ns
ppm
%
Reference clock frequency stability
(0 °C to 70 °C).
100
60
REFCLK duty cycle in both 25 MHz and
125 MHz modes.
40
50
JREFCLK25,
JREFCLK125
Total jitter of 25 MHz or 125 MHz reference
clock (peak-to-peak).
300
ps
Reference clock rise time, 25 MHz mode
(20% to 80%).
tR/F (REFCLK25)
tR/F (REFCLK125)
4
1
ns
ns
Reference clock rise time, 125 MHz mode
(20% to 80%).
TDUTY
TREFCLK
80%
20%
REFCLK
tR, tF
Figure 27. REFCLK AC Timing
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28.6 CLKOUT and CLKOUTMiCRO Timing
The following specifications are valid only when the i/O power supply (VDDiO for CLKOUT and VDDiOMiCRO for
CLKOUTMiCRO) is at either 3.3 V ±5%, or 2.5 V ±5%.
.
Table 58. CLKOUT and CLKOUTMiCRO Timing Specifications
Symbol
Min
Typ
Max
Unit
Parameter Description & Conditions
Clock period.
TCLKOUT
8
ns
Clock period. Either:
4 MHz or
125 MHz.
TCLKOUTMiCRO
250
8
ns
FSTABiLiTY
TDUTY
100
60
ppm
%
Clock frequency stability (0 °C to 70 °C).
Clock duty cycle.
40
50
JCLK125
300
1
ps
Total jitter of clock (peak-to-peak).
Clock rise time (20% to 80%).
tR/F (CLK125)
ns
TDUTY
TCLKOUT
80%
20%
CLKOUT
tR, tF
Figure 28. CLKOUT AC Timing
TDUTY
TCLKOUTMICRO
80%
20%
CLKOUTMICRO
tR, tF
Figure 29. CLKOUTMiCRO AC Timing
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28.7 Reset Timing
The following specifications are valid only when the i/O power supply (VDDiOmicro) is at either 3.3 V, ±5%, or 2.5 V, ±5%.
Table 59. RESET AC Timing Specification
Symbol
Min
Typ
Max
Unit
Description
Conditions
TRESET
100
ns
Reset assertion time
if EEPROM is present, an
additional 100ms is
required
TREADY
13
20
ms
Reset to SMi active time
REFCLK
TRESET
RESET
MDIO
TREADY
Figure 30. RESET AC Timing
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29 PACKAGING SPECIFICATIONS
29.1 100-Ball 9 × 9mm TFBGA Mechanical Specification
Dimensions are in millimeters (mm).
Ball Pitch : 0.80
Ball Diameter: 0.4
Substrate Thickness: 0.21
Mold Thickness: 0.53
Figure 31. 100-Ball 9 × 9mm TFBGA Mechanical Specification
29.2 Package Moisture Sensitivity
Moisture sensitivity level ratings for Microsemi products comply with JEDEC standard iPC/JEDEC J-STD-020B. All Microsemi
products are rated moisture sensitivity level 3 or better unless specified otherwise. For more information, see the JEDEC
standard.
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30 Ordering information
Lead-free products from Microsemi comply with the temperatures and profiles defined in the JEDEC standard
PC/JEDEC J-STD-020. For more information, see the JEDEC standard.
30.1 Devices
Table 60. Part Number for the VSC8221
Part Number
Package Type
Description
100 TFBGA
0.8mm ball pitch
9mm x 9mm
body
VSC8221HH
Single port, low power, triple-speed PHY
100 TFBGA
0.8mm ball pitch
9mm x 9mm
body
VSC8221XHH
Lead-free, single port, low power, triple-speed PHY
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31 DESIGN GUIDELINES
Although copper-based Ethernet physical layer devices (PHY) have been developed from an established iEEE standard, some
PHYs available in the marketplace are either non-compliant with the standard or implement non-standard features that cause
interoperability issues with the SimpliPHYTM series of gigabit Ethernet PHYs.
31.1 Required PHY Register Write Sequence
issue: At initialization, a number of internal registers must be changed from their default values.
Description: A series of register writes must be performed after device power-up or reset. These writes can be done using the
EEPROM connected to the EEPROM interface or by the Switch/Station Manager.
Workaround: The required register writes are as follows:
• 2A30h to PHY Register 31
• 0212h to PHY Register 8
• 52B5h to PHY Register 31
• 000Fh to PHY Register 2
• 472Ah to PHY Register 1
• 8FA4h to PHY Register 0
• 2A30h to PHY Register 31
• 0012h to PHY Register 8
• 0000h to PHY Register 31
31.2 interoperability with intel 82547Ei Gigabit Ethernet MAC+PHY iC
issue: Due to a non-standard startup-sequence in the intel 82547Ei MAC+PHY iC, the VSC8221 might take multiple attempts to
establish link.
Workaround: The following PHY register write can be performed to avoid this issue:
• 0049h to Mii Register 18
31.3 SerDes Jitter
issue: Under worst case conditions, total jitter performance may exceed the iEEE specifications for 1000BASE-X, as noted in
the table below.
impact: in typical applications with robust PCB design practices, however, actual performance is typically better than the figures
noted below.
Symbol
Min
Typ
Max
Unit
Parameter Description and Conditions
Worst case total transmit jitter in media converter
applications.
J(TOTAL, TX)
290
ps
Worst case total receive jitter tolerance in media
converter applications.
J(TOTAL, RX)
400
ps
Workaround: None.
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31.4 SGMii 100BASE-TX Corruption of Packets with Odd Preambles
Description: in SGMii-CAT5 mode and while receiving 100BASE-TX packets with odd preambles, the VSC8221 device’s
receive rate adaptation block will not properly encode the packet.
The following diagram is an excerpt from Figure 2 of the Cisco SGMii Specification v1.7.
RXD[3:0] for 10/100BT
RXD[7:0] for 1000BT
RX
RX_ER
RX
ENC_RXD [0:9]
PCS
Transmit
State
PHY
Receive
Rate
Serializer
RXD[7:0]
RX_CLK @ 2.5/25/125 MHz
From CAT-5
Machine
Adaptation
RX_CLK @ 25 MHz
To MAC
Figure 32. SGMii Rx Path from the PHY to the MAC
impact: This will cause a normal packet with an odd preamble to become corrupted. The corruption occurs while encoding the
SFD. This may cause an otherwise normal packet to be dropped at the MAC.
Example:
Case i : even preamble (correct)
55555Dxyz : encoded as 55, 55, D5, yx …
Case ii : odd preamble (incorrect)
5555Dxyz : encoded as 55, 55, xD, zy …
Note no SFD in above
Workaround: There is no workaround at the physical layer of the PHY’s packet transmission. if higher layers are being
employed on this receive path such as TCP/iP, then a re-transmission request could occur to recover from the loss. This is a
problem only when the preamble is corrupted by noise in the CAT5 link or when the link partner PHY is transmitting a non-
compliant preamble.
31.5 SGMii 100BASE-TX Corruption of Packets with no ESDs
Description: in SGMii-to-CAT5 mode and while receiving 100BASE-XT packets with no ESD from the CAT5 interface, the
100BASE-TX receive PCS extends the packet by a nibble while asserting RX_ER.
impact: The rate adaption block subsequently will not transmit this additional nibble and the RX_ER to the MAC. The MAC may
then consider this a normal packet.
Workaround: There is no workaround at the PHY’s SGMii layer. The likelihood of receiving a packet with no ESD and no CRC
error is low. During such an event (if it does occur), the data address and payload are not corrupted. The only item that would
be lost is that an RX_ER event occurred to mark the missing ESD during transmission.
For more information, see Figure 32, above.
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31.6 Software Reset Time
Description: The VSC8221 device’s software reset timing depends on the values of its Mii Register 22.9 (Sticky Reset Enable)
and its Extended Mii Register 21.14 (Re-Read EEPROM on Software Reset).
Table 61. Software Reset Times
Re-Read
EEPROM
(21E.14)
Sticky Reset
Enable (22.9)
Reset Time
1
0
0
1
0
0
1
1
4 microseconds (default)
300 microseconds
200 milliseconds
200 milliseconds
For more information, see Register 0 (00h) – Mode Control Register, page 67, Register 21E (15h) - EEPROM interface Status
and Control Register, page 101, and Register 22 (16h) – Control & Status Register, page 84.
impact: May cause errors if sufficient delay is not added between software reset and the next register access.
Workaround: System software must ensure that adequate delay is inserted between software reset and the next register
address.
31.7 Reducing EMi
Description: in systems that do not use the CLKOUT or the CLKOUTmicro outputs, radiated emissions can be reduced by
disabling these outputs. Under the default PHY settings, CLKOUT and CLKOUTmicro are enabled.
impact: Reduction of radiated emissions by disabling these unused clock outputs may enable customers to use less expensive
system enclosures or shielding methods to reduce system cost.
Workaround: For information about enabling or disabling the CLKOUT output, see Register 18 (12h) – Bypass Control
Register, page 81. For information about enabling or disabling the CLKOUTmicro output, see Register 17E (11h) - Serdes
Control Register, page 98.
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31.8 Clause 40 Auto MDi/MDi-X interoperability Testing
Description: The VSC8221 device’s Auto MDi/MDi-X will not pass the UNH iOL’s Clause 40 Auto-crossover test suite.
impact: Although the VSC8221 will not technically pass the entire Auto MDi/MDi-X test suite at the UNH iOL, extensive Auto
MDi/MDi-X interoperability testing has been performed in Microsemi’s internal interoperability lab, in addition to performing
standard interoperability testing at the UNH iOL. Due to the robust Auto MDi/MDi-X implementation in the VSC8221, there are
no known interoperability issues with Auto MDi/MDi-X at any speed. Please contact Microsemi for additional interoperability and
validation results, including the UNH iOL Test Report.
Workaround: None.
31.9 10BASE-T HDX issue with iXiA Test Suite
Description: A jam signal generated by an iXiA tester and sent to the VSC8221 in 10BASE-T HDX cannot be seen by a
receiving MAC. When a jam signal of 0xFF is generated by an iXiA test suite and transmitted at the start of the packet, the PHY
does not report any receive information on its SGMii interface. in SGMii, carrier sense in the MAC is derived from TX_DX, so the
MAC is not able to detect a collision.
impact: The only known situation that could be affected by this issue is if a receive error corrupts the entire preamble. Extensive
testing has only shown this error to occur when used with an iXiA tester. This error has not occurred in interoperability testing.
Workaround: None.
31.10 100BASE-FX initialization Script
The 100BASE-FX initialization script does the following:
•
•
•
•
initializes the copper section of DSP to support the 100BASE-FX mode
Disables the pair swap option
Sets 100BASE-X PCS into FX mode
Forces the PHY into 100Mbps mode
The following script is provided as an attached text file so that you can copy it electronically. in Acrobat, double-click the
attachment icon.
//--100BASE-FX initialization script for VSC8221.--//
phy_write( phynum(dec), regnum(dec), value(hex) );
phy_write(0, 31, 0x2a30);
phy_write(0, 8, 0x0212);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa7fa);
phy_write(0, 2, 0x0012);
phy_write(0, 1, 0x3001);
phy_write(0, 0, 0x87fa);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa240);
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phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x0001);
phy_write(0, 0, 0x8240);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa70c);
phy_write(0, 2, 0x00e0);
phy_write(0, 1, 0x000d);
phy_write(0, 0, 0x870c);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa70c);
phy_write(0, 2, 0x00e0);
phy_write(0, 1, 0x0000);
phy_write(0, 0, 0x870c);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa258);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x2140);
phy_write(0, 0, 0x8258);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa258);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x21c0);
phy_write(0, 0, 0x8258);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25a);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x2940);
phy_write(0, 0, 0x825a);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25a);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x29c0);
phy_write(0, 0, 0x825a);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25c);
phy_write(0, 2, 0x0000);
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phy_write(0, 1, 0x3000);
phy_write(0, 0, 0x825c);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25c);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x3000);
phy_write(0, 0, 0x825c);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25e);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x38a0);
phy_write(0, 0, 0x825e);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa25e);
phy_write(0, 2, 0x0000);
phy_write(0, 1, 0x3800);
phy_write(0, 0, 0x825e);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xafa2);
phy_write(0, 2, 0x0098);
phy_write(0, 1, 0x000);
phy_write(0, 0, 0x8fa2);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xafa2);
phy_write(0, 2, 0x009c);
phy_write(0, 1, 0x0000);
phy_write(0, 0, 0x8fa2);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xafa0);
phy_write(0, 2, 0x0013);
phy_write(0, 1, 0x1b00);
phy_write(0, 0, 0x8fa0);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xafa0);
phy_write(0, 2, 0x0013);
phy_write(0, 1, 0x9b00);
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phy_write(0, 0, 0x8fa0);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa708);
phy_write(0, 2, 0x000e);
phy_write(0, 1, 0x0004);
phy_write(0, 0, 0x8708);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa708);
phy_write(0, 2, 0x000e);
phy_write(0, 1, 0x000c);
phy_write(0, 0, 0x8708);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa708);
phy_write(0, 2, 0x000e);
phy_write(0, 1, 0x001c);
phy_write(0, 0, 0x8708);
phy_write(0, 31, 0x52b5);
phy_write(0, 0, 0xa708);
phy_write(0, 2, 0x000e);
phy_write(0, 1, 0x003c);
phy_write(0, 0, 0x8708);
phy_write(0, 31, 0x0000);
phy_write(0, 18, 0x0069);
phy_write(0, 31, 0x0000);
phy_write(0, 18, 0x7069);
phy_write(0, 31, 0x0000);
phy_write(0, 0, 0x2100);
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32 Product Support
All support documents for the VSC8221 can be accessed on the Microsemi Web site at www.Microsemi.com. Access to some
documents may require filing a non-disclosure agreement with Microsemi.
32.1 Available Documents and Application Notes
•
•
•
•
•
•
•
•
•
iBiS Model
OrCAD Symbol
BSDL File
Copper SFP PHY Performance Comparison White Paper
Design and Layout Guidelines application note
Magnetics Guide
Using Jumbo Packets with SimpliPHYs application note
UNH Test Report (requires NDA)
Designing a Copper SFP using the VSC8221 PHY application note
For additional application notes and information about reference designs using the VSC8221 PHY device, visit the Microsemi
Web site at www.Microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo, CA 92656 USA
Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com
www.microsemi.com
© 2004–2006 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All
other trademarks and service marks are the property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any
particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder
and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or
applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other
testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters
provided by Microsemi. it is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information
provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer.
Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other iP rights, whether with regard to such information itself or
anything described by such information. information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes
to the information in this document or to any products and services at any time without notice.
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data
center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASiCs;
power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF
solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions;
Power-over-Ethernet iCs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has
approximately 4,800 employees globally. Learn more at www.microsemi.com.
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33 DOCUMENT HISTORY AND NOTICES
Revision
Date
Comments
Number
0.1.0
Feb 10, 04
May 11, 04
First Preliminary Release
Added VDD12A pin reference.
Added Errata Section and added errata no. 6
Updated ‘specification’ section with VDD12A reference
Updated LED ECO
0.1.1
Added ‘Connector Loopback section’
Added power consumption data.
Removed Errata Section, added design guidelines section.
0.1.2
Jun 22, 04
Updated Mii Register 0.15, 24.0 removed column S.no from table 27.2 (Register 23)
Updated document style to reflect Microsemi corporate standards.
Added two power consumption tables.
2.0
2.1
Aug 18, 04
Sep 13, 04
Added new package diagram.
Replaced Cicada silicon revision conventions with the Microsemi silicon revision
conventions. A0 (Cicada) is now A (Microsemi). A1 (Cicada) is now C (Microsemi).
Changed ambient free-air operating temperature and thermal resistance specifications.
Removed reference to support of 100BASE-FX (100 Mbps) modules in the Features
and Benefits section.
Changed description of the System Clock interface Signals - in XTAL1 crystal oscillator
input section. For more information, see Table 5, “System Clock interface Signals
(SCi),” on page 17.
Deleted the system schematics that showed power supply connections.
Added descriptive information to the section about the device twisted pair interface. For
more information, see Section 10, “Twisted Pair interface” on page 10-29.
Added information about the device Auto-MDi/MDi-X in Forced 10/100 Link Speeds.
For more information, see Section 10.3, “Auto MDi/MDi-X in Forced 10/100 Link
Speeds” on page 10-30.
Added information about Forcing the PHY into MDi or MDi-X mode in 10/100/1000 Link
Speeds. For more information, see Section 10.4, “Forcing the PHY into MDi or MDi-X
mode in 10/100/1000 Link Speeds” on page 10-31.
4.0
May 02, 05
Changed title of SMi pin descriptions table. For more information, see Table 18, “SMi
Pin Descriptions - iEEE Mode,” on page 38.
Added information to the LED Function Assignments table. For more information, see
Table 20, “LED Function Assignments,” on page 41.
Changed the information associated with the device Parallel LED functions. For more
information, see Table 21, “Parallel LED Functions,” on page 41.
Changed information associated with the device identification register. For more
information, see Section 14, “Test Mode interface (JTAG)” on page 14-44.
in the Operation in enhanced ActiPHY mode section, changed the illustration showing
the enhanced ActiPHY state. For more information, see Figure 16 on page 15-47.
in the description of near-end loopback testing, the information about what happens to
the signal was changed. For more information, see Section 17.4, “Near-End Loopback”
on page 17-52.
(continues)
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Revision
Number
Date
Comments
(continued)
in the description of the connector loopback, the information about connecting the PHY
to a loopback connector or loopback cable. For more information, see Section 17.5,
“Connector Loopback” on page 17-52.
Deleted information about the device SGMii-to-100BASE-FX operation (was page 60 in
the previous version of the datasheet).
Deleted information about the device’s iEEE 802.3 Clause 28 and 37 Remote Fault
indication support (was page 61 in the previous version of the datasheet).
Added information to the description of the device mode control register. For more
information, see Section 23.2.1, “Register 0 (00h) – Mode Control Register” on page
23-67.
Added information to the description of the device mode status register. For more
information, see Section 23.2.2, “Register 1 (01h) – Mode Status Register” on page 23-
69.
Changed information associated with the reset value of the device identification register
#2. For more information, see Section 23.2.4, “Register 3 (03h) – PHY identifier
Register #2” on page 23-71.
Changed the information associated with certain reset values in the device PHY control
register #2. For more information, see Section 23.2.25, “Register 24 (18h) – PHY
Control Register #2” on page 23-87.
Changed the information associated with the reset value in the device LED control
register. For more information, see Section 23.2.28, “Register 27 (1Bh) – LED Control
Register” on page 23-92.
Changed the information associated with the enhanced ActiPHY mode enable bit in the
device auxilliary control and status register. For more information, see Section 23.2.29,
“Register 28 (1Ch) – Auxiliary Control and Status Register” on page 23-94.
4.0
(continued)
May 02, 05
information on the SiGDET pin direction when the device is operating in serial MAC-to-
CAT-5 media and Fiber media modes was changed. For more information, see Section
23.3.4, “Register 19E (13h) - SerDes Control # 2” on page 23-99.
The reset value for bits 8 and 4 in the Extended PHY control register #3 were changed.
For more information, see Section 23.3.5, “Register 20E (14h) - Extended PHY Control
Register #3” on page 23-100. Also changed description of bit 5 in this register.
The specification for ESD according to the Machine Model (VESD(MM)) was deleted
from the Electrical Specifications section.
information about the ESD sensitivity of the device was added. For more information,
see Section 24.1, “Absolute Maximum Ratings” on page 24-107.
The device operating temperature specification was changed. For more information,
see Section 24.2, “Recommended Operating Conditions” on page 24-107.
Added qualifying description to estimates of current and power consumption. For more
information, see Section 24.5, “Current and Power Consumption Estimates” on page
24-109.
Changed the power consumption specification for the device with VDDiO at 3.3V, in
SerDes-to-Cat-5 mode, FD, 1518-byte randmom data packet, 100% utilization; and
with SCLK, SFT and regulator off. For more information, see Table 39, “VDDiO at 3.3 V,
SerDes-Cat-5, SCLK Disabled,” on page 109.
Changed the power consumption specification for the device with VDDiO at 3.3V, in
SGMii-to-Cat-5 mode (1000 Mbps), FD, 1518-byte randmom data packet, 100%
utilization; and with SCLK, SFT and regulator off. For more information, see Table 40,
“VDDiO at 3.3 V, SGMii-Cat-5 (1000 Mbps), SCLK Disabled,” on page 110.
(continues)
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Revision
Number
Date
Comments
(continued)
Changed the power consumption specification for the device with VDDiO at 3.3V, in
SGMii-to-Cat-5 mode (100 Mbps), FD, 1518-byte randmom data packet, 100%
utilization; and with SCLK, SFT and regulator off. For more information, see Table 41,
“VDDiO at 3.3 V, SGMii-Cat-5 (100 Mbps), SCLK Disabled,” on page 110.
Changed the power consumption specification for the device with VDDiO at 3.3V, in
SGMii-to-Cat-5 mode (10 Mbps), FD, 1518-byte randmom data packet, 100%
utilization; and with SCLK, SFT and regulator off. For more information, see Table 42,
“VDDiO at 3.3 V, SGMii-Cat-5 (10 Mbps), SCLK Disabled,” on page 111.
Changed the power consumption specification for the device with VDDiO at 3.3V, in
SerDes-to-Cat-5 mode, FD, 1518-byte randmom data packet, 100% utilization; and
with SFT and regulator off, SCLK on. For more information, see Table 43, “VDDiO at
3.3 V SerDes-Cat-5, SCLK Enabled,” on page 111.
Changed the output high voltage specification for the digital pins when VDDiO = 3.3 V.
Also changed the specification for the output low voltage. Also changed the
specification for the input high voltage. Also changed the specification for the input low
voltage. For more information, see Table 47, “Digital Pins Specifications (VDDiO =
3.3 V),” on page 114.
Changed the specification for random jitter (RJ) in the SerDes specifications table. For
more information, see Table 52, “SerDes Specifications,” on page 117. Also changed
deterministic jitter specification (DJ) in the same table.
4.0
(continued)
May 02, 05
Added specifications for the device reset timing. For more information, see Section
28.7, “Reset Timing” on page 24-123.
Added information about the moisture sensitivity of the device package. For more
information, see Section 29.2, “Package Moisture Sensitivity” on page 25-124.
Deleted temperature range information from the device ordering information.
Added descriptive information and specifications for the device SerDes jitter. For more
information, see Section 31.3, “SerDes Jitter” on page 27-126.
Added descriptive information, specifications, illustrations and example cases related to
the device's corruption of packets with odd preambles when operating in SGMii
100BASE-TX mode. For more information, see Section 31.4, “SGMii 100BASE-TX
Corruption of Packets with Odd Preambles” on page 27-127.
Added descriptive information related to the device's corruption of packets with no
ESDs when operating in SGMii 100BASE-TX mode. For more information, see Section
31.5, “SGMii 100BASE-TX Corruption of Packets with no ESDs” on page 27-127.
Added descriptive information and specifications related to the device's software reset
timing. For more information, see Section 31.6, “Software Reset Time” on page 27-128.
Added descriptive information related to the reduction of EMi. For more information,
see Section 31.7, “Reducing EMi” on page 27-128.
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Revision
Number
Date
Comments
•
•
in the media converter application diagram, the RJ-45 speed was corrected from 10/
100/1000BASE-T to 1000BASE-T.
Throughout the datasheet, information was added regarding the 100BASE-FX
mode. The following lists the main information:
–
–
–
For information about twisted pair signals in 100BASE-FX mode, see Table 12:
“Twisted Pair interface Signals”.
For information about 100BASE-FX system schematics, see Figure 5: "System
Schematic - 100Mbps Fiber Media implementation".
For information about 100BASE-FX connections and initialization, see Section
10.6: "100Mbps Fiber Support Over Copper Media interface" and Section 31.10:
"100BASE-FX initialization Script".
4.1
December 06
–
For information about 100BASE-FX current consumption, see Table 45: “VDDiO
at 3.3V SGMii-100BASE-FX, SFP Mode Off”.
•
•
•
in the listing of JTAG interface instruction codes, the register width given for the
instructions EXTEST and SAMPLE/PRELOAD was corrected from 196 bits to
72 bits.
in the reset AC timing diagram, the MDiO signal pulse width was widened to be
more accurate relative to the pulse width of the REFCLK signal. For more
information about this specification, see Figure 30: "RESET AC Timing".
in the reset AC timing specifications, TREADY signal, a condition was added that if
EEPROM is present, an additional 100ms is required. For more information about
reset AC timing, see Table 59: “RESET AC Timing Specification”.
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Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo, CA 92656 USA
Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com
www.microsemi.com
© 2004–2006, 2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation.
All other trademarks and service marks are the property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any
particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder
and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or
applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other
testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters
provided by Microsemi. it is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information
provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer.
Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other iP rights, whether with regard to such information itself or
anything described by such information. information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes
to the information in this document or to any products and services at any time without notice.
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data
center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASiCs;
power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF
solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions;
Power-over-Ethernet iCs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has
approximately 4,800 employees globally. Learn more at www.microsemi.com.
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