W364M72V-133SBI中文资料_数据手册_规格书

W364M72V-XSBX

64Mx72 Synchronous DRAM

FEATURES

BENEFITS

 High Frequency = 100, 125, 133MHz

 66% SPACE SAVINGS

 Package:

 Reduced part count from 9 to 1

 Reduced I/O count

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

 3.3V ±0.3V power supply for core and I/Os

• 55% I/O Reduction

 Fully Synchronous; all signals registered on positive edge

 Reduced trace lengths for lower parasitic capacitance

 Suitable for hi-reliability applications

 Laminate interposer for optimum TCE match

of system clock cycle

 Internal pipelined operation; column address can be

changed every clock cycle

 Internal banks for hiding row access/precharge

 Programmable Burst length 1,2,4,8 or full page

 8,192 refresh cycles

GENERAL DESCRIPTION

The 512MByte (4.5Gb) SDRAM is a high-speed CMOS, dynamic

random-access, memory using 9 chips containing 512M bits.

Each chip is internally conﬁgured as a quad-bank DRAM with a

synchronous interface. Each of the chip’s 134,217,728-bit banks

is organized as 8,192 rows by 2,048 columns by 8 bits.

 Commercial, Industrial and Military Temperature Ranges

 Organized as 64M x 72

 Weight: W364M72V-XSBX - TBD grams typical

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command,

which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-12 select the row). The address bits registered

coincident with the READ or WRITE command are used to select

This product is subject to change without notice.

the starting column location for the burst access.

Continued on page 4

DENSITY COMPARISONS

W364M72V-XSBX

25

W364M72V-XSBX

32

Area = 800mm²

I/O Count = 219 Balls

SAVINGS — Area: 66%

I/O Count: 55%

Discrete Approach (mm)

11.9

54

TSOP

54

TSOP

54

TSOP

54

TSOP

54

TSOP

54

TSOP

54

TSOP

54

TSOP

54

TSOP

22.3

Area 9 x 265mm²= 2,385mm²

I/O Count 9 x 54 pins = 486 pins

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

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W364M72V-XSBX

FIGURE 1 – PIN CONFIGURATION

Top View

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

DQ0

DQ2

DQ4

DQ5

DQ14

DQ12

DQ10

DQ8

VCC

DQ15

DQ13

DQ11

DQ9

VSS

V^CC

V^CCQ

NC

VSS

A9

A10

A11

A8

VCCQ

VCC

VSS

NC

VCCQ

VCC

VSS

NC

DQ16

DQ18

DQ20

DQ22

DQML1

DQ17

DQ19

DQ21

DQ23

VSS

DQ31

DQ29

DQ27

DQ26

NC

V^SS

DQ30

DQ28

DQ25

DQ24

CLK1

CKE1

V^CC

A

B

C

D

E

F

DQ1

DQ3

DQ6

DQ7

VSS

A0

A2

A7

A6

A1

VCC

VCCQ

NC

A5

A4

A3

A12

NC

DNU

BA0

DNU

BA1

DNU

NC

DQML0

DQMH0

CLK0

CKE0

V^CCQ

VCCQ

CS3#

CAS0# WE0#

CS0# RAS0#

VCC

NC

RAS1# WE1#

CAS1# CS1#

V^SS

DQMH1

NC

VCC

NC

V^SS

G

H

J

V^SS

VCC

V^SS

VSS

NC

V^CC

VCC

NC

V^SS

Vss

VCCQ

V^SS

VCC

VSS

V^SS

VCC

NC

CKE3

CLK3

DQMH3

DQ58

DQ59

DQ61

DQ63

VCC

CKE2

CLK2

DQMH2

DQ41

DQ43

DQ45

DQ47

VSS

RAS2# CS2#

WE2# CAS2#

K

L

NC

VCC

CAS3# RAS3#

V^SS

DQ56

DQ57

DQ60

DQ62

Vss

VCC

WE3#

DQ54

DQ52

DQ50

DQ48

DQML3

NC

CKE4

NC

CLK4 CAS4# WE4# RAS4# CS4#

V^SS

DQML2

DQ37

DQ36

DQ34

DQ32

DQ39

DQ38

DQ35

DQ33

V^CC

M

N

P

R

T

DQ55

DQ53

DQ51

DQ49

NC

DQ71

DQ69

DQ67

DQ65

DQ70

DQ68

DQ66

DQ64

DQML4

V^CC

VSS

NC

V^CC

V^SS

VSS

DQ40

DQ42

DQ44

DQ46

VSS

V^SS

VCC

VCCQ

V^SS

NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.

NC = Not Connected Internally.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

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W364M72V-XSBX

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

WE

RAS

CAS

0

#

WE# RAS# CAS#

0-12

WE# RAS# CAS#

A

0-12

A

A0-12

DQ

0

DQ8

DQ

0

DQ

0

BA0-1

CLK

CKE

0

CLK

CKE

CS#

CLK

CKE

CS0#

0

CLK

CKE

CS#

DQM

IC0

IC5

CS0

#

DQML

0

DQML

DQMH

0

DQ7

DQ15

DQ

7

DQ7

WE

RAS

CAS

1

#

1

WE# RAS# CAS#

0-12

WE# RAS# CAS#

A0-12

A

DQ

DQ16

DQ23

DQ

DQ24

DQ31

BA0-1

CLK

CKE

1

CLK

CKE

CS#

DQM

CLK

CKE

CS1#

1

CLK

CKE

CS#

DQM

IC1

IC6

CS1

#

DQML

1

DQMH

1

DQ

7

DQ7

WE

RAS

CAS

2

#

WE# RAS# CAS#

0-12

WE# RAS# CAS#

A0-12

A

DQ

DQ32

DQ39

DQ

DQ40

DQ47

BA0-1

CLK

CKE

2

CLK

CKE

CS#

DQM

CLK

CKE

2

CLK

CKE

CS#

DQM

IC2

IC7

CS2

#

CS2#

DQML

2

DQMH2

DQ

7

DQ7

WE

RAS

CAS

3

#

WE# RAS# CAS#

0-12

WE# RAS# CAS#

A0-12

A

DQ

DQ48

DQ55

DQ

DQ56

DQ63

BA0-1

CLK

CKE

3

CLK

CKE

CS#

DQM

CLK

CKE

3

CLK

CKE

CS#

DQM

IC3

IC8

CS3

#

CS3#

DQML

3

DQMH3

DQ

7

DQ7

WE

RAS

CAS

4

#

WE# RAS# CAS#

0-12

A

DQ

DQ64

DQ71

BA0-1

CLK

CKE

4

CLK

CKE

CS#

DQM

IC4

CS4#

DQML

4

DQ

7

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W364M72V-XSBX

The SDRAM provides for programmable READ or WRITE burst

lengths of 1, 2, 4 or 8 locations, or the full page, with a burst

terminate option.AnAUTO PRECHARGE function may be enabled

to provide a self-timed row precharge that is initiated at the end

of the burst sequence.

After the AUTO REFRESH cycles are complete, the SDRAM is ready

for Mode Register programming. Because the Mode Register will

power up in an unknown state, it should be loaded prior to applying

any operational command.

REGISTER DEFINITION

MODE REGISTER

The Mode Register is used to deﬁne the speciﬁc mode of operation

of the SDRAM. This deﬁnition includes the selec-tion of a burst

length, a burst type, a CAS latency, an operating mode and a

write burst mode, as shown in Figure 3. The Mode Register is

programmed via the LOAD MODE REGISTER command and will

retain the stored information until it is programmed again or the

device loses power.

The 4.5Gb SDRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compatible with the 2n rule

of prefetch architectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed, fully random

access. Precharging one bank while accessing one of the other three

banks will hide the precharge cycles and provide seamless, high-

speed, random-access operation.

The 4.5Gb SDRAM is designed to operate at 3.3V.An auto refresh

mode is provided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance, including

the ability to synchronously burst data at a high data rate with

automatic column-address generation, the ability to interleave

between internal banks in order to hide precharge time and the

capability to randomly change column addresses on each clock

cycle during a burst access.

Mode register bits M0-M2 specify the burst length, M3 speciﬁes

the type of burst (sequential or interleaved), M4-M6 specify the

FIGURE 3 – MODE REGISTER DEFINITION

A12

A11 A10

A9

A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

FUNCTIONAL DESCRIPTION

Mode Register (Mx)

Reserved*

WB Op Mode CAS Latency BT

Burst Length

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence.

Accesses begin with the registration of anACTIVE command which

is then followed by a READ or WRITE command. The address bits

registered coincident with theACTIVE command are used to select

the bank and row to be accessed (BA0 and BA1 select the bank,

A0-12 select the row). The address bits (A0-9, A11) registered

coincident with the READ or WRITE command are used to select

the starting column location for the burst access.

*Should program

M12, M11, M10 = 0, 0

to ensure compatibility

with future devices.

Burst Length

M2 M1M0

M3 = 0

M3 = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

Reserved

Full Page

Reserved

Prior to normal operation, the SDRAM must be initialized. The

following sections provide detailed information covering device

initialization, register deﬁnition, command descriptions and device

operation.

Burst Type

M3

0

Sequential

Interleaved

1

INITIALIZATION

CAS Latency

M6 M5M4

SDRAMs must be powered up and initialized in a predeﬁned

manner. Operational procedures other than those speciﬁed may

result in undeﬁned operation. Once power is applied to V_CCand

V_CCQ(simultaneously) and the clock is stable (stable clock is

deﬁned as a signal cycling within timing constraints speciﬁed for the

clock pin), the SDRAM requires a 100μs delay prior to issuing any

command other than a COMMAND INHIBIT or a NOP. Starting at

some point during this 100μs period and continuing at least through

the end of this period, COMMAND INHIBIT or NOP commands

should be applied.

Reserved

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

Reserved

M8

0

M7

0

M6-M0

Defined

-

Operating Mode

Standard Operation

Once the 100μs delay has been satisfied with at least one

COMMAND INHIBIT or NOP command having been applied, a

PRECHARGE command should be applied. All banks must be

precharged, thereby placing the device in the all banks idle state.

-

All other states reserved

Write Burst Mode

M9

0

Programmed Burst Length

Single Location Access

1

Once in the idle state, two AUTO REFRESH cycles must be performed.

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W364M72V-XSBX

CAS latency, M7 and M8 specify the operating mode, M9 speciﬁes

the WRITE burst mode, and M10 and M11 are reserved for future

use. Address A12 (M12) is undeﬁned but should be driven LOW

during loading of the mode register.

TABLE 1 – BURST DEFINITION

Order of Accesses Within a Burst

Burst

Length

Starting Column

Address

Type = Sequential

Type = Interleaved

A0

The Mode Register must be loaded when all banks are idle, and

the controller must wait the speciﬁed time before initiating the

subsequent operation. Violating either of these requirements will

result in unspeciﬁed operation.

2

4

0

1

0-1

1-0

0-1

1-0

A1

0

A0

0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0

1

BURST LENGTH

1

0

Read and write accesses to the SDRAM are burst oriented, with

the burst length being programmable, as shown in Figure 3. The

burst length determines the maximum number of column locations

that can be accessed for a given READ or WRITE command.

Burst lengths of 1, 2, 4 or 8 locations are available for both the

sequential and the interleaved burst types, and a full-page burst

is available for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command to generate

arbitrary burst lengths.

1

A2

0

A1

0

A0

0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0

1

0

1

0

8

0

1

0

1

0

1

0

Reserved states should not be used, as unknown operation or

incompatibility with future versions may result.

1

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1,

Full

Page

(y)

When a READ or WRITE command is issued, a block of columns

equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst will

wrap within the block if a boundary is reached. The block is uniquely

selected by A1-9, A11 when the burst length is set to two; by A2-9,

A11 when the burst length is set to four; and by A3-9, A11 when

the burst length is set to eight. The remaining (least signiﬁcant)

address bit(s) is (are) used to select the starting location within

the block. Full-page bursts wrap within the page if the boundary

is reached.BURST TYPE

n = A 0-9

Not Supported

(location 0-y)

Cn…

NOTES:

1. For full-page accesses: y = 2,048.

2. For a burst length of two, A1-9, A11 select the block-of-two burst; A0 selects the starting column

within the block.

3. For a burst length of four, A2-9, A11 select the block-of-four burst; A0-1 select the starting

column within the block.

4. For a burst length of eight, A3-9, A11 select the block-of-eight burst; A0-2 select the starting

column within the block.

5. For a full-page burst, the full row is selected and A0-9, A11 select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

Accesses within a given burst may be programmed to be either

sequential or interleaved; this is referred to as the burst type and

is selected via bit M3.

7. For a burst length of one, A0-9, A11 select the unique column to be accessed, and Mode

Register bit M3 is ignored.

The ordering of accesses within a burst is determined by the burst

length, the burst type and the starting column address, as shown

in Table 1.

OPERATING MODE

The normal operating mode is selected by setting M7and M8 to

zero; the other combinations of values for M7 and M8 are reserved

for future use and/or test modes. The programmed burst length

applies to both READ and WRITE bursts.

CAS LATENCY

The CAS latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the ﬁrst

piece of output data. The latency can be set to two or three clocks.

Test modes and reserved states should not be used because

unknown operation or incompatibility with future versions may

result.

If a READ command is registered at clock edge n, and the latency

is m clocks, the data will be available by clock edge n+m. The I/

Os will start driving as a result of the clock edge one cycle earlier

(n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming

that the clock cycle time is such that all relevant access times are

met, if a READ command is registered at T0 and the latency is

programmed to two clocks, the I/Os will start driving after T1 and

the data will be valid by T2. Table 2 below indicates the operating

frequencies at which each CAS latency setting can be used.

TABLE 2 – CAS LATENCY

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

SPEED

-100

-125

-133

LATENCY = 2

LATENCY = 3

 75

 100

 125

 133

Reserved states should not be used as unknown operation or

incompatibility with future versions may result.

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W364M72V-XSBX

FIGURE 4 – CAS LATENCY

T0

T1

T2

T3

CLK

Command

I/O

READ

NOP

t_LZ

NOP

t_OH

D_OUT

t_AC

DON'T CARE

UNDEFINED

CAS Latency = 2

T0

T1

T2

T3

T4

CLK

Command

I/O

READ

NOP

t_LZ

NOP

t_OH

D_OUT

t_AC

CAS Latency = 3

WRITE BURST MODE

ACTIVE

When M9 = 0, the burst length programmed via M0-M2 applies

to both READ and WRITE bursts; when M9 = 1, the programmed

burst length applies to READ bursts, but write accesses are single-

location (nonburst) accesses.

The ACTIVE command is used to open (or activate) a row in a

particular bank for a subsequent access. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs

A0-12 selects the row. This row remains active (or open) for

accesses until a PRECHARGE command is issued to that bank. A

PRECHARGE command must be issued before opening a different

row in the same bank.

COMMANDS

The Truth Table provides a quick reference of available commands.

This is followed by a written description of each command. Three

additional Truth Tables appear following the Operation section;

these tables provide current state/next state information.

READ

The READ command is used to initiate a burst read access to an

active row. The value on the BA0, BA1 inputs selects the bank,

and the address provided on inputs A0-9, A11 selects the starting

column location. The value on inputA10 determines whether or not

AUTO PRECHARGE is used. If AUTO PRECHARGE is selected,

the row being accessed will be precharged at the end of the READ

burst; if AUTO PRECHARGE is not selected, the row will remain

open for subsequent accesses. Read data appears on the I/Os

subject to the logic level on the DQM inputs two clocks earlier. If a

given DQM signal was registered HIGH, the corresponding I/Os

will be High-Z two clocks later; if the DQM signal was registered

LOW, the I/Os will provide valid data.

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from

being executed by the SDRAM, regardless of whether the CLK

signal is enabled. The SDRAM is effectively deselected. Operations

already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP

to an SDRAM which is selected (CS# is LOW). This prevents

unwanted commands from being registered during idle or wait

states. Operations already in progress are not affected.

WRITE

The WRITE command is used to initiate a burst write access to

an active row. The value on the BA0, BA1 inputs selects the bank,

and the address provided on inputs A0-9, A11 selects the starting

column location. The value on inputA10 determines whether or not

AUTO PRECHARGE is used. If AUTO PRECHARGE is selected,

the row being accessed will be precharged at the end of the

WRITE burst; if AUTO PRECHARGE is not selected, the row will

remain open for subsequent accesses. Input data appearing on

LOAD MODE REGISTER

The Mode Register is loaded via inputsA0-11 (A12 should be driven

low). See Mode Register heading in the Register Deﬁnition section.

The LOAD MODE REGISTER command can only be issued when

all banks are idle, and a subsequent executable command cannot

be issued until t_MRDis met.

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TRUTH TABLE – COMMANDS AND DQM OPERATION

(NOTE 1)

NAME (FUNCTION)

CS#

H

L

RAS#

CAS#

WE#

X

DQM

X

ADDR

I/Os

COMMAND INHIBIT (NOP)

X

H

L

X

H

L

X

NO OPERATION (NOP)

H

L

X

ACTIVE (Select bank and activate row) ( 3)

READ (Select bank and column, and start READ burst) (4)

WRITE (Select bank and column, and start WRITE burst) (4)

BURST TERMINATE

L

X

Bank/Row

X

L

H

L

L/H ⁸

X

Bank/Col

X

L

Bank/Col

Valid

Active

X

L

H

L

X

PRECHARGE (Deactivate row in bank or banks) ( 5)

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)

LOAD MODE REGISTER (2)

L

X

Code

L

H

L

X

L

X

Op-Code

X

Write Enable/Output Enable (8)

–

L

–

Active

High-Z

Write Inhibit/Output High-Z (8)

–

H

NOTES:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-11 deﬁne the op-code written to the Mode Register and A12 should be driven low.

3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-9, A11 provide column address; A10 HIGH enables the auto precharge feature

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for

CKE.

8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock

delay).

(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which

bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged

and BA0, BA1 are “Don’t Care.”

the I/Os is written to the memory array subject to the DQM input

logic level appearing coincident with the data. If a given DQM

signal is registered LOW, the corresponding data will be written to

memory; if the DQM signal is registered HIGH, the corresponding

data inputs will be ignored, and a WRITE will not be executed to

that byte/column location.

PRECHARGE is nonpersistent in that it is either enabled or disabled

for each individual READ or WRITE command.

AUTO PRECHARGE ensures that the precharge is initiated at the

earliest valid stage within a burst. The user must not issue another

command to the same bank until the precharge time (t_RP) is completed.

This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time.

PRECHARGE

The PRECHARGE command is used to deactivate the open row

in a particular bank or the open row in all banks. The bank(s) will

be available for a subsequent row access a speciﬁed time (tRP)

after the PRECHARGE command is issued. InputA10 determines

whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select

the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once

a bank has been precharged, it is in the idle state and must be

activated prior to any READ or WRITE commands being issued

to that bank.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either

ﬁxed-length or full-page bursts. The most recently registered READ

or WRITE command prior to the BURST TERMINATE command

will be truncated.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM

and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in

conventional DRAMs. This command is nonpersistent, so it must

be issued each time a refresh is required.

AUTO PRECHARGE

The addressing is generated by the internal refresh controller. This

makes the address bits “Don’t Care” during an AUTO REFRESH

command. Each 512Mb SDRAM requires 8,192AUTO REFRESH

cycles every refresh period (t_REF). Providing a distributed AUTO

REFRESH command will meet the refresh requirement and ensure

that each row is refreshed. Alternatively, 8,192 AUTO REFRESH

commands can be issued in a burst at the minimum cycle rate

(t_RC), once every refresh period (t_REF).

AUTO PRECHARGE is a feature which performs the same individual-

bank PRECHARGE function described above, without requiring an

explicit command. This is accomplished by using A10 to enable

AUTO PRECHARGE in conjunction with a speciﬁc READ or WRITE

command. A precharge of the bank/row that is addressed with

the READ or WRITE command is automatically performed upon

completion of the READ or WRITE burst, except in the full-page

burst mode, where AUTO PRECHARGE does not apply. AUTO

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W364M72V-XSBX

SELF REFRESH*

The SELF REFRESH command can be used to retain data in the

SDRAM, even if the rest of the system is powered down. When in

the self refresh mode, the SDRAM retains data without external

clocking. The SELF REFRESH command is initiated like anAUTO

REFRESH command except CKE is disabled (LOW). Once the

SELF REFRESH command is registered, all the inputs to the

SDRAM become “Don’t Care,” with the exception of CKE, which

must remain LOW.

The procedure for exiting self refresh requires a sequence of

commands. First, CLK must be stable (stable clock is deﬁned as a

signal cycling within timing constraints speciﬁed for the clock pin)

prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM

must have NOP commands issued (a minimum of two clocks) for

t

_XSR, because time is required for the completion of any internal

refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands

must be issued as both SELF REFRESH and AUTO REFRESH

utilize the row refresh counter.

Once self refresh mode is engaged, the SDRAM provides its own

internal clocking, causing it to perform its own AUTO REFRESH

cycles. The SDRAM must remain in self refresh mode for a

minimum period equal to tRAS and may remain in self refresh

mode for an indeﬁnite period beyond that.

* Self refresh available in commercial and industrial temperatures only.

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

Voltage on V_CC, V_CCQSupply relative to Vss

Voltage on NC or I/O pins relative to Vss

Operating Temperature TA (Mil)

Operating Temperature TA (Ind)

Storage Temperature, Plastic

NOTE:

-1 to 4.6

V

-55 to +125

-40 to +85

-55 to +125

°C

Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions

greater than those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE

(NOTE 2)

Parameter

Symbol

CI1

Max

12

Unit

pF

Input Capacitance: CLK

Addresses, BA0-1 Input Capacitance

Input Capacitance: All other input-only pins

Input/Output Capacitance: I/Os

CA

50

pF

CI2

12

pF

CIO

12

pF

BGA THERMAL RESISTANCE

Description

Symbol

Theta JA

Theta JB

Theta JC

Max

TBD

Unit

C/W

Junction to Ambient (No Airﬂow)

Junction to Ball

Junction to Case (Top)

NOTE:

Refer to Application Note “PBGA Thermal Resistance Correlation” at www.whiteedc.com in the application notes section for modeling conditions.

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W364M72V-XSBX

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(NOTES 1, 6)

V_CC, V_CCQ= +3.3V ± 0.3V; -55°C ≤ T_A≤+125°C

Parameter/Condition

Symbol

Min

3

Max

Units

V

Supply Voltage

V

_CC,V_CCQ

3.6

Input High Voltage: Logic 1; All inputs (21)

Input Low Voltage: Logic 0; All inputs (21)

V_IH

V_IL

I_I

2

V_CC+ 0.3

V

-0.3

10

-45

-5

0.8

10

45

5

V

Input Leakage Current: Any input 0V ≤ V_IN≤ V_CC(All other pins not under test = 0V)

Input Leakage Address Current (All other pins not under test = 0V)

Output Leakage Current: I/Os are disabled; 0V ≤ V_OUT≤ V_CCQ

μA

V

I_I

I_OZ

V_OH

Output Levels:

2.4

–

Output High Voltage (I_OUT= -4mA)

Output Low Voltage (I_OUT= 4mA)

V_OL

–

0.4

V

ICC SPECIFICATIONS AND CONDITIONS

(NOTES 1,6,11,13)

V_CC, V_CCQ= +3.3V ± 0.3V; -55°C ≤ T_A≤+125°C

Parameter/Condition

Symbol

Max

Units

Operating Current: Active Mode;

Burst = 2; Read or Write; t_RC= t_RC(min); CAS latency = 3 (3, 18, 19)

I_CC1

900

mA

Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;

All banks active after t_RCDmet; No accesses in progress (3, 12, 19)

I_CC3

I_CC4

I_CC7

405

1,035

54

Operating Current: Burst Mode; Continuous burst;

Read or Write; All banks active; CAS latency = 3 (3, 18, 19)

Self Refresh Current: CKE ≤ 0.2V (Commercial and Industrial Temperature: -40°C to +

85°C) (27)

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W364M72V-XSBX

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

(NOTES 5, 6, 8, 9, 11)

-100

-125

-133

Parameter

Symbol

t_AC

Unit

ns

ms

ns

—

ns

Min

Max

7

Min

Max

6

Min

Max

5.5

6

CL = 3

CL = 2

Access time from CLK (pos. edge)

t_AC

7

6

Address hold time

Address setup time

CLK high-level width

CLK low-level width

t_AH

1

2

1

2

0.8

1.5

2.5

7.5

10

t_AS

t_CH

3

t_CL

3

CL = 3

CL = 2

t_CK

10

13

1

8

Clock cycle time (22)

t_CK

10

1

CKE hold time

t_CKH

t_CKS

t_CMH

t_CMS

t_DH

0.8

1.5

0.8

1.5

0.8

1.5

CKE setup time

2

CS#, RAS#, CAS#, WE#, DQM hold time

CS#, RAS#, CAS#, WE#, DQM setup time

Data-in hold time

1

2

1

Data-in setup time

t_DS

2

CL = 3 (10)

CL = 2 (10)

t_HZ

7

6

5.5

6

Data-out high-impedance time

t_HZ

Data-out low-impedance time

t_LZ

1

3

1

3

1

3

Data-out hold time (load) (26)

Data-out hold time (no load)

t_OH

t_OHN

t_RAS

t_RC

1.8

50

70

20

1.8

50

68

20

1.8

50

68

20

ACTIVE to PRECHARGE command

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

120,000

t_RCD

t_REF

t_RFC

t_RP

Refresh period (8,192 rows) – Commercial, Industrial

Refresh period (8,192 rows) – Military

AUTO REFRESH period

64

16

64

16

64

16

70

20

0.3

70

20

0.3

PRECHARGE command period

20

ACTIVE bank A to ACTIVE bank B command

Transition time (7)

t_RRD

t_T

20

0.3

1.2

(23)

(24)

1 CLK + 7ns

1 CLK + 7.5ns

WRITE recovery time

t_WR

15

80

15

80

15

75

Exit SELF REFRESH to ACTIVE command

t_XSR

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W364M72V-XSBX

AC FUNCTIONAL CHARACTERISTICS

(NOTES 5,6,7,8,9,11)

Parameter/Condition

Symbol

t_CCD

t_CKED

t_PED

-100

1

-125

1

-133

1

Units

t_CK

READ/WRITE command to READ/WRITE command (17)

CKE to clock disable or power-down entry mode (14)

CKE to clock enable or power-down exit setup mode (14)

DQM to input data delay (17)

1

t_DQD

t_DQM

t_DQZ

t_DWD

t_DAL

0

DQM to data mask during WRITEs

0

DQM to data high-impedance during READs

WRITE command to input data delay (17)

Data-in to ACTIVE command (15)

2

0

4

5

Data-in to PRECHARGE command (16)

Last data-in to burst STOP command (17)

Last data-in to new READ/WRITE command (17)

Last data-in to PRECHARGE command (16)

t_DPL

2

t_BDL

1

t_CDL

1

t_RDL

2

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

t_MRD

t_ROH

2

CL = 3

CL = 2

3

Data-out to high-impedance from PRECHARGE command (17)

NOTES:

2

—

1. All voltages referenced to V_SS

2. This parameter is not tested but guaranteed by design. f = 1 MHz, T_A= 25°C.

3. _CCis dependent on output loading and cycle rates. Speciﬁed values are obtained with minimum

cycle time and the outputs open.

.

12. Other input signals are allowed to transition no more than once every two clocks and are

otherwise at valid V_IHor V_ILlevels.

13. I_CCspeciﬁcations are tested after the device is properly initialized.

I

14. Timing actually speciﬁed by t_CKS; clock(s) speciﬁed as a reference only at minimum cycle rate.

4. Enables on-chip refresh and address counters.

15. Timing actually speciﬁed by t_WRplus t_RP; clock(s) speciﬁed as a reference only at minimum cycle

5. The minimum speciﬁcations are used only to indicate cycle time at which proper operation over

the full temperature range is ensured.

rate.

16. Timing actually speciﬁed by t_WR

.

6. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. (V_CCand V_CCQmust be powered up

simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time the

17. Required clocks are speciﬁed by JEDEC functionality and are not dependent on any timing

parameter.

18. The I_CCcurrent will decrease as the CAS latency is reduced. This is due to the fact that the

maximum cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

t_REFrefresh requirement is exceeded.

7. AC characteristics assume t_T= 1ns.

8. In addition to meeting the transition rate speciﬁcation, the clock and CKE must transit between V_IH

and V_IL(or between V_ILand V_IH) in a monotonic manner.

21.

V

_IHovershoot: V_IH(MAX) = V_CCQ+ 2V for a pulse width ≤ 3ns, and the pulse width cannot be

9. Outputs measured at 1.5V with equivalent load:

greater than one third of the cycle rate. V_ILundershoot: V_IL(MIN) = -2V for a pulse width ≤3ns.

22. The clock frequency must remain constant (stable clock is deﬁned as a signal cycling within

timing constraints speciﬁed for the clock pin) during access or precharge states (READ, WRITE,

including t_WR, and PRECHARGE commands). CKE may be used to reduce the data rate.

23. Auto precharge mode only. The precharge timing budget (t_RP) begins 7.5ns/7ns after the ﬁrst

clock delay, after the last WRITE is executed.

Q

50pF

24. Precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. Parameter guaranteed by design.

27. Self refresh available in commercial and industrial temperatures only.

10. t_HZdeﬁnes the time at which the output achieves the open circuit condition; it is not a reference to

V

_OHor V_OL. The last valid data element will meet t_OHbefore going High-Z.

11. AC timing and I_CCtests have V_IL= 0V and V_IH= 3V, with timing referenced to 1.5V crossover

point.

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Rev. 4

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W364M72V-XSBX

PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA), 32mm x 25mm

Bottom View

32.1 (1.264) MAX

1 2 3 4 5 6 7 8 9 10 111213141516

T

R

P

N

M

L

K

J

H

G

F

19.05 (0.750)

NOM

25.1 (0.988)

MAX

E

D

C

B

A

0.61

(0.024)

NOM

1.27 (0.050)

NOM

219 x Ø 0.762 (0.030) NOM

19.05 (0.750) NOM

2.96 (0.116)

MAX

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

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W364M72V-XSBX

ORDERING INFORMATION

W 3 64M 72 V - XXX SB X

MICROSEMI CORPORATION

SDRAM

CONFIGURATION, 64M x 72

3.3V Power Supply

FREQUENCY (MHz)

100 = 100MHz

125 = 125MHz

133 = 133MHz

PACKAGE:

SB = 219 Plastic Ball Grid Array (PBGA), 32mm x 25mm

Device Grade:

M = Military

-55°C to +125°C

-40°C to +85°C

I = Industrial

C = Commercial 0°C to +70°C

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

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W364M72V-XSBX

Document Title

64M x 72 SDRAM Multi-Chip Package, 32mm x 25mm

Revision History

Rev #

History

Release Date Status

Rev 0

Initial Release

May 2004

Advanced

Rev 1

Rev 2

Changes (Pg. 1, 5-15)

January 2005

Advanced

1.1 Added additional product data

Changes (Pg. 1, 10, 16)

September 2005

Preliminary

2.1 Update status to Preliminary

2.2 Update capacitance table values

2.3 Add 133MHz speed option

Rev 3

Rev 4

Changes (Pg. All)

January 2008

February 2011

Final

3.1 Update status to Final

3.2 Add 133 MHz data to table 2 CAS Latency

Changes (Pg. 1-14)

4.1 Change document layout from White Electronic Designs to Microsemi

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是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	包装说明：	BGA,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.4
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.5 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PBGA-B219
内存密度：	4831838208 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	72	功能数量：	1
端口数量：	1	端子数量：	219
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64MX72
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

型号	制造商	描述	价格	文档
W364M72V-133SBM	MICROSEMI	Synchronous DRAM, 64MX72, 5.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219	获取价格
W364M72V-ESSB	WEDC	64Mx72 Synchronous DRAM	获取价格
W364M72V-ESSBC	WEDC	64Mx72 Synchronous DRAM	获取价格
W364M72V-ESSBI	WEDC	64Mx72 Synchronous DRAM	获取价格
W364M72V-ESSBM	WEDC	64Mx72 Synchronous DRAM	获取价格
W364M72V-XSBX	WEDC	64Mx72 Synchronous DRAM	获取价格
W3697VC160	LITTELFUSE	Rectifier Diode, 1 Phase, 1 Element, 3697A, 1600V V(RRM), Silicon,	获取价格
W3697VC180	LITTELFUSE	Rectifier Diode, 1 Phase, 1 Element, 3697A, 1800V V(RRM), Silicon,	获取价格
W3697VC200	LITTELFUSE	Rectifier Diode, 1 Phase, 1 Element, 3697A, 2000V V(RRM), Silicon,	获取价格
W3697VC220	LITTELFUSE	Rectifier Diode, 1 Phase, 1 Element, 3697A, 2200V V(RRM), Silicon,	获取价格

W364M72V-133SBI

W364M72V-133SBI 概述

W364M72V-133SBI 规格参数

W364M72V-133SBI 数据手册

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