W3H128M72E-533SBI_技术文档

W3H128M72E-XSBX

W3H128M72E-XNBX

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

 Commercial, Industrial and Military Temperature Ranges

 Organized as 128M x 72

FEATURES

 Data rate = 667, 533, 400

 Weight: W3H128M72E-XSBX - 4 grams max

 Weight: W3H128M72E-XNBX - TBD

 Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

• 1.0mm pitch

BENEFITS

 56% space savings vs. FBGA

 Core Supply Voltage = 1.8V ± 0.1V

 I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18 compatible)

 Differential data strobe (DQS, DQS#) per byte

 Internal, pipelined, double data rate architecture

 4-bit prefetch architecture

 Reduced part count

 50% I/O reduction vs FBGA

 Reduced trace lengths for lower parasitic capacitance

 Suitable for hi-reliability applications

 DLL for alignment of DQ and DQS transitions with clock

signal

* This product is subject to change without notice.

 Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

TYPICAL APPLICATION

 Programmable Burst lengths: 4 or 8

 Auto Refresh and Self Refresh Modes

 On Die Termination (ODT)

 Adjustable data – output drive strength

 Programmable CAS latency: 4, 5 or 6

 CK/CK# Termination options available

• 0 ohm, 20 ohm

RAM

DDR2/DDR3

W3X128M72-XBI

Host

FPGA/

Processor

 Posted CAS additive latency: 0, 1, 2, 3 or 4

 Write latency = Read latency - 1* t_CK

SSD (SLC)

MSM32/MSM64 (SATA BGA)

W7N16GVHxxBI (PATA BGA)

M400/M100/M50 (SATA, 2.5in)

FIGURE 1 – DENSITY COMPARISONS

CSP Approach (mm)

W3H128M72E-XXXX

S

A

V

I

N

G

S

11.5

22

84

FBGA

84

FBGA

84

FBGA

84

FBGA

84

FBGA

14.0

W3H128M72E-XXXX

16

Area

5 x 161mm²= 805mm²

5 x 84 balls = 420 balls

352mm²

56%

50%

I/O Count

208 Balls

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

1

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

CS#

WE#

RAS#

CAS#

CKE

CS# WE# RAS# CAS# CKE

ODT

A0-13

BA0-2

ODT

A0-13

BA0-2

DQ0

CK0

CK0#

CK

¥

CK#

LDM0

LDM

U0

UDM0

UDM

LDQS0

LDQS0#

UDQS0

UDQS0#

LDQS

LDQS#

UDQS

UDQS#

¥

DQ15

CS# WE# RAS# CAS# CKE

ODT

A0-13

BA0-2

CK

DQ0

¥

DQ16

¥

CK1

CK1#

CK#

LDM1

LDM

U1

¥

UDM1

UDM

LDQS1

LDQS1#

UDQS1

UDQS1#

LDQS

LDQS#

UDQS

UDQS#

DQ15

DQ31

CS# WE# RAS# CAS# CKE

ODT

A0-13

DQ0

¥

DQ32

¥

BA0-2

CK2

CK2#

CK

CK#

U2

LDM2

LDM

UDM2

UDM

LDQS2

LDQS2#

UDQS2

UDQS2#

LDQS

LDQS#

UDQS

UDQS#

¥

DQ15

DQ47

CS# WE# RAS# CAS# CKE

ODT

A0-13

DQ0

¥

DQ48

¥

BA0-2

CK3

CK3#

CK

CK#

LDM3

LDM

U3

¥

UDM3

UDM

LDQS3

LDQS3#

UDQS3

UDQS3#

LDQS

LDQS#

UDQS

UDQS#

DQ15

DQ63

CS# WE# RAS# CAS# CKE

ODT

A0-13

BA0-2

DQ0

DQ64

¥

CK4

CK4#

CK

CK#

LDM4

LDM

U4

VCC

UDM

LDQS4

LDQS4#

UDQS4

UDQS4#

LDQS

LDQS#

UDQS

UDQS#

¥

DQ7

DQ71

NOTE: USQS4 and UDQS4# require a 10KΩ pull up resistor.

UDM4 is internally tied to V_CC

.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

2

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www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 3 – PIN CONFIGURATION

TOP VIEW

1

2

3

4

5

6

7

8

9 10 11

V_CC

V_SS

V_CC

V_SS

V_CC

V_SS

V_CC

V_SS

A

B

C

D

E

F

V_CC

V_SS

NC

V_SS

V_CC

V_SS

DQ35

DQ52

LDM3

DQ38

UDM3

V_CC

NC

DQ34

DQ53

CK3

DQ37

CK3#

CK2#

DQ51

DQ36

LDM2

DQ54

DQ44

A6

NC

DQ50

CK2

DQ32

DQ33

DQ49

DQ60

DQ41

A10

NC

BA2

DQ59

DNU

V_SS

V_CC

V_SS

V_REF

V_SS

V_CC

V_SS

ODT

DQ39 LDQS2 LDQS3 DQ48

DQ43

DQ55

DQ63

DQ58

DQ56

DQ42 LDQS2# LDQS3#

DQ57 UDM2

DQ40

DQ61

DQ45

G

H

J

DQ46

A9

DQ62

V_CC

UDQS2# DQ47 UDQS2 UDQS3 UDQS3#

V_CC

V_SS

A3

A12

A1

A13

BA1

V_CC

V_SS

A0

A11

V_CC

V_SS

V_CC

K

L

V_CC

A2

A4

A8

V_CC

BA0

A5

A7

V_CC

UDQS1# UDQS1

UDQS0

DQ8

DQ10

DQ15

DQ24

DQ26

UDQS0#

DQ31

DQ23

DQ7

DQ18

RAS#

CS#

DQ30

UDM0

DQ27

DQ14

DQ25

DQ11

DQ9

DQ28

DQ17

DQ1

DQ12

DQ22

LDM0

DQ4

DQ19

DQ68

V_SS

UDM1

DQ6

LDM1

DQ20

DQ3

M

N

P

R

T

DQ13

DQ29

LDQS1# LDQS0#

DQ0

CK0

V_SS

DQ16 LDQS1 LDQS0

LDQS4# UDQS4 UDQS4#

CK0#

CK1#

V_SS

DQ5

CK1

CK4#

V_SS

DQ21

DQ2

CK4

V_CC

LDQS4

CAS#

DQ66

V_SS

DQ71

DQ64

DQ69

Vcc

CKE

DQ70

LDM4

V_CC

WE#

DQ65

DQ67

V_SS

U

V

W

V_CC

V_SS

V_CC

V_SS

NOTE: UDQS4 and UDQS4# require a 10KΩ pull up resistor.

UDM4 is internally tied to Vcc

Balls F6 and E6 are reserved for A14 and A15 on future densities.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

3

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W3H128M72E-XSBX

W3H128M72E-XNBX

TABLE 1 – BALL DESCRIPTIONS

Symbol

Type

Description

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only

applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if

disabled via the LOAD MODE command.

ODT

Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge

of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

CK, CK#

Input

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The

speciﬁc circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁguration and operating mode. CKE LOW provides

PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE

is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during

self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V_CCis applied during ﬁrst power-up. After V_REFhas

become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For

proper SELF-REFRESH operation, V_REFmust be maintained.

CKE

Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when

CS# is registered HIGH.

CS#

Input

RAS#, CAS#, WE#

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a

WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of

DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4

LDM, UDM

BA0–BA2

Input

Bank address inputs: BA0–BA2 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–

BA2 deﬁne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10

HIGH) The address inputs also provide the op-code during a LOAD MODE command.

A0-A13

Input

DQ0-71

I/O

Data input/output: Bidirectional data bus

Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

UDQS, UDQS#

Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

LDQS, LDQS#

I/O

V_CC

V_REF

V_SS

Supply

Power Supply: I/O + core, V_CCQis common to V_CC

SSTL_18 reference voltage.

Supply

Ground

NC

-

No connect: These balls should be left unconnected.

Future use; address bits A14 and A15 are reserved for future densities.

DNU

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

4

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

DESCRIPTION

GENERAL NOTES

The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-

access memory containing ﬁve 2Gb 2, 147, 483, 648 bits chips.

Each of the ﬁve chips in the MCP are internally conﬁgured as

8-bank DRAM. The block diagram of the device is shown in Figure

2. Ball assignments and are shown in Figure 3.

The functionality and the timing speciﬁcations discussed in this

data sheet are for the DLL-enabled mode of operation.

Throughout the data sheet, the various ﬁgures and text refer to

DQs as “DQ.” The DQ term is to be interpreted as any and all

DQ collectively, unless speciﬁcally stated otherwise. Additionally,

each chip is divided into 2 bytes, the lower byte and upper byte.

For the lower byte (DQ0–DQ7), DM refers to LDM and DQS

refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to

UDM and DQS refers to UDQS. Note that the there is no upper

byte for U4 and therefore no UDM4.

The 8Gb DDR2 SDRAM uses a double-data-rate architecture to

achieve high-speed operation. The double data rate architecture is

essentially a 4n-prefetch architecture, with an interface designed

to transfer two data words per clock cycle at the I/O balls. A single

read or write access for the 8Gb DDR2 SDRAM effectively consists

of a single 4n-bit-wide, one-clock-cycle data transfer at the internal

DRAM core and four corresponding n-bit-wide, one-half-clock-cycle

data transfers at the I/O balls.

Complete functionality is described throughout the document

and any page or diagram may have been simpliﬁed to convey a

topic and may not be inclusive of all requirements.

A bidirectional data strobe (DQS, DQS#) is transmitted externally,

along with data, for use in data capture at the receiver. DQS is a

strobe transmitted by the DDR2 SDRAM during READs and by

the memory controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for WRITEs. There

are strobes, one for the lower byte (LDQS, LDQS#) and one for

the upper byte (UDQS, UDQS#).

Any speciﬁc requirement takes precedence over a general

statement.

INITIALIZATION

DDR2 SDRAMs must be powered up and initialized in a

predeﬁned manner. Operational procedures other than those

speciﬁed may result in undeﬁned operation. The following

sequence is required for power up and initialization and is

shown in Figure 4 on page 7.

The 8Gb DDR2 SDRAM operates from a differential clock (CK and

CK#); the crossing of CK going HIGH and CK# going LOW will

be referred to as the positive edge of CK. Commands (address

and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin

with the registration of anACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered coincident

with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write

burst lengths of four or eight locations. DDR2 SDRAM supports

interrupting a burst read of eight with another read, or a burst

write of eight with another write. An auto precharge function may

be enabled to provide a self-timed row precharge that is initiated

at the end of the burst access.

As with standard DDR SDRAMs, the pipelined, multibank

architecture of DDR2 SDRAMs allows for concurrent operation,

thereby providing high, effective bandwidth by hiding row precharge

and activation time.

Aself refresh mode is provided, along with a power-saving power-

down mode.

All inputs are compatible with the JEDEC standard for SSTL_18.

All full drive-strength outputs are SSTL_18-compatible.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

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W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 4 – POWER-UP AND INITIALIZATION

VCC

V

CC

Q

1

^tVTD¹

V

TT

V

REF

Tk0

Tl0

Tm0

Tg0

Th0

Ti0

Tj0

Te0

Tf0

Tc0

Td0

Tb0

T0

Ta0

t

CK

CK#

CK

t

CL

See

note

3

SSTL_18

LOW LEVEL⁸

LVCMOS

CKE LOW LEVEL⁸

ODT

COMMAND

LM

REF

LM

VALID³

2

LM

PRE

LM

PRE

LM

REF

NOP

DM⁷

9

ADDRESS

CODE

A10 = 1

CODE

A10 = 1

VALID

High-Z

7

DQS

DQ⁷

High-Z

RTT

t

MRD

T = 200μs (MIN)

Power-up:

CC and stable

clock (CK, CK#)

t

MRD

t

T = 400ns

(MIN)

RPA

MRD

EMR with

DLL ENABLE⁵

RPA

RFC

MRD

Seenote4

V

EMR(2)

EMR(3)

MRw/o

EMR with

DLL RESET OCD Default

EMR with

10

11

OCD Exit

Normal

Operation

3

200 cycles of CK

MR with

DLL RESET

Indicates a break in

time scale

DON’T CARE

NOTES:

1. Applying power; if CKE is maintained below 0.2 x V_CCQ, outputs remain disabled. To guarantee

_TT(ODT resistance) is off, V_REFmust be valid and a low level must be applied to the ODT ball

3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR =

extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode register

3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE

= desired value for mode registers (blank addresses are required to be decoded), VALID - any

valid command/address, RA = row address, bank address.

R

(all other inputs may be undeﬁned, I/Os and outputs must be less than V_CCQduring voltage ramp

time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions

(A or B) must be met to obtain a stable supply state (stable supply deﬁned as V_CC, V_CCQ,V_REF

,

and V_TTare between their minimum and maximum values as stated in DC Operating Conditions

table):

4. DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS#,

DQ represents DQ0-71.

A. (single power source) The V_CCvoltage ramp from 300mV to V_{CC (MIN)}must take no longer

than 200ms; during the V_CCvoltage ramp, |V_CC- V_CCQ| ≤ 0.3V. Once supply voltage ramping

is complete (when V_CCQcrosses V_{CC (MIN)}, DC Operating Conditions table speciﬁcations

apply.

5. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT

commands, then take CKE HIGH.

6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.

7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command, provide LOW to

BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or "1;" all others must be "0".

8. Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command, provide HIGH to

BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".

•

V

_CC, V_CCQare driven from a single power converter output

_TTis limited to 0.95V MAX

_REFtracks V_CCQ/2; V_REFmust be within ±0.3V with respect to V_CCQ/2during supply ramp

time.

V_CCQ≥ V_REFat all times

B. (multiple power sources) V_CC≥ V_CCQmust be maintained during supply voltage ramping,

9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL ENABLE command

provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits E7, E8 and E9 can be set to "0" or

"1;" Micron recommends setting them to "0".

•

for both AC and DC levels, until supply voltage ramping completes (V_CCQcrosses

10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock the

DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2 = BA1 = BA0 = 0.)

CKE must be HIGH the entire time. .

V_CC[MIN]). Once supply voltage ramping is complete, DC Operating Conditions table

speciﬁcations apply.

•

Apply V_CCbefore or at the same time as V_CCQ; V_CCvoltage ramp time must be ≤ 200ms

from when V_CCramps from 300mV to V_{CC (MIN)}

Apply V_CCQbefore or at the same time as V_TT; the V_CCQvoltage ramp time from when

11. Issue PRECHARGE ALL command.

12. Issue two or more REFRESH commands.

13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program

operating parameters without resetting the DLL). To access the mode registers, BA0 = 0, BA1 =

0, BA2 = 0.

14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and

E9 to “1,” and then setting all other desired parameters. To access the extended mode register,

BA2 = 0, BA1 = 0, BA0 = 1.

15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to

“0,” and then setting all other desired parameters. To access the extended mode registers, BA2

= 0, BA1 = 0, BA0 = 1.

16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the

DLL RESET at Tf0.

V_{CC (MIN)}is achieved to when V_{CCQ (MIN)}is achieved must be ≤ 500ms; while V_CCis

ramping, current can be supplied from V_CCthrough the device to V_CCQ

V_REFmust track V_CCQ/2, V_REFmust be within ±0.3V with respect to V_CCQ/2during supply

ramp time; V_CCQ≥ V_REFmust be met at all times

Apply V_TT; The V_TTvoltage ramp time from when V_{CCQ (MIN)}is achieved to when _{VTT (MIN)}

is achieved must be no greater than 500ms

•

2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-

up prior to V_REF. being stable. After state T0, Cke is required to have SSTL_18 input levels.

Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization

sequence.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

6

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 5 – MODE REGISTER (MR) DEFINITION

MODE REGISTER (MR)

The mode register is used to deﬁne the speciﬁc mode of operation

of the DDR2 SDRAM. This deﬁnition includes the selection of a

burst length, burst type, CL, operating mode, DLL RESET, write

recovery, and power-down mode, as shown in Figure 5. Contents of

the mode register can be altered by re-executing the LOAD MODE

(LM) command. If the user chooses to modify only a subset of the

MR variables, all variables (M0–M14) must be programmed when

the command is issued.

BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Mode Register (Mx)

MR

0

PD

WR

DLL TM CAS# Latency BT Burst Length

Mode

Normal

Test

M7

0

The mode register is programmed via the LM command (bits

BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will retain the stored

information until it is programmed again or the device loses power

(except for bit M8, which is self-clearing). Reprogramming the

mode register will not alter the contents of the memory array,

provided it is performed correctly.

M2 M1 M0

Burst Length

Reserved

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PD mode

Fast Exit

(Normal)

Slow Exit

M12

0

DLL Reset

No

M8

0

8

1

Reserved

1

Yes

(Low Power)

The LM command can only be issued (or reissued) when all

banks are in the precharged state (idle state) and no bursts are in

progress. The controller must wait the speciﬁed time t_MRDbefore

initiating any subsequent operations such as anACTIVE command.

Violating either of these requirements will result in unspeciﬁed

operation.

WRITE RECOVERY

M11 M10 M9

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

Burst Type

Sequential

Interleaved

M3

0

3

4

1

5

6

CAS Latency (CL)

M6 M5 M4

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BURST LENGTH

Reserved

Burst length is deﬁned by bits M0–M3, as shown in Figure 5. Read

and write accesses to the DDR2 SDRAM are burst-oriented, with

the burst length being programmable to either four or eight. The

burst length dete rmines the maximum number of column locations

that can be accessed for a given READ or WRITE command.

Reserved

Mode Register Definition

Mode Register (MR)

M17 M16 M15

3

0

1

0

1

0

1

4

Extended Mode Register (EMR)

5

6

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

Reserved

When a READ or WRITE command is issued, a block of columns

equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst

will wrap within the block if a boundary is reached. The block is

uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =

8 (where Ai is the most signiﬁcant column address bit for a given

conﬁguration). The remaining (least signiﬁcant) address bit(s)

is (are) used to select the starting location within the block. The

programmed burst length applies to both READ and WRITE bursts.

NOTE: Not all listed CL options are supported in any individual speed grades.

BURST TYPE

Accesses within a given burst may be programmed to be either

sequential or interleaved. The burst type is selected via bit M3,

as shown in Figure 5. The ordering of accesses within a burst is

determined by the burst length, the burst type, and the starting

column address, as shown in Table 2. DDR2 SDRAM supports

4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,

full interleave address ordering is supported; however, sequential

address ordering is nibble-based.

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WR values of 2, 3, 4, 5, or 6 clocks may be used for programming

bits M9–M11. The user is required to program the value of WR,

which is calculated by dividing t_WR(in ns) by t_CK(in ns) and rounding

up a non integer value to the next integer; WR [cycles] = t_WR[ns] /

TABLE 2 – BURST DEFINITION

Order of Accesses Within a Burst

Burst

Length

Starting Column

Address

Type = Sequential

Type = Interleaved

A1

0

A0

t

_CK[ns]. Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

0

1

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

4

0

POWER-DOWN MODE

1

0

Active power-down (PD) mode is deﬁned by bit M12, as shown

in Figure 5. PD mode allows the user to determine the active

power-down mode, which determines performance versus power

savings. PD mode bit M12 does not apply to precharge PD mode.

1

A2

0

A1

0

A0

0

0-1-2-3-4-5-6-7

1-2-3-0-5-6-7-4

2-3-0-1-6-7-4-5

3-0-1-2-7-4-5-6

4-5-6-7-0-1-2-3

5-6-7-4-1-2-3-0

6-7-4-5-2-3-0-1

7-4-5-6-3-0-1-2

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

0

1

When bit M12 = 0, standard active PD mode or “fast-exit” active PD

mode is enabled. The t_XARDparameter is used for fast-exit active

PD exit timing. The DLL is expected to be enabled and running

during this mode.

0

1

0

8

0

1

0

1

0

1

When bit M12 = 1, a lower-power active PD mode or “slow-exit”

active PD mode is enabled. The t_XARDparameter is used for slow-

exit active PD exit timing. The DLL can be enabled, but “frozen”

during active PD mode since the exit-to-READ command timing is

relaxed. The power difference expected between PD normal and

PD low-power mode is deﬁned in the I_CCtable.

1

0

1

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column

within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column

within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting

column within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

OPERATING MODE

The normal operating mode is selected by issuing a command

with bit M7 set to “0,” and all other bits set to the desired values,

as shown in Figure 5. When bit M7 is “1,” no other bits of the

mode register are programmed. Programming bit M7 to “1” places

the DDR2 SDRAM into a test mode that is only used by the

manufacturer and should not be used. No operation or functionality

is guaranteed if M7 bit is ‘1.’

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 5.

Programming bit M8 to “1” will activate the DLL RESET function.

Bit M8 is self-clearing, meaning it returns back to a value of “0”

after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must

occur before a READ command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing

to wait for synchronization to occur may result in a violation of the

t

_ACor t_DQSCKparameters.

WRITE RECOVERY

Write recovery (WR) time is deﬁned by bits M9–M11, as shown in

Figure 5. The WR register is used by the DDR2 SDRAM during

WRITE with auto precharge operation. During WRITE with auto

precharge operation, the DDR2 SDRAM delays the internal auto

precharge operation by WR clocks (programmed in bits M9–M11)

from the last data burst.

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CAS LATENCY (CL)

The CAS latency (CL) is deﬁned by bits M4–M6, as shown in Figure

5. CL is the delay, in clock cycles, between the registration of a

READ command and the availability of the ﬁrst bit of output data.

The CL can be set to 4, 5 or 6 clocks, depending on the speed

grade option being used.

DDR2 SDRAM also supports a feature called posted CAS additive

latency (AL). This feature allows the READ command to be issued

prior to t_{RCD (MIN)}by delaying the internal command to the DDR2

SDRAM by AL clocks.

An example of CL = 4 is shown in Figure 6; assume AL = 0. If a

READ command is registered at clock edge n, and the CL is m

clocks, the data will be available nominally coincident with clock

edge n+m (this assumes AL = 0).

DDR2 SDRAM does not support any half-clock latencies. Reserved

states should not be used as unknown operation or incompatibility

with future versions may result.

FIGURE 6 – CAS LATENCY (CL)

T0

T1

T2

T3

T4

T5

T6

CK#

CK

READ

NOP

COMMAND

DQS, DQS#

D

OUT

D

OUT

D

OUT

DOUT

n + 3

DQ

n

n + 1

n + 2

CL = 4 (AL = 0)

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal t_AC, t_DQSCKand t_DQSQ

TRANSITIONING DATA

DON’T CARE

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EXTENDED MODE REGISTER (EMR)

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are

DLL enable/disable, output drive strength, on die termination

(ODT) (RTT), posted AL, off-chip driver impedance calibration

(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,

and output disable/enable. These functions are controlled via the

bits shown in Figure 7. The EMR is programmed via the LOAD

MODE (LM) command and will retain the stored information until it

is programmed again or the device loses power. Reprogramming

the EMR will not alter the contents of the memory array, provided

it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the speciﬁed time t_MRD

before initiating any subsequent operation. Violating either of these

requirements could result in unspeciﬁed operation.

FIGURE 7 – EXTENDED MODE REGISTER DEFINITION

BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

Extended Mode

Register (Ex)

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

RDQS DQS# OCD Program R_{TT Posted CAS#}R_{TT ODS DLL}

0 out

MRS

0

Outputs

Enabled

Disabled

E0

DLL Enable

Enable (Normal)

Disable (Test/Debug)

E12

0

1

R_TT(nominal)

E6 E2

1

R

_TTdisabled

75Ω

0

1

0

1

0

1

RDQS Enable

150Ω

E11

0

E1

0

Output Drive Strength

Full strength (18Ω target)

No

50Ω

1

Yes

1

Reduced strength (40Ω target)

E10 DQS# Enable

E5 E4 E3 Posted CAS# Additive Latency (AL)

0

1

Enable

Disable

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

E9 E8 E7

OCD Operation

OCD not supported¹

3

0

1

0

1

0

1

0

1

0

1

4

Reserved

OCD default state¹

E17 E16 E15

Mode Register Set

Mode register set (MRS)

0

1

0

1

0

1

Extended mode register (EMRS)

Extended mode register (EMRS2)

Extended mode register (EMRS3)

NOTES:

1.

During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before

initialization is ﬁnished, as detailed in the initialization procedure.

E14 (A14) is not used on this device.

2..

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resistance value is elected by enabling switch “sw1,” which enables

all R1 values that are 150Ω each, enabling an effective resistance

of 75Ω (R_TT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2

values that are 300Ω each, enable an effective ODT resistance

of 150Ω (R_TT2(EFF) = R2/2). Switch “sw3” enables R1 values of

100Ω enabling effective resistance of 50Ω Reserved states should

not be used, as unknown operation or incompatibility with future

versions may result.

DLL ENABLE/DISABLE

The DLL may be enabled or disabled by programming bit E0

during the LM command, as shown in Figure 7. The DLL must

be enabled for normal operation. DLL enable is required during

power-up initialization and upon returning to normal operation after

having disabled the DLLfor the purpose of debugging or evaluation.

Enabling the DLL should always be followed by resetting the DLL

using an LM command.

The ODT control ball is used to determine when R_TT(EFF) is turned

on and off, assuming ODT has been enabled via bits E2 and E6 of

the EMR. The ODT feature and ODT input ball are only used during

active, active power-down (both fast-exit and slow-exit modes), and

precharge power-down modes of operation. ODT must be turned

off prior to entering self refresh. During power-up and initialization

of the DDR2 SDRAM, ODT should be disabled until issuing the

EMR command to enable the ODT feature, at which point the ODT

ball will determine the R_TT(EFF) value. Any time the EMR enables

the ODT function, ODT may not be driven HIGH until eight clocks

after the EMR has been enabled. See “ODT Timing” section for

ODT timing diagrams.

The DLL is automatically disabled when entering SELF REFRESH

operation and is automatically re-enabled and reset upon exit of

SELF REFRESH operation.

Any time the DLL is enabled (and subsequently reset), 200 clock

cycles must occur before a READ command can be issued, to

allow time for the internal clock to synchronize with the external

clock. Failing to wait for synchronization to occur may result in a

violation of the t_ACor t_DQSCKparameters.

OUTPUT DRIVE STRENGTH

The output drive strength is deﬁned by bit E1, as shown in Figure

7. The normal drive strength for all outputs are speciﬁed to be

SSTL_18. Programming bit E1 = 0 selects normal (full strength)

drive strength for all outputs. Selecting a reduced drive strength

option (E1 = 1) will reduce all outputs to approximately 60 percent of

the SSTL_18 drive strength. This option is intended for the support

of lighter load and/or point-to-point environments.

DQS# ENABLE/DISABLE

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is

the complement of the differential data strobe pair DQS/DQS#.

When disabled (E10 = 1), DQS is used in a single ended mode

and the DQS# ball is disabled. When disabled, DQS# should be

left ﬂoating. This function is also used to enable/disable RDQS#. If

RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then

both DQS# and RDQS# will be enabled.

OUTPUT ENABLE/DISABLE

The OUTPUT ENABLE function is deﬁned by bit E12, as shown in

Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,

RDQS, RDQS#) function normally. When disabled (E12 = 1), all

DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are

disabled, thus removing output buffer current. The output disable

feature is intended to be used during I_CCcharacterization of read

current.

ON-DIE TERMINATION (ODT)

ODT effective resistance, R_TT(EFF), is deﬁned by bits E2 and E6

of the EMR, as shown in Figure 7. The ODT feature is designed

to improve signal integrity of the memory channel by allowing the

DDR2 SDRAM controller to independently turn on/off ODT for

any or all devices. R_TTeffective resistance values of 50Ω ,75Ω,

and 150Ω are selectable and apply to each DQ, DQS/DQS#,

RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/

LDM signals. Bits (E6, E2) determine what ODT resistance is

enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective

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POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make the

command and data bus efﬁcient for sustainable bandwidths in

DDR2 SDRAM. Bits E3–E5 deﬁne the value of AL, as shown in

Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM

with an inverseAL of 0, 1, 2, 3, or 4 clocks. Reserved states should

not be used as unknown operation or incompatibility with future

versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE

command to be issued prior to t_{RCD (MIN)}with the requirement

that AL ≤ t_{RCD (MIN)}. A typical application using this feature would

set AL = t_{RCD (MIN)}- 1x t_CK. The READ or WRITE command is

held for the time of the AL before it is issued internally to the

DDR2 SDRAM device. RL is controlled by the sum of AL and CL;

RL = AL+CL. Write latency (WL) is equal to RL minus one clock;

WL = AL + CL - 1 x t_CK

.

FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION

BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

Extended Mode

Register (Ex)

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DQS# OCD Program R_TT

R

MRS

0

out RDQS

Posted CAS#

ODS DLL

TT

Mode Register Definition

Mode register (MR)

M17 M16 M15

High Temperature Self Refresh rate enable

Commercial temperature default

E7

0

1

0

1

0

1

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

Industrial temperature option;

use if T_Cexceeds 85°C

1

NOTE: 1. E14 (A14)-E8(A8) and E6 (A6) - E0 (A0) are reserved for future use and must be

programmed to "0." A14 is not used in this device.

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EMR3 must be loaded when all banks are idle and no bursts are

in progress, and the controller must wait the speciﬁed time t_MRD

before initiating any subsequent operation. Violating either of these

requirements could result in unspeciﬁed operation.

EXTENDED MODE REGISTER 2

The extended mode register 2 (EMR2) controls functions beyond

those controlled by the mode register. Currently all bits in EMR2

are reserved, as shown in Figure 8. The EMR2 is programmed

via the LM command and will retain the stored information until it

is programmed again or the device loses power. Reprogramming

the EMR will not alter the contents of the memory array, provided

it is performed correctly.

COMMAND TRUTH TABLES

The following tables provide a quick reference of DDR2 SDRAM

available commands, including CKE power-down modes, and

bank-to-bank commands.

Bit E7 (A7) must be programmed as"1" to provide a faster refresh

rate on devices if the T_CASEexceeds 85°C

EMR2 must be loaded when all banks are idle and no bursts are

in progress, and the controller must wait the speciﬁed time ^tMRD

before initiating any subsequent operation. Violating either of these

requirements could result in unspeciﬁed operation.

EXTENDED MODE REGISTER 3

The extended mode register 3 (EMR3) controls functions beyond

those controlled by the mode register. Currently, all bits in EMR3

are reserved, as shown in Figure 9. The EMR3 is programmed

via the LM command and will retain the stored information until it

is programmed again or the device loses power. Reprogramming

the EMR will not alter the contents of the memory array, provided

it is performed correctly.

FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION

BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

Extended Mode

Register (Ex)

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DQS# OCD Program R_TT

R_TT

ODS DLL

EMR3

0

out RDQS

Posted CAS#

M17 M16 M15

Mode Register Definition

Mode register (MR)

0

1

0

1

0

1

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

NOTE: 1. E14 (A14)-E0 (A0) are reserved for future use and must be programmed to "0." A14 is not used in this device.

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TABLE 3 – TRUTH TABLE - DDR2 COMMANDS

Notes 1, 5, and 6 apply to all

CKE

BA2

A13

Function

CS#

RAS#

CAS#

WE#

BA1

BA0

A12

A11

A10

A9-A0

Notes

Current Cycle

LOAD MODE

REFRESH

H

L

H

L

X

H

L

H

X

H

L

BA

X

OP Code

2

X

SELF-REFRESH Entry

L

X

H

SELF-REFRESH Exit

L

H

X

7

2

Single bank precharge

All banks PRECHARGE

Bank activate

H

X

L

H

X

L

BA

Row Address

Column

Address

Column

Address

WRITE

H

L

H

L

BA

L

H

L

2, 3

Column

Address

Column

Address

WRITE with auto precharge

READ

Column

Address

Column

Address

H

Column

Address

Column

Address

READ with auto precharge

H

NO OPERATION

H

X

L

H

L

H

X

H

X

H

X

H

X

H

X

H

X

H

X

Device DESELECT

POWER-DOWN entry

POWER-DOWN exit

H

L

X

4

H

L

H

NOTES:

1. All DDR2 SDRAM commands are deﬁned by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.

2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.

3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.

4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.

6. “X” means “H or L” (but a deﬁned logic level).

7. Self refresh exit is asynchronous.

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FIGURE 10 – ACTIVE COMMAND

DESELECT

The DESELECT function (CS# HIGH) prevents new commands

from being executed by the DDR2 SDRAM. The DDR2 SDRAM

is effectively deselected. Operations already in progress are not

affected.

CK#

CK

NO OPERATION (NOP)

CKE

CS#

The NO OPERATION (NOP) command is used to instruct the

selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,

CAS#, and WE are HIGH). This prevents unwanted commands

from being registered during idle or wait states. Operations already

in progress are not affected.

RAS#

CAS#

WE#

LOAD MODE (LM)

The mode registers are loaded via inputs BA2–BA0, andA12–A0.

BA2–BA0 determine which mode register will be programmed.

See “Mode Register (MR)”. The LM command can only be issued

when all banks are idle, and a subsequent execute able command

cannot be issued until t_MRDis met.

Row

ADDRESS

BANK ADDRESS

Bank

BANK/ROW ACTIVATION

ACTIVE COMMAND

DON’T CARE

The ACTIVE command is used to open (or activate) a row in a

particular bank for a subsequent access. The value on the BA2–

BA0 inputs selects the bank, and the address provided on inputs

A12–A0 selects the row. This row remains active (or open) for

accesses until a PRECHARGE command is issued to that bank. A

PRECHARGE command must be issued before opening a different

row in the same bank.

ACTIVE OPERATION

Before any READ or WRITE commands can be issued to a

bank within the DDR2 SDRAM, a row in that bank must be

opened (activated), even when additive latency is used. This is

accomplished via the ACTIVE command, which selects both the

bank and the row to be activated.

After a row is opened with an ACTIVE command, a READ or

WRITE command may be issued to that row, subject to the t_RCD

speciﬁcation. t_{RCD (MIN)}should be divided by the clock period and

rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or

WRITE command can be entered. The same procedure is used

to convert other speciﬁcation limits from time units to clock cycles.

For example, a t_{RCD (MIN)}speciﬁcation of 20ns with a 266 MHz clock

(t_CK= 3.75ns) results in 5.3 clocks, rounded up to 6.

A subsequent ACTIVE command to a different row in the same

bank can only be issued after the previous active row has

been closed (precharged). The minimum time interval between

successiveACTIVE commands to the same bank is deﬁned by t_RC

A subsequent ACTIVE command to another bank can be issued

while the ﬁrst bank is being accessed, which results in a reduction

of total row-access overhead. The minimum time interval between

successiveACTIVE commands to different banks is deﬁned by t_RRD

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FIGURE 11 – READ COMMAND

READ COMMAND

The READ command is used to initiate a burst read access to an

active row. The value on the BA2–BA0 inputs selects the bank,

and the address provided on inputs A0–i (where i = A9) selects

the starting column location. The value on input A10 determines

whether or not auto precharge is used. If auto precharge is

selected, the row being accessed will be precharged at the end

of the READ burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

CK#

CK

CKE

CS#

READ OPERATION

RAS#

CAS#

READ bursts are initiated with a READ command. The starting

column and bank addresses are provided with the READ command

and auto precharge is either enabled or disabled for that burst

access. If auto precharge is enabled, the row being accessed is

automatically precharged at the completion of the burst. If auto

precharge is disabled, the row will be left open after the completion

of the burst.

WE#

ADDRESS

Col

During READ bursts, the valid data-out element from the starting

column address will be available READ latency (RL) clocks later.

RL is deﬁned as the sum of AL and CL; RL = AL + CL. The value

forAL and CL are programmable via the MR and EMR commands,

respectively. Each subsequent data-out element will be valid

nominally at the next positive or negative clock edge (i.e., at the

next crossing of CK and CK#).

ENABLE

A10

AUTO PRECHARGE

BANK ADDRESS

DISABLE

Bank

DON’T CARE

DQS/DQS# is driven by the DDR2 SDRAM along with output data.

The initial LOW state on DQS and HIGH state on DQS# is known

as the read preamble (t_RPRE). The LOW state on DQS and HIGH

state on DQS# coincident with the last data-out element is known

as the read postamble (t_RPST).

Upon completion of a burst, assuming no other commands have

been initiated, the DQ will go High-Z.

Data from any READ burst may be concatenated with data from a

subsequent READ command to provide a continuous ﬂow of data.

The ﬁrst data element from the new burst follows the last element

of a completed burst. The new READ command should be issued x

cycles after the ﬁrst READ command, where x equals BL/ 2 cycles.

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Data for any WRITE burst may be concatenated with a subsequent

WRITE command to provide continuous ﬂow of input data. The ﬁrst

data element from the new burst is applied after the last element

of a completed burst. The new WRITE command should be issued

x cycles after the ﬁrst WRITE command, where x equals BL/2.

WRITE COMMAND

The WRITE command is used to initiate a burst write access to an

active row. The value on the BA2–BA0 inputs selects the bank,

and the address provided on inputs A0–9 selects the starting

column location. The value on input A10 determines whether or

not auto precharge is used. If auto precharge is selected, the

row being accessed will be precharged at the end of the WRITE

burst; if auto precharge is not selected, the row will remain open

for subsequent accesses.

DDR2 SDRAM supports concurrent auto precharge options, as

shown in Table 4.

DDR2 SDRAM does not allow interrupting or truncating any WRITE

burst using BL = 4 operation. Once the BL = 4 WRITE command is

registered, it must be allowed to complete the entire WRITE burst

cycle. However, a WRITE (with auto precharge disabled) using BL

= 8 operation might be interrupted and truncated ONLY by another

WRITE burst as long as the interruption occurs on a 4-bit boundary,

due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst

BL = 8 operations may not to be interrupted or truncated with any

command except another WRITE command.

Input data appearing on the DQ is written to the memory array

subject to the DM input logic level appearing coincident with the

data. If a given DM signal is registered LOW, the corresponding

data will be written to memory; if the DM signal is registered HIGH,

the corresponding data inputs will be ignored, and a WRITE will

not be executed to that byte/column location.

WRITE OPERATION

Data for any WRITE burst may be followed by a subsequent READ

command. The number of clock cycles required to meet t_WTRis

either 2 or t_WTR/t_CK, whichever is greater. Data for any WRITE burst

may be followed by a subsequent PRECHARGE command. t_WT

starts at the end of the data burst, regardless of the data mask

condition.

WRITE bursts are initiated with a WRITE command, as shown in

Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock

cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting column and

bank addresses are provided with the WRITE command, and auto

precharge is either enabled or disabled for that access. If auto

precharge is enabled, the row being accessed is precharged at

the completion of the burst.

During WRITE bursts, the first valid data-in element will be

registered on the ﬁrst rising edge of DQS following the WRITE

command, and subsequent data elements will be registered on

successive edges of DQS. The LOW state on DQS between the

WRITE command and the ﬁrst rising edge is known as the write

preamble; the LOW state on DQS following the last data-in element

is known as the write postamble.

The time between the WRITE command and the ﬁrst rising DQS

edge is WL ± t_DQSS. Subsequent DQS positive rising edges are

timed, relative to the associated clock edge, as ± t_DQSS. t_DQSSis

speciﬁed with a relatively wide range (25 percent of one clock

cycle). All of the WRITE diagrams show the nominal case, and

where the two extreme cases (t_DQSS[MIN] and t_DQSS[MAX]) might

not be intuitive, they have also been included. Upon completion of

a burst, assuming no other commands have been initiated, the DQ

will remain High-Z and any additional input data will be ignored.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

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FIGURE 12 – WRITE COMMAND

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

CA

ADDRESS

EN AP

A10

DIS AP

BANK ADDRESS

BA

DON’T CARE

NOTE: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.

TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE

Minimum Delay

(With Concurrent Auto Precharge)

From Command (Bank n)

To Command (Bank m)

Units

READ OR READ w/AP

WRITE or WRITE w/AP

PRECHARGE or ACTIVE

(CL-1) + (BL/2) + t_WTR

t_CK

WRITE with Auto Precharge

(BL/2)

1

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FIGURE 13 – PRECHARGE COMMAND

PRECHARGE COMMAND

The PRECHARGE command, illustrated in Figure 13, is used

to deactivate the open row in a particular bank or the open row

in all banks. The bank(s) will be available for a subsequent row

activation a speciﬁed time (t_RP) after the PRECHARGE command

is issued, except in the case of concurrent auto precharge, where

a READ or WRITE command to a different bank is allowed as long

as it does not interrupt the data transfer in the current bank and

does not violate any other timing parameters. Once a bank has

been precharged, it is in the idle state and must be activated prior

to any READ or WRITE commands being issued to that bank. A

PRECHARGE command is allowed if there is no open row in that

bank (idle state) or if the previously open row is already in the

process of precharging. However, the precharge period will be

determined by the last PRECHARGE command issued to the bank.

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

PRECHARGE OPERATION

InputA10 determines whether one or all banks are to be precharged,

and in the case where only one bank is to be precharged, inputs BA2–

BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.”

ADDRESS

A10

ALL BANKS

ONE BANK

BA

When all banks are to be precharged, inputs BA2–BA0 are treated

as “Don’t Care.” Once a bank has been precharged, it is in the

idle state and must be activated prior to any READ or WRITE

commands being issued to that bank. t_RPAtiming applies when the

PRECHARGE (ALL) command is issued, regardless of the number

of banks already open or closed. If a single-bank PRECHARGE

command is issued, t_RPtiming applies. t_{RPA (MIN)}applies to all

8-bank DDR2 devices.

BA0 - BA2

DON’T CARE

NOTE: BA = bank address (if A10 is LOW; otherwise "Don't Care").

SELF REFRESH COMMAND

The SELF REFRESH command can be used to retain data in the

DDR2 SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the DDR2 SDRAM retains data

without external clocking. All power supply inputs (including V_REF

)

must be maintained at valid levels upon entry/exit and during SELF

REFRESH operation.

The SELF REFRESH command is initiated like a REFRESH

command except CKE is LOW. The DLL is automatically disabled

upon entering self refresh and is automatically enabled upon exiting

self refresh (200 clock cycles must then occur before a READ

command can be issued). The differential clock should remain

stable and meet t_CKEspeciﬁcations at least 1 x t_CKafter entering

self refresh mode. All command and address input signals except

CKE are “Don’t Care” during self refresh.

The procedure for exiting self refresh requires a sequence of

commands. First, the differential clock must be stable and meet

t_CKspeciﬁcations at least 1 x t_CKprior to CKE going back HIGH.

Once CKE is HIGH (t_CLE(MIN)has been satisﬁed with four clock

registrations), the DDR2 SDRAM must have NOP or DESELECT

commands issued for t_XSNRbecause time is required for the

completion of any internal refresh in progress. A simple algorithm

for meeting both refresh and DLL requirements is to apply NOP

or DESELECT commands for 200 clock cycles before applying

any other command.

NOTE: Self refresh not available at military temperature.

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DC OPERATING CONDITIONS

All voltages referenced to V_SS

Parameter

Symbol

Min

1 .7

Typical

1 .8

Max

1 .9

Unit

V

Notes

1, 5

4, 5

2

Supply voltage

V_CC

V_CCL Supply voltage

I/O Supply voltage

I/O Reference voltage

I/O Termination voltage

NOTEs:

V_CCL

1.7

1.8

1.9

V

V_CCQ

V_REF

V_TT

1 .7

1 .8

1 .9

V

0.49 x V_CCQ

V_REF-0.04

0.50 x V_CCQ

V_REF

0.51 x V_CCQ

V_REF+ 0.04

V

3

1.

2.

V

_CCand V_CCQmust track each other. V_CCQmust be less than or equal to V_CC

_REFis expected to equal V_CCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on V_REFmay not exceed ±1 percent of the DC value. Peak-to-peak AC noise

.

on V_REFmay not exceed ±2 percent of V_REF. This measurement is to be taken at the nearest V_REFbypass capacitor.

3.

4.

5.

V

_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to V_REFand must track variations in the DC level of V_REF.

_CCQtracks with V_CC, V_CCL tracks with V_CC

.

_SSQ= V_SSL = V_SS

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

V_CC

MIN

-1.0

-0.5

-55

MAX

2.3

U nit

V

Voltage on V_CCpin relative to V_SS

Voltage on V_CCQpin relative to V_SS

Voltage on any pin relative to V_SS

Storage temperature

V_CCQ

2.3

V

V_IN, V_OUT

T_STG

2.3

V

125

°C

Input leakage current; Any input 0V<V_IN<V_CC; V_REFinput 0V<V_IN<0.95V; Other pins

not under test = 0V

I_L

-25

25

μA

Output leakage current;

0V<V_OUT<V_CCQ; DQs and ODT are disable

I_OZ

-25

-10

25

10

μA

I_VREF

V_REFleakage current; V_REF= Valid V_REFlevel

INPUT/OUTPUT CAPACITANCE

T_A= 25°C, f = 1MHz, V_CC= V_CCQ= 1.8V

Parameter

Symbol

C_IN1

Max

24

Unit

pF

Input capacitance (A0 - A12, BA0 - BA2 ,CS#, RAS#, CAS#, WE#, CKE, ODT)

Input capacitance CK, CK#

C_IN2

9.5

pF

Input capacitance DM, DQS, DQS#

C_IN3

10.5

pF

Input capacitance DQ0 - 71

C_OUT

pF

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W3H128M72E-XSBX

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BGA THERMAL RESISTANCE

Description

Symbol

Theta JA

Theta JB

Theta JC

Typical

19.7

Units

°C/W

Notes

Junction to Ambient (No Airﬂow)

Junction to Ball

1

20.6

Junction to Case (Top)

10.8

INPUT DC LOGIC LEVEL

All voltages referenced to V_SS

Parameter

Symbol

V_IH(DC)

V_IL(DC)

Min

Max

Unit

V

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

V_REF+ 0.1 25

-0.300

V_CCQ+ 0.300

V_REF- 0.125

V

INPUT AC LOGIC LEVEL

All voltages referenced to V_SS

Parameter

Symbol

V_IH(AC)

V_IL(AC)

Min

Max

—

Unit

V

AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533

AC Input High (Logic 1) Voltage DDR2-667

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533

AC Input Low (Logic 0) Voltage DDR2-667

V_REF+ 0.250

V_REF+ 0.200

—

V

—

V_REF- 0.250

V_REF- 0.200

V

ODT DC ELECTRICAL CHARACTERISTICS

All voltages referenced to V_SS

Parameter

Symbol

R_TT1_(EFF)

R_TT2_(EFF)

R_TT3_(EFF)

∆VM

Min

52

Nom

75

Max

97

Unit

Ω

Notes

R_TTeffective impedance value for 75Ω setting EMR (A6, A2) = 0, 1

1

2

R

_TTeffective impedance value for 150Ω setting EMR (A6, A2) = 1, 0

_TTeffective impedance value for 50Ω setting EMR (A6, A2) = 1, 1

105

35

150

50

195

65

Ω

R

Ω

Deviation of VM with respect to V_CCQ/2

-6

6

%

NOTE: 1. R_TT1_(EFF)and R_TT2_(EFF)are determined by separately applying V_IH(AC)and V_{IL (AC)}to the ball being tested, and then measuring current, I(V_IH(AC)), and I(V_IL(AC)), respectively.

R_TT(EFF)

=

V_IH(AC)- V_IL(AC)

I(V_IH(AC)) - I(V_IL(AC)

)

2. Measure voltage (VM) at tested ball with no load

∆VM =

(

2 x VM - 1

V_CC

)

x 100

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DDR2 I_CCSPECIFICATIONS AND CONDITIONS

V_CC= 1.8V ±0.1V; -55°C ≤ T_A≤ 125°C

Symbol

Proposed Conditions

667 CL6 533 CL5 400 CL4

Units

Operating one bank active-precharge current;

I_CC0

t_CK= t_CK(I_CC), t_RC= t_RC(I_CC), t_RAS= t_RASmin(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

675

800

55

575

675

55

574

675

55

mA

Operating one bank active-read-precharge current;

I_CC1

I_CC2P

I_CC2Q

I_CC2N

I_OUT= 0mA; BL = 4, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RC= t_RC(I_CC), t_RAS= t_RASmin(I_CC), t_RCD= t_RCD(I_CC); CKE is

mA

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as I_DAD6W

Precharge power-down current;

All banks idle; t_CK= t_CK(I_CC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Precharge quiet standby current;

All banks idle; t_CK= t_CK(I_CC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

325

350

225

300

200

250

Precharge standby current;

All banks idle; t_CK= t_CK(I_CC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active power-down current;

All banks open; t_CK= t_CK(I_CC); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

200

50

175

50

150

50

mA

I_CC3P

Active standby current;

I_CC3N

All banks open; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC), t_RP= t_RP(I_CC); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

375

275

950

250

800

mA

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC), t_RP= t_RP(I_CC);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

I_CC4W

1,250

Operating burst read current;

All banks open, Continuous burst reads, I_OUT= 0mA; BL = 4, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC),

t_RP= t_RP(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data

pattern is same as I_DAD6W

I_CC4R

1,375

975

900

mA

Burst auto refresh current;

I_CC5

t

_CK= t_CK(I_CC); Refresh command at every t_RFC(I_CC) interval; CKE is HIGH, CS# is HIGH between valid commands;

1,400

45

1,300

45

1,250

45

mA

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs

are FLOATING; Data bus inputs are FLOATING

I_CC6

Normal

Operating bank interleave read current;

All bank interleaving reads, I_OUT= 0mA; BL = 4, CL = CL(I_CC), AL = t_RCD(I_CC)-1*t_CK(I_CC); t_CK= t_CK(I_CC), t_RC= t_RC(I_CC),

_RRD= t_RRD(I_CC), t_RCD= 1*t_CK(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

I_CC7

t

1,975

1,775

mA

are STABLE during DESELECTs; Data pattern is same as I_DAD6R; Refer to the following page for detailed timing

conditions

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W3H128M72E-XSBX

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AC TIMING PARAMETERS

-55°C ≤ T_A≤ +125°C; V_CCQ= + 1.8V ± 0.1V, V_CC= +1.8V ± 0.1V

667Mbs CL6

Min

533Mbs CL5

400Mbs CL4

Unit

Parameter

Symbol

Max

8,000

0.52

Min

Max

Min

Max

CL=6

CL=5

CL=4

t_CK(6)

3,000

Clock cycle time

t

_CK(5)

_CK(6)

t_CH

3,750

5,000

8,000

0.52

5,000

8,000

0.52

ps

t_CK

ps

5,000

CK high-level width

CK low-level width

Half clock period

0.48

t_CL

0.48

0.52

0.48

0.52

0.48

0.52

t_HP

MIN (t_CH, t_CL)

AVG

t_CK

abs

PER

DTY

PER

DTY

PER

Absolute ^tCK

t_CK

_(MIN)+ t_JIT

_(MAX)+ t_JIT

_(MIN)+ t_JIT

_(MAX)+ t_JIT

_(MIN)+ t_JIT

_(MAX)+ t_JIT

ps

(MIN)

(MAX)

(MIN)

(MAX)

(MIN)

(MAX)

AVG

t_CK

AVG

t_CK

*

(MAX)

AVG

DTY

_(MIN)* t_CH

_(MIN)+ t_JIT

_(MIN)* t_CH

_(MIN)+ t_JIT

_(MIN)* t_CH

_(MIN)+ t_JIT

_(MAX)* t_CH

_(MAX)+ t_JIT

abs

AVG

Absolute CK high-level width

t_CH

ps

DTY

_(MAX)+ t_JIT

(MIN)

(MAX)

AVG

t_CK

*

(MIN)

AVG

(MAX)

AVG

(MIN)

AVG

(MAX)

AVG

(MIN)

AVG

(MAX)

AVG

abs

Absolute CK low-level width

t_CL

ps

DTY

_(MIN)+ t_JIT

_(MAX)+ t_JIT

_(MIN)+ t_JIT

_(MAX)+ t_JIT

_(MIN)+ t_JIT

_(MAX)+ t_JIT

(MIN)

-125

(MAX)

(MIN)

-125

(MAX)

(MIN)

-125

(MAX)

PER

Clock jitter - period

t_JIT

125

ps

DUTY

Clock jitter - half period

t_JIT

CC

Clock jitter - cycle to cycle

t_JIT

250

Cumulative jitter error, 2 cycles

Cumulative jitter error, 3 cycles

Cumulative jitter error, 4 cycles

Cumulative jitter error, 5 cycles

Cumulative jitter error, 6-10 cycles

Cumulative jitter error, 11-50 cycles

t_ERR2per

t_ERR3per

-175

-225

-250

-350

-450

175

225

250

350

450

-175

-225

-250

-350

-450

175

225

250

350

450

-175

-225

-250

-350

-450

175

225

250

350

450

t_ERR4per

t_ERR5per

t_ERR6-10per

t_ERR11-50per

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AC TIMING PARAMETERS (continued)

-55°C ≤ T_A≤ +125°C; V_CCQ= + 1.8V ± 0.1V, V_CC= +1.8V ± 0.1V

667Mbs CL6

533Mbs CL5

400Mbs CL4

Unit

Parameter

DQ hold skew factor

Symbol

Min

Max

400

Min

-

Max

400

Min

Max

t_QHS

t_AC

-

450

ps

DQ output access time from CK/CK#

Data-out high impedance window from CK/CK#

DQS Low-Z window from CK/CK#

DQ Low-Z window from CK/CK#

-100

1,250

t_AC(MAX)

-100

1,350

t_AC(MAX)

-100

1,350

t_AC(MAX)

t_HZ

1

t_LZ

t_AC(MN)

2*t_AC(MN)

400

t_AC(MN)

2*t_AC(MN)

400

t_AC(MN)

2*t_AC(MN)

400

2

t_LZ

t_DSa

t_DHa

t_DSb

t_DHb

t_DIPW

t_QHS

350

400

DQ and DM input setup time relative to DQS

100

150

225

275

DQ and DM input pulse width (for each input)

Data hold skew factor

0.35

400

450

DQ-DQS hold, DQS to ﬁrst DQ to go nonvalid, per

access

t_QH

t_HP- t_QHS

ps

Data valid output window (DVW)

DQS input high pulse width

t_DVW

t_DQSH

t_DQSL

t_DQSCK

t_DSS

t_QH- t_DQSQ

0.35*t_CK

-100

t_QH- t_DQSQ

0.35*t_CK

-100

t_QH- t_DQSQ

0.35*t_CK

-100

ns

t_CK

ps

DQS input low pulse width

DQS output access time fromCK/CK#

DQS falling edge to CK rising - setup time

DQS falling edge from CK rising - hold time

1,250

240

1,350

300

1,350

350

0.2*t_CK

t_CK

t_DSH

DQS-DQ skew, DOS to last DQ valid, per group, per

access

t_DQSQ

ps

DQS read preamble

t_RPRE

t_RPST

0.9*t_CK

0.4*t_CK

0

1.1*t_CK

0.6*t_CK

0.9*t_CK

0.4*t_CK

0

1.1*t_CK

0.6*t_CK

0.9*t_CK

0.4*t_CK

0

1.1*t_CK

0.6*t_CK

t_CK

ps

DQS read postamble

DQS write preamble setup time

t_WPRES

DQS write preamble

t_WPRE

0.35*t_CK

0.25*t_CK

0.25

t_CK

DQS write postamble

t_WPST

t_DQSS

0.4*t_CK

-0.25*t_CK

WL-T_DQSS

0.6*t_CK

0.25*t_CK

0.4*t_CK

-0.25*t_CK

WL-T_DQSS

0.6*t_CK

0.25*t_CK

0.4*t_CK

-0.25*t_CK

WL-T_DQSS

0.6*t_CK

0.25*t_CK

t_CK

Positive DQS latching edge to associated clock edge

Write command to ﬁrst DQS latching transition

WL+T_DQSS

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

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W3H128M72E-XSBX

W3H128M72E-XNBX

AC TIMING PARAMETERS (continued)

-55°C ≤ T_A≤ +125°C; V_CCQ= + 1.8V ± 0.1V, V_CC= +1.8V ± 0.1V

667Mbs CL6

533Mbs CL5

400Mbs CL4

Unit

Parameter

Address and control input pulse width for each input

Symbol

Min

Max

Min

Max

Min

Max

t_IPW

t_ISa

0.6

t_CK

ps

t_CK

ns

t_CK

ns

400

500

600

Address and control input setup time

Address and control input hold time

t_ISb

200

250

350

t_IHa

400

500

600

t_IHb

275

375

475

CAS# to CAS# command delay

t_CCD

t_RC

2

ACTIVE to ACTIVE (same bank) command

ACTIVE bank a to ACTIVE bank b command

ACTIVE to READ or WRITE delay

Four Bank Activate period

55

t_RRD

t_RCD

t_FAW

t_RAS

t_RTP

t_WR

10

15

50

ACTIVE to PRECHARGE command

Internal READ to precharge command delay

Write recovery time

40

70,000

40

70,000

40

70,000

7.5

15

Auto precharge write recovery + precharge time

Internal WRITE to READ command delay

PRECHARGE command period

t_DAL

t_WTR

t_RP

t_WR+ t_RP

7.5

10

15

PRECHARGE ALL command period

LOAD MODE command cycle time

CKE low to CK, CK# uncertainty

t_RPA

t_MRD

t_DELAY

15

2

15

2

15

2

t_IS+t_IH+ t_CK

REFRESH to Active or Refresh to Refresh command

interval

t_RFC

t_REFI

195

70,000

195

70,000

195

70,000

ns

Average periodic refresh interval (commercial and

industrial)

7.8

μs

Average periodic refresh interval (military)

Exit self refresh to non-READ command

Exit self refresh to READ

Exit self refresh timing reference

ODT turn-on delay

t_REFIM

t_XSNR

t_XSRD

t_lSXR

1.95

μs

ns

t_CK

ps

t_CK

ps

t_CK

ps

t_RFC(MIN)+ 10

200

t_IS

200

t_IS

200

t_IS

t_AOND

t_AON

t_AOFD

t_AOF

2

ODT turn-on

t_AC(MIN)

2.5

t_AC(MAX)+ 1000

2.5

t_AC(MIN)

2.5

t_AC(MAX)+ 1000

2.5

t_AC(MIN)

2.5

t_AC(MAX)+ 1000

2.5

ODT turn-off delay

ODT turn-off

t_AC(MIN)

t_AC(MAX)+ 600

t_AC(MIN)

t_AC(MAX)+ 600

t_AC(MIN)

t_AC(MAX)+ 600

t_AC(MIN)

2000

+

2 x t_CK

t_AC(MAX)+ 1000

2 x t_CK

t_AC(MAX)+ 1000

+

t_AC(MIN)

2000

+

2 x t_CK

t_AC(MAX)+ 1000

2 x t_CK

t_AC(MAX)+ 1000

+

t_AC(MIN)

2000

+

2 x t_CK

t_AC(MAX)+ 1000

2 x t_CK

t_AC(MAX)+ 1000

+

ODT turn-on (power-down mode)

ODT turn-off (power-down mode)

t_AONPD

t_AOFPD

ps

t_AC(MIN)

2000

+

t_AC(MIN)

2000

+

t_AC(MIN)

2000

+

ODT to power-down entry latency

ODT power-down exit latency

ODT enable from MRS command

t_ANPD

t_AXPD

t_MOD

3

8

3

8

3

8

t_CK

ns

12

Exit active power-down to READ command,

MR[bit12=0]

t_XARD

2

t_CK

Exit active power-down to READ command,

MR[bit12=1]

t_XARDS

7-AL

6-AL

Exit precharge power-down to any non-READ

command

t_XP

2

3

2

3

2

3

t_CK

CKE minimum high/low time

t_CKE

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

25

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

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W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 14 – W3H128M72E-XSBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)

BOTTOM VIEW

208 x Ø 0.60 (0.024) NOM

11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

1.0 (0.039)NOM

0.50

(0.020)

NOM

10.0 (0.394) NOM

16.10 (0.634) MAX

4.57 (0.180) MAX

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

26

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

FIGURE 15 – W3H128M72E-XNBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY LOW PROFILE (PBGA)

BOTTOM VIEW

208 x Ø 0.60 (0.024) NOM

11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

1.0 (0.039)NOM

0.50

(0.020)

NOM

10.0 (0.394) NOM

16.10 (0.634) MAX

3.94 (0.155) MAX

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

27

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

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W3H128M72E-XSBX

W3H128M72E-XNBX

ORDERING INFORMATION

W 3H 128M 72 E X - XXX XX X

MICROSEMI CORPORATION

DDR2 SDRAM

CONFIGURATION, 128M x 72

1.8V POWER SUPPLY

OPTIONS*

Blank = 0 ohm termination on CK\CK#

2 = 20 ohm termination on CK\CK#

DATA RATE (Mbs)

400 = 400Mb/s

533 = 533Mb/s

667 = 667Mb/s

PACKAGE:

SB = 4.57 mm package (Fig. 14)

NB = 3.94 mm package (Fig. 15)

DEVICE GRADE:

M = Military

-55°C to +125°C

I

= Industrial

-40°C to +85°C

0°C to +70°C

C

= Commercial

* Other termination values may be available, contact factory for options.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

28

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

Document Title

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Revision History

Rev #

History

Release Date Status

Rev 0

Initial Release

May 2008

Advanced

Rev 1

Changes (Pg. 1, 2, 22, 33)

September 2008

Advanced

1.1 Weight 4 grams max

1.2 Changed A0-12 to A0-13

1.3 Added input/output capacitance

1.4 Added BGA thermal resistance

Rev 2

Rev 3

Change (Pg. 1)

October 2008

Preliminary

2.1 Change SPACE SAVINGS to space savings

Change (Pg. 24)

3.1 Reduce DDR2 I_CC7

• CL6 from (1,975 to 1,580) mA

• CL5 from (1,775 to 1,420) mA

• CL4 from (1,775 to 1,420) mA

Rev 4

Change (Pg. 1, 5, 6, 19, 22, 23, 30)

December 2008

Final

4.1 Remove "P" from FBGA, take out "Actual Size" off of Figure 1

4.2 Remove V_CCQ; and I/O + core; V_CCQis common to V_CCin V_CCbox

4.3 Change page 8 to page 7 in initialization paragraph

4.4 Change ^tWT to t_WT

4.5 In BGA thermal resistance, change note to read - to obtain the junction

temperature increase, multiply the thermal resistance by the power dissipated

in each die in the MCP

4.6 In DC operating conditions add "and" to note 1

4.7 Put "/" in between Mbs to read Mb/s

4.8 Change data sheet to ﬁnal

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

29

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp

W3H128M72E-XSBX

W3H128M72E-XNBX

Document Title

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Revision History Continued

Rev #

History

Release Date Status

Rev 5

Changes (Pg. 1)

March 2009

Final

5.1 Change "This product is under development, is not fully qualiﬁed or

characterized and is subject to change without notice

5.2 Add thinner "NB" version of part is under development. Only difference

between "NB" and "SB" is thickness. "SB" = 4.65mm (0.283) max and "NB" =

3.97mm (0.156) max; a difference of .68mm (0.027) max

Rev 6

Changes (Pg. 24, 26)

September 2009

Final

6.1 Change I_CC2Pto 55mA on all speed grades

6.2 Change I_CC6to 45mA on all speed grades

6.3 Change I_CC7to 1,775mA on "400 and 533" speed grades and 1,975mA on

667 speed grade

6.4 Change t_ACto -100ps min on all speed grades and 1,250ps max on 667

speed grade, 1,350ps on 400 and 533 speed grades

6.5 Change t_DSAto 400ps on 533 speed grade

6.6 Change t_DQSCKto -100ps min on all speed grades and 1,250ps max on 667

speed grade, 1,350ps on 400 and 533 speed grades

Rev 7

Changes (Pg. 1, 29, 30)

March 2010

Final

7.1 Add weight of W3H128M72E-XNBX

7.2 Remove Thinner "NB" note

7.3 Add new W3H128M72E-XNBX package dimension

7.4 Change W3H128M72E-XSBX from 4.65 mm to 4.57 mm

7.5 Change length to 22.10 (0.870) max and width to 16.10 (0.634) max on both

"SB" and "NB" packages.

7.6 Remove note from BGA thermal resistance.

Rev 8

Rev 9

Changes (Pg. 25)

February 2011

August 2011

Final

8.1 Correct t_RFC= 195 ns for all speed grades

Changes (Pg. 1, 29, 30)

9.1 Add "1GB" to doc title

9.2 Add "Typical Applications" diagram

Rev 10

Changes (Pg. 26-28)

10.1 Fix typos

January 2012

Final

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 10

30

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com/pmgp


型号：	W3H128M72E-533SBI
厂家：	Microsemi
描述：	DDR DRAM, 128MX72, 1.35ns, CMOS, PBGA208, 16 X 22 MM, 1 MM PITCH, PLASTIC, BGA-208 动态存储器双倍数据速率内存集成电路
文件：	总30页 (文件大小：1272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W3H128M72E-533SBI [MICROSEMI]

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