首页 |元器件品牌

W3HG264M64EEU403D4IGG [MICROSEMI]

DDR DRAM Module, 128MX64, 0.6ns, CMOS, ROHS COMPLIANT, SO-DIMM-200;
W3HG264M64EEU403D4IGG
型号： W3HG264M64EEU403D4IGG
厂家： Microsemi    Microsemi
描述：

DDR DRAM Module, 128MX64, 0.6ns, CMOS, ROHS COMPLIANT, SO-DIMM-200

动态存储器 双倍数据速率
文件： 总12页 (文件大小：174K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
W3HG264M64EEU-D4  
White Electronic Designs  
1GB – 2x64Mx64 DDR2 SDRAM SO-DIMM UNBUFFERED  
FEATURES  
DESCRIPTION  
„
„
„
200-pin, dual in-line memory module (SO-DIMM).  
Raw card "E"  
The W3HG264M64EEU is a 2x64Mx64 Double Data Rate  
DDR2 SDRAM high density SO-DIMM. This memory  
module consists of sixteen 64Mx8 bit with 4 banks DDR2  
Synchronous DRAMs in FBGA packages, mounted on a  
200-pin SO-DIMM FR4 substrate.  
Fast data transfer rates: PC2-6400, PC2-5300,  
PC2-4200 and PC2-3200  
Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM  
components  
* This product is subject to change without notice.  
„
„
„
„
„
„
„
V
V
CC = 1.8V  
NOTE: Consult factory for availability of:  
• Vendor source control options  
• Industrial temperature option  
CCSPD = 1.7V to 3.6V  
JEDEC standard 1.8V I/O (SSTL_18-compatible)  
Differential data strobe (DQS, DQS#) option  
Four-bit prefetch architecture  
DLL to align DQ and DQS transitions with CK  
Multiple internal device banks for concurrent  
operation  
„
„
„
„
„
„
„
„
„
„
Programmable CAS# latency (CL): 3, 4, 5 and 6  
Adjustable data-output drive strength  
On-die termination (ODT)  
Posted CAS# latency: 0, 1, 2, 3 and 4  
Serial Presence Detect (SPD) with EEPROM  
64ms: 8,192 cycle refresh  
Gold edge contacts  
Dual Rank  
RoHS compliant  
JEDEC Package option  
• 200 Pin (SO-DIMM)  
• PCB – 30.00mm (1.181") TYP.  
OPERATING FREQUENCIES  
PC2-3200  
200MHz  
3-3-3  
PC2-4200  
266MHz  
4-4-4  
PC2-5300  
333MHz  
5-5-5  
PC2-6400  
400MHz  
6-6-6  
PC2-6400  
400MHz  
5-5-5  
Clock Speed  
CL-tRCD-tRP  
March 2008  
Rev. 6  
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
PIN CONFIGURATION  
PIN NAMES  
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL  
Pin Name  
CK0,CK1  
CK0#, CK1#  
CKE0, CKE1  
RAS#  
Function  
1
VREF  
VSS  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
DQS2  
DM2  
VSS  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
A1  
A0  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
DQ42  
DQ46  
DQ43  
DQ47  
VSS  
Clock Inputs, positive line  
Clock Inputs, negative line  
Clock Enables  
2
3
VSS  
VCC  
4
5
6
7
8
9
DQ4  
DQ0  
DQ5  
DQ1  
VSS  
VSS  
VCC  
A10/AP  
BA1  
Row Address Strobe  
Column Address Strobe  
Write Enable  
DQ18  
DQ22  
DQ19  
DQ23  
VSS  
CAS#  
VSS  
WE#  
BA0  
DQ48  
DQ52  
DQ49  
DQ53  
VSS  
VSS  
NC  
CK1  
VSS  
CK1#  
DQS6#  
VSS  
DQS6  
DM6  
VSS  
RAS#  
WE#  
CS0#  
VCC  
CS0#, CS1#  
A0-A13  
Chip Selects  
VSS  
Address Inputs  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
DM0  
DQS0#  
VSS  
DQS0  
DQ6  
VSS  
DQ7  
DQ2  
VSS  
DQ3  
DQ12  
VSS  
DQ13  
DQ8  
VSS  
DQ9  
DM1  
VSS  
VSS  
BA0,BA1  
ODT0,ODT1  
SCL  
SDRAM Bank Address  
On-die termination control  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input/Output  
SPD address  
DQ24  
DQ28  
DQ25  
DQ29  
VSS  
VCC  
CAS#  
ODT0  
CS1#  
A13  
VCC  
VCC  
ODT1  
NC  
VSS  
SDA  
SA1,SA0  
DQ0-DQ63  
DM0-DM7  
DQS0-DQS7  
DQS0#-DQS7#  
VCC  
VSS  
Data Input/Output  
Data Masks  
DM3  
DQS3#  
NC  
DQS3  
VSS  
Data strobes  
Data strobes complement  
Core and I/O Power  
Ground  
VSS  
VSS  
VSS  
VSS  
VREF  
Input/Output Reference  
SPD Power  
DQ26  
DQ30  
DQ27  
DQ31  
VSS  
DQ32  
DQ36  
DQ33  
DQ37  
VSS  
DQ50  
DQ54  
DQ51  
DQ55  
VSS  
VCCSPD  
NC  
Spare pins, No connect  
VSS  
VSS  
VSS  
VSS  
DQS1#  
CK0  
DQS1  
CK0#  
VSS  
CKE0  
CKE1  
VCC  
VCC  
NC  
NC  
NC  
NC  
VCC  
VCC  
A12  
A11  
A9  
A7  
A8  
A6  
VCC  
VCC  
DQS4#  
DM4  
DQS4  
VSS  
DQ56  
DQ60  
DQ57  
DQ61  
VSS  
VSS  
VSS  
DQ38  
DQ34  
DQ39  
DQ35  
VSS  
VSS  
DQ10  
DQ14  
DQ11  
DQ15  
VSS  
VSS  
VSS  
VSS  
DQ16  
DQ20  
DQ17  
DQ21  
VSS  
VSS  
DQS2#  
NC  
DM7  
DQS7#  
VSS  
DQS7  
DQ58  
VSS  
DQ59  
DQ62  
VSS  
DQ63  
SDA  
VSS  
VSS  
DQ44  
DQ40  
DQ45  
DQ41  
VSS  
VSS  
DQS5#  
DM5  
DQS5  
VSS  
A5  
A4  
A3  
A2  
SCL  
SA0  
VCCSPD  
SA1  
VSS  
March 2008  
Rev. 6  
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
FUNCTIONAL BLOCK DIAGRAM  
?
+
3 ohm ꢀ5  
CKE1  
ODT1  
CS1#  
CKE0  
ODT0  
CS0#  
CS#  
CS#  
CS#  
CS#  
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
DQS0  
DQS0#  
DM0  
DQS4  
DQS4#  
DM4  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQꢀ  
DQ6  
DQ7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
DQ32  
DQ33  
DQ34  
DQ3ꢀ  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
CS#  
CS#  
CS#  
CS#  
DQS1  
DQS1#  
DM1  
DQSꢀ  
DQSꢀ#  
DMꢀ  
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQ8  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ4ꢀ  
DQ46  
DQ47  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ1ꢀ  
CS#  
CS#  
CS#  
CS#  
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
DQS2  
DQS2#  
DM2  
DQS6  
DQS6#  
DM6  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQS  
DQS#  
DM  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
DQ48  
DQ49  
DQꢀ0  
DQꢀ1  
DQꢀ2  
DQꢀ3  
DQꢀ4  
DQꢀꢀ  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
CS#  
CS#  
CS#  
CS#  
DQS3  
DQS3#  
DM3  
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS7  
DQS7#  
DM7  
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQS  
DQS#  
DM  
O
D
T
C
K
E
DQ24  
DQ2ꢀ  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
DQꢀ6  
DQꢀ7  
DQꢀ8  
DQꢀ9  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O ꢀ  
I/O 6  
I/O 7  
* Cloꢃk Wiring  
DDR2 SDRAMs  
10 ohm ꢀ5  
BA0 - BA1  
A0 - A13  
RAS#  
DDR2 SDRAMs  
DDR2 SDRAMs  
DDR2 SDRAMs  
DDR2 SDRAMs  
DDR2 SDRAMs  
SCL  
SA0  
SA1  
SCL  
A0  
Cloꢃk Inꢂut  
SPD  
*CK0/CK0#  
*CK1/CK1#  
8 DDR2 SDRAMs  
8 DDR2 SDRAMs  
A1  
SDA  
A2  
WP  
* Wire ꢂer Cloꢃk Loading  
Table/Wiring Diagrams  
CAS#  
WE#  
V
V
V
V
SPD  
Serial PD  
DDR2 SDRAMs  
CC  
Note :  
1. All resistor values are 22 ohms ꢀ5 unless otherꢁise sꢂeꢃiꢄied  
REF  
CC  
DDR2 SDRAMs, VCC,  
DDR2 SDRAMs, SPD  
VCCQ and VCCL  
SS  
March 2008  
Rev. 6  
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
DC OPERATING CONDITIONS  
All voltages referenced to VSS  
Rating  
Parameter  
Symbol  
VCC  
Min.  
1.7  
Typ.  
1.8  
Max.  
1.9  
Units  
Notes  
Supply Voltage  
I/O Reference Voltage  
I/O Termination Voltage  
Notes:  
V
V
V
VREF  
VTT  
0.49 x VCC  
VREF-0.04  
0.50 x VCC  
VREF  
0.51 x VCC  
VREF+0.04  
1
2
1.  
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1percent of the DC  
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.  
TT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF  
2.  
V
.
ABSOLUTE MAXIMUM RATINGS  
Symbol  
VCC  
Parameter  
Min  
-0.5  
-0.5  
-55  
Max  
2.3  
2.3  
100  
32  
Units  
V
Voltage on VCC pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
VIN, VOUT  
TSTG  
V
˚C  
IL  
Input leakage current; Any input 0V<VIN<VCC; VREF input  
0V<VIN<0.95V; Other pins not under test = 0V  
Command/Address,  
RAS#, CAS#, WE#  
-32  
μA  
CS#, CKE  
CK, CK#  
-16  
-16  
-4  
16  
16  
4
μA  
μA  
μA  
μA  
DM  
IOZ  
Output leakage current; 0V<VIN<VCC; DQs and ODT are  
disable  
DQ, DQS, DQS#  
-10  
10  
March 2008  
Rev. 6  
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
OPERATING TEMPERATURE CONDITION  
Parameter  
Symbol  
TOPER  
TOPER  
Rating  
0° to 85°  
-40° to 85°  
Units  
°C  
Notes  
1, 2  
Operating temperature  
Operating temperature (industrial temp modules only)  
Notes:  
°C  
1, 3  
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2  
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.  
3. Average refresh period 7.8us at Dram Tcase lower than 85°C, 3.9us for Dram Tcase 85°C-95°C.  
INPUT DC LOGIC LEVEL  
All voltages referenced to VSS  
Parameter  
Symbol  
VIH(DC)  
VIL(DC)  
Min  
VREF + 0.125  
-0.300  
Max  
Units  
Input High (Logic 1) Voltage - All data rate  
Input Low (Logic 0) Voltage - All data rate  
VCC + 0.300  
VREF - 0.125  
V
V
INPUT AC LOGIC LEVEL  
All voltages referenced to VSS  
Parameter  
Symbol  
VIH(AC)  
VIH(AC)  
VIL(AC)  
VIL(AC)  
Min  
Max  
Units  
Input High (Logic 1) Voltage DDR2-400 & DDR2-533  
Input Low (Logic 1) Voltage DDR2-667 & DDR2 800  
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533  
Input Low (Logic 0) Voltage DDR2-667 & DDR2-800  
VREF + 0.250  
-
V
V
V
V
VREF + 0.200  
-
-
-
VREF - 0.250  
VREF - 0.200  
March 2008  
Rev. 6  
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
ICC SPECIFICATION  
Symbol Proposed Conditions  
Operating one bank active-precharge;  
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid  
805  
806  
665  
534  
403  
Units  
ICC0*  
t
728  
696  
624  
576  
544  
mA  
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
Operating one bank active-read-precharge;  
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS  
min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are  
SWITCHING; Data pattern is same as ICC4W  
ICC1*  
856  
816  
736  
656  
616  
mA  
Precharge power-down current;  
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are  
STABLE; Data bus inputs are FLOATING  
112  
720  
720  
112  
720  
720  
112  
640  
640  
112  
560  
608  
112  
512  
544  
mA  
mA  
mA  
Precharge quiet standby current;  
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus  
inputs are STABLE; Data bus inputs are FLOATING  
Precharge standby current;  
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus  
inputs are STABLE; Data bus inputs are SWITCHING  
Active power-down current;  
Fast PDN Exit MRS(12) = 0  
Slow PDN Exit MRS(12) = 1  
624  
144  
624  
144  
528  
144  
448  
144  
384  
144  
mA  
mA  
All banks open; tCK = tCK(ICC); CKE is LOW; Other control  
and address bus inputs are STABLE; Data bus inputs are  
FLOATING  
ICC3P**  
ICC3N**  
ICC4W*  
ICC4R*  
Active standby current;  
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH  
between valid commands; Other control and address bus inputs are SWITCHING; Data bus  
inputs are SWITCHING  
960  
960  
800  
688  
936  
936  
624  
816  
816  
mA  
mA  
mA  
Operating burst write current;  
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS  
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address  
bus inputs are SWITCHING; Data bus inputs are SWITCHING  
=
1,296 1,296 1,096  
1,296 1,296 1,096  
Operating burst read current;  
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK  
= tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid  
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W  
Burst auto refresh current;  
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH  
between valid commands; Other control and address bus inputs are SWITCHING; Data bus  
inputs are SWITCHING  
ICC5*  
1,216 1,216 1,176 1,096 1,056  
mA  
mA  
Self refresh current;  
ICC6**  
CK and CK# at 0V; CKE 0.2V; Other control and address  
bus inputs are FLOATING; Data bus inputs are FLOATING  
Normal  
112  
112  
112  
112  
112  
Operating bank interleave read current;  
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC);  
CK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH  
ICC7*  
t
1,416 1,336 1,272 1,216 1,184  
mA  
between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus  
inputs are SWITCHING.  
ICC specification is based on QIMONDA components. Other DRAM manufactures specification may be different.  
Note:  
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.  
** Value calculated reflects all module ranks in this operating condition.  
March 2008  
Rev. 6  
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS  
AC CHARACTERISTICS  
805  
806  
665  
534  
403  
SYMBOL  
UNIT  
PARAMETER  
MIN  
MAX  
8,000  
8,000  
8,000  
8,000  
MIN  
MAX  
8,000  
8,000  
8,000  
8,000  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
CL = 6  
CL = 5  
CL = 4  
CL = 3  
tCK (6)  
tCK (5)  
tCK (4)  
tCK (3)  
2,500  
2,500  
3,750  
5,000  
2,500  
3,000  
3,750  
5,000  
ps  
ps  
ps  
ps  
3,000  
3,750  
5,000  
8,000  
8,000  
8,000  
Clock cycle time  
3,750  
5,000  
8,000  
8,000  
5,000  
5,000  
8,000  
8,000  
CK high-level width  
CK low-level width  
tCH  
tCL  
0.48  
0.48  
0.52  
0.52  
0.48  
0.48  
0.52  
0.52  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tCK  
tCK  
MIN (tCH  
,
MIN (tCH  
,
MIN (tCH  
,
MIN (tCH  
,
MIN (tCH  
,
Half clock period  
tHP  
tAC  
tHZ  
ps  
ps  
ps  
tCL)  
tCL)  
tCL)  
tCL)  
tCL)  
DQ output access time from CK/CK#  
-400  
+400  
-400  
+400  
-450  
+450  
-500  
+500  
-600  
+600  
Data-out high-impedance window from  
CK/CK#  
tAC MAX  
tAC MAX  
tAC MAX  
tAC MAX  
tAC MAX  
Data-out low-impedance window from  
CK/CK#  
2x  
tAC MIN  
2x  
tAC MIN  
2x  
tAC MIN  
2x  
tAC MIN  
2x  
tAC MIN  
tLZ  
t
AC MAX  
t
AC MAX  
t
AC MAX  
t
AC MAX  
t
AC MAX  
ps  
DQ and DM input setup time relative to DQS  
DQ and DM input hold time relative to DQS  
DQ and DM input pulse width (for each input)  
Data hold skew factor  
tDS  
tDH  
tDIPW  
tQHS  
50  
50  
100  
175  
0.35  
100  
225  
0.35  
150  
275  
0.35  
ps  
ps  
tCK  
ps  
125  
0.35  
125  
0.35  
300  
300  
340  
400  
450  
DQ - DQS hold, DQS to first DQ to go  
nonvalid, per access  
tQH  
tHP - tQHS  
tHP - tQHS  
tHP - tQHS  
tHP - tQHS  
tHP - tQHS  
ps  
DQS input high pulse width  
tDQSH  
tDQSL  
tDQSCK  
tDSS  
0.35  
0.35  
-350  
0.2  
0.35  
0.35  
-350  
0.2  
0.35  
0.35  
-400  
0.2  
0.35  
0.35  
-450  
0.2  
0.35  
0.35  
-500  
0.2  
tCK  
tCK  
ps  
DQS input low pulse width  
DQS output access time from CK/CK#  
DQS falling edge to CK rising - setup time  
DQS falling edge from CK rising - hold time  
+350  
200  
+350  
200  
+400  
240  
+450  
300  
+500  
350  
tCK  
tCK  
tDSH  
0.2  
0.2  
0.2  
0.2  
0.2  
DQS - DQ skew, DQS to last DQ valid, per  
group, per access  
tDQSQ  
ps  
DQS read preamble  
DQS read postamble  
DQS write preamble  
DQS write postamble  
tRPRE  
tRPST  
tWPRE  
tWPST  
0.9  
0.4  
1.1  
0.6  
0.9  
0.4  
1.1  
0.6  
0.9  
0.4  
1.1  
0.6  
0.9  
0.4  
1.1  
0.6  
0.9  
0.4  
1.1  
0.6  
tCK  
tCK  
tCK  
tCK  
0.35  
0.4  
0.35  
0.4  
0.35  
0.4  
0.25  
0.4  
0.25  
0.4  
0.6  
0.6  
0.6  
0.6  
0.6  
WL  
- 0.25  
WL +  
0.25  
WL  
- 0.25  
WL +  
0.25  
WL  
- 0.25  
WL +  
0.25  
WL  
- 0.25  
WL +  
0.25  
WL  
- 0.25  
WL +  
0.25  
Write command to first DQS latching transition  
tDQSS  
tIPW  
tCK  
tCK  
Address and control input pulse width for  
each input  
0.6  
0.6  
0.6  
0.6  
0.6  
Address and control input setup time  
Address and control input hold time  
Address and control input hold time  
tIS  
tIH  
175  
250  
2
175  
250  
2
200  
275  
2
250  
375  
2
350  
475  
2
ps  
ps  
tCK  
tCCD  
AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different.  
Continued on next page  
March 2008  
Rev. 6  
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)  
AC CHARACTERISTICS  
805  
806  
665  
534  
403  
SYMBOL  
UNIT  
PARAMETER  
MIN  
57.5  
7.5  
MAX  
MIN  
60  
MAX  
MIN  
60  
MAX  
MIN  
60  
MAX  
MIN  
55  
MAX  
ACTIVE to ACTIVE (same bank) command  
ACTIVE bank a to ACTIVE bank b command  
ACTIVE to READ or WRITE delay  
ACTIVE to PRECHARGE command  
Internal READ to precharge command delay  
Write recovery time  
tRC  
tRRD  
tRCD  
tRAS  
tRTP  
tWR  
ns  
ns  
ns  
ns  
ns  
ns  
7.5  
15  
7.5  
15  
7.5  
15  
7.5  
15  
12.5  
45  
70,000  
45  
70,000  
45  
70,000  
45  
70,000  
40  
70,000  
7.5  
7.5  
15  
7.5  
15  
7.5  
15  
7.5  
15  
15  
Auto precharge write recovery + precharge  
time  
tWR  
+
tWR  
+
tWR  
+
tWR  
+
tWR  
+
tDAL  
ns  
tRP  
tRP  
tRP  
tRP  
tRP  
Internal WRITE to READ command delay  
PRECHARGE command period  
tWTR  
tRP  
tRPA  
tMRD  
tDELAY  
7.5  
7.5  
15  
7.5  
15  
7.5  
15  
10  
15  
ns  
ns  
ns  
tCK  
12.5  
PRECHARGE ALL command period  
LOAD MODE command cycle time  
tRP+tCK  
tRP+tCK  
tRP+tCK  
tRP+tCK  
tRP+tCK  
2
2
2
2
2
tIS + tCK  
+ tIH  
tIS + tCK  
+ tIH  
tIS + tCK  
+ tIH  
tIS + tCK  
+ tIH  
tIS + tCK  
+ tIH  
CKE low to CK,CK# uncertainty  
ns  
REFRESH to Active of Refresh to Refresh  
command internal  
tRFC  
REFI  
105  
105  
105  
105  
105  
ns  
Average periodic refresh interval  
t
7.8  
7.8  
7.8  
7.8  
7.8  
μs  
tRFC  
(MIN) +  
10  
tRFC (MIN)  
+ 10  
tRFC (MIN)  
+ 10  
tRFC (MIN)  
+ 10  
tRFC (MIN)  
+ 10  
Exit self refresh to non-READ command  
tXSNR  
ns  
Exit self refresh to READ command  
ODT turn-on delay  
tXSRD  
tAOND  
200  
2
200  
2
200  
2
200  
2
200  
2
tCK  
tCK  
2
2
2
2
2
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
ODT turn-on  
tAON  
tAOFD  
tAOF  
(MAX)  
+ 700  
(MAX)  
+ 700  
(MAX)  
+ 700  
(MAX)  
+ 1000  
(MAX)  
+ 700  
ps  
tCK  
ps  
(MIN)  
(MIN)  
(MIN)  
(MIN)  
(MIN)  
ODT turn-off delay  
ODT turn-off  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
tAC  
(MAX)  
+ 600  
tAC  
(MAX)  
+ 600  
tAC  
(MAX)  
+ 600  
tAC  
(MAX)  
+ 600  
tAC  
(MAX)  
+ 600  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
2 x tCK  
+ tAC  
2 x tCK  
+ tAC  
2 x tCK  
+ tAC  
2 x tCK  
+ tAC  
2 x tCK  
+ tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
ODT turn-on (power-down mode)  
ODT turn-off (power-down mode)  
tAONPD  
(MIN)  
+ 2000  
(MIN)  
+ 2000  
(MIN)  
+ 2000  
(MIN)  
+ 2000  
(MIN)  
+ 2000  
ps  
ps  
(MAX)  
+ 1000  
(MAX)  
+ 1000  
(MAX)  
+ 1000  
(MAX)  
+ 1000  
(MAX)  
+ 1000  
2.5  
x tCK  
+ tAC  
2.5  
x tCK  
+ tAC  
2.5  
x tCK  
+ tAC  
2.5  
x tCK  
+ tAC  
2.5  
x tCK  
+ tAC  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
tAC  
(MIN)  
tAOFPD  
+ 2000 (MAX) + 2000 (MAX) + 2000 (MAX) + 2000 (MAX) + 2000 (MAX)  
+ 1000  
+ 1000  
+ 1000  
+ 1000  
+ 1000  
ODT to power-down entry latency  
ODT power-down exit latency  
tANPD  
tAXPD  
3
8
3
8
3
8
3
8
3
8
tCK  
tCK  
tCK  
Exit active power-down to READ command,  
MR[bit12=0]  
tXARD  
2
2
2
2
2
Exit active power-down to READ command,  
MR[bit12=1]  
tXARDS  
8-AL  
8-AL  
7 - AL  
6 - AL  
6 - AL  
tCK  
A Exit precharge power-down to any non-  
READ command.  
tXP  
2
3
2
3
2
3
2
3
2
3
tCK  
tCK  
CKE minimum high/low time  
tCKE  
AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different.  
March 2008  
Rev. 6  
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
ORDERING INFORMATION FOR D4  
Part Number  
Clock/Data Rate Speed  
CAS Latency  
Height**  
W3HG264M64EEU805D4xxG  
W3HG264M64EEU806D4xxG  
W3HG264M64EEU665D4xxG  
W3HG264M64EEU534D4xxG  
W3HG264M64EEU403D4xxG  
400MHz/800Mb/s  
400MHz/800Mb/s  
333MHz/667Mb/s  
266MHz/533Mb/s  
200MHz/400Mb/s  
5
6
5
4
3
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
ORDERING INFORMATION FOR INDUSTRIAL TEMP  
Part Number  
Clock/Data Rate Speed  
CAS Latency  
Height**  
W3HG264M64EEU665AD4IxG  
W3HG264M64EEU534AD4IxG  
W3HG264M64EEU403AD4IxG  
333MHz/667Mb/s  
266MHz/533Mb/s  
200MHz/400Mb/s  
5
4
3
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
30.00mm (1.181") TYP  
NOTES:  
• Industrial grade product is tested from -40°C to +85°C  
• For part numbering interpretation, please see "part number guide" on page 11.  
March 2008  
Rev. 6  
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
PACKAGE DIMENSIONS FOR D4  
FRONT VIEW  
3.80 (0.1ꢀ0)  
MAX  
67.7ꢀ (2.667)  
67.4ꢀ (2.6ꢀ6)  
4.10(0.161)  
3.90(0.1ꢀ4)  
(2X)  
30.1ꢀ (1.187)  
29.8ꢀ (1.17ꢀ)  
1.80 (0.071)  
(2X)  
20.00 (0.787)  
TYP  
6.00 (0.236)  
2.ꢀꢀ (0.100)  
1.10 (0.043)  
0.90 (0.03ꢀ)  
2.1ꢀ (0.08ꢀ)  
1.00 (0.039)  
TYP  
PIN 1  
0.4ꢀ (0.018)  
TYP  
0.60 (0.024)  
TYP  
PIN 199  
63.60 (2.ꢀ04)  
TYP  
BACK VIEW  
4.2 (0.16ꢀ)  
TYP  
PIN 200  
PIN 2  
47.40 (1.866)  
TYP  
11.40 (0.449)  
TYP  
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
March 2008  
Rev. 6  
10  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
PART NUMBERING GUIDE  
W 3 H G 2 64M 64 E E U xxx A D4 x x G  
WEDC  
MEMORY (SDRAM)  
DDR 2  
GOLD  
DUAL RANK  
DEPTH  
BUS WIDTH  
COMPONENT WIDTH x8  
1.8V  
UNBUFFERED  
SPEED (Mb/s)  
PRODUCT REVISION  
Commercial Revision = BLANK  
Industrial Revision = A  
PACKAGE 200 PIN  
INDUSTRIAL TEMP OPTION  
(For commercial leave "blank" for industrial add "I")  
(Industrial Temp: -40°C to +85°C)  
COMPONENT VENDOR NAME  
(G = Qimonda)  
Note: Consult factory for other vendor options.  
G = RoHS COMPLIANT  
March 2008  
Rev. 6  
11  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
W3HG264M64EEU-D4  
White Electronic Designs  
Document Title  
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED  
DRAM DIE OPTIONS:  
• QIMONDA: B-Die, 800Mbs and Industrial temp modules use B2 - Die  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Created  
January 2007  
Concept  
Rev 1  
Rev 2  
January 2007  
Advanced  
1.0 Moved from concept to advanced  
1.1 Updated AC timing specifications  
1.2 Corrected part numbering guide  
May 2007  
Advanced  
2.0 Updated AC's & IDD specs to indicate 800Mb/s Data rate  
speed  
2.1 Added 800Mb/s with CAS latency 5  
Rev 3  
Rev 4  
Rev 5  
Rev 6  
June 2007  
Advanced  
Advanced  
Final  
3.0 Updated specifications  
June 2007  
4.0 Added industrial temp clarification to ordering information  
and part numbering guide  
January 2008  
March 2008  
5.0 Update the Industrial temp ordering information to clarify  
revision A which designates the Qimonda B2 die revision  
Final  
6.0 Fix CAS latency designation on "805" on ordering  
information chart  
March 2008  
Rev. 6  
12  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

相关型号：

W3HG264M64EEU403D6IGG

 DDR DRAM Module, 128MX64, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240
MICROSEMI

W3HG264M64EEU534D4GG

 DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI

W3HG264M64EEU534D4GG

 DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
WEDC

W3HG264M64EEU534D4IGG

 DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI

W3HG264M64EEU534D6GG

 DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240
MICROSEMI

W3HG264M64EEU534D6IGG

 DDR DRAM Module, 128MX64, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240
MICROSEMI

W3HG264M64EEU665D4GG

 DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI

W3HG264M64EEU665D4IGG

 DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI

W3HG264M64EEU665D6GG

 DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240
MICROSEMI

W3HG264M64EEU665D6IGG

 DDR DRAM Module, 128MX64, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240
MICROSEMI

W3HG264M64EEU805D4GG

 DDR DRAM Module, 128MX64, 0.4ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI

W3HG264M64EEU805D4IGG

 DDR DRAM Module, 128MX64, 0.4ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
MICROSEMI
©2020 ICPDF网 联系我们和版权申明