WED9LC6816V1310BI [MICROSEMI]
Memory Circuit, SDRAM+SRAM, 4MX32, CMOS, PBGA153, 14 X 22 MM, MO-163, BGA-153;
| 型号： | WED9LC6816V1310BI |
| 厂家： | 
Microsemi |
| 描述： | Memory Circuit, SDRAM+SRAM, 4MX32, CMOS, PBGA153, 14 X 22 MM, MO-163, BGA-153 动态存储器 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：1482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED9LC6816V
256Kx32 SSRAM/4Mx32 SDRAM – External Memory
Solution for Texas Instruments TMS320C6000 DSP
FEATURES
DESCRIPTION
Clock speeds:
The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline
SRAM and a 4Mx32 Synchronous DRAM array constructed with
one 256K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on
a multilayer laminate substrate. The device is packaged in a 153
lead, 14mm x 22mm, BGA.
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
Packaging:
The WED9LC6816V provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150 and 133 MHz, allowing the user to develop a fast
external memory for the SSRAM interface port .
• 153 pin BGA, JEDEC MO-163
3.3V Operating supply voltage
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the SDRAM
interface port.
Direct control interface to both the SSRAM and SDRAM
ports on the “C6x”
The WED9LC6816V is available in both commercial and industrial
temperature ranges.
Common address and databus
65% space savings vs. monolithic solution
Reduced system inductance and capacitance
This product is subject to change without notice.
Figure 1 – PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-17
DQ0-31
SSCK
Address Bus
Data Bus
1
2
3
4
5
6
7
8
9
DQ19
DQ18
VCCQ
DQ17
DQ16
VCCQ
NC
DQ23
DQ22
VCCQ
DQ21
DQ20
VCCQ
NC
VCC
VCC
VCC
VCC
VCC
VCC
NC
A8
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
VSS
VSS
VSS
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
A2
DQ24
DQ25
VCCQ
DQ26
DQ27
VCCQ
A4
DQ28
DQ29
VCCQ
DQ30
DQ31
VCCQ
A5
A
B
C
D
E
F
SSRAM Clock
SDCE#
SSADC#
SSWE#
SSOE#
SDCK
SSRAM Address Status Control
SSRAM Write Enable
SSRAM Output Enable
SDRAM Clock
SDWE# SDA10
VSS
VSS
VSS
VSS
SDCK
VSS
SDRAS#
SDCAS#
SDWE#
SDA10
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Write Enable
SDRAM Address 10/auto precharge
SDRAS# SDCAS#
G
H
J
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
A1
A3
A10
A6
A7
A9
A0
A11
A12
BWE0-3#
SSRAM Byte Write Enables SDRAM
SDQM 0-3
A17
NC/A18 NC/A19
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
A13
A14
K
L
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
BWE2# BWE3#
BWE0# BWE1#
A15
A16
SSCE#
SDCE#
VCC
Chip Enable SSRAM Device
Chip Enable SDRAM Device
Power Supply pins
VCCQ
DQ12
DQ13
VCCQ
DQ14
DQ15
VCCQ
DQ11
DQ10
VCCQ
DQ9
DQ8
VCCQ
DQ4
DQ5
VCCQ
DQ6
DQ7
VCCQ
DQ0
DQ1
VCCQ
DQ2
DQ3
M
N
P
R
T
VSS
VSS
VSS
VSS
SSCK
VSS
VCCQ
VSS
Data Bus Power Supply pins,
Ground
NC
No Contact
SSADC# SSWE#
SSOE# SSCE#
U
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July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
Figure 2 – BLOCK DIAGRAM
A
0-17
A
0
1
A0
A
A1
A2
A3
A4
DQ1-8
DQ0-7
A5
A6
DQ9-16
DQ8-15
DQ16-23
A7
A8
DQ17-24
DQ25-32
A9
DQ24-31
A10
A11
A12
A13
A14
A15
A16
SSWE#
BWE#
BWE
BWE
BWE
BWE
0
1
2
3
#
#
#
#
BW1
BW2
BW3
BW4
#
#
#
#
SSCE#
SSOE#
CE
2
#
OE#
SSADC#
ADSC#
CK#
SSCK#
DQ0-31
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
DQ0-7
DQ0-7
9
DQ8-15 DQ8-15
11
SDA10
10/AP
A
12
13
BA
BA
0
A
1
LDQM#
UDQM#
CS#
SDCE#
SDRAS#
SDCAS#
SDWE#
RAS#
CAS#
WE#
SDCK#
CK#
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
DQ16-23
DQ0-7
9
DQ24-31
DQ8-15
11
10/AP
BA
A
12
13
0
A
BA
1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK#
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July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol
Type
Signal
Polarity
Function
SSCK
Input
Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADC#
SSOE#
SSWE#
When sampled at the positive rising edge of the clock, SSADC#, SSOE#, and SSWE# define the operation
to be executed by the SSRAM.
Input
Pulse
Active Low
SSCE#
SDCK
Input
Input
Input
Pulse
Pulse
Pulse
Active Low
SSCE# disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE#
Active Low
Active Low
SDCE# disable or enable device operation by masking or enabling all inputs except SDCK and BWE0
SDRAS#
SDCAS#
SDWE#
When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE# define
the operation to be executed by the SDRAM.
Input
Input
Pulse
Level
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the
rising clock edge.
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the
rising clock edge. In addition to the row address, SDA10 is used to invoke autoprecharge operation at the
end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define
the bank to be precharged. If SDA10 is low, autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which
bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13.
If SDA10 is low, then A12 and A13 are used to define which bank to precharge.
A0-17,
SDA10
—
—
Input
Output
DQ0-31
Level
Pulse
Data Input/Output are multiplexed on the same pins.
BWE0-3# perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0#
is associated with DQ0-7, BWE1# with DQ8-15, BWE2# with DQ16-23 and BWE3# with DQ24-31.
BWE0-3#
Input
VCC, VSS
VCCQ
Supply
Supply
Power and ground for the input buffers and the core logic.
Data power supply pins, VCC and VCCQ are internally tied together
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July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Voltage on VCC Relative to VSS
IN (DQx)
-0.5V to +4.6V
-0.5V to VCC +0.5V
-55°C to +125°C
+150°C
V
Parameter
Symbol
VCC
VIH
Min
3.135
2.0
Max
3.6
Units
V
Storage Temperature (BGA)
Junction Temperature
Supply Voltage (1)
Input High Voltage (1,2)
Input Low Voltage (1,2)
Input Leakage Current 0 ≤ VIN ≤ VCC
Output Leakage (Output Disabled) 0 ≤
VCC +0.3
0.8
V
Short Circuit Output Current
100 mA
VIL
-0.3
-10
V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in operational sections of this specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ILI
10
μA
μA
ILO
-10
10
VIN ≤ VCC
SSRAM Output High (IOH = -4mA) (1)
SSRAM Output Low (IOL = 8mA) (1)
SDRAM Output High (IOH = -2mA)
SDRAM Output Low (IOL = 2mA)
VOH
VOL
VOH
VOL
2.4
—
—
0.4
—
V
V
V
V
2.4
—
0.4
NOTES:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tKC/2
Underershoot: VIL ≤ -2.0V for t ≤ tKC/2
DC ELECTRICAL CHARACTERISTICS
(0°C tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Description
Conditions
Symbol
Frequency
133MHz
150MHz
166MHz
200MHz
133MHz
150MHz
166MHz
200MHz
83MHz
Typ
500
500
550
600
325
350
400
450
500
500
550
20.0
Max
Units
Power Supply Current Operating
(1,2,3)
SSRAM Active / DRAM Auto Refresh
ICC1
ICC2
ICC3
625
650
700
800
425
450
495
585
625
650
700
40.0
mA
mA
mA
Power Supply Current Operating
(1,2,3)
SSRAM Active / DRAM Idle
Power Supply Current Operating
(1,2,3)
SSRAM Active / SSRAM Idle
100MHz
125MHz
CMOS Standby
TTL Standby
SSCE# and SDCE# ≤ VCC -0.2V, All other inputs at VSS +0.2 ≤
VIN or VIN ≤ VCC -0.2V, CK frequency = 0
ISB1
ISB2
ICC5
mA
mA
mA
SSCE# and SDCE# ≤ VIH min All other inputs at VIL max ≤ VIN
or VIN ≤ VCC -0.2V, CK frequency = 0
30.0
250
55.0
300
Auto Refresh
NOTES:
1.
ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE = VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
SSRAM AC CHARACTERISTICS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
200MHz
Min
166MHz
Min
150MHz
Min
133MHz
Parameter
Symbol
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX
tKQLZ
tKQHZ
tOELQV
tOELZ
tOEHZ
tS
Max
Max
Max
Min
8
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
5
6
7
Clock HIGH Time
1.6
1.6
2.4
2.4
2.6
2.6
2.8
2.8
Clock LOW Time
Clock to output valid
2.5
3.5
3.8
4.0
Clock to output invalid
1.5
0
1.5
0
1.5
0
1.5
0
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
1.5
3
1.5
3.5
3.5
1.5
3.8
3.8
1.5
4.0
4.0
2.5
0
0
0
0
3.0
3.5
3.5
3.8
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
tH
SSRAM OPERATION TRUTH TABLE
Operation
Address Used
None
SSCE#
SSADC#
SSWE#
SSOE#
DQ
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
H
L
L
L
X
L
X
X
L
High-Z
External
External
External
Current
Current
Current
Current
Current
Current
D
Q
L
L
H
H
H
H
H
H
L
L
L
H
L
High-Z
Q
X
X
H
H
X
H
H
H
H
H
H
H
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time for SSOE# and staying HIGH through out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
BGA CAPACITANCE
Description
Conditions
Symbol
CI
Max
8
Units
pF
Address Input Capacitance (1)
Input/Output Capacitance (DQ) (1)
Control Input Capacitance (1)
Clock Input Capacitance (1)
tA = 25°C; f = 1MHz
tA = 25°C; f = 1MHz
tA = 25°C; f = 1MHz
tA = 25°C; f = 1MHz
CO
10
8
pF
CA
pF
CCK
6
pF
NOTE:
1. This parameter is sampled.
SSRAM PARTIAL TRUTH TABLE
Function
SSWE#
BWE0#
BWE1#
BWE2#
BWE3#
READ
H
L
L
X
L
L
X
H
L
X
H
L
X
H
L
WRITE one Byte (DQ0-7)
WRITE all Bytes
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July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
Figure 3 – SSRAM READ TIMING
tKHKL tKLKH
tKHKH
SSCK
tS
tH
SSADC#
SSCE#
tS
tS
tH
A1
A5
A2
A3
A4
ADDR
tH
SSOE#
tOEHZ
tOELQV
SSWE#
DQ
tKHQX
tKQLZ
tKHQV
Q(A2)
Q(A1)
Q(A3)
Q(A4)
Q(A5)
Figure 4 – SSRAM WRITE TIMING
tKHKH
tKHKL tKLKH
SSCK
tS
tH
SSADC#
tH
SSCE#
tH
tS
A4
A1
A2
A3
A5
ADDR
SSOE#
SSWE#
tH
tOEHZ
Must be HIGH
KHGWX
tS
tH
tH
tS
D(A1)
D(A2)
D(A3)
D(A5)
D(A4)
DQ
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
SDRAM AC CHARACTERISTICS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Parameter
Symbol
125MHz
100MHz
83MHz
Units
Min
8
Max
1000
1000
6
Min
10
Max
1000
1000
7
Min
12
Max
1000
1000
8
Clock Cycle Time (1)
CL = 3
CL = 2
tCC
tCC
tSAC
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
ea
10
12
15
Clock to valid Output delay (1,2)
Output Data Hold Time (2)
Clock HIGH Pulse Width (3)
Clock LOW Pulse Width (3)
Input Setup Time (3)
3
3
3
2
1
2
3
3
3
2
1
2
3
3
3
2
1
2
tCH
tCL
tSS
Input Hold Time (3)
tSH
CK to Output Low-Z (2)
tSLZ
tSHZ
tRRD
tRCD
tRP
CK to Output High-Z
7
7
8
Row Active to Row Active Delay (4)
RAS\ to CAS\ Delay (4)
20
20
20
50
70
70
1
20
20
20
50
80
80
1
24
24
24
60
90
90
1
Row Precharge Time (4)
Row Active Time (4)
tRAS
tRC
10,000
10,000
10,000
Row Cycle Time - Operation (4)
Row Cycle Time - Auto Refresh (4,8)
tRFC
tCDL
tRDL
tBDL
tCCD
Last Data in to New Column Address Delay (5)
Last Data in to Row Precharge (5)
1
1
1
Last Data in to Burst Stop (5)
1
1
1
Column Address to Column Address Delay (6)
Number of Valid Output Data (7)
1.5
2
1.5
2
1.5
2
1
2
1
NOTES:
1. Parameters depend on programmed CAS# latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
CLOCK FREQUENCY AND LATENCY PARAMETERS – 125MHz SDRAM (Unit = number of clock)
CAS
Latency
tRC
70ns
tRAS
50ns
tRP
20ns
tRRD
20ns
tRCD
20ns
tCCD
10ns
tCDL
10ns
tRDL
10ns
Frequency
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
3
3
2
9
7
6
6
5
4
3
2
2
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
CLOCK FREQUENCY AND LATENCY PARAMETERS – 100MHz SDRAM (Unit = number of clock)
CAS
Latency
tRC
70ns
tRAS
50ns
tRP
20ns
tRRD
20ns
tRCD
20ns
tCCD
10ns
tCDL
10ns
tRDL
10ns
Frequency
100MHz (10.0ns)
83MHz (12.0ns)
3
2
7
6
5
5
2
2
2
2
2
2
1
1
1
1
1
1
REFRESH CYCLE PARAMETERS
-10
-12
Parameter
Symbol
tREF
Units
Min
Max
Min
Max
Refresh Period (1,2)
—
64
—
64
ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
SDRAM COMMAND TRUTH TABLE
Function
SDCE#
SDRAS#
SDCAS#
SDWE#
BWE#
A12, A13
SDA10 A11-0
Notes
Mode Register Set
Auto Refresh (CBR)
L
L
L
L
L
L
L
L
L
L
L
H
X
X
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
X
BA
X
X
L
Single Bank
L
H
H
H
L
2
Precharge
Precharge all Banks
L
L
H
Bank Activate
Write
L
H
L
BA
BA
BA
BA
BA
X
Row Address
2
2
2
2
2
3
H
H
H
H
H
H
X
X
X
L
H
L
Write with Auto Precharge
Read
L
L
L
L
Read with Auto Precharge
Burst Termination
No Operation
L
H
L
H
X
X
X
X
X
H
H
X
X
X
H
X
X
X
X
Device Deselect
X
Data Write/Output Disable
Data Mask/Output Disable
NOTES:
X
4
4
H
X
1. All of the SDRAM operations are defined by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE 0-3 at the positive rising edge of the clock.
2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled and become high impedance after a two
clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
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MODE REGISTER SET TABLE
A11 A10
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Mode Register (Mx)
Reserved* WB Op Mode
CAS Latency BT
Burst Length
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
2
4
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
-
-
All other states reserved
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
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SDRAM CURRENT STATE TRUTH TABLE
Current
State
Command
Action
Notes
SDCE#
SDRAS# SDCAS#
SDWE#
A12 & A13
(BA)
A11-A0
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
Set the Mode Register
Start Auto
1
1
Idle
Row Active
Read
X
X
X
L
H
H
L
X
No Operation
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Activate the specified bank and row
ILLEGAL
H
H
H
H
X
L
Column
2
1
1
L
H
L
Column
ILLEGAL
H
H
X
L
X
X
X
No Operation
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Precharge
3
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
1
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
4,5
4,5
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
H
H
H
H
X
L
Column
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
OP Code
Write
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
H
H
H
H
X
Column
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
5,6
5,6
L
H
L
Column
Read
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
H
X
X
X
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SDRAM CURRENT STATE TRUTH TABLE (cont'd)
Current
State
Command
Action
Notes
SDCE#
SDRAS# SDCAS#
SDWE#
A12 & A13
(BA)
A11-A0
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
Read with Auto
Precharge
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
ILLEGAL
H
H
H
H
X
L
Column
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
H
X
L
X
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
Write with Auto
Precharge
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
H
X
L
X
Continue the Burst
Continue the Burst
ILLEGAL
X
OP Code
Precharging
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
No Operation; Bank(s) idle after tRP
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
2
2
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
ILLEGAL
20
H
H
X
L
X
X
X
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
ILLEGAL
H
X
L
X
X
OP Code
Row Activating
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
No Operation; Row active after tRCD
No Operation; Row active after tRCD
No Operation; Row active after tRCD
H
X
X
X
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WED9LC6816V
SDRAM Current State Truth Table (cont'd)
Current
State
Command
Action
Notes
SDCE#
SDRAS# SDCAS#
SDWE#
A12 & A13
(BA)
A11-A0
Description
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto orSelf Refresh
Precharge
ILLEGAL
Write Recovering
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
6
6
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row active after tDPL
No Operation; Row active after tDPL
No Operation; Row active after tDPL
ILLEGAL
H
H
H
H
X
L
Column
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
H
X
L
X
X
OP Code
Write Recovering
with Auto
Precharge
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
2
H
H
H
H
X
L
Column
ILLEGAL
2,6
2,6
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
ILLEGAL
H
X
L
X
X
OP Code
Refreshing
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
H
X
L
X
X
OP Code
Mode Register
Accessing
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
ILLEGAL
H
X
X
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
X
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal
depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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Figure 5 – SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3,
BURST LENGTH = 1
6
0
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
tCH
tCL
tCC
tRCD
tRAS
SDCE#
tSS
tSH
tRP
tRCD
tSH
tSS
SDRAS#
tCCD
tSS
tSH
SDCAS#
ADDR
tSS
tSH
tSH
tSS
Cb
BS
Cc
Ra
Ca
Rb
BA0, 1
[A12,A13]
BS
Rb
BS
Ra
BS
BS
BS
SDA10
tRAC
tSS
tSS
tSS
tSH
tSH
tSH
tSAC
Qa
Db
Qc
DQ
tSLZ
tOH
SDWE#
BWE#
Read
Read
Write
Row Active
Row Active
DON’T CARE
Precharge
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Figure 6 – SDRAM POWER UP SEQUENCE
6
0
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
tRFC
tRFC
tRP
SDRAS#
SDCAS#
ADDR
Key
RAa
BA0,1
[A12,A13]
RAa
SDA10
DQ
HIGH-Z
SDWE#
BWE#
High level is necessary
Auto Refresh
Mode Register Set
Precharge
(All Banks)
Auto Refresh
Row Active
(A-Bank)
DON’T CARE
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Figure 7 – SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
Note 1
tRC
tRCD
SDRAS#
SDCAS#
ADDR
Ra
Ca0
Rb
Cb0
BA0, 1
[A12,A13]
Ra
Rb
SDA10
tSHZ Note 4
tRAC
Note 3
tRDL
Db0 Db1 Db2 Db3
tOH
tSAC
Qa0 Qa1 Qa2 Qa3
CL=2
DQ
tSHZ Note 4
tRAC
Note 3
tRDL
tOH
tSAC
Qa3
Db0 Db1 Db2 Db3
Qa0 Qa1 Qa2
CL=3
SDWE#
BWE#
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ
)
after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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Figure 8 – SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
tRCD
SDRAS#
Note 2
SDCAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA0, 1
[A12,A13]
Ra
SDA10
tRDL
Dd1
Qa0
Qa1
Qb1
Qb2
Dc0
Dc0
Dc1
tCDL
Dc1
Qb0
Dd0
CL=2
DQ
Qa3
Dd0 Dd1
Qa0 Qa1 Qa2
CL=3
SDWE#
BWE#
Note 3
Note 1
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
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Figure 9 – SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
Note 1
SDCE#
SDRAS#
SDCAS#
ADDR
Note 2
RAa
CAa RBb
CBb
CAc
CAe
CBd
BA0, 1
[A12,A13]
RAa
RBb
SDA10
QAa0 QAa1 QAa2
QAa0 QAa1
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa3
QAa2
CL=2
DQ
QAa3 QBb0 QBb1 QBb2 Qbb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
CL=3
SDWE#
BWE#
Read
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Row Active
Precharge
(A-Bank)
(B-Bank)
(B-Bank)
DON’T CARE
Read
(A-Bank)
NOTES:
1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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Figure 10 – SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
Note 2
SDCAS#
ADDR
RAa
CAa RBb
CBb
CAc
CBb
BA0, 1
[A12,A13]
SDA10
DQ
RAa
RBb
tCDL
tRDL
DBd1
DAa3
DBb1 DBb2 DBb3 DAc0 DAc1
DAa0 DAa1 DAa2
DBb0
DBd0
SDWE#
BWE#
Note 1
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(B-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
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Figure 11 – SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA0, 1
[A12,A13]
RAa
RBb
RAc
SDA10
tCDL
Note 1
QAa0
DBb0 DBb1
DBb0 DBb1
DBb3
DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
QAa1 QAa2
QAa0 QAa1
DBb2
DBb2
QAa3
QAa2
CL=2
DQ
CL=3
QAa3
SDWE#
BWE#
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
DON’T CARE
Row Active
(A-Bank)
Row Active
(A-Bank)
NOTES:
1. CDL should be met to complete write.
t
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Figure 12 – SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCLK
SDCE#
SDRAS#
SDCAS#
ADDR
Ra
Rb
Ca
Cb
BA0, 1
[A12,A13]
Ra
Rb
SDA10
Qa0
Db0
Db0
Db1 Db2
Db3
Qa1 Qa2 Qa3
CL=2
DQ
CL=3
Qa3
Db1
Db3
Qa0 Qa1
Db2
Qa2
SDWE#
BWE#
Row Active
(A-Bank)
Auto Precharge
Start Point
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
DON’T CARE
NOTES:
1. CDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
t
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Figure 13 – SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @
BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13]
RAa
SDA10
CL=2
Note 2
1
1
QAb2 QAb3 QAb4 QAb5
QAb0
QAb1
QAa0 QAa1
QAa3 QAa4
QAa2
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=3
SDWE#
BWE#
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Burst Stop
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
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Figure 14 – SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @
BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13]
RAa
SDA10
DQ
tBDL
tRDL
Note 2
DAb0 DAb1 DAb2 DAb3 DAB4 DAb5
DAa0 DAa1 DAa2 DAa3 DAa4
SDWE#
BWE#
Write
(A-Bank)
Row Active
(A-Bank)
Burst Stop
Precharge
(A-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE# at write interrupt by
precharge command is needed to prevent invalid write.
BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row recharge cycle will be masked
internally.
3. Burst stop is valid at every burst length.
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Figure 15 – SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
RBb CAb
RAc
CBc
CAd
BA0, 1
[A12,A13]
RAa
RBb
RAc
SDA10
DAa0
DAa0
QAb0
DBc0
DBc0
QAd1
QAb1
QAd0
CL=2
DQ
CL=3
QAd0 QAd1
QAa1 QAb1
SDWE#
BWE#
Row Active
(A-Bank)
Precharge
(Both Banks)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Row Active
(B-Bank)
Read with
Write
Auto Precharge
(A-Bank)
(A-Bank)
DON’T CARE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in
the case of BRSW write command, the next cycle starts the precharge.
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Rev. 2
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WED9LC6816V
Figure 16 –
SDRAM MODE REGISTER SET CYCLE
SDRAM AUTO REFRESH CYCLE
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
SDCK
HIGH
SDCE#
Note 2
tRFC
SDRAS#
Note 1
Note 3
SDCAS#
ADDR
Key
Ra
DQ
HI-Z
HI-Z
SDWE#
BWE#
MRS
New
Command
Auto Refresh
New Command
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS# activation.
3. Please refer to Mode Register Set Table.
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July 2010 © 2010 Microsemi Corporation. All rights reserved.
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WED9LC6816V
PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY) JEDEC MP-163
153x Ø 0.762 (0.030) NOM
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.61 (0.024)
NOM
1.27 (0.050) TYP
10.16 (0.400) NOM
14.1 (0.555) MAX
1.97 (0.078)
MAX
NOTE:
Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Ordering Information
Commercial (0°C ≤ TA ≤ 70°C)
Industrial (-40°C ≤ TA ≤ 85°C)
Part Number
SSRAM Access
200MHz
SDRAM Access
Part Number
SSRAM Access
200MHz
SDRAM Access
WED9LC6816V2012BC
WED9LC6816V2010BC
WED9LC6816V1612BC
WED9LC6816V1610BC
WED9LC6816V1512BC
WED9LC6816V1510BC
WED9LC6816V1312BC
WED9LC6816V1310BC
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
WED9LC6816V2012BI
WED9LC6816V2010BI
WED9LC6816V1612BI
WED9LC6816V1610BI
WED9LC6816V1512BI
WED9LC6816V1510BI
WED9LC6816V1312BI
WED9LC6816V1310BI
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
200MHz
200MHz
166MHz
166MHz
166MHz
166MHz
150MHz
150MHz
150MHz
150MHz
133MHz
133MHz
133MHz
133MHz
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2010 © 2010 Microsemi Corporation. All rights reserved.
Rev. 2
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WED9LC6816V
Document Title
256Kx32 SSRAM/4Mx32 SDRAM – External Memory Solution for Texas Instruments TMS320C6000 DSP
Revision History
Rev #
History
Release Date Status
Rev 2
Changes (Pg. 1, 26)
July 2010
FINAL
2.1 Corrected pinout – Row C missing - added, B4 - VSS, B5 - SDCE#
2.2 Corrected MO drawing
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2010 © 2010 Microsemi Corporation. All rights reserved.
Rev. 2
26
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
WED9LC6816V1512BC
Memory Circuit, SDRAM+SRAM, 4MX32, CMOS, PBGA153, 14 X 22 MM, MO-163, BGA-153
MICROSEMI
WED9LC6816V2010BC
Memory Circuit, SDRAM+SRAM, 4MX32, CMOS, PBGA153, 14 X 22 MM, MO-163, BGA-153
MICROSEMI
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