WEDPN16M64VR-100BI [MICROSEMI]
Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPN16M64VR-100BI |
| 厂家： | 
Microsemi |
| 描述： | Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219 动态存储器 |
| 文件： | 总13页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPN16M64VR-XBX
16MX64REGISTEREDSYNCHRONOUSDRAM
FEATURES
GENERAL DESCRIPTION
! Registered for enhanced performace of bus speeds
The 128MByte (1Gb) SDRAMis a high-speed CMOS, dynamic
random-access,memoryusing4 chipscontaining268,435,456
bits. Each chip is internally configured as a quad-bank DRAM
with a synchronous interface. Each of the chip’s 67,108,864-
bit banks is organized as 8,192 rows by 512 columns by 16
bits. The MCP also incorporates two 16-bit universal bus
drivers for input control signals and addresses.
• 66, 100, 125, 133** MHz
! Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
! Single 3.3V ± 0.3V power supply
! Fully Synchronous; all signals registered on positive edge
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-12 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column
location for the burst access.
of system clock cycle
! Internal pipelined operation; column address can be
changed every clock cycle
! Internal banks for hiding row access/precharge
! Programmable Burst length 1,2,4,8 or full page
! 8,192 refresh cycles
! Commercial, Industrial and Military Temperature Ranges
! Organized as 16M x 64
• User configureable as 32M x 32
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be
enabled to provide a self-timed row precharge thatisinitiated
at the end of the burst sequence.
! Weight: WEDPN16M64VR-XBX - 2.5 grams typ ical
BENEFITS
! 37% SPACE SAVINGS
The 1Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve ahigh-speed,fullyrandomaccess.Precharging
one bank while accessing one of the other three banks will
hide the precharge cycles and provide seamless, high-
speed, random-access operation.
! 17% I/O Reduction
! Reduced part count
! Reduced trace lengths for lower parasitic capacitance
! Glue-less connection to memory controller/PCI Bridge
! Suitable for hi-reliability applications
! Laminate interposer for optimum TCE match
! Upgradeable to 32M x 64 density (contact factory for
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.
information)
*This data sheet describes a product that is subject to change without notice.
**Available in commercial and industrial temperatures only.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability to
interleave between internal banks in order to hide precharge
time and the capability to randomly change column ad-
dresses on each clock cycle during a burst access.
November 2003 Rev. 4
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WEDPN16M64VR-XBX
FIG. 1 PIN CONFIGURATION
TOP VIEW
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
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WEDPN16M64VR-XBX
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
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WEDPN16M64VR-XBX
FUNCTIONAL DESCRIPTION
mode and a write burstmode, asshowninFigure 3. The Mode
Register is programmed via the LOAD MODE REGISTER com-
mand and will retain the stored information until it is pro-
grammed again or the device loses power.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-12 select the
row). The address bits (A0-8) registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
Mode register bits M0-M2 specify the burst length, M3 speci-
fies the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITEburst mode, and M10 and M11
are reserved for future use. Address A12 (M12) is undefined
butshould be drivenLOWduringloadingofthe mode register.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either ofthese
requirements will result in unspecified operation.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering
device initialization, register definition, command descrip-
tions and device operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Figure
3. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available forthe sequentialtype.
The full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied to
VDD and VDDQ (simultaneously) and the clock is stable
(stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires
a 100µs delay prior to issuing any command other than a
COMMAND INHIBIT or a NOP. Starting at some point during
this 100µs period and continuing at least through the end of
this period, COMMAND INHIBIT or NOP commands should
be applied.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-8 when the
burst length is set to two; by A2-8 when the burst length is
set to four; and by A3-8 when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
be precharged, therebyplacingthe device inthe allbanksidle
state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. Afterthe AUTO REFRESHcycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Registerwillpowerup inanunknownstate, itshould be
loaded prior to applying any operational command.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit M3.
REGISTER DEFINITION
MODE REGISTER
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in Table 1.
The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion ofa burst length, a burst type, a CASlatency, an operating
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WEDPN16M64VR-XBX
TABLE 1 - BURST DEFINITION
FIG. 1 MODE REGISTER DEFINITION
Burst
Length
StartingColumn
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
A0
0
2
4
0-1
1-0
0-1
1-0
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A4
A
3
A
2
A
1
A
0
Address Bus
1
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency BT
Burst Length
Unused
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
Burst Length
A2 A1 A0
M2 M1M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Full
Page
(y)
n = A0-9/8/7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Sequential
Interleaved
NotSupported
1
(location 0-y)
Cn…
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects
the starting column within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select
the starting column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2
select the starting column within the block.
3
Reserved
Reserved
Reserved
Reserved
5. For a full-page burst, the full row is selected and A0-8 select the starting
column.
6. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed,
and Mode Register bit M3 is ignored.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
-
-
All other states reserved
Write Burst Mode
M9
0
1
Programmed Burst Length
Single Location Access
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WEDPN16M64VR-XBX
FIG. 4 CAS LATENCY
CAS LATENCY
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions
may result.
The CAS latency is the delay, in clock cycles, between the
registration ofa READcommand and the availabilityofthe first
piece of output data. The latency can be set to two or three
clocks.
WRITE BURST MODE
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+ m. The I/Os will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge n
+ m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is
registered atT0 and the latencyis programmed to two clocks,
the I/Os will start driving after T1 and the data will be valid by
T2. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
CAS
SPEED
-133
-125
-100
-66
LATENCY = 2
LATENCY = 3
≤ 100
≤ 100
≤ 66
≤ 133
≤ 125
≤ 100
≤ 66
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
≤ 50
OPERATING MODE
COMMANDS
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
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WEDPN16M64VR-XBX
TRUTH TABLE - COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION)
CS
H
L
L
L
L
L
L
L
L
–
RAS
X
H
L
CAS
X
H
H
L
WE
X
H
H
H
L
DQM
X
ADDR
I/Os
X
COMMAND INHIBIT (NOP)
X
NO OPERATION (NOP)
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
X
X
H
H
H
L
L/H 8
L/H 8
X
X
L
Valid
Active
X
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
X
Code
X
L
H
L
X
X
L
L
X
Op-Code
–
X
Write Enable/Output Enable (8)
–
–
–
L
Active
High-Z
Write Inhibit/Output High-Z (8)
–
–
–
–
H
–
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register.
3. A0-12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internalrefresh countercontrols row addressing;allinputs and I/Os are “Don’t Care”except forCKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
REGISTER FUNCTION TABLE
LOAD MODE REGISTER
INPUTS
OE LE CLK
OUTPUT
Y
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
A
H
L
L
L
L
L
X
L
X
X
L
Z
L
H
L
H
X
L
X
H
L
H
H
H
I
I
H
X
ACTIVE
L or H
Y (1)
0
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A12 selects the row. This row remains active
(or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
NOTES:
1. Output level before the indicated steady-state input
conditions were established.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
READ
The READ command is used to initiate a burst read access to
an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-8 selects the
starting column location. The value on input A10 determines
whetherornotAUTO PRECHARGEisused.IfAUTO PRECHARGE
isselected, the row beingaccessed willbe precharged at the
end of the READ burst; if AUTO PRECHARGE is not selected,
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOPto anSDRAMwhichisselected (CSisLOW). Thisprevents
unwanted commandsfrombeingregistered duringidle orwait
states. Operations already in progress are not affected.
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WEDPN16M64VR-XBX
the row willremain open forsubsequent accesses. Read data
appears on the I/Os subject to the logic level on the DQM
inputs two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding I/Os willbe High-Ztwo clocks later;
if the DQM signal was registered LOW, the I/Os will provide
valid data.
AUTO PRECHARGE does not apply. AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
AUTO PRECHARGEensuresthatthe precharge isinitiated atthe
earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP)iscompleted.Thisisdetermined asifanexplicitPRECHARGE
command was issued at the earliest possible time.
WRITE
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-8 selects the
starting column location. The value on input A10 determines
whetherornotAUTO PRECHARGEisused.IfAUTO PRECHARGE
is selected, the row beingaccessed willbe precharged at the
end of the WRITE burst; if AUTO PRECHARGE is not selected,
the row willremainopenforsubsequent accesses. Input data
appearing on the I/Os is written to the memory array subject
to the DQM input logic level appearing coincident with the
data. Ifa givenDQMsignalis registered LOW, the correspond-
ing data will be written to memory; if the DQM signal is
registered HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.
AUTO REFRESH
AUTO REFRESHis used during normaloperation ofthe SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in
conventional DRAMs. This command is nonpersistent, so it
must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller.
This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each 256Mb SDRAM requires 8,192
AUTO REFRESH cycles every refresh period (tREF). Providing
a distributed AUTO REFRESH command will meet the refresh
requirement and ensure that each row is refreshed. Alterna-
tively, 8,192 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (tRC), once every refresh
period (tREF).
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is
disabled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care,” with
the exception of CKE, which must remain LOW.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bankPRECHARGEfunctiondescribed above,without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a
specific READ or WRITE command. A precharge of the bank/
row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
Once self refresh mode is engaged, the SDRAM provides its
own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh mode
for a minimum period equal to tRAS and may remain in self
refresh mode for an indefinite period beyond that.
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WEDPN16M64VR-XBX
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defined
as a signal cycling within timing constraints specified for the
clock pin) prior to CKE going back HIGH. Once CKE is HIGH,
the SDRAM must have NOP commands issued (a minimum of
two clocks) for tXSR, because time is required for the
completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
* Self refresh available in commercial and industrial temperatures only.
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (NOTE 2)
Parameter
Unit
V
Parameter
Symbol Max
Unit
Voltage on VDD, VDDQ Supply relative to Vss
Voltage on NC or I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
-1 to 4.6
-1 to 4.6
Input Capacitance: CLK
CI1
CA
CI2
CIO
20
8
pF
V
Addresses, BA0-1 Input Capacitance
InputCapacitance:Allotherinput-onlypins
Input/OutputCapacitance:I/Os
pF
pF
pF
-55 to + 125
-40 to + 85
-55 to + 150
°C
10
10
°C
°C
NOTE:Stress greaterthan those listed under"Absolute MaximumRatings"may
cause permanent damage to the device. This is a stress rating only and
functionaloperation ofthe device at these oranyotherconditions greaterthan
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximumratingconditions forextended periods may
affect reliability.
BGA THERMAL RESISTANCE
Description
Symbol
Max
Unit Notes
Junction to Ambient (No Airflow)
Theta JA
14.7
ºC/W
ºC/W
ºC/W
1
1
1
Junction to Bail
Theta JB
ThetaJC
10.7
4.0
Junctionto Case (Top)
NOTE:
Refer to PBGA Thermal Resistance Correlation Application note at
www.whiteedc.com in the application notes section for modeling conditions.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Min
Units
Max
SupplyVoltage
VCC
VIH
VIL
II
3
2
3.6
V
V
InputHighVoltage:Logic 1;Allinputs(21)
InputLow Voltage:Logic 0;Allinputs(21)
InputLeakage Current:Anyinput0V-VIN -VCC(Allotherpinsnotundertest= 0V)
OutputLeakage Current:I/Osare disabled;0V-VOUT -VCC
OutputHighVoltage (IOUT = -4mA)
VCC + 0.3
-0.3
-5
0.8
5
V
µA
µA
V
IOZ
VOH
VOL
-5
5
2.4
–
–
OutputLow Voltage (IOUT = 4mA)
0.4
V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Max
Units
OperatingCurrent:Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
ICC1
700
mA
StandbyCurrent:Active Mode;CKE= HIGH;CS= HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19)
ICC3
240
mA
OperatingCurrent:BurstMode;Continuousburst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
ICC4
ICC7
750
20
mA
mA
SelfRefreshCurrent:CKE-0.2V (27, 28)
9
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WEDPN16M64VR-XBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11, 29)
Parameter
Symbol
-133
Max
-125
-100
-66
Min
Unit
Min
Min
Max
Min
Max
Max
CL = 3
CL = 2
tAC
tAC
tAH
tAS
5.4
6
5.8
6
6
6
7.5
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
—
ns
ns
Access time from CLK (pos. edge)
Addresshold time
Addresssetup time
CLKhigh-levelwidth
CLKlow-levelwidth
0.8
1.5
2.5
2.5
7.5
10
1
2
1
2
1
2
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
3
3
3
3
3
3
CL = 3
8
10
15
1
15
20
1
Clock cycle time (22)
CL = 2
10
1
CKEhold time
0.8
1.5
0.8
1.5
0.8
1.5
CKEsetup time
2
2
2
CS, RAS, CAS, WE, DQMhold time
CS, RAS, CAS, WE, DQMsetup time
Data-inhold time
1
1
1
2
2
2
1
1
1
Data-insetup time
2
2
2
CL = 3 (10)
CL = 2 (10)
tHZ
5.4
6
5.8
6
6
6
7.5
9
Data-out high-impedance time
tHZ
Data-outlow-impedance time
Data-outhold time (load)
tLZ
1
1
1
2
3
tOH
3
3
3
Data-outhold time (no load)(26)
ACTIVE to PRECHARGE command
ACTIVEto ACTIVEcommand period
ACTIVE to READ or WRITE delay
tOH
N
1.8
44
66
20
1.8
50
70
20
1.8
50
70
20
1.8
60
70
30
tRAS
tRC
120,000
120,000
120,000
120,000
tRCD
tREF
tREF
tRFC
tRP
Refresh period (8,192 rows) – Commercial, Industrial
Refreshperiod (8,192 rows)–Military
AUTO REFRESH period
64
16
64
16
64
16
64
16
66
20
70
20
70
20
90
PRECHARGEcommand period
30
ACTIVEbankAto ACTIVEbankBcommand
Transitiontime (7)
tRRD
tT
15
20
20
20
0.3
1.2
0.3
1.2
0.3
1.2
1
1 CLK + 7.5ns
15
1.2
WRITE recovery time
(23)
(24)
1CLK + 7.5ns
15
1CLK + 7.5ns
15
1 CLK + 7.5ns
15
tWR
tXSR
Exit SELF REFRESH to ACTIVE command
75
80
80
90
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10
WEDPN16M64VR-XBX
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11, 29)
Parameter/Condition
Symbol
tCCD
tCKED
tPED
-133
1
-125
1
-100
1
-66
1
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
READ/WRITEcommand to READ/WRITEcommand (17)
CKEto clockdisable orpower-downentrymode (14)
CKEto clockenable orpower-downexitsetup mode (14)
DQMto inputdatadelay(17)
1
1
1
1
1
1
1
1
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
0
0
0
0
DQMto datamaskduringWRITEs
0
0
0
0
DQMto datahigh-impedance duringREADs
WRITEcommand to inputdatadelay(17)
Data-into ACTIVEcommand (15)
2
2
2
2
0
0
0
0
5
5
4
4
Data-into PRECHARGEcommand (16)
2
2
2
2
Lastdata-into burstSTOPcommand (17)
Lastdata-into new READ/WRITEcommand (17)
Lastdata-into PRECHARGEcommand (16)
LOADMODEREGISTERcommand to ACTIVEorREFRESHcommand (25)
tBDL
1
1
1
1
tCDL
tRDL
1
1
1
1
2
2
2
2
tMRD
2
2
2
2
CL = 3
CL = 2
tROH
3
3
3
3
Data-outto high-impedance fromPRECHARGEcommand (17)
tROH
2
2
2
2
NOTES:
1. All voltages referenced to VSS.
12. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL levels.
2. Thisparameterisnottested butguaranteed bydesign.f= 1 MHz,TA= 25°C.
3. IDD is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
4. Enableson-chip refreshand addresscounters.
5. The minimum specifications are used only to indicate cycle time at which
properoperationoverthe fulltemperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two
AUTO REFRESHcommands, before properdevice operation is ensured. (VCC
must be powered up simultaneously.) The two AUTO REFRESH command
wake-ups should be repeated any time the tREFrefresh requirement is
exceeded.
13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only
at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a
reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not
dependentonanytimingparameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to
the fact that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition everytwo clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width - 3ns, and the
pulse width cannot be greater than one third of the cycle rate. VIL undershoot:
VIL (MIN) = -2V for a pulse width - 3ns.
22. The clock frequency must remain constant (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin) during
access or precharge states (READ, WRITE, including tWR, and PRECHARGE
commands). CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins
7.5ns after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE
must transit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
9. Outputs measured at 1.5Vwith equivalent load:
25. JEDEC and PC100 specify three clocks.
10. tHZ defines the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data element will
meet tOH before going High-Z.
26. Parameterguaranteed bydesign.
27. Self refresh available in commercial and industrial temperatures only.
28. OE high.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing
referenced to 1.5Vcrossoverpoint.
29. All AC timings do not count extra clock cycle needed on control signals
to be registered.
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPN16M64VR-XBX
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM View
32.1 (1.264) MAX
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
25.1 (0.988)
MAX
19.05 (0.750)
NOM
H
G
F
E
D
C
B
A
1.27 (0.050)
NOM
0.61 (0.024) NOM
219 x
Ø 0.762 (0.030) NOM
2.03 (0.080)
MAX
19.05 (0.750) NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P N 16M64 V R - XXX B X
DEVICEGRADE:
M = Military
-55°C to + 125°C
I = Industrial
C = Commercial
-40°C to + 85°C
0°C to + 70°C
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA)
FREQUENCY(MHz)
133 = 133MHz*
125 = 125MHz
100 = 100MHz
66 = 66MHz
IMPROVEMENT MARK
R = Registered
3.3V Power Supply
CONFIGURATION, 16 M x 64
SDRAM
PLASTIC
WHITEELECTRONICDESIGNSCORP.
*133 MHz available in Commercial and Industrial Temperatures Only
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
12
WEDPN16M64VR-XBX
Document Title
16M x 64 Registered Synchronous DRAM
Revision History
Rev #
Rev 0
Rev 1
History
Release Date
July 2001
Status
Initial Release
Advanced
Advanced
Changes (Pg. 1, 3, 9, 10, 11)
September 2001
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Change speed to 66MHz-133MHz for commercial and industrial temperature.
Change speed to 66MHz-125MHz for Military temperature.
Add 125 MHz and 133 MHz AC characteristics
Correct typo on Pg. 3 Block Diagram, U4 and U5
Remove Input Leakage Address Current from DC Characteristics
Change Icc4 to 750mA
Change Icc7 to 20mA
Remove Self Refresh Current for Industrial Temperatures
Update AC Characteristics Pg. 10 and 11
1.10 Add notes 28 and 29 on Pg. 11
Changes (Pg. 1)
Rev 2
Rev 3
1.1
Change status to Preliminary
January 2002
June 2003
Preliminary
Final
Changes (Pg. 1)
1.1
1.2
Change Status to Final
Add Thermal Resistance Table
Rev 4
Changes (Pg. 1, 12, 13)
1.1 Change mechanical drawing to new style
November 2003
Final
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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