WEDPN8M72V-133B2I [MICROSEMI]
Synchronous DRAM, 8MX72, 5.5ns, CMOS, PBGA219, 21 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPN8M72V-133B2I |
| 厂家： | 
Microsemi |
| 描述： | Synchronous DRAM, 8MX72, 5.5ns, CMOS, PBGA219, 21 X 25 MM, PLASTIC, BGA-219 动态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPN8M72V-XB2X
8Mx72 Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
High Frequency = 100, 125, 133MHz
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134,217,728
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chip’s 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits.
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm
Single 3.3V ± 0.3V power supply
Fully Synchronous; all signals registered on positive edge
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of anACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-11 select
the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location
for the burst access.
of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1, 2, 4, 8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 8M x 72
Weight: WEDPN8M72V-XB2X - 2 grams typical
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option.AnAUTO PRECHARGE function may be enabled
to provide a self-timed row precharge that is initiated at the end
of the burst sequence.
BENEFITS
60% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
The 512Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible with
the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing
one of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
Upgradeable to 16M x 72 and 32M x 72 densities (contact
factory for information)
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
* This product is subject to change without notice.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave between internal
banks in order to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a burst access.
Continued on page 4
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
WEDPN8M72V-XB2X
S
A
11.9
11.9
11.9
11.9
11.9
V
I
21
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
22.3
N
G
S
WEDPN8M72V-XB2X
25
Area
5 x 265mm2 = 1,328mm2
5 x 54 balls = 270 pins
525mm2
60%
19%
I/O Count
219 Balls
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February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 5
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WEDPN8M72V-XB2X
FIGURE 1 – PIN CONFIGURATION
Top View
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DQ0
DQ2
DQ4
DQ5
DQ14 DQ15
DQ12 DQ13
DQ10 DQ11
VSS
VSS
VCC
VCC
NC
NC
NC
VSS
VSS
NC
VSS
VSS
VCC
VCC
NC
A9
A0
A2
A10
A11
A8
A1
A3
VCC
VCC
VSS
VSS
NC
VCC
VCC
VSS
VSS
NC
DQ16 DQ17 DQ31
VSS
A
B
C
D
E
F
DQ1
DQ3
DQ6
DQ7
A7
A6
DQ18 DQ19 DQ29 DQ30
DQ20 DQ21 DQ27 DQ28
DQ22 DQ23 DQ26 DQ25
A5
A4
DQ8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ9
DQMH0
CLK0
CKE0
VCC
DNU* DNU DNU DNU
DQML
0
NC
BA0
BA1
NC
DQML1
VSS
VSS
VSS
Vss
VSS
VSS
VSS
VSS
NC
DQMH1
NC
DQ24
CLK1
CKE1
VCC
CAS0# WE0#
CS0# RAS0#
RAS1# WE1#
CAS1# CS1#
G
H
J
VSS
VSS
NC
NC
VSS
VSS
VCC
VCC
NC
NC
VSS
VSS
VCC
VCC
VCC
VCC
CKE3
CLK3
CS3#
CKE2
CLK2
DQMH2
RAS2# CS2#
WE2# CAS2#
K
L
CAS3# RAS3#
DQ56 DQMH3
WE3# DQML3 CKE4 DQMH4 CLK4 CAS4# WE4# RAS4# CS4#
DQML2
DQ39
M
N
P
R
T
DQ57 DQ58 DQ55 DQ54
DQ60 DQ59 DQ53 DQ52
DQ62 DQ61 DQ51 DQ50
NC
VSS
VCC
VCC
NC
VSS
VCC
VCC
DQ73 DQ72 DQ71 DQ70
DQ75 DQ74 DQ69 DQ68
DQ77 DQ76 DQ67 DQ66
DQ79 DQ78 DQ65 DQ64
DQML4
VCC
VSS
NC
VCC
VSS
VSS
DQ41 DQ40 DQ37 DQ38
DQ43 DQ42 DQ36 DQ35
DQ45 DQ44 DQ34 DQ33
Vss
DQ63 DQ49 DQ48
VSS
DQ47 DQ46 DQ32
VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
* Pin D7 is DNU for 8M x 72 product, Pin D7 is A12 for 16M x 72 and higher densities.
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WEDPN8M72V-XB2X
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE0#
RAS
CAS
0#
0
#
CAS#
WE# RAS#
A0-11
A0-11
DQ0
DQ0
BA0-1
BA0-1
•
•
•
•
CLK
CKE
0
0
CLK
CKE
CS#
DQML
DQMH
•
•
U0
•
•
CS0
#
•
•
•
DQML
DQMH
0
•
DQ15
DQ15
0
WE1#
RAS
CAS
1#
1
#
WE# RAS# CAS#
A0-11
DQ0
DQ16
BA0-1
•
•
•
•
CLK
CKE
1
1
CLK
CKE
CS#
DQML
DQMH
•
•
U1
•
•
CS1
#
•
•
•
•
DQML
DQMH
1
DQ15
DQ31
1
WE2#
RAS
CAS
2#
2
#
WE# RAS# CAS#
A0-11
DQ0
DQ32
BA0-1
•
•
•
•
CLK
CKE
2
2
CLK
CKE
CS#
DQML
DQMH
•
•
U2
•
•
CS2
#
•
•
•
•
DQML
DQMH
2
DQ15
DQ47
2
WE3#
RAS
CAS
3#
3
#
WE# RAS#
CAS#
A0-11
DQ0
DQ48
BA0-1
•
•
•
•
CLK
CKE
3
3
CLK
CKE
CS#
DQML
DQMH
•
•
U3
•
•
CS3
#
•
•
•
•
DQML
DQMH
3
DQ15
DQ63
3
WE4#
RAS
CAS
4#
4
#
WE# RAS# CAS#
A0-11
DQ0
DQ64
BA0-1
•
•
•
•
CLK
CKE
4
4
CLK
CKE
CS#
DQML
DQMH
•
•
U4
•
•
CS4
#
•
•
•
•
DQML
DQMH
4
DQ15
DQ79
4
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FUNCTIONAL DESCRIPTION
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of anACTIVE command which
is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank, A0-11 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register definition, command descriptions and device
operation.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected byA1-8 when the burst length is set to two; byA2-8 when
the burst length is set to four; and by A3-8 when the burst length
is set to eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Once power is applied to VDD and
the clock is stable (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin), the SDRAM
requires a 100μs delay prior to issuing any command other than a
COMMAND INHIBIT or a NOP. Starting at some point during this
100μs period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied. Once
the 100μs delay has been satisfied with at least one COMMAND
INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must be precharged,
thereby placing the device in the all banks idle state.
FIGURE 3 – MODE REGISTER DEFINITION
A11 A10
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency BT
Burst Length
*Should program
Burst Length
M11, M10 = 0, 0 to
ensure compatibility
with future devices.
M2 M1M0
M3 = 0
M3 = 1
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should be
loaded prior to applying any operational command.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
2
4
4
8
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation
of the SDRAM. This definition includes the selec-tion of a burst
length, a burst type, a CAS latency, an operating mode and a
write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
Mode register bits M0-M2 specify the burst length, M3 specifies the
type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the
WRITE burst mode, and M10 and M11 are reserved for future use.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
-
-
All other states reserved
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecified operation.
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
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met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after T1 and
the data will be valid by T2. Table 2 below indicates the operating
frequencies at which each CAS latency setting can be used.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
OPERATING MODE
TABLE 1 – BURST DEFINITION
The normal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length
applies to both READ and WRITE bursts.
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst
Length
Starting Column
Address
A0
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions may
result.
2
4
0
1
0-1
0-1
1-0
1-0
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
WRITE BURST MODE
0
1
When M9 = 0, the burst length programmed via M0-M2 applies
to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
TABLE 2 – CAS LATENCY
0
0
1
ALLOWABLE OPERATING FREQUENCY (MHz)
0
1
0
SPEED
-100
CAS LATENCY = 2
CAS LATENCY = 3
≤ 100
8
0
1
1
≤ 75
≤ 100
≤ 100
1
0
0
-125
≤ 125
1
0
1
-133
≤ 133
1
1
0
1
1
1
COMMANDS
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1, Cn…
Full Page
(y)
n = A0-9/8/7
(location 0-y)
Not Supported
The Truth Table provides a quick reference of available commands.
This is followed by a written description of each command. Three
additional Truth Tables appear following the Operation section;
these tables provide current state/next state information.
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting column
within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK signal
is enabled. The SDRAM is effectively deselected. Operations already
in progress are not affected.
7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode Register bit
M3 is ignored.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP
to an SDRAM which is selected (CS# is LOW). This prevents
unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
LOAD MODE REGISTER
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle earlier
(n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
The Mode Register is loaded via inputsA0-11. See Mode Register
heading in the Register Definition section. The LOAD MODE
REGISTER command can only be issued when all banks are
idle, and a subsequent executable command cannot be issued
until tMRD is met.
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FIGURE 4 – CAS LATENCY
T1
T2
T3
T0
CLK
Command
I/O
READ
NOP
NOP
tLZ
tOH
DON'T CARE
UNDEFINED
DOUT
tAC
CAS Latency = 2
T1
T0
T2
T3
T4
CLK
Command
I/O
READ
NOP
NOP
NOP
tLZ
tOH
DOUT
tAC
CAS Latency = 3
coincident with the data. If a given DQM signal is registered LOW,
the corresponding data will be written to memory; if the DQM signal
is registered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs
A0-11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a different
row in the same bank.
PRECHARGE
The PRECHARGE command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row access a specified time (tRP
)
after the PRECHARGE command is issued. InputA10 determines
whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select
the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once
a bank has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being issued
to that bank.
READ
The READ command is used to initiate a burst read access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. IfAUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain open
for subsequent accesses. Read data appears on the I/Os subject
to the logic level on the DQM inputs two clocks earlier. If a given
DQM signal was registered HIGH, the corresponding I/Os will be
High-Z two clocks later; if the DQM signal was registered LOW,
the I/Os will provide valid data.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst, except
in the full-page burst mode, where AUTO PRECHARGE does
not apply. AUTO PRECHARGE is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE command.
WRITE
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. IfAUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the WRITE burst;
ifAUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is written
to the memory array subject to the DQM input logic level appearing
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge time (tRP) is completed.
This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time.
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TRUTH TABLE — COMMANDS AND DQM OPERATION1
NAME (FUNCTION)
CS#
H
L
RAS#
CAS#
WE#
X
DQM
X
ADDR
I/Os
COMMAND INHIBIT (NOP)
X
H
L
X
H
H
L
X
X
X
NO OPERATION (NOP)
H
H
H
L
X
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
L
X
Bank/Row
X
L
H
H
H
L
L/H 8
L/H 8
X
Bank/Col
X
L
L
Bank/Col
Valid
Active
X
L
H
H
L
L
X
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
X
Code
L
L
H
L
X
X
X
L
L
L
X
Op-Code
X
Write Enable/Output Enable (8)
–
–
–
–
L
–
–
Active
High-Z
Write Inhibit/Output High-Z (8)
–
–
–
–
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for
3. A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock
delay).
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered READ
or WRITE command prior to the BURST TERMINATE command
will be truncated.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two clocks) for
AUTO REFRESH
t
XSR, because time is required for the completion of any internal
AUTO REFRESH is used during normal operation of the SDRAM and is
analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional
DRAMs. This command is nonpersistent, so it must be issued each time
a refresh is required.
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands
must be issued as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each 128Mb SDRAM requires 4,096AUTO REFRESH
cycles every refresh period (tREF). Providing a distributed AUTO
REFRESH command will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate
(tRC), once every refresh period (tREF).
* Self refresh available in commercial and industrial temperatures only.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in the
self refresh mode, the SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like anAUTO REFRESH
command except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM become “Don’t
Care,” with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
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WEDPN8M72V-XB2X
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
(NOTE 2)
Parameter
Unit
V
Voltage on VDD, VDDQ Supply relative to VSS
Voltage on NC or I/O pins relative to VSS
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
NOTE:
-1 to 4.6
-1 to 4.6
Parameter
Input Capacitance: CLK
Symbol
Max
6
Unit
pF
V
CI1
CA
CI2
CIO
-55 to +125
-40 to +85
-55 to +125
°C
°C
°C
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
21
7
pF
pF
9
pF
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
BGA THERMAL RESISTANCE
Description
Symbol
Max
Unit
C/W
C/W
C/W
Notes
Junction to Ambient (No Airflow)
Junction to Ball
Theta JA 16.3
Theta JB 11.6
1
1
1
Junction to Case (Top)
NOTE:
Theta JC
7.2
Refer to PBGA Thermal Resistance Correlation application note at www.whiteedc.com in the
application notes section for modeling conditions.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(NOTES 1, 6)
VCC = +3.3V ±0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Min
3
Max
Units
V
Supply Voltage
VCC
VIH
VIL
II
3.6
Input High Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
2
VCC + 0.3
V
-0.3
-5
0.8
5
V
Input Leakage Current: Any input 0V-VIN-VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V VOUT VCC
Output Levels:
μA
μA
μA
II
-25
-5
25
5
IOZ
Output High Voltage (IOUT = -4mA)
VOH
VOL
2.4
–
–
V
V
Outpt Low Voltage (IOUT = 4mA)
0.4
ICC SPECIFICATIONS AND CONDITIONS
(NOTES 1,6,11,13)
VCC = +3.3V ±0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
ICC1
Max
750
250
Units
Operating Current: Active Mode; Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
mA
mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress
(3, 12, 19)
ICC3
Operating Current: Burst Mode; Continuous burst; Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
Self Refresh Current: CKE 0.2V Commercial and Industrial temperatures only (27)
ICC4
ICC7
750
10
mA
mA
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WEDPN8M72V-XB2X
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
Symbol
-100
Min
-125
-133
Unit
Max
7
Min
Max
6
Min
Max
5.5
6
CL = 3
CL = 2
tAC
tAC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
Access time from CLK (pos. edge)
7
6
Address hold time
Address setup time
CLK high-level width
CLK low-level width
tAH
1
2
1
2
0.8
1.5
2.5
2.5
7.5
10
tAS
tCH
3
3
tCL
3
3
CL = 3
CL = 2
tCK
10
13
1
8
Clock cycle time (22)
tCK
10
1
CKE hold time
tCKH
tCKS
tCMH
tCMS
tDH
0.8
1.5
0.8
1.5
0.8
1.5
CKE setup time
2
2
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1
1
2
2
1
1
Data-in setup time
tDS
2
2
CL = 3 (10)
CL = 2 (10)
tHZ
7
7
6
6
5.5
6
Data-out high-impedance time
tHZ
Data-out low-impedance time
tLZ
1
3
1
3
1
3
Data-out hold time (load)
tOH
tOHN
tRAS
tRC
Data-out hold time (no load) (26)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows) – Commercial, Industrial
Refresh period (4,096 rows) – Military
AUTO REFRESH period
1.8
1.8
50
68
20
1.8
50
68
20
50
70
20
120,000
120,000
120,000
tRCD
tREF
tREF
tRFC
tRP
64
16
64
16
64
16
70
20
15
0.3
70
20
16
0.3
70
20
16
0.3
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
tRRD
tT
1.2
1.2
1.2
1 CLK +
7.5ns
(23)
(24)
1 CLK + 7ns
1 CLK + 7ns
—
WRITE recovery time
tWR
15
80
15
80
15
80
ns
ns
Exit SELF REFRESH to ACTIVE command
tXSR
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WEDPN8M72V-XB2X
AC FUNCTIONAL CHARACTERISTICS
(NOTES 5,6,7,8,9,11)
Parameter/Condition
Symbol
tCCD
tCKED
tPED
-100
1
-125
1
-133
1
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
1
1
1
1
1
1
tDQD
tDQM
tDQZ
tDWD
tDAL
0
0
0
DQM to data mask during WRITEs
0
0
0
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
2
2
2
0
0
0
4
5
5
Data-in to PRECHARGE command (16)
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
tDPL
2
2
2
tBDL
1
1
1
tCDL
1
1
1
tRDL
2
2
2
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
tMRD
tROH
tROH
2
2
2
CL = 3
CL = 2
3
3
3
Data-out to high-impedance from PRECHARGE command (17)
NOTES:
2
—
—
1. All voltages referenced to VSS
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. DD is dependent on output loading and cycle rates. Specified values are obtained with minimum
cycle time and the outputs open.
.
13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle
I
rate.
4. Enables on-chip refresh and address counters.
16. Timing actually specified by tWR.
5. The minimum specifications are used only to indicate cycle time at which proper operation over
the full temperature range is ensured.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing
parameter.
6. An initial pause of 100ms is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. The two AUTO REFRESH command
wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the
maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between
21.
V
IH overshoot: VIH (MAX) = VCC + 2V for a pulse width ≤ 3ns, and the pulse width cannot be
VIH and VIL (or between VIL and VIH) in a monotonic manner.
greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns.
9. Outputs measured at 1.5V with equivalent load:
22. The clock frequency must remain constant (stable clock is defined as a signal cycling within
timing constraints specified for the clock pin) during access or precharge states (READ, WRITE,
including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first
clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
50Ω
Q
1.5V
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference
to VOH or VOL. The last valid data element will meet tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover
point.
12. Other input signals are allowed to transition no more than once every two clocks and are
otherwise at valid VIH or VIL levels.
Microsemi Corporation reserves the right to change products or specifications without notice.
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WEDPN8M72V-XB2X
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
Bottom View
25.1 (0.988) MAX
4 5 6 7 9 10 11 12 13 14 15 16
1 2
3
8
T
R
P
N
M
L
K
J
H
G
19.05
(0.750)
NOM
21.1 (0.831)
MAX
F
E
D
C
B
A
1.27
(0.050)
NOM
0.61
(0.024)
NOM
219 x Ø0.762 (0.030) NOM
19.05 (0.750) NOM
2.03 (0.080)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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WEDPN8M72V-XB2X
ORDERING INFORMATION
WED P N 8M 72 V - XXX B2 X
MICROSEMI CORPORATION
PLASTIC
SDRAM
CONFIGURATION, 8M x 72
3.3V Power Supply
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz
PACKAGE:
B2 = 219 Plastic Ball Grid Array (PBGA) - 21mm x 25mm
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
I = Industrial
C = Commercial 0°C to +70°C
Microsemi Corporation reserves the right to change products or specifications without notice.
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WEDPN8M72V-XB2X
Document Title
8M x 72 Synchronous DRAM, 21mm x 25mm PBGA
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
January 2004
Advanced
Rev 1
Changes (Pg. 1, 5, 9, 13)
February 2004
Advanced
1.1 Correct text allignment in Table 1
1.2 Add PBGA Thermal Resistence values to Table, page 9
Rev 2
Changes (Pg. 1, 5, 9, 13)
February 2004
Advanced
2.1 Correct text in note for figure 3.
2.2 Correct typo in II in DC Electrical table
Rev 3
Rev 4
Changes (Pg. 1-13)
July 2004
Final
Final
3.1 Change status to final
Changes (Pg. 1, 9, 10, 13)
January 2005
4.1 Update capacitance table values
4.2 Change max storage temperature to +125°C
4.3 Add 133 MHz speed grade
4.4 Add commercial and industrial only note to ICC7
Rev 5
Changes (Pg. 1-13)
February 2011
Final
5.1 Change document layout from White Electronic Designs to Microsemi
Microsemi Corporation reserves the right to change products or specifications without notice.
February 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 5
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