WEDPN8M72VR-66M [MICROSEMI]
Synchronous DRAM Module, 8MX72, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPN8M72VR-66M |
| 厂家： | 
Microsemi |
| 描述： | Synchronous DRAM Module, 8MX72, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPN8M72VR-XBX
HI-RELIABILITY PRODUCT
8Mx72 Registered Synchronous DRAM ADVANCED*
FEATURES
GENERAL DESCRIPTION
■ Registered for enhanced performance of bus speeds of 66 MHz
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134,217,728
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chip’s 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits. The MCP
also incorporates two 16-bit universal bus drivers for address and
input control signals.
and 100 MHz
■ Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
■ Single 3.3V ±0.3V power supply
■ Fully Synchronous; all signals registered on positive edge of
system clock cycle
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command, which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0, BA1 select the bank;
A0-11 select the row). The address bits registered coincident with
the READ or WRITE command are used to select the starting
column location for the burst access.
■ Internal pipelined operation; column address can be changed
every clock cycle
■ Internal banks for hiding row access/precharge
■ Programmable Burst length 1,2,4,8 or full page
■ 4096 refresh cycles
■ Commercial, Industrial and Military Temperature Ranges
■ Organized as 8M x 72
TheSDRAMprovidesforprogrammableREADorWRITEburstlengths
of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option.
An AUTO PRECHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst sequence.
The512MbSDRAMusesaninternalpipelinedarchitecturetoachieve
high-speed operation. This architecture is compatible with the 2nrule
of prefetch architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer substan-
tialadvancesinDRAMoperatingperformance, includingtheabilityto
synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks
in order to hide precharge time and the capability to randomly change
column addresses on each clock cycle during a burst access.
■ Weight: WEDPN8M72VR-XBX - 2.5 grams typical
BENEFITS
■ 48% SPACE SAVINGS
■ Reduced part count
■ Reduced I/O count
• 40% I/O Reduction
■ Laminate interposer for optimum TCE match
■ Glueless connection to memory controller/PCI bridge
■ Suitable for hi-reliability applications
■ Upgradeable to 16M x 72 density (contact factory for information)
*
This data sheet describes a product under development, non-qualified, and is
subject to change without notice.
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
December 2000 Rev. 1
WEDPN8M72VR-XBX
FIG. 1 PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DQ
DQ
DQ
DQ
0
DQ14 DQ15
DQ12 DQ13
DQ10 DQ11
V
SS
V
SS
A
A
A
9
A
10
A
11
A
A
A
8
1
3
V
CC
V
V
CC
DQ16 DQ17 DQ31
VSS
A
B
C
D
E
F
DQ
DQ
DQ
DQ
1
3
6
7
2
4
5
V
SS
VSS
0
2
A
7
A
6
VCC
CC
DQ18 DQ19 DQ29 DQ30
DQ20 DQ21 DQ27 DQ28
DQ22 DQ23 DQ26 DQ25
V
V
CC
CC
V
V
CC
CC
A
5
A
4
V
V
SS
SS
V
V
SS
SS
DQ8
DQ
9
DNU DNU DNU DNU
DQMB
0
V
V
V
V
V
V
V
V
CC
DQMB1
NC
NC
NC
NC
NC
BA
0
BA
1
NC
NC
NC
NC
NC
DQMB
2
V
V
V
SS
SS
SS
NC
DQMB
NC
DQ24
CAS
WE
CC
CLK
0
OE
3
CLK
1
CS0
RAS
CC
CC
CC
CC
CC
CC
CKE
CS1
LE
G
H
J
V
V
SS
V
SS
SS
V
CC
CC
V
V
SS
SS
V
CC
CC
VSS
Vss
VCC
V
V
CC
SS
V
V
V
V
SS
V
V
V
V
SS
SS
SS
SS
V
CC
CC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DNU*
NC
K
L
CLK
2
DQ56 DQMB
7
DQMB6
NC
NC
NC
DQMB9
NC
NC
NC
NC
DQMB5
DQMB4 DQ39
M
N
P
R
T
DQ57 DQ58 DQ55 DQ54
DQ60 DQ59 DQ53 DQ52
DQ62 DQ61 DQ51 DQ50
Vss DQ63 DQ49 DQ48
DQ73 DQ72 DQ71 DQ70
DQ75 DQ74 DQ69 DQ68
DQ77 DQ76 DQ67 DQ66
DQ79 DQ78 DQ65 DQ64
DQMB8
DQ41 DQ40 DQ37 DQ38
DQ43 DQ42 DQ36 DQ35
DQ45 DQ44 DQ34 DQ33
V
SS
VSS
VCC
VCC
V
V
CC
CC
V
V
CC
CC
V
V
SS
SS
V
V
SS
SS
DQ47 DQ46 DQ32
VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
DNU*= Pin K16 is reserved for optional CS2 pinout (CS of U4). Contact factory for information.
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2
WEDPN8M72VR-XBX
FIG. 2 FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CAS
B
B
B
WE RAS CAS
A
0-12
DQ
•
0
DQ
•
0
BA0-1
•
•
CLK0
CLK
•
•
U0
CKE
B
CKE
•
•
CS0B
DQMB0B
DQMB1B
CS
DQML
DQMH
•
•
•
•
DQ15
DQ15
WE RAS
CAS
DQ
74ALVC16334
A
0-12
A
0-12
0
DQ16
BA0-BA
1
BA0-1
•
•
•
•
•
•
•
•
CLK
0
CLK
U5
•
U1
CKE
B
CKE
•
CLK
2
CLK
OE
LE
CS1B
DQMB2B
DQMB3B
CS
DQML
DQMH
•
•
OE
LE
DQ15
DQ31
DQMB0-9
WE
CKE
DQMB0B-9B
WE
CKE
RAS
CAS
WE RAS
CAS
DQ
74ALVC16334
B
A
0-12
0
DQ32
B
BA0-1
•
•
•
•
•
•
•
RAS
CAS
B
B
•
CLK
1
CLK
U6
•
U2
CS0-1
CS0B-1B
CKE
B
CKE
CS
•
CS0B
DQMB4B
DQMB5B
•
•
CLK
OE
LE
DQML
DQMH
DQ15
DQ47
WE RAS
CAS
DQ
A
0-12
0
DQ48
BA0-1
•
•
•
•
•
•
•
•
CLK1
CLK
•
U3
CKE
B
CKE
•
CS1B
DQMB6B
DQMB7B
CS
DQML
DQMH
•
•
DQ15
DQ63
WE RAS
CAS
DQ
A
0-12
0
DQ64
BA0-1
•
•
•
•
•
•
•
•
CLK0
CLK
•
U4
CKE
B
CKE
•
CS0B
DQMB8B
DQMB9B
CS
DQML
DQMH
•
•
DQ15
DQ79
8mx72reg/blockdiag.eps
8
3
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WEDPN8M72VR-XBX
Mode register bits M0-M2 specify the burst length, M3 specifies
the type of burst (sequential or interleaved), M4-M6 specify the
CAS latency, M7 and M8 specify the operating mode, M9 speci-
fies the WRITE burst mode, and M10 and M11 are reserved for
future use.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank, A0-11 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecified operation.
Burst Length
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register definition, command descriptions and de-
vice operation.
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Once power is applied to VDD and
VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for
the clock pin), the SDRAM requires a 100µs delay prior to issuing
any command other than a COMMAND INHIBIT or a NOP. Starting
at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is
uniquely selected by A1-8 when the burst length is set to two; by
A2-8 when the burst length is set to four; and by A3-8 when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the boundary
is reached.
Once the 100µs delay has been satisfied with at least one COM-
MANDINHIBITorNOPcommandhavingbeenapplied,aPRECHARGE
command should be applied. All banks must be precharged,
thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be per-
formed. After the AUTO REFRESH cycles are complete, the SDRAM
is ready for Mode Register programming. Because the Mode
Register will power up in an unknown state, it should be loaded
prior to applying any operational command.
Burst Type
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of opera-
tion of the SDRAM. This definition includes the selec-tion of a
burst length, a burst type, a CAS latency, an operating mode and
a write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
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4
WEDPN8M72VR-XBX
TABLE 1 - BURST DEFINITION
FIG. 3 MODE REGISTER DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
A0
2
4
0
1
0-1
1-0
0-1
1-0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
Address Bus
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency BT
Burst Length
*Should program
A2 A1 A0
M11, M10 = 0, 0
to ensure compatibility
with future devices.
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
M2 M1M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
8
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
n = A0-9/8/7 Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
(location 0-y)
Not Supported
…Cn - 1,
Cn…
Burst Type
M3
0
NOTES:
Sequential
Interleaved
1. For full-page accesses: y = 512.
1
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects
the starting column within the block.
CAS Latency
M6 M5 M4
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select
the starting column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2
select the starting column within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting
column.
6. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
7. For a burst length of one, A0-8 select the unique column to be accessed,
and Mode Register bit M3 is ignored.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
-
-
All other states reserved
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
5
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WEDPN8M72VR-XBX
FIG. 4 CAS LATENCY
T0
T1
T2
T3
CLK
COMMAND
I/O
READ
NOP
tLZ
NOP
tOH
D
OUT
tAC
CAS Latency = 2
T1
T0
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
tLZ
NOP
tOH
DOUT
I/O
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
unknown operation or incompatibility with future versions may
result.
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to
both READ and WRITE bursts; when M9 = 1, the programmed burst
length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle earlier
(n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after T1 and
the data will be valid by T2. Table 2 below indicates the operating
frequencies at which each CAS latency setting can be used.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
LATENCY = 2
CAS
LATENCY = 3
SPEED
-100
-66
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
≤ 66
≤ 50
≤ 100
≤ 66
Operating Mode
COMMANDS
The normal operating mode is selected by setting M7and M8 to
zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length
applies to both READ and WRITE bursts.
The Truth Table provides a quick reference of available com-
mands. This is followed by a written description of each com-
mand. Three additional Truth Tables appear following the Opera-
tion section; these tables provide current state/next state infor-
mation.
Test modes and reserved states should not be used because
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6
WEDPN8M72VR-XBX
TRUTH TABLE - COMMANDS AND DQM OPERATION (Note 1)
NAME (FUNCTION)
CS
H
L
RAS
X
CAS
X
WE
X
DQM
ADDR
I/Os
COMMAND INHIBIT (NOP)
X
X
X
X
NO OPERATION (NOP)
H
L
H
H
L
H
H
H
L
X
X
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
L
X
Bank/Row
L
H
H
H
L
L/H 8
L/H 8
X
Bank/Col
X
L
L
Bank/Col
Valid
Active
X
L
H
H
L
L
X
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
X
Code
L
L
H
L
X
X
X
L
L
L
X
Op-Code
X
Write Enable/Output Enable (8)
–
–
–
–
L
–
–
Active
High-Z
Write Inhibit/Output High-Z (8)
–
–
–
–
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-11 define the op-code written to the Mode Register.
3. A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
LOAD MODE REGISTER
COMMAND INHIBIT
The Mode Register is loaded via inputs A0-11. See Mode Register
heading in the Register Definition section. The LOAD MODE REGIS-
TER command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK
signal is enabled. The SDRAM is effectively deselected. Opera-
tions already in progress are not affected.
FUNCTION TABLE
ACTIVE
INPUTS
OUTPUT
TheACTIVEcommandisusedtoopen(oractivate)arowinaparticular
bank for a subsequent access. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-11 selects the
row.Thisrowremainsactive(oropen)foraccessesuntilaPRECHARGE
command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
OE LE CLK
A
Y
H
L
L
L
L
L
X
L
X
X
L
Z
L
X
L
X
H
L
H
H
H
H
I
L
I
H
X
H
READ
L or H
Y0†
The READ command is used to initiate a burst read access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row
being accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Read data appears on the I/Os subject to the
logiclevelontheDQMinputstwoclocksearlier. IfagivenDQMsignal
was registered HIGH, the corresponding I/Os will be High-Z two
clocks later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
†Output level before the indicated steady-state
input conditions were established
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to
an SDRAM which is selected (CS is LOW). This prevents unwanted
commands from being registered during idle or wait states. Op-
erations already in progress are not affected.
7
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WEDPN8M72VR-XBX
WRITE
BURST TERMINATE
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-8 selects the starting column
location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent
accesses. Input data appearing on the I/Os is written to the memory
array subject to the DQM input logic level appearing coincident with
the data. If a given DQM signal is registered LOW, the corresponding
data will be written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
The BURST TERMINATE command is used to truncate either fixed-
length or full-page bursts. The most recently registered READ or
WRITE command prior to the BURST TERMINATE command will be
truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in conven-
tional DRAMs. This command is nonpersistent, so it must be
issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each 128Mb SDRAM requires 4,096 AUTO REFRESH
cycles every refresh period (tREF). Providing a distributed AUTO RE-
FRESH command will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 4,096 AUTO REFRESH com-
mands can be issued in a burst at the minimum cycle rate (tRC), once
every refresh period (tREF).
PRECHARGE
The PRECHARGE command is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be
available for a subsequent row access a specified time (tRP) after
the PRECHARGE command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has
been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down. When in
the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which must
remain LOW.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same indi-
vidual-bank PRECHARGE function described above, without re-
quiring an explicit command. This is accomplished by using A10 to
enable AUTO PRECHARGE in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in the full-
page burst mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGEisnonpersistentinthatitiseitherenabledordisabledfor
each individual READ or WRITE command.
Once self refresh mode is engaged, the SDRAM provides its own
internal clocking, causing it to perform its own AUTO REFRESH
cycles. The SDRAM must remain in self refresh mode for a
minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal refresh
in progress.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge time (tRP) is
completed. This is determined as if an explicit PRECHARGE com-
mand was issued at the earliest possible time.
Upon exiting the self refresh mode, AUTO REFRESH commands
must be issued as both SELF REFRESH and AUTO REFRESH utilize
the row refresh counter.
* Self refresh available in commercial and industrial tempera-
tures only.
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8
WEDPN8M72VR-XBX
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (Note 2)
Parameter
Unit
V
V
°C
°C
°C
W
Parameter
Symbol
Max
Unit
Voltage on VDD, VDDQ Supply relative to Vss
Voltage on NC or I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
-1 to 4.6
-1 to 4.6
-55 to +125
-40 to +85
-55 to +150
5
Input Capacitance: CLK
CI1
CA
CI2
CIO
10
pF
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
10
10
12
pF
pF
pF
Power Dissipation
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions greater than those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes 1, 6)
(VCC = +3.3V ±0.3V; TA = -55°C to +125°C)
Parameter/Condition
Symbol
Units
Min
Max
Supply Voltage
VCC
VIH
VIL
II
3
3.6
V
V
Input High Voltage: Logic 1; All inputs (21)
2
VCC + 0.3
Input Low Voltage: Logic 0; All inputs (21)
-0.3
-5
0.8
5
V
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
µA
µA
µA
II
-25
-5
25
5
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
IOZ
VOH
VOL
2.4
–
–
V
V
0.4
ICC SPECIFICATIONS AND CONDITIONS (Notes 1,6,11,13)
(VCC = +3.3V ±0.3V; TA = -55°C to +125°C)
Parameter/Condition
Symbol
Max
Units
Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
ICC1
750
mA
Standby Current: Active Mode; CKE = HIGH; CS = HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19)
ICC3
ICC4
250
750
mA
mA
Operating Current: Burst Mode; Continuous burst;
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
Self Refresh Current: CKE ≤ 0.2V (Commercial Temperature: 0°C to + 70°C) (27)
Self Refresh Current: CKE ≤ 0.2V (Industrial Temperature: (-40°C to + 85°C) (27)
ICC7
10
10
mA
mA
ICC7
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPN8M72VR-XBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 5, 6, 8, 9, 11)
Parameter
Symbol
-100
-66
Unit
Min
Max
Min
Max
CL = 3
CL = 2
tAC
tAC
6
6
7.5
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
—
ns
ns
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
tAH
tAS
1
2
1
2
tCH
tCL
3
3
3
3
CL = 3
CL = 2
tCK
8
10
15
1
Clock cycle time (22)
tCK
12
1
CKE hold time
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
CKE setup time
2
2
CS, RAS, CAS, WE, DQM hold time
CS, RAS, CAS, WE, DQM setup time
Data-in hold time
1
1
2
2
1
1
Data-in setup time
2
2
CL = 3 (10)
CL = 2 (10)
6
7
8
Data-out high-impedance time
tHZ
10
Data-out low-impedance time
Data-out hold time (load)
tLZ
1
3
2
3
tOH
Data-out hold time (no load) (26)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
tOH
1.8
50
70
20
1.8
60
70
30
N
tRAS
tRC
120,000
120,000
tRCD
tREF
tREF
tRFC
tRP
Refresh period (4,096 rows) – Commercial, Industrial
Refresh period (4,096 rows) – Military
AUTO REFRESH period
64
16
64
16
70
90
30
20
1
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
20
tRRD
tT
20
0.3
1.2
1.2
WRITE recovery time
(23)
(24)
1 CLK + 7ns
1 CLK + 7ns
tWR
15
80
15
90
Exit SELF REFRESH to ACTIVE command
tXSR
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10
WEDPN8M72VR-XBX
AC FUNCTIONAL CHARACTERISTICS (Notes 5,6,7,8,9,11)
Parameter/Condition
Symbol
tCCD
-100
1
-66
1
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
tCKED
tPED
1
1
1
1
tDQD
tDQM
tDQZ
0
0
DQM to data mask during WRITEs
0
0
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
2
2
tDWD
tDAL
0
0
4
4
Data-in to PRECHARGE command (16)
tDPL
2
2
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
tBDL
1
1
tCDL
1
1
tRDL
2
2
tMRD
tROH
tROH
2
2
CL = 3
CL = 2
3
3
Data-out to high-impedance from PRECHARGE command (17)
2
2
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA =
12. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL levels.
25°C.
13. ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference
only at minimum cycle rate.
3. IDD is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range is ensured.
6. An initial pause of 100ms is required after power-up, followed by two
AUTO REFRESH commands, before proper device operation is ensured.
(VCC must be powered up simultaneously.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not depen-
dent on any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due
to the fact that the maximum cycle rate is slower as the CAS latency is
reduced.
7. AC characteristics assume tT = 1ns.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL undershoot:
VIL (MIN) = -2V for a pulse width ≤ 3ns.
22. The clock frequency must remain constant (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
during access or precharge states (READ, WRITE, including tWR, and
PRECHARGE commands). CKE may be used to reduce the data rate.
8. In addition to meeting the transition rate specification, the clock and CKE
must transit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
23. Auto precharge mode only. The precharge timing budget (tRP) begins
7.5ns/7ns after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
10. tHZ defines the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data element
will meet tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point.
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPN8M72VR-XBX
PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
32.32 (1.272) MAX
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
T
R
P
N
M
L
1.27/2
K
J
25.25 (0.994)
MAX
19.05 (0.750)
NOM
H
G
F
E
D
C
B
A
1.27 (0.050)
BSC
1.27/2
0.835
0.60 (0.024)
± 0.10 (0.004)
219 x
2.34 (0.092)
MAX
19.05 (0.750) NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P N 8M 72 V R - XXX B X
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
I
= Industrial
C = Commercial
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA)
FREQUENCY (MHz)
100 = 100MHz
66 = 66MHz
IMPROVEMENT MARK:
R = Registered
3.3V Power Supply
CONFIGURATION, 8M x 72
SDRAM
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
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12
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