WV3EG2128M72EFSU403AD4-MG [MICROSEMI]
DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, SODIMM-200;
| 型号： | WV3EG2128M72EFSU403AD4-MG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, SODIMM-200 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总11页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED*
2GB – 2x128Mx72 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
FEATURES
DESCRIPTION
Fast data transfer rate: PC-2700 & PC-3200*
The WV3EG2128M72EFSU is a 2x128Mx72 Double
Data Rate SDRAM memory module based on 1Gb DDR
SDRAM components. The module consists of eighteen
128Mx8 DDR SDRAMs die stacked in FBGA packages
mounted on a 200 pin FR4 substrate.
Data rate of 333 Mb/s & 400 Mb/s*
V
CC = VCCQ = 2.5V +/-0.2V
CCSPD = 2.3V to 3.6V
V
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Auto and self refresh, 7.8 μs refresh interval
(8K/64ms fresh)
Serial presence detect (SPD) with EEPROM
Dual Rank
Gold edge contacts
200 pin, SO-DIMM package
•
PCB height option:
30.48 mm (1.20”)
OPERATING FREQUENCIES
DDR400@CL=3*
200MHz
DDR333@CL=2.5
166MHz
Clock Speed
CL-tRCD-tRP
3-3-3
2.5-3-3
* Consult factory for availability.
March 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
Symbol
A0-A12
BA0, BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0, CK0#
CKE0-CKE1
CS0#-CS3#
RAS#
Description
1
VREF
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A9
A8
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
VCC
Address input
2
Bank Address
3
4
5
6
7
8
9
DQ19
DQ23
DQ24
DQ28
VCC
VSS
VSS
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
A10/AP
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
Input/Output: Data I/Os, Data bus
Input/Output: Check Bits
Data Strobe
VSS
DQ0
DQ4
DQ1
DQ5
VCC
VCC
VCC
NC
VSS
NC
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VCC
Clock Input
VCC
Clock Enable Input
Chip Select Input
DQ25
DQ29
DQS3
DM3
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
Row Address Strobe
Column Address Strobe
Write Enable
DQS0
DM0
DQ2
DQ6
VSS
CAS#
WE#
DM0-DM8
VCC
Data Write Mask
VSS
Supply: Power Supply: +2.5V ±0.2V
Power Supply for DQS
Supply: Ground
DQ26
DQ30
DQ27
DQ31
VCC
VSS
VCCQ
DQ3
DQ7
DQ8
DQ12
VCC
VSS
VCC
VREF
Supply: SSTL_2 reference voltage
DQS6
DM6
DQ50
DQ54
VSS
VCCSPD
Supply: Serial EEPROM Positive
Power Supply
VCC
CB0
CB4
CB1
CB5
VSS
SDA
Input/Output: Serial Presence-Detect
Data
VCC
DQ9
DQ13
DQS1
DM1
VSS
SCL
Serial Clock
CS2#
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VCC
VSS
SA0-SA2
NC
Presence Detect Address Input
No Connect
DQ51
DQ55
DQ56
DQ60
VCC
VSS
DQS8
DM8
CB2
CB6
VCC
VSS
DQ10
DQ14
DQ11
DQ15
VCC
VCC
CK0
VCC
VCC
DQ57
DQ61
DQS7
DM7
VSS
VCC
VCC
CB3
CB7
CS3#
NC
VSS
VSS
NC
VSS
NC
VCC
VCC
VCC
CKE1
CKE0
NC
NC
A12
A11
DQS4
DM4
DQ34
DQ38
VSS
VSS
CK0#
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VCC
SDA
SA0
SCL
SA1
VCCSPD
SA2
NC
VSS
DQ35
DQ39
DQ40
DQ44
VCC
VSS
DQ16
DQ20
DQ17
DQ21
VCC
VCC
DQ41
DQ45
DQS5
DM5
VSS
VCC
DQS2
DM2
DQ18
DQ22
VSS
NC
March 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS3#
CS2#
CS1#
CS0#
DQS0
DM0
DQS S0# S2#
DM
DQS S1# S3#
DM
DQS4
DM4
DQS S0# S2#
DM
DQS S1# S3#
DM
DQ0
I/O 0
I/O 0
DQ32
I/O 0
I/O 0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 1
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DQS1
DM1
DQS S0# S2#
DM
DQS S1# S3#
DM
DQS5
DQS S0# S2#
DM
DQS S1# S3#
DM
DM5
DQ8
I/O 0
I/O 0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 1
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DQS2
DQS S0# S2#
DM
DQS S1# S3#
DM
DQS6
DM6
DQS S0# S2#
DM
DQS S1# S3#
DM
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ52
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DQS3
DM3
DQS S0# S2#
DM
DQS S1# S3#
DM
DQS7
DM7
DQS S0# S2#
DM
DQS S1# S3#
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 1
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS S0# S2#
DM
DQS S1# S3#
DM
SERIAL PD
A0 A1 A2
SCL
WP
I/O 0
I/O 0
SDA
I/O 1
I/O 1
I/O 2
I/O 2
I/O 3
I/O 3
SA1 SA2
I/O 4
I/O 4
I/O 5
I/O 5
HARDWARE ON MEMORY MODULE
SERIAL PD
I/O 6
I/O 6
SCL
WP
I/O 7
I/O 7
SDA
A0 A1 A2
vcc SA1 SA2
HARDWARE ON MEMORY MODULE
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CKE0
CKE1
DDR SDRAMs
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAM x 4
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
120
CK0
CK0#
PLL
Note: 1. All resistor values are 22 Ω unless otherwise specified.
March 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VCC/VCCQ
VREF
TSTG
TA
Value
-0.5 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-55 to +150
0 to 70
Units
V
V
Voltage on any pin relative to VSS
Voltage on VCC and VCCQ supply relative to VSS
Voltage on VREF supply relative to VSS
Storage Temperature
Operating Temperature
Power Dissipation
V
°C
°C
W
PD
36
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
AC OPERATING CONDITIONS
Parameter
Input high (logic 1) voltage
Input Low (logic 0) voltage
Input differential voltage, CK and CK# inputs
Input crossing point voltage, CK and CK# input
Symbol
VIN(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF+0.31
Max
Unit
V
V
V
V
VREF-0.31
VCCQ+0.6
0.5*VCCQ+0.2
0.7
0.5*VCCQ-0.2
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
Min
95.8
104.8
49.9
6
Max
119.2
115.6
61.6
7.5
Unit
pF
pF
pF
pF
pF
pF
Input capacitance (A0 ~ A12, BA0 ~ BA1, RAS#, CAS#, WE#)
Input capacitance (CKE0, CKE1)
Input capacitance (CS0# ~ CS3#)
Input capacitance (CK, CK#)
Input capacitance (DM0 ~ DM8), (DQS0 ~ DQS8)
Input capacitance (DQ0 ~ DQ63), (CB0 ~ CB7)
CIN5
COUNT1
22.8
22.8
24
24
March 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
DC CHARACTERISTICS
0°C TA 70°C
Parameter
Symbol
VCC
VCCQ
VREF
Min
2.3
2.3
0.49*VCCQ
VREF-0.04
VREF+0.15
-0.3
-0.3
0.3
0.3
-72
Max
2.7
2.7
Unit
V
V
V
V
V
V
V
V
Note
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Reference voltage
I/O Termination voltage
Input logic high voltage
0.51*VCCQ
VREF+0.04
VCCQ+0.30
VREF-0.15
VCCQ+0.30
VCCQ+0.60
VCCQ+0.60
72
1
2
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
Input logic low voltage
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
3
V
μA
Addr, CAS#,
RAS#, WE#
CS#
CKE
CK, CK#
DM
-18
-36
-10
-8
-20
-16.8
16.8
-9
18
36
10
8
20
—
—
—
—
μA
μA
μA
μA
μA
mA
mA
mA
mA
Input leakage current
II
Output leakage current
IOZ
IOH
IOL
IOH
IOL
Output high current (normal strength); VOUT = V +0.84V
Output high current (normal strength); VOUT = VTT -0.84V
Output high current (half strength); VOUT = VTT +0.45V
Output high current (half strength); VOUT = VTT -0.45V
9
NOTES:
1.
V
REF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed ±2% of the DC
value.
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.
2.
V
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
March 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
ICC SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Parameter
Symbol
Conditions
DDR400 @ DDR333 @
Unit
CL = 3
CL = 2.5
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN)
;
Operating current
Operating current
ICC0*
DQ, DM and DQS inputs change once per clock cycle; Address and control
inputs change once every two clock cycles
1,585
mA
TBD
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN)
IOUT = 0mA; Address and control inputs change once per clock cycle
;
ICC1*
1,855
460
mA
mA
TBD
TBD
Percharge power-
down standby current
ICC2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address
and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS and DM
Idle standby current
ICC2F**
ICC3P**
ICC3N**
ICC4R*
ICC4W*
1,900
1,540
2,080
1,900
1,990
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
Active power-down
standby current
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX)
;
Active standby
current
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address
and other control inputs changing once per clock cycle
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA
Operating current
Operating current
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and
DQS inputs change twice per clock cycle
Auto refresh current
Self refresh current
ICC5**
ICC6**
tRC = tRFC(MIN)
CKE < 0.2V
10,720
460
mA
mA
TBD
TBD
Four device bank interleaving Reads Burst = 4 with auto precharge;
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during
Active READ, or WRITE commands
Operating current
ICC7*
4,060
mA
TBD
NOTE:
I
CC specification is based on Micron components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in ICC2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
March 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS AND SPECIFICATIONS
403
335
Parameter
Symbol
Unit
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
Min
60
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
Refresh row cycle time
Row active time
72
42
120K
RAS# to CAS# delay
Row precharge time
Row active to Row active delay
Write recovery time
18
18
tRRD
tWR
12
15
Last data into Read command
tWTR
1
CL = 3
—
—
Clock cycle time
tCK
CL = 2.5
6
12
Clock high level width
tCH
tCL
tDQSCK
tAC
0.45
0.55
-0.6
-0.7
—
0.55
0.55
+0.6
+0.7
0.45
1.1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Clock low level width
DQS-out access time from CK/CK#
Output data access time from CK/CK#
Data strobe edge to output data edge
Read Preamble
tDQSQ
tRPRE
tRPST
tDQSS
0.9
0.4
0.75
Read Postamble
0.6
CK to valid DQS-in
1.25
tCK
Continued on next page
March 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS AND SPECIFICATIONS (continued)
403
335
Parameter
Symbol
Unit
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
0
Max
DQS-in setup time
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
DQS-in hold time
0.25
0.2
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
0.2
0.35
0.35
0.75
0.75
0.7
DQS-in low level width
Address and Control Input setup time (fast)
Address and Control Input hold time (fast)
Address and Control Input setup time (slow)
Address and Control Input hold time (slow)
Data-out high impedance time from CK/CK#
Data-out low impedance time from CK/CK#
Mode register set cycle time
tIH
tIS
tIH
0.7
tHZ
-0.7
-0.7
10
+0.7
+0.7
tLZ
tMRD
tDS
DQ & DM setup time to DQS
0.4
DQ & DM hold time to DQS
tDH
0.4
Control & Address input pulse width
DQ & DM input pulse width
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
2.2
1.75
75
Exit self refresh o non-Read command
Exit self refresh to read command
Refresh interval time
200
7.8
—
Output DQS valid window
tHP - tQHS
tCL(min) or
tCH(min)
Clock half period
tHP
—
ns
Data hold skew factor
tQHS
tWPST
tRAP
0.55
0.6
ns
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS write postamble time
0.4
18
Active to Read with Auto precharge command
(tWR/tCK) +
(tRP/tCK
Auto precharge write recovery + Precharge time
tRAL
tCK
)
March 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height**
WV3EG2128M72EFSU403AD4-xx*
200MHz/400Mbps
166MHz/333Mbps
3
30.48 (1.20") MAX
30.48 (1.20") MAX
WV3EG2128M72EFSU335AD4-xx
*Consult factory for availability.
NOTES:
2.5
3
3
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option.
200-PIN DDR2 SO-DIMM DIMENSIONS
FRONT VIEW
4.06 (0.160)
MAX
67.75 (2.667)
MAX
4.10 (0.161) (2X)
MAX
30.48 (1.20)
MAX
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
MAX
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
W 3 E G 2128M 72 E F S U xxx AD4 x x
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH
BUS WIDTH
x8
FBGA
2.5V
UNBUFFERED
DATA RATE Mb/s
PACKAGE 200 PIN
PCB Height: 30.48mm (1.20”)
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
March 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WV3EG2128M72EFSU-AD4
White Electronic Designs
ADVANCED
Document Title
2GB – 2x128Mx72 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
Revision History
Rev #
History
Release Date Status
Rev 0
Created
3-06
Advanced
March 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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