WV3HG32M72EEU665D4MG [MICROSEMI]
DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200;
| 型号： | WV3HG32M72EEU665D4MG |
| 厂家： | 
Microsemi |
| 描述： | DDR DRAM Module, 32MX72, 0.45ns, CMOS, ROHS COMPLIANT, SODIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总12页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED*
256MB – 32Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
FEATURES
DESCRIPTION
ꢀ
200-pin, Small-Outline DIMM (SO-DIMM)
The WV3HG32M72EEU is a 32Mx72 Double Data Rate 2
SDRAM memory module based on 256Mb DDR2 SDRAM
components. The module consists of nine 32Mx8, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
ꢀ
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
ꢀ
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
CC = 1.8V 0.1V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
CCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
RoHS Compliant
Single Rank
JEDEC Package
• 200 Pin (SO-DIMM): 31.75mm (1.25") TYP.
OPERATING FREQUENCIES
PC2-6400*
400MHz
6-6-6
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
January 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
SYMBOL
A0-A12
ODT0
CK, CK#
CB0-CB7
CKE0
DESCRIPTION
Address input
On-Die Termination
Differential Clock Inputs
Check Bits
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VCC
A6
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
VSS
VSS
2
3
DQ0
DQ4
VSS
DQ5
DQ1
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
A5
DQS5#
DM5
DQS5
VSS
4
A4
5
A3
Clock Enable input
Chip select
6
VCC
CS0#
7
A2
VSS
8
A1
DQ46
DQ42
DQ47
DQ43
VSS
RAS#, CAS#, WE# Command Inputs
9
DQS0#
DM0
DQS0
VSS
DQ25
DM3
VSS
VCC
BA0, BA1
DM0-DM8
DQ0-DQ63
DQS0-DQS8
DQS0#-DQS8#
Bank Address Inputs
Input Data Mask
Data Input/Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A0
A10/AP
BA1
BA0
VCC
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
Data Strobe
DQ6
DQ2
DQ7
DQ3
VSS
DQ52
DQ48
DQ53
DQ49
VSS
SCL
Serial Clock for Presence Detect
Presence Detect Address Inputs
Address input/Auto precharge
Serial Presence Detect Data
Power Supply: +1.8V 0.1V
SSTL_18 reference voltage
Ground
Serial EEPROM Positive Power
Supply
No Connect
RAS#
WE#
VCC
CS0#
CAS#
ODT0
SA0-SA1
A10/AP
SDA
VCC
VREF
VSS
DQ26
CB4
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
DM6
DQS6#
VSS
DQ27
CB5
121 NC/CS1# 171
VSS
VCCSPD
122
123
124
NC/A13
VCC
VCC
172
173
174
VSS
DQS6
DQ54
VSS
DQ55
DQ50
VSS
DQ51
DQ60
VSS
DQ61
DQ56
VSS
DQ57
DM7
VSS
DQ62
DQS7#
VSS
VSS
NC
VSS
CB0
125 NC/ODT1 175
DM1
DQS1#
VSS
DM8
CB1
126
CK
176
127 NC/CS3# 177
VSS
128
129
130
131
132
133
134
135
136
137
138
CK#
DQ32
VSS
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Note: 1. NC/CS2#, NC/CS3# (pins 91, 127) are used for 4 rank DIMMs.
2. RESET (pin 42) RESET is connected to both OE of the PLL
and Reset of the register for 72-bit Registered SO DIMM
ONLY.
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
DQ20
VSS
DQ21
DQ16
VSS
VSS
CB6
DQS8#
CB7
VSS
DQ36
DQ33
DQ37
DQS4#
VSS
DQS8
VSS
VSS
CB2
CKE0
CB3
DQS4
DM4
VSS
89 NC/CKE1 139
90 VSS 140
91 NC/CS2# 141
VSS
DQ17
RESET#
VSS
DM2
DQS2#
VSS
DQ34
DQ38
DQ35
DQ39
VSS
DQS7
DQ63
DQ58
SDA
92
93
94
95
96
97
98
99
100
NC/BA2 142
VCC
NC/A14
A12
A11
A9
143
144
145
146
147
148
149
150
VSS
VSS
SCL
DQ59
SA1
VCCSPD
SA0
DQS2
DQ22
VSS
DM40
DQ44
DQ41
DQ45
VCC
A7
A8
DQ23
January 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1#
DQS4#
DQS1
DM1
DQS4
DM4
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
DQ
RDQS
DQ
DQ8
DQ40
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2#
DQS5#
DQS2
DM2
DQS5
DM5
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3#
DQS7#
DQS3
DM3
DQS7
DM7
DM/
DM/
CS#
DQS
DQS#
CS#
DQS
DQS#
RDQS
RDQS
DQ24
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS8#
VCCSPD
VCC
VREF
VSS
Serial PD
DQS8
DM8
Serial PD
WP A0 A1 A2
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SCL
SDA
DM/
CS#
DQS
DQS#
RDQS
DQ
CB0
SA0 SA1
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
CK#
PCK0, PCK4-PCK6, PCK9 -> CK: DDR2 SDRAMs
P
L
L
PCK0#, PCK4#-PCK6#, PCK9# -> CK#: DDR2 SDRAMs
CS#: SDRAMs
CS0#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
BA0-BA1: DDR2 SDRAMs
A0-A12: DDR2 SDRAMs
RAS#: DDR2 SDRAMs
CAS#: DDR2 SDRAMs
WE#: DDR2 SDRAMs
CKE: DDR2 SDRAMs
ODT: DDR2 SDRAMs
CKE0
ODT0
NOTE: 1. All resistor values are 22 ohm unless otherwise specified.
January 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM DC CHARACTERISTICS
Symbol Parameter
Min
-1.0
-0.5
-55
0
Max
2.3
2.3
100
85
Units
V
V
°C
°C
°C
VCC
Voltage on VCC pin relative to VSS
VIN, VOUT Voltage on any pin relative to VSS
TSTG
TCASE
TOPR
Storage Temperature
DDR2 SDRAM Device Operating Temperature*
Operating Temperature (Ambient)
-45
45
Command/Address,
RAS#, CAS#, WE# CS#,
CKE
CK, CK#
DM
-45
45
Input Leakage Current; Any input 0V ≤ VIN ≤ VCC
;
II
VREF input 0V ≤ VIN ≤0.95V; (All other pins not under
test = 0V)
µA
-10
-5
10
5
Output Leakage Current; 0V ≤ VOUT ≤ VCC; DQs and
ODT are disabled
VREF Leakage Current; VREF = Valid VREF level
IOZ
DQ, DQS, DQS#
-5
5
µA
µA
IVREF
-18
18
* TCASE specifies as the temperature at the top center of the memory devices.
RECOMMENDED DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Symbol
VCC
VREF
VTT
Min
1.7
0.49 x VCC
VREF - 0.04
Typ
1.8
0.51 x VCC
VREF
Max
1.9
0.51 x VCC
VREF + 0.04
Units
V
V
Notes
1
1
2
mV
NOTE:
1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.
1
2.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF
.
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 1MHz, V = 1.8V
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5 (E6)
CIN5 (D5)
COUT (E6)
COUT (D5)
Min
13
13
13
6
6.5
6.5
6.5
6.5
Max
22
22
22
7
7.5
8
7.5
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12, BA0~BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0), (ODT0)
Input Capacitance (CS0#)
Input Capacitance (CK, CK#)
Input Capacitance (DQS0~DQS8)
Input Capacitance (DQ0~DQ63), (CB0~CB7)
January 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Temperature
TOPER
0ºC to 85ºC
ºC
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIL(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667, DDR2-800 (TBD)
VREF+ 0.250
VREF+ 0.200
V
V
V
V
VREF - 0.250
VREF + 0.200
January 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Active
Rank
Parameter
State Condition
806
665
553
403
Units
Operating one device
bank active-precharge
current;
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
ICC0
TBD
1,245
1,200
1,155
mA
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC),
tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
Operating one device
bank active-read-
precharge current;
ICC1
TBD
1,335
1,290
1,200
mA
pattern is same as ICC4W
.
Precharge power-down
current;
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
ICC2P
TBD
TBD
372
570
375
525
372
525
mA
mA
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2Q control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet
standby current;
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2N control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Precharge standby
current;
TBD
615
570
570
mA
Fast PDN Exit
TBD
TBD
615
435
570
435
570
435
mA
mA
All device banks open; tCK = tCK (ICC); CKE is LOW;
ICC3P Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
MR[12] = 0
Active power-down
current;
Slow PDN Exit
MR[12] = 1
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC);
ICC3N CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Active standby current;
TBD
TBD
975
930
885
mA
mA
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC),
Operating burst write
current;
AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is
ICC4W
2,190
1,875
1,515
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
Operating burst read
current;
= CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC);
ICC4R
TBD
1,965
1,740
1,470
mA
CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE
Burst refresh current;
Self refresh current;
ICC5
is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
TBD
1,830
45
1,785
45
1,740
45
mA
mA
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
ICC6
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC),
AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING; See ICC7 Conditions for detail.
Operating device bank
interleave read current;
ICC7
TBD
2,685
2,595
2,595
mA
Note:
• ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
January 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
AC OPERATING CONDITIONS
≤TCASE ≤ +85°C; VCC = +1.8V 0.1V
AC Characteristics
806
665
534
403
Symbol
Units
Parameter
Min
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
Min
Max
Min
Max
Min
Max
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
ps
ps
ps
ps
tCK
tCK
tCK (5)
3,000 8,000
3, 750 8,000 3,750 8,000 5,000 8,000
5,000 8,000 5,000 8,000 5,000 8,000
-
-
-
-
Clock cycle time
tCK (4)
tCK (3)
CK high-level width
CK low-level width
tCH
tCL
0.45
0.45
MIN
0.55
0.55
0.45
0.45
MIN
0.55
0.55
0.45
0.45
MIN
0.55
0.55
Half clock period
tHP
ps
TBD
TBD
t
( CH,tCL)
t
( CH,tCL)
t
( CH,tCL)
Clock jitter
tJIT
tAC
tHZ
tLZ
tDS
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQ output access time from CK/CK#
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
-450
-450
tAC (MAX)
-500
+500
tAC (MAX)
-600
+600
tAC (MAX) ps
tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) ps
100
225
0.35
100
275
0.35
ps
ps
tCK
ps
ps
100
225
0.35
tDH
tDIPW
tQHS
tQH
340
400
450
DQ–DQS hold, DQS to first DQ to go nonvalid, per access
tHP-tQHS
tHP-tQHS
tHP-tQHS
tQH
- tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
Data valid output window (DVW)
tDVW
ns
TBD
TBD
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising – setup time
DQS falling edge from CK rising – hold time
DQS–DQ skew, DQS to last DQ valid, per group, per
access
tDQSH
tDQSL
tDQSCK
tDSS
0.35
0.35
-400
0.2
0.35
0.35
-450
0.2
0.35
0.35
-500
0.2
tCK
tCK
ps
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
+400
240
+450
300
+500
350
tDSH
0.2
0.2
0.2
tDQSQ
ps
TBD
TBD
DQS read preamble
tRPRE
tRPST
tWPRES
tWPRE
tWPST
0.9
0.4
0
0.35
0.4
1.1
0.6
0.9
0.4
0
0.25
0.4
1.1
0.6
0.9
0.4
0
0.25
0.4
1.1
0.6
tCK
tCK
ps
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
0.6
0.6
0.6
WL
- 0.25
WL+
0.25
WL
- 0.25
WL+
0.25
WL
- 0.25
WL+
0.25
Write command to first DQS latching transition
tDQSS
tCK
TBD
TBD
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
January 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
AC OPERATING CONDITIONS (continued)
≤TCASE ≤ +85°C; VCC = +1.8V 0.1V
AC Characteristics
806
665
534
403
Symbol
Units
Parameter
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
0.6
200
275
2
55
7.5
15
37.5
40
7.5
15
Max
Min
0.6
250
375
2
60
7.5
15
37.5
40
7.5
15
Max
Min
0.6
250
475
2
65
7.5
15
37.5
40
7.5
15
Max
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
CACS# to CACS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tIPW
tCK
ps
tIS
b
tIH
b
tCCD
tRC
tCK
ns
ns
ns
ns
ns
ns
ns
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
70,000
70,000
70,000
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tWR +
tRP
tWR +
tRP
Auto precharge write recovery + precharge time
tDAL
tWR + tRP
ns
TBD
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
tRP
10
15
7.5
15
10
15
ns
ns
TBD
TBD
TBD
TBD
tRP +
tCK
tRP +
tCK
PRECHARGE ALL command period
tRPA
tRP + tCK
ns
TBD
TBD
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tMRD
tDELAY
2
4.375
2
4.375
2
4.375
tCK
ns
TBD
TBD
TBD
TBD
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
January 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
AC OPERATING CONDITIONS (continued)
≤TCASE ≤ +85°C; VCC = +1.8V 0.1V
AC Characteristics
Parameter
806
665
534
403
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
70,000 ns
REFRESH to Active or Refresh to Refresh command
interval
tRFC (256MB)
tREFI
127.5 70,000
7.8
75
70,000
7.8
75
TBD
TBD
Average periodic refresh interval
7.8
µs
ns
TBD
TBD
TBD
TBD
TBD
TBD
tRFC (MIN)
tRFC (MIN)
tRFC (MIN)
Exit self refresh to non-READ command
Exit self refresh to READ command
tXSNR
+ 10
+ 10
+ 10
tXSRD
200
tIS
200
200
tCK
Exit self refresh timing reference
ODT turn-on delay
tISXR
tAOND
tIS
2
tIS
2
ps
tCK
TBD
TBD
TBD
TBD
2
2
2
tAC (MAX +
tAC (MAX +
tAC (MAX +
ODT turn-on
tAOND
tAOFD
tAOF
tAC (MIN)
2.5
tAC (MIN)
tAC (MIN)
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
700)
1,000)
1,000)
ODT turn-off delay
ODT turn-off
2.5
tAC (MAX +
600)
2.5
2.5
tAC (MAX +
600)
2.5
2.5
tAC (MAX +
600)
tAC (MIN)
tAC (MIN)
tAC (MIN)
tAC (MIN) + tAC (MAX) + tAC (MIN) + tAC (MAX) + tAC (MIN) + tAC (MAX) +
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAOFPD
ps
ps
TBD
TBD
TBD
TBD
2,000
1,000
2,000
1,000
2,000
1,000
tAC (MIN) + tAC (MAX) + tAC (MIN) + tAC (MAX) + tAC (MIN) + tAC (MAX) +
2,000
1,000
2,000
1,000
2,000
1,000
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command.
CKE minimum high/low time
tANPD
tAXPD
tXARD
tXARDS
tXP
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
7 - AL
2
2
6 - AL
2
2
6 - AL
2
tCK
tCK
tCKE
3
3
3
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specifications may be different.
January 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D4
Clock/Data Rate
Frequency
CAS
Latency
Part Number
tRCD
tRP
Height**
WV3HG32M72EEU806D4xG*
WV3HG32M72EEU665D4xG*
WV3HG32M72EEU534D4xG
WV3HG32M72EEU403D4xG
* Consult Factory for availability
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
31.75mm (1.25") TYP
31.75mm (1.25") TYP
31.75mm (1.25") TYP
31.75mm (1.25") TYP
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
3.302 (0.130)
MAX
FRONT VIEW
67.75 (2.667) MAX
4.10 (0.161) (2x)
3.90 (0.154)
1.80
(0.071)
(2X)
31.90 (1.256)
31.60 (1.244)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
2.15 (0.085)
1.00 (0.039)
TYP
0.60 (0.024)
TYP
0.45 (0.018)
TYP
1.10 (0.043)
0.90 (0.035)
MAX
PIN 199
PIN 1
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 32M 72 E E U xxx D4 x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
DATA RATE (Mb/s)
PACKAGE 200 PIN SO-DIMM
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
January 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
Document Title
256Mb – 32Mx72 DDR2 SDRAM UNBUFFERED, w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Created
January 2006
Advanced
January 2006
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
©2020 ICPDF网 联系我们和版权申明