ZL50074GDC [MICROSEMI]
Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484;
| 型号： | ZL50074GDC |
| 厂家： | 
Microsemi |
| 描述： | Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484 电信 电信集成电路 |
| 文件： | 总55页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL50074
32 K x 32 K Channel TDM Switch
with 128 Input and 128 Output Streams
Data Sheet
January 2004
Ordering Information
Features
•
32,768 channel x 32,768 channel non-blocking
digital TDM switch at 65.536 Mbps, 32.768 Mbps
or 16.384 Mbps
ZL50074GDC 484 Ball LBGA
•
16,384 channel x 16,384 channel non-blocking
digital TDM switch at 8.192 Mbps
-40°C to +85°C
•
•
•
•
•
•
•
128 inputs and 128 outputs at 16 Mbps or 8 Mbps
64 inputs and 64 outputs at 32 Mbps
32 inputs and 32 outputs at 65 Mbps
ST-BUS or GCI-Bus modes
•
•
IEEE 1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant inputs; 1.8 V core
Applications
Per-stream bit delay on TDM inputs
Per-stream bit advancement on TDM outputs
•
•
•
•
•
•
•
Large Switching Platforms
Central Office Switches
Per-channel constant or variable throughput
delay for frame integrity and low latency
applications
Wireless Base Stations and Controllers
Multi-service Access Platforms
Digital Loop Carriers
•
•
•
•
•
Per-channel high impedance output control
Per-channel force-high output control
Per-channel message mode
Time Division Multiplexers
Media Gateways
Connection Memory block programming
Control interface compatible with Intel and
Motorola Selectable 32 bit and 16 bit
non-multiplexed buses
VDD_CORE
VDD_IO
VSS
ODE
PWR
STiA0
STiB0
STiC0
STiD0
:
SToA0
SToB0
SToC0
SToD0
Data Memory
P/S
Converter
S/P
Converter
:
:
:
STiA31
STiB31
STiC31
STiD31
SToA31
SToB31
Connection Memory
SToC31
SToD31
Input
Timing
Output
Timing
FPi2-0
CKi2-0
CK_SEL1-0
FPo3-0
Timing
Test Access
Port
Microprocessor Interface
and Control Registers
CKo3-0
Figure 1 - ZL50074 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50074
Data Sheet
Description
The ZL50074 is a 32K x 32K channel non-blocking Time Division Multiplex (TDM) switch. The device can switch
64 kbps or Nx64 kbps TDM channels from any input stream to any output stream.
All TDM input and output streams operate at the same rate, either 65 Mbps, 32 Mbps, 16 Mbps or 8 Mbps,
programmed by the Global Rate Control Register. In 65 Mbps mode, only STiA and SToA streams are used,
resulting in 32 input and 32 output streams. In 32 Mbps mode, both STiA, SToA, STiB and SToB streams are
available, resulting in 64 input and 64 output streams. In 16 Mbps or 8 Mbps mode, STiA, SToA, STiB, SToB, STiC,
SToC, STiD and SToD streams are available, resulting in 128 input and 128 output streams.
The ZL50074 uses a master clock (CKi0) and frame pulse (FPi0) to define the input frame boundary and timing. An
Analog Phase Lock Loop (APLL) is used to generate the internal system clock. The ZL50074 has the option to
clock the input and output TDM data streams with either an internal APLL derived clock or directly using the CKi0
master reference.
The ZL50074 has a variety of user configurable options designed to provide flexibility when data streams are
connected to multiple TDM components or circuits. These include:
•
•
•
•
Two additional programmable reference inputs, CKi2 - 1 and FPi2 - 1, which can be used to provide
alternative sources for input and output stream timing
Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams
connected through different data paths
Four timing outputs, CKo3 - 0 and FPo3 - 0, which can be configured independently to provide a variety of
clock and frame pulse options
Support of both ST-BUS and GCI-Bus formats
The device contains two types of internal memory: Data Memory and Connection Memory. Incoming TDM data is
stored in the Data Memory. TDM Data is read from the Data Memory controlled by the Connection Memory, and
output on the TDM Output Streams.
There are two modes of operation: Connection Mode and Message Mode. In Connection Mode, the contents of the
Connection Memory define, for each output stream and channel, the input source stream and channel. In Message
Mode, the Connection Memory is used for the storage of microprocessor data. Using Zarlink's Message Mode
capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is
useful for transferring control and status information for external circuits or other TDM devices.
The non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and
configuration registers used to program ZL50074 options. The port is configurable to interface with either Motorola
or Intel-type microprocessors.
The mandatory requirements of IEEE 1149.1 (JTAG) standard are fully supported via the dedicated test access
port.
2
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Diagram (as viewed through top of package)
A1 corner identified by metallized marking
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
CKo STiA D[30] D[25] D[20] D[16] D[15] D[11] D[7] D[4] D[0] A[18] A[14] A[10] A[7] A[2] A[1]
[0] [0]
IC
DTA PWR SToA TCK
[31]
A
B
C
D
E
SToB STiD SToA D[31] D[26] D[21] D16B D[13] D[9] D[5] D[3] A[17] A[11] A[8] A[6] A[0] BERR SIZ[0] SToB STiA TDo STiA
[1] [1] [0] [31] [31] [30]
STiA STiA STiB STiD IM D[27] D[22] D[19] D[12] D[6] D[1] A[15] A[9] A[3] R/W CS
[2] [3] [1] [0]
FPo STiD TRST SToD STiB STiD
[3] [31] [30] [30] [29]
STiC STiD SToC SToD SToB STiC D[28] D[23] D[17] D[8] A[16] A[13] A[5]
[3] [2] [1] [0] [0] [0]
DS WAIT SToD STiB TDi SToB STiC SToA SToD
[31] [31] [30] [30] [29] [28]
STiD SToB STiC SToA STiA SToC STiB D[24] D[18] D[14] D[2] A[12] A[4] CKo SIZ[1] STiC TMS SToC STiD SToD STiA STiB
[4] [3] [2] [1] [1] [0] [0] [3] [31] [30] [30] [29] [29] [28]
SToB SToC SToB SToD STiC VSS VDD_ D[29] VDD_ VDD_ D[10] VDD_ VDD_ SToC VDD_ VSS VDD_ SToA SToC STiC SToB STiA
[4] [3] [2] [1] [1] [31] [30] [29] [29] [28] [28]
F
CORE
IO
CORE
IO
CORE
IO
CORE
SToD SToD SToD STiB FPo VDD_ VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS VDD_ VDD_ VSS SToB STiB STiC CKi STiD
[4] [3] [2] [2] [0] [29] [29] [28] [2] [27]
G
H
J
IO
CORE
IO
CORE
IO
CORE
IO
STiA STiA STiD SToC SToA VDD_ VDD_ VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS VDD_ SToA SToC STiD SToD STiC STiA
[5] [4] [3] [2] [2] [28] [28] [28] [27] [27] [27]
CORE
IO
CORE
IO
CORE
IO
CORE
STiB CKi STiC SToA STiB VDD_ VDD_ VDD_ VSS VSS VSS VSS VSS VSS VDD_ VSS VDD_ SToB SToC STiB
[5] [1] [4] [3] [3] [27] [27] [27]
IC SToC
[26]
IO
CORE
IO
IO
IO
SToB STiD FPi SToC SToA STiB VSS VDD_ VSS VSS VSS VSS VSS VSS VDD_ VDD_ VDD_ SToA FPi SToA SToB STiD
[5] [5] [1] [4] [4] [4] [27] [2] [26] [26] [26]
K
L
CORE
CORE
IO
CORE
ODE SToD SToC STiD STiC VDD_ VDD_ VSS VSS VSS VSS VSS VSS VSS VSS VDD_ SToD STiC STiB STiA SToD SToC
[5] [5] [6] [5] [26] [26] [26] [26] [25] [25]
CORE
IO
CORE
STiA STiB STiC STiC SToA VDD_ VDD_ VDD_ VSS VSS VSS VSS VSS VSS VDD_ VSS VDD_ STiA STiD SToB SToA IC
[6] [6] [6] [7] [5] [25] [25] [25] [25]
M
N
P
IO
CORE
IO
IO
IO
SToB SToC SToD SToA SToA VSS VSS VDD_ VSS VSS VSS VSS VSS VSS VDD_ VDD_ SToD SToC STiD SToB STiB STiC
[6] [6] [6] [7] [6] [23] [24] [24] [24] [25] [25]
CORE
CORE
IO
STiA STiB SToB STiA SToA VDD_ VDD_ VDD_ VSS VSS VSS VSS VSS VSS VDD_ VDD_ VDD_ SToA STiC STiB SToA SToD
[7] [7] [7] [8] [8] [23] [23] [24] [24] [24]
CORE
IO
IO
IO
CORE CORE
STiD SToC IC SToB STiB VDD_ VDD_ VSS VSS VDD_ VDD_ VSS VDD_ VDD_ VSS VSS VDD_ CKo STiD STiB STiA STiC
[7] [7] [8] [8] [2] [22] [23] [24] [24]
R
T
IO
CORE
CORE
IO
CORE
IO
IO
SToD VSS SToC STiD STiB SToD VSS VSS VDD_ VDD_ VSS VDD_ VSS VSS VDD_ VDD_ VSS SToA FPo SToC STiD SToC
[7] [8] [9] [10] [9] [21] [2] [22] [23] [23]
CORE
IO
CORE
CORE
IO
STiC SToD STiC STiA SToC VSS VDD_ SToC VDD_ VDD_ STiA VDD_ VDD_ SToA VDD_ STiC VDD_ SToC STiD STiC SToD SToB
[8] [8] [9] [10] [10] [12] [16] [18] [19] [20] [21] [22] [22] [23]
U
V
IO
IO
CORE
IO
CORE
IO
CORE
STiD STiB SToC SToB SToD SToB STiC STiB SToA STiC SToB SToC IC
[8] [9] [9] [10] [10] [11] [12] [13] [13] [15] [16] [16]
CK_ STiB SToA STiA SToB SToD SToC SToA STiA
SEL[1] [18] [19] [20] [20] [20] [21] [22] [23]
STiA SToB STiD STiA SToA STiB SToD STiC STiA SToD SToC CKi
[9] [9] [10] [11] [11] [12] [12] [13] [14] [14] [15] [0]
IC SToB CK_ SToC STiD SToD STiD STiC STiA SToB
[17] SEL[0] [18] [19] [19] [20] [21] [22] [22]
W
Y
SToA SToA STiB SToC SToA FPo STiD STiB SToB STiD SToD SToD IC
[9] [10] [11] [11] [12] [1] [13] [14] [14] [15] [15] [16]
STiC SToC STiA SToB STiB STiB SToA SToB STiB
[17] [17] [18] [18] [19] [20] [20] [21] [22]
STiC STiC SToD STiD STiA SToB SToD SToA STiA SToA STiB SToA FPi STiA SToA IC
IC SToD SToB SToC STiA SToD
[18] [19] [19] [21] [21]
AA
AB
[10] [11]
[11] [12] [13] [13] [13] [14] [15] [15] [16] [16]
[0]
[17] [17]
STiD STiA SToB CKo SToC STiC STiD SToC STiB SToB STiC STiD NC
[11] [12] [12] [1] [13] [14] [14] [14] [15] [15] [16] [16]
NC STiB STiD SToD STiC STiD STiA STiC STiB
[17] [17] [17] [18] [18] [19] [20] [21]
Table 1 - ZL50074 23 mm x 23 mm 484 Ball PBGA
3
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description
Pin
Name
Description
TDM Interface
F7, F10, F13, F17,
G9, G12, G15, H6,
H10, H13, H16, J7,
K8, K15, K17, L6, L16,
M7, N8, N15, P6, P16,
P17, R7, R10, R13,
T9, T12, T15, U10,
U13, U17
V
Power Supply for the Core Logic: +1.8 V
Power Supply for the I/O: +3.3 V
Ground
DD_CORE
F9, F12, F15, G6,
G10, G13, G16, H7,
H11, H14, J6, J8, J15,
J17, K16, L7, M6, M8,
M15, M17, N16, P7,
P8, P15, R6, R11,
V
DD_IO
R14, R17, T10, T16,
U7, U9, U12, U15
F6, F16, G7, G8, G11,
G14, G17, H8, H9,
H12, H15, J9, J10,
J11, J12, J13, J14,
J16, K7, K9, K10, K11,
K12, K13, K14, L8, L9,
L10, L11, L12, L13,
L14, L15, M9, M10,
M11, M12, M13, M14,
M16, N6, N7, N9, N10,
N11, N12, N13, N14,
P9, P10, P11, P12,
P13, P14, R8, R9,
R12, R15, R16, T2,
T7, T8, T11, T13, T14,
T17, U6
V
SS
A2, E5, C1, C2, H2,
H1, M1, P1, P4, W1,
U4, W4, AB2, AA5,
W9, AA9, U11, AA14,
Y16, AB20, V17,
AA21, W21, V22, R21,
M18, L20, H22, F22,
E21, B22, B20
STiA0-31
STiB0-31
Serial TDM Input Data ’A’ Streams (5 V Tolerant Input with Internal
Pull-down)
32 serial TDM input data streams. All streams are at the same rate:
either 65.536 Mbps, 32.678 Mbps, 16.384 Mbps or 8.192 Mbps,
programmed by the Global Rate Control Register, see Section 15.5.
Unused inputs are pulled low by internal pull-down resistors and may be
left unconnected.
E7, C3, G4, J5, K6,
J1, M2, P2, R5, V2,
T5, Y3, W6, V8, Y8,
AB9, AA11, AB15,
V15, Y18, Y19, AB22,
Y22, R20, P20, N21,
L19, J20, E22, G19,
C21, D17
Serial TDM Input Data ’B’ Streams (5 V Tolerant Input with Internal
Pull-down)
32 serial TDM input data streams. All streams are at the same rate:
either 65.536 Mbps, 32.678 Mbps, 16.384 Mbps or 8.192 Mbps,
programmed by the Global Rate Control Register, see Section 15.5.
Unused inputs are pulled low by internal pull-down resistors and may be
left unconnected.
4
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description (continued)
Pin
Name
Description
D6, F5, E3, D1, J3,
L5, M3, M4, U1, U3,
AA1, AA2, V7, W8,
AB6, V10, AB11, Y14,
AB18, U16, AB21,
W20, U20, P19, R22,
N22, L18, H21, G20,
F20, D20, E16
STiC0-31
STiD0-31
SToA0-31
SToB0-31
SToC0-31
Serial TDM Input Data ’C’ Streams (5 V Tolerant Input with Internal
Pull-down)
32 serial TDM input data streams. All streams are at the same rate:
either 16.384 Mbps or 8.192 Mbps, programmed by the Global Rate
Control Register, see Section 15.5.
Unused inputs are pulled low by internal pull-down resistors and may be
left unconnected.
C4, B2, D2, H3, E1,
K2, L4, R1, V1, T4,
W3, AB1, AA4, Y7,
AB7, Y10, AB12,
Serial TDM Input Data ’D’ Streams (5 V Tolerant Input with Internal
Pull-down)
32 serial TDM input data streams. All streams are at the same rate:
either 16.384 Mbps or 8.192 Mbps, programmed by the Global Rate
Control Register, see Section 15.5.
AB16, AB19, W17,
W19, U19, R19, T21,
N19, M19, K22, G22,
H19, C22, E19, C18
Unused inputs are pulled low by internal pull-down resistors and may be
left unconnected.
B3, E4, H5, J4, K5,
M5, N5, N4, P5, Y1,
Y2, W5, Y5, V9, AA8,
AA10, AA12, AA15,
U14, V16, Y20, T18,
V21, P18, P21, M21,
K20, K18, H17, D21,
F18, A21
Serial TDM Output Data ’A’ Streams (5 V Tolerant, 3.3 V Tri-state
Slew-Rate Controlled Outputs)
32 serial TDM output data streams. All streams in are at the same rate:
65.536 Mbps, 32.678 Mbps, 16.384 Mbps or 8.192 Mbps. These pins
are activated when outputs are programmed for 32 Mbps, 16 Mbps or
8 Mbps operation via the Global Rate Control Register, see Section
15.5.
D5, B1, F3, E2, F1,
K1, N1, P3, R4, W2,
V4, V6, AB3, AA6, Y9,
AB10, V11, W14, Y17,
AA19, V18, Y21, W22,
U22, N20, M20, K21,
J18, F21, G18, D19,
B19
Serial TDM Output Data ’B’ Streams (5 V Tolerant, 3.3 V Tri-state
Slew-Rate Controlled Outputs)
32 serial TDM output data streams. All streams in are at the same rate:
32.678 Mbps, 16.384 Mbps or 8.192 Mbps. These pins are activated
when outputs are programmed for 32 Mbps, 16 Mbps or 8 Mbps
operation via the Global Rate Control Register, see Section 15.5. When
not activated, these outputs are high impedance.
E6, D3, H4, F2, K4,
L3, N2, R2, T3, V3,
U5, Y4, U8, AB5, AB8,
W11, V12, Y15, W16,
AA20, U18, V20, T20,
T22, N18, L22, J22,
J19, H18, F19, E18,
F14
Serial TDM Output Data ’C’ Streams (5 V Tolerant, 3.3 V Tri-state
Slew-Rate Controlled Outputs)
32 serial TDM output data streams. All streams in are at the same rate:
16.384 Mbps or 8.192 Mbps. These pins are activated when outputs are
programmed for 32 Mbps, 16 Mbps or 8 Mbps operation via the Global
Rate Control Register, see Section 15.5. When not activated, these
outputs are high impedance.
5
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description (continued)
Pin
Name
SToD0-31
Description
D4, F4, G3, G2, G1,
L2, N3, T1, U2, T6,
V5, AA3, W7, AA7,
W10, Y11, Y12, AB17,
AA18, W18, V19,
Serial TDM Output Data ’D’ Streams (5 V Tolerant, 3.3 V Tri-state
Slew-Rate Controlled Outputs)
32 serial TDM output data streams. All streams in are at the same rate:
16.384 Mbps or 8.192 Mbps. These pins are activated when outputs are
programmed for 32 Mbps, 16 Mbps or 8 Mbps operation via the Global
Rate Control Register, see Section 15.5. When not activated, these
outputs are high impedance.
AA22, U21, N17, P22,
L21, L17, H20, D22,
E20, C20, D16
W12
CKi0
ST-BUS/GCI-Bus Clock Input (5 V Tolerant Schmitt-Triggered
Input)
This pin accepts an 8.192 MHz, 16.384 MHz, 32.678 MHz or
65.536 MHz clock. This clock must be provided for correct operation of
the ZL50074. The frequency of the CKi0 input is selected by the
CK_SEL1-0 inputs. The active clock edge may be either rising or falling,
programmed by the Input Clock Control Register, see Section 15.1.
AA13
FPi0
ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input)
This pin accepts the 8 kHz frame pulse which marks the frame
boundary of the TDM data streams. The pulse width is nominally one
CKi0 clock period (Assuming ST-BUS mode) selected by the CK_SEL1-
0 inputs. The active state of the frame pulse may be either high or low,
programmed by the Input Clock Control Register, see Section 15.1.
J2, G21
CKi1-2
ST-BUS/GCI-Bus Clock Inputs (5 V Tolerant Schmitt Triggered
Inputs)
These optional TDM clock inputs are at 8.192 MHz, 16.384 MHz,
32.678 MHz or 65.536 MHz. The frequency of each clock input is
automatically detected by the ZL50074. Refer to Section 2.0 for TDM
timing options. The active clock edge may be either rising or falling,
programmed by the Input Clock Control Register, see Section 15.1.
Unused inputs must be connected to either high or low.
K3, K19
FPi1-2
ST-BUS/GCI-Bus Frame Pulse Inputs (5 V Tolerant Inputs)
These 8 kHz input pulses correspond to the optional CKi2-1 clock
inputs. The frame pulses mark the frame boundary of the TDM data
streams. Refer to Section 2.0 for TDM timing options. Each pulse width
is nominally one CKi clock period (Assuming ST-BUS mode). The active
state of the frame pulse may be either high or low, programmed by the
Input Clock Control Register, see Section 15.1. Unused inputs must be
connected to a logic 1 or logic 0.
A1, AB4, R18, E14
CKo0-3
ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate
Control)
These clock outputs can be programmed to generate an 8.192 MHz,
16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock output. The active
edge can be programmed to be either rising or falling. The source of the
clock outputs can be derived from either the CKi2-0 inputs or the
internal system clock. The frequency, active edge and source of each
clock output can be programmed independently by the Output Clock
Control Register, see Section 15.2.
6
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description (continued)
Pin
Name
FPo0-3
Description
G5, Y6, T19, C17
W15, V14
L1
ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with Slew-
Rate Control)
These 8 kHz output pulses mark the frame boundary of the TDM data
streams. The pulse width is nominally one clock period of the
corresponding CKo output. The active state of each frame pulse may be
either high or low, independently programmed by the Output Clock
Control Register, see Section 15.2.
CK_SEL0-1 Master Clock Input Select (5 V Tolerant Inputs)
Inputs used to select the frequency and frame alignment of CKi0 and
FPi0:
CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz
CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz
CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz
CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz
ODE
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
This is the asynchronous output enable control for the output streams.
When it is high, the streams are enabled. When it is low, the output
streams are tristated.
A18, J21, M22, R3,
V13, W13, Y13, AA16,
AA17
IC
Internal Connections
In normal mode these pins MUST be connected low
AB13, AB14
NC
No Connection
In normal mode these pins MUST be left unconnected.
Microprocessor Port and Reset
A11, C11, E11, B11,
A10, B10, C10, A9,
D10, B9, F11, A8, C9,
B8, E10, A7, A6, D9,
E9, C8, A5, B6, C7,
D8, E8, A4, B5, C6,
D7, F8, A3, B4
D0-31
Microprocessor Port Data Bus (5 V Tolerant Bi-directional with
Slew-Rate Output Control)
32 or 16 bit bidirectional data bus. Used for microprocessor access to
internal memories and registers. When 16 bit mode is selected (D16B is
logic 1), D31-16 are unused and must be connected to either high or
low.
B16, A17, A16, C14,
E13, D13, B15, A15,
B14, C13, A14, B13,
E12, D12, A13, C12,
D11, B12, A12
A0-18
Microprocessor Port Address Bus (5 V Tolerant Inputs)
19 bit address bus for the internal memories and registers. In 16 bit bus
mode (D16B is logic 1), please note A0 is not used and must be
connected to either high or low.
In Intel 32 bit mode: A1 = BE , A0 = BE
3
2
C16
CS
DS
Chip Select Input (5 V Tolerant Input)
Active low input used with DS to enable read and write access to the
ZL50074.
D14
Data Strobe Input (5 V Tolerant Input)
Active low input used with CS to enable read and write access to the
ZL50074.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description (continued)
Pin
Name
Description
Read/Write Input (5 V Tolerant Input)
C15
R/W
This input controls the direction of the data bus lines (D31 - 0) during a
microprocessor access. This pin is set high and low for the read and
write access respectively.
A19
B17
DTA
Data Transfer Acknowledge (5 V Tolerant, 3.3 V Tri-state Output
with Slew-Rate)
This active low output indicates that a data bus transfer is complete. An
external pull-up resistor is required to hold this pin HIGH when not in
use.
BERR
Transfer Bus Error Output with Slew Rate Control (5 V Tolerant,
3.3 V Tri-state Outputs with Slew-Rate Control)
This pin goes low whenever the microprocessor attempts to access an
invalid memory space inside the device. In Motorola bus mode, if this
bus error signal is activated, the data transfer acknowledge signal, DTA,
will not be generated. In Intel bus mode, the generation of the DTA is
not affected by this BERR signal. An external pull-up resistor is required
to hold a HIGH level when output is high-impedance.
D15
WAIT
Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-state Output with
Slew Rate)
Active low wait signal output
B18, E15
SIZ0-1
Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V
Tolerant Inputs)
Motorola 32-bit mode - signals indicate data transfer size, refer to
Section 8.0.
Motorola 16-bit mode:SIZ0 - LDS, SIZ1 - UDS.
Active low upper and lower data strobes, UDS and LDS, indicate
whether the upper byte, D15 - 8, and/or lower byte, D7 - 0, is being
accessed.
Intel 32/16-bit mode: SIZ0 - BE0, SIZ1 - BE1
Active low Intel type bus-enable signals, BE1 and BE0
C5
B7
IM
Microprocessor Port Bus Mode Select (5 V Tolerant Input)
Control input:
0 = Motorola mode
1 = Intel mode
D16B
Microprocessor Port Bus 16/32 Bit Mode Select (5 V Tolerant Input
with Internal Pull-down)
Control input:
0 = 32 bit data bus
1 = 16 bit data bus
A20
PWR
Device Reset (5 V Tolerant Schmitt-Triggered Input)
Asynchronous reset input used to initialize the ZL50074.
0 = Reset
1 = Normal
See Section 9.0, Power-up and Initialization of the ZL50074 for detailed
description of Reset state.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Pin Description (continued)
Pin
Name
Description
IEEE 1149.1 Test Access Port (TAP)
D18
TDi
Test Data (5 V Tolerant Input with Internal Pull-up)
Serial test data input. When not used, this input may be left
unconnected.
B21
A22
TDo
TCK
Test Data (3.3 V Output)
Serial test data output
Test Clock (5 V Tolerant Schmitt-Triggered Input with Internal Pull-
up)
Provides the clock to the JTAG test logic
C19
TRST
Test Reset (5 V Tolerant Schmitt-Triggered Input with Internal Pull-
up)
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. This pin should be pulsed low during power-up
to ensure that the device is in the normal functional mode. When JTAG
is not being used, this pin should be pulled low during normal operation.
E17
TMS
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller. This
pin is pulled high by an internal pull-up resistor when it is not driven.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Table of Contents
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Stream Provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 Output Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Fractional Bit Advancement on Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.0 Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Data Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 32 bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.3 16 bit Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.4 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.4.1 Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.4.2 Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.0 Power-up and Initialization of the ZL50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.0 IEEE 1149.1 Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.4 Boundary Scan Description Language (BSDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.0 Memory Map of ZL50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Connection Memory Bit Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13.0 Connection Memory LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14.0 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.0 Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.1 Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15.2 Output Clock Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15.3 Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
15.4 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
15.5 Global Rate Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
List of Figures
Figure 1 - ZL50074 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3 - Output Bit Advance Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4 - Data Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5 - Read Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6 - Write Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7 - Frame Pulse Input and Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8 - Frame Skew Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 9 - Serial Data Timing to CKi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10 - Serial Data Timing to CKo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 11 - Microprocessor Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12 - Intel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13 - JTAG Test Port & PWR Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
List of Tables
Table 1 - ZL50074 23 mm x 23 mm 484 Ball PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2 - Data Rate and Maximum Switch Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 - TDM Stream Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4 - CKi0 and FPi0 Setting via CK_SEL1 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5 - Example of Address and Byte Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6 - 32 bit Motorola Mode Byte Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7 - 32 bit Motorola Mode Access Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8 - 32 bit Intel Mode Bus Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9 - Byte Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10 - 16 bit Mode Word Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11 - 16 bit Mode Example Byte Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13 - Connection Memory Stream Control Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14 - Output Control at Various Output Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15 - Stream Offset Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16 - Connection Memory Bits (CMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17 - Connection Memory LSB Stream Control Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18 - Connection Memory LSB Output Group Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19 - Data Memory Stream Control Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20 - Data Memory Stream Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21 - Group Control Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 22 - Group Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23 - Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24 - Output Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 25 - Block and Power-up Initialization Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1.0 Functional Description
1.1 Overview
The device has 128 ST-BUS/GCI-Bus inputs (STiA0 - 31, STiB0 - 31, STiC0 - 31, STiD0 - 31) and 128
ST-BUS/GCI-Bus outputs (SToA0 - 31, SToB0 - 31, SToC0 - 31, SToD0 - 31). It is a non-blocking digital switch with
32,768 64 kbps channels and is capable of operating at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps.
There are 32 input groups with each group consisting of four streams (‘A’, ‘B’, ‘C’ and ‘D’). If the data rate is set to
16.384 Mbps or 8.192 Mbps, then STiA0 - 31, STiB0 - 31, STiC0 - 31 and STiB0 - 31 are used for the input traffic.
When the data rate is set to 32.768 Mbps then STiA0-31and STiB0 - 31 are used for the input traffic and STiC0-31
and STiD0-31 are not used. When the data rate is set to 65.536 Mbps then STiA0-31 are used for the input traffic
and STiB0-31, STiC0-31, and STiD0-31 are not used. The outputs deliver serial data streams with data rates of
8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 output groups with each group consisting of
4 streams (‘A’, ‘B’, ‘C’, and ‘D’). If the data rate is set to 16.384 Mbps or 8.192 Mbps, then SToA0-31, SToB0-31
SToC0-31 and SToD0-31 are used are used for the output traffic. If the data rate is set to 32.768 Mbps, then
SToA0-31 and SToB0-31 are used are used for the output traffic and STiC0-31and STiD0-31 are in high
impedance. When the data rate is set to 65.536 Mbps then SToA0 - 31 are used for the output traffic and SToB0-31,
SToC0-31, SToC0-31 are in high impedance.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
The ZL50074 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input
clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams. The
rate of the input clock is defined by setting the CK_SEL0-1 pins.
A selectable Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device
to operate in various modes under different switching configurations. Users can use the microprocessor port to
perform internal register and memory read and write operations. The microprocessor port can be selectable to be
either a 32 bit or 16 bit data bus and to have either a 19 bit or 17 bit address bus. This is selected by setting the
D16B pin. There are seven control signals (CS, DS, R/W, DTA, WAIT, BERR and IM).
The device supports the mandatory requirements for the IEEE 1149.1 (JTAG) standard via the test port.
1.2 Switching Configuration
The ZL50074 switches 64kbps and Nx64 kbps data channels from the TDM input streams, to timeslots in the TDM
output streams. The device is non-blocking; all 32 K input channels can be switched through to the outputs. Any
input channel can be switched to any available channel.
The number of 64 kbps channel timeslots per stream is shown in Table 2.
Number of Input
TDM Data
Number of Output
TDM Data
Number of
64 kbpsChannels
per Stream
TDM Stream Data
Rate
Maximum Switch
Capacity (channels)
Streams
Streams
65 Mbps
32 Mbps
16 Mbps
8 Mbps
32
64
32
64
1024
512
256
128
32x1024 = 32,768
64x512 = 32,768
64x256 = 32,768
64x128 = 8,192
128
128
128
128
Table 2 - Data Rate and Maximum Switch Size
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1.3 Stream Provisioning
The ZL50074 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features.
In order to facilitate ease of use, the ZL50074 offers a simple programming model. Streams are grouped in sets of
four, with each group sharing the same configured characteristics. In this way it is possible to reduce programming
complexity, while still maintaining flexible ’per-stream’ configuration options:
•
•
•
•
•
Input and output device rate selection, see Section 15.5
Input stream clock source selection, see Section 2.0
Output stream clock source selection, see Section 3.0
Input stream sampling point selection, see Section 5.1
Output stream fractional bit advance, see Section 5.2
There are 32 input and 32 output groups. Depending on the data rate set for the device there will be either 1, 2 or 4
streams activated. If the data rate is set for 65.536 Mbps, the ‘A’ stream will be activated and the ‘B’, ‘C’ and ‘D’
streams will not be activated. If the data rate is set for 32.768 Mbps the ‘A’ and ‘B’ streams will be activated. If the
data rate is set for 16.384 Mbps or 8.192 Mbps, the ‘A’, ‘B’, ‘C’ and ‘D’ streams will be activated. Input and Output
Device Rate Selection.
Table 2 shows the maximum number of streams available at different bit rates. The ZL50074 deactivates unused
streams when operating at the higher bit rates as shown in Table 3.
Input or Output Group n
65 Mbps
32 Mbps
16 Mbps
8 Mbps
(n = 0 - 31)
STiAn / SToAn
STiBn / SToBn
STiCn / SToCn
STiDn / SToDn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Not Active
Not Active
Not Active
Not Active
Not Active
Table 3 - TDM Stream Bit Rates
All TDM input and output data streams operate at the same rate, programmed by the Global Rate Control Register,
see Section 15.5.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
2.0 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The input timing for the ZL50074 can be set for one of four different input values. They can be set for ST-BUS or
GCI-Bus with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the device to
be used. CKi0 is used to generate the internal clock. This clock is used for all internal logic and can be used as one
of the clocks that defines the timing for the input and output data. The input stream clock source is selected by the
ISSRC1 - 0 (bits 1 - 0) in the Group Control Register. The output stream clock source is selected by the OSSRC1 -
0 (bits 17 - 16) in the Group Control Register.
The CKi0 and FPi0 input values are set via the CK_SEL1 - 0 pins as shown in Table 4. By default the CKi0 and FPi0
pins accept ST-BUS, negative input timing. By setting the GCISEL0 (bit 2) in the Input Clock Control Register
(ICCR) the input timing is set for GCI-Bus mode. The FPIPOL0 (bit 1) in the Input Clock Control Register (ICCR)
sets the input frame pulse is positive. The CKIPSL0 (bit 0) in the Input Clock Control Register (ICCR) sets the input
clock is positive.
CK_SEL1
CK_SEL0
Input CKi0 and FPi0
0
0
1
1
0
1
0
1
8.192MHz
16.384MHz
32.768MHz
65.536MHz
Table 4 - CKi0 and FPi0 Setting via CK_SEL1 - 0
Two additional input clocks (CKi2 - 1) and frame pulse (FPi2 - 1) signals can be accepted. These signals can be
8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz and the rates are automatically detected by the ZL50073.
These clocks must be phase aligned with the CKi0 within a 30 ns skew but can have different jitter values. The
clocks do not have to have the same frequency. If these additional clocks are not used, the pins must be connected
to ground. The additional signals can be used as the clock source for input streams, output stream and output clock
and frame pulse signals. The Input Stream Clock Source (bits 1 - 0) in the Group Control Register (SCR) are used
to set the clock source to either the internal clock or one of the three input clock signals. The Output Stream Clock
Source (bits 17 - 16) in the Group Control Register (SCR) is used to set the clock source to either the internal clock
or one of the three input clock signals. These are used to provide a direct interface to jittery peripherals.
3.0 Output Clock (CKo) and Output Frame Pulse (FPo) Timing
There are four output timing pairs, CKo3 - 0 and FPo3 - 0. By default these signals generate ST-BUS, negative
timing. Each can be set individually to produce 8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz timing through
the programming of the CKO3RATE1 - 0 (bits 24 - 23), CKO2RATE1 - 0 (bits 17 - 16), CKO1RATE1 - 0 (bits 10 - 9),
CKO0RATE1 - 0 (bits 3 - 2) in the Output Clock Control Register (OCCR). With the setting of the GCOSEL3 (bit 27),
GCOSEL2 (bit 20), GCOSEL1 (bit 13) and GCOSEL0 (bit 6) in the Output Clock Control Register (OCCR) the
output conforms the GCI-Bus standard. The signals can be adjusted to provide positive frame pulses with the
setting of the FPOPOL3 (bit 26), FPOPOL2 (bit 19), FPOPOL1 (bit 12) and FPOPOL0 (bit 5) in the Output Clock
Control Register (OCCR). The signals can be adjusted to provide positive clocks with the setting of the CKOPOL3
(bit 25), CKOPOL2 (bit 18), CKOPOL1 (bit 11) and CKOPOL0 (bit 4) in the Output Clock Control Register (OCCR).
The output clocks use the CKO3SRC1 - 0 (bits 22 - 21), CKO2SRC1 - 0 (bits 15 - 14), CKO1SRC1 - 0 (bits 8 - 7)
and CKO0SRC1- 0 (bits 1 - 0) in the Output Clock Control Register (OCCR) to set their timing reference to either
the internal clock or one of the three input clock signals. If the input clocks are selected as the reference source, the
output clock can not be programmed to generate a higher clock frequency than the reference source. As each
output timing pair has its own bit settings, they can be set to provide different output timing.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
4.0 Output Channel Control
To be able to interface with external buffers, the output signals can be set to enter a high impedance or drive high
state on a per-channel basis. The Per Channel Function (bits 31 - 29) in the Connection Memory Bits can be set to
001 to drive the channel output high or to any one of the following, 000, 110 or 111, to set the channel into a high
impedance state.
5.0 Data Input Delay and Data Output Advancement
The Group Control Register (SCR) is used to adjust the input delay and output advancement for each input and
output data groups. Each group is independently programmed.
5.1 Input Sampling Point Delay Programming
The input sampling point delay programming feature provides users with the flexibility of handling different wire
delays when incoming traffic is from different sources.
By default, all input streams have zero delay, such that bit 7 is the first bit that appears after the input frame
boundary (Assuming ST-BUS formatting). The nominal input sampling point with zero delay is at the 3/4 bit time.
The input delay is enabled by the Input Sample Point Delay (bit 8 - 4) in the Group Control Register0 - 31 (SCR0 -
31) as described in Section 15.0 on page 34. The input sampling point delay can range from 0 delay to 7 3/4 bit
delay with a 1/4 bit resolution on a per group basis.
Nominal Channel n Boundary
Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7
6
00000 (Default)
00001
00010
11111
11110
11101
00011
00100
11100
11011
00101
00110
00111
01000
01001
11010
11001
11000
10111
10110
01010
01011
10101
10100
01100
01101
01110
01111
10011
10010
10001
10000
Example: With a setting of 01111 the sampling point will be 3 1/2 bits
Figure 2 - Input Sampling Point Delay Programming
There are limitations when the ZL50074 is programmed to use CKi0 as the input stream clock source as opposed
to the internal clock:
•
•
The granularity of the delay becomes 1/2 the selected reference clock period, or 1/4 bit, whichever is longer.
If the selected reference clock frequency is the same as the stream bit rate, the granularity of the delay is 1/2 bit.
In this case, the least significant bit of the ISPD register is not used; the remaining 4 bits select the total delay in
1/2 bit increments, to a maximum of 7 1/2 bits. Also, the 0 bit delay reference point changes from the 3/4 bit
position to the 1/2 bit position.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
5.2 Fractional Bit Advancement on Output
See Section 15.0, Group Control Registers, for programming details.
This feature is used to advance the output data of groups with respect to the output frame boundary. Each group
has its own bit advancement value which can be programmed in the Group Control Register0 - 31 (SCR0 - 31).
By default all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (Assuming ST-BUS formatting). The output advancement is enabled by the Output Stream Bit
Advancement (bits 21 - 20) of the Group Control Register0 - 31 (SCR0 - 31) as described in Section 15.0, Group
Control Registers. The output delay can vary from 0 to 22.8 ns with a 7.6 ns increment. The exception to this is
when the device is programmed at 65 Mbps, in which case the increment is 3.8 ns with a total advancement of
11.4 ns.
Nominal 8 MHz
Clock
Nominal 16 MHz
Clock
Nominal 32/65 MHz
Clock
Nominal Output
Bit Timing
OSBA = 00
OSBA = 01
7.6 ns (~3.8 ns at 65 Mbps)
15.2 ns (~7.6 ns at 65 Mbps)
Level 1
Advance
Level 2
Advance
OSBA = 10
OSBA = 11
22.8 ns (~11.4 ns at 65 Mbps)
Level 3
Advance
Figure 3 - Output Bit Advance Timing
This programming feature is provided to assist in designs where per stream routing delays are significant and
different.
The OSBA bits, in the Group Control Registers, are used to set the bit-advance for each of the corresponding serial
output streams. Figure 3 illustrates the effect of the OSBA settings on the output timing.
There are limitations when the ZL50074 are programmed to use CKi0 as the output stream clock source:
•
If the selected reference clock frequency is 65 MHz or 32 MHz, the granularity of the advance is reduced to
1/2 the clock period.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
•
If the selected reference clock frequency is 16 MHz or 8 MHz, bit advancement is not available and the
output streams are driven at the nominal times.
6.0 Message Mode
In Message Mode (MSG), microprocessor data can be broadcast to the output data streams on a per-channel
basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.
For a given output channel, when the corresponding Per Channel Function (bits 31 - 29) in the Connection Memory
Bits are set to Message Mode (010), the ZL50074 writes the Connection Address (bits 7 - 0) of the Connection
Memory, in the outgoing timeslot. Refer to Section 12.1, Connection Memory Bit Functions, for programming
details.
6.1 Data Memory Read
All TDM input channels can be read via the microprocessor port. This feature is useful for receiving control and
status information from external circuits or other TDM devices. Each 32 bit Data Memory access enables up to four
consecutive input channels to be monitored. The Data Memory field is read only, any attempt to write to this
address range will result in a bus error condition signalled back to the host processor. Refer to Section 14.0, Data
Memory, for programming details.
The latency of data reads is up to 3 frames, depending on when the input timeslots are sampled.
6.2 Connection Memory Block Programming
See Section 15.3, Block Init Register, and Section 15.4, Block Init Enable Register, for programming details.
This feature allows for fast initialization of the connection memory after power up. When the block programming
mode is enabled, the contents of Block Init Register are written to all Connection Memory Bits. This operation
completes in one 125 µs frame. During Connection Memory initialization, all TDM output streams are set to high
impedance.
7.0 Data Delay Through the Switching Paths
See Section 12.1, Connection Memory Bit Functions, for programming details.
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
In wideband data application, constant delay maintains the frame integrity of the information through the switch.
The delay though the switch is 2 frames - Input Channel + Output Channel. This can result in a minimum delay of 1
frame + 1 channel if the last channel of a stream is switched to the first channel of a stream. The maximum delay is
1 channel short of 3 frames delay. This occurs when the first channel of a stream is switched to the last channel of
a stream.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (n) and
output channel number (m). The data throughput delay (T) is:
T = 2 frames + (n - m)
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2 CH3
N-2 N-1 CH0 CH1 CH2CH3
N = Last Channel
N-2 N-1 CH0CH1 CH2CH3
N-2 N-1 CH0 CH1CH2 CH3
Figure 4 - Data Throughput Delay
8.0 Microprocessor Port
The ZL50074 has a generic microprocessor port that provides access to the internal Data Memory (read access
only), Connection Memory and the Control Registers.
The port size can be configured to be either 32 bit or 16 bit, controlled by the D16B pin.
The port works with either Motorola or Intel type microprocessor buses, selected by the IM pin.
8.1 Addressing
The Data Memory, Connection Memory and Control Registers are assigned 32 bit fields in the ZL50074 memory
space. The Address Bus, A18 - 0, controls access to each 32 bit location. Byte addressing is also provided to give
the user programming flexibility, if access to less than 32 bits is required.
Each 32 bit memory or register location spans four consecutive addresses. Example:
•
The 32 bit Group Control Register for TDM Stream 0 is located at address range 40200 - 40203 Hex
The Least Significant address identifies the Most Significant Byte (MSB) in the 32 bit field, see Table 5.
Address (Hex)
Memory/Register Bits
40200
40201
40202
40203
Bits 31:24 (MSB)
Bits 23:16
Bits 15:8
Bits 7:0 (LSB)
Table 5 - Example of Address and Byte Significance
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
8.2 32 bit Bus Operation
In 32 bit mode (D16B = 0), all 32 bits of the Data Bus, D31 - 0, may be used for write and read transfers. D31 on the
bus maps to Bit 31 of the internal memory or register, D30 maps to Bit 30, etc. The least significant address bits, A1
- 0, and the Data Transfer Size inputs, SIZ0 - 1, identify which bytes are being accessed.
In Motorola Bus mode (IM = 0), A1 - 0 identify the first byte in the 32 bit field to be transferred, see Table 6. The
SIZ0 - 1 inputs, indicate the access transfer size, as shown in Table 7.
A1
A0
Byte Addressed
0
0
1
1
0
1
0
1
Bit 31:24
Bit 23:16
Bit 15:8
Bit 7:0
Table 6 - 32 bit Motorola Mode Byte Addressing
For example, to transfer all 32 bits in a single access: A1 = 0. A0 = 0, SIZ1 = 0, SIZ0 = 0. To transfer D15 - 8 only:
A1 = 1, A0 = 0, SIZ1 = 0, SIZ0 = 1.
SIZ1
SIZ0
Access Transfer Size
0
0
1
1
0
1
0
1
4 bytes
1 Byte
2 Bytes
3 Bytes
Table 7 - 32 bit Motorola Mode Access Transfer Size
In Intel Bus Mode (IM = 1), A1 - 0, and SIZ1 - 0 form active low byte enable signals, consistent with BE3 - 0
available on the Intel i960 processor, see Table 8.
Equivalent
i960 Signal
Byte
Pin
Addressed
A1
A0
BE3
BE2
BE1
BE0
Bit 31:24
Bit 23:16
Bit 15:8
Bit 7:0
SIZ1
SIZ0
Table 8 - 32 bit Intel Mode Bus Enable Signals
Byte addressing applies only to write accesses. On read cycles, all 32 bits are output on every access.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
8.3 16 bit Bus Operation
In 16 bit mode (D16B = 1). D15 - 0 are used for data transfers to/from the ZL50074. D31 - 16 are unused and must
be connected to a defined logic level. D15 on the bus maps to Bit 31 and Bit 15 of the internal 32 bit memory or
register, D14 maps to Bit 30 and Bit 14, etc.
In 16 bit mode, the least significant address bit, A0, is not used, and must be connected to defined logic level. In this
case, address bit A1 and the Data Transfer Size inputs, SIZ1 - 0, identify which bytes are being accessed.
In Motorola Bus Mode (IM = 0), SIZ1 - 0 form active low data strobe signals, consistent with UDS and LDS available
on the MC68000 and MC68302 processors, see Table 9
In Intel Bus Mode (IM = 1), SIZ1 - 0 form active low byte enable signals, consistent with BE1 and BE0 available on
the Intel i960 processor as shown in Table 9.
Motorola Mode
Intel Mode i960 Equivalent
MC68000, MC68302
Pin Name
Function
IM = 1
Data Bus Bytes Enabled
Equivalent Function
IM = 0
SIZ1
SIZ0
UDS
LDS
BE1
BE0
D15-8
D7-0
Table 9 - Byte Enable Signals
In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory.
A1 = 0
A1 = 1
Bits 31:16
Bits 15:0
16-bit word alignment are shown in Table 10. An example of byte addressing is given in Table 11.
Microprocessor
16 bit Data Bus
Internal 32-bit Memory
SIZ1
SIZ0
A1
or Register
D15 - 8
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
0
1
Bits 31:24
Bits 15:8
Bits 23:16
Bits 7:0
D7 - 0
D15 - 0
Bits 31:16
Bits 15:0
No access
1
X
Table 10 - 16 bit Mode Word Alignment
1. X - Don’t Care
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Address
(Hex)
Register
Register
Byte
A18 - 0 (binary)
SIZ1 SIZ0
Comments
Description
40200 or
Stream Control
Register (Group 0)
Bits 23:16
Bits 15:8
Bits 15:0
Bits 31:16
100 0000 0010 0000
000X
1
0
0
0
0
1
0
0
8 bit transfer
†
40201
40282 or
40283
Input Clock Control
Register
100 0000 0010 1000
8 bit transfer
16 bit transfer
16 bit transfer
†
001X
40286 or
40287
Output Clock
Control Register
100 0000 0010 1000
†
011X
40284 or
40285
Output Clock
Control Register
100 0000 0010 1000
†
010X
Table 11 - 16 bit Mode Example Byte Address
† Don’t Care. A0 is not used
8.4 Bus Operation
8.4.1 Read Cycle
The operation of a read cycle is illustrated in Figure 5.
•
The microprocessor asserts the R/W control signal high, to signal a read cycle. It also drives the address A,
transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50074.
•
The microprocessor then drives the DS signal active low, to signal the start of the bus cycle. The DS signal
is held low for the duration of the bus cycle.
•
•
WAIT is asserted active low
The ZL50074 accesses the requested memory or register location(s), and places the requested data onto
the data bus, D31 - 0 (D15 - 0 in 16 bit Mode). All data bus pins are driven, whether or not they are being
used for the specific data transfer. Unused pins will present unknown data. If the address is to an unused
area of the memory space, unknown data is presented on the data bus.
•
•
•
•
The ZL50074 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal, it terminates the bus
cycle by driving the DS pin inactive high
When the ZL50074 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50074 sees the CS signal go inactive high, it tri-states the data bus, D31 - 0 (D15 - 0 in 16 bit
Mode) and the DTA and BERR signals. However, if CS goes inactive high before DS goes inactive high, the
DTA and BERR signals are driven inactive high before they are tri-stated.
•
In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Address A,
SIZ1 - 0
CS
R/W
DS
Hi-Z
Data
Hi-Z
DTA
BERR
WAIT
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Figure 5 - Read Cycle Operation
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
8.4.2 Write Cycle
The operation of the write cycle is illustrated in Figure 6.
•
The microprocessor asserts the R/W control signal low, to signal a write cycle. It also drives the address A,
data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50074
•
The microprocessor then drives the data bus, D31 - 0 (D15 - 0 in 16 bit Mode) with the data to be written,
and then drives the DS signal active low, to signal the start of the bus cycle. The DS signal is held low for the
duration of the bus cycle
•
•
WAIT is asserted active low
The ZL50074 transfers the data presented on the data bus pins into the indicated memory or register
location(s). If the address is to an unused area of the memory space, or to the data memory, no data is
transferred. The microprocessor port cannot write to the Data Memory.
•
•
•
•
The ZL50074 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal, it terminates the bus
cycle by driving the DS pin inactive high
When the ZL50074 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50074 sees the CS signal go inactive high, it tri-states the DTA and BERR signals. However, if
CS goes inactive high before DS goes inactive high, the DTA and BERR signals are driven inactive high
before they are tri-stated.
•
In Intel mode, DTA is always driven to signal the end of a bus cycle, regardless of BERR
Address
SIZ1 - 0
CS
R/W
DS
Data
DTA
Hi-Z
BERR
WAIT
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Figure 6 - Write Cycle Operation
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Zarlink Semiconductor Inc.
ZL50074
9.0 Power-up and Initialization of the ZL50074
9.1 Device Reset and Initialization
Data Sheet
The PWR pin is used to reset the ZL50074. When this pin is low, the following functions are performed:
•
•
•
•
Asynchronously puts the microprocessor port in a reset state
Tristates all of the output streams (SToA0 - 31, SToB0 - 31, SToC0 - 31, SToD0 - 31)
Preloads all of the registers with their default values (refer to the individual registers for default values)
Clears all internal counters
9.2 Power Supply Sequencing
The ZL50074 has two separate power supplies: V
(3.3V) and V
(1.8V). The recommended power-up
DD_IO
DD_CORE
sequence is for V
to be applied first, followed by the V
supply. V
should not lead V
DD_CORE DD_IO
DD_IO
DD_CORE
supply by more than 0.3V. Both supplies may be powered-down simultaneously.
9.3 Initialization
Upon power up, the ZL50074 should be initialized as follows:
•
•
•
•
Assert PWR to low immediately after power is applied
Set the TRST pin low to disable the JTAG TAP controller
Deassert the PWR pin.
Apply the Master Clock Input (CKi0) and Master Frame Pulse Input (FPi0) to the values defined by the
CK_SEL1 - 0 pins
Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes
approximately 1ms for the internal initialization to complete
•
•
•
Automatic block initialization of the Connection Memory to all zeros occurs, without microprocessor
intervention
All Group Control Registers are preset to 000C000C , corresponding to no link inversions, no fractional
H
output bit advancements, internal clock source, and no input sample point delays
The Input Clock Control Register is preset to 0DB , corresponding to:
H
-
-
-
All clock inputs set to negative logic sense
All frame pulse inputs set to negative logic sense
All input frame pulses set to ST-BUS timing
•
The Output Clock Control Register is pre-set to 060D1C3C , corresponding to:
H
-
-
-
-
-
All clock outputs set to negative logic sense
All frame pulse outputs set to negative logic sense
All output frame pulses set to ST-BUS timing
All output clock source selections to internal
Clock outputs, CKo0 - 3 are preset to rates of 65MHz, 32MHz, 16MHz and 8MHz, respectively
•
Global Bit Rate Register is set to 00, corresponding to a bit rate of 8 Mbps
Note: If the master clock input, CKi0, is not available, the microprocessor port will assert BERR on all accesses and
read cycles.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
10.0 IEEE 1149.1 Test Access Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE 1149.1 (JTAG) standard. The
operation of the boundary-scan circuity is controlled by an external Test Access Port (TAP) Controller.
The ZL50074 uses the public instructions defined in IEEE 1149.1, with the provision of a 16-bit Instruction Register,
and three scannable Test Data Registers: Boundary Scan Register, Bypass Register and Device Identification
Register.
10.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50074 test functions. The interface consists of four input and one
output signal. as follows:
•
Test Clock (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out
of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
•
•
Test Mode Select (TMS) - The TAP Controller uses the logic signals received at the TMS input to control
test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally
pulled to V
when it is not driven from an external source.
DD_IO
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to V
when it is not driven from an external source.
DD_IO
•
•
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDo driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to V
when it is not
DD_IO
driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation.
The TAP signals are only applied when the ZL50074 is required to be in test mode. When in normal, non-test mode,
TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected.
10.2 Instruction Register
The ZL50074 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG interface contains a
sixteen bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the
TAP controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic
functions: to select the test data register that may operate while the instruction is current and to define the serial test
data register path that is used to shift data between TDi and TDo during register scanning.
26
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
10.3 Test Data Register
As specified in the IEEE 1149.1 standard, the ZL50074 JTAG Interface contains three test data registers:
•
•
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50074 core logic
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo
The Device Identification Register - The JTAG device ID for the ZL50074 is C39A14B
H
Version
<31:28>
<27:12>
<11:1>
<0>
0000
Part Number
Manufacturer ID
LSB
1100 0011 1001 1010
0001 0100 101
1
10.4 Boundary Scan Description Language (BSDL)
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
11.0 Memory Map of ZL50074
The memory map for the ZL50074 is given in Table 12.
Address (Hex)
Description
00000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 401FF
40200 - 4027F
40280 - 40283
40284 - 40287
40288 - 4028B
4028C - 4028F
40290 - 40293
40294 - 7FFFF
Connection Memory
Invalid Address. Access causes Bus error (BERR)
Data Memory: Read only; Bus error on write (BERR)
Invalid Address. Access causes Bus error (BERR)
Group Control Registers
Input Clock Control Register
Output Clock Control Register
Block Init Register
Block Init Enable
Global Rate Control Register
Invalid Address. Access causes Bus error (BERR)
Table 12 - Memory Map
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
12.0 Connection Memory
Address range 00000 - 1FFFF hex.
On power-up, all Connection Memory locations are initialized automatically to 00000000 , using the Block
H
Initialization feature, see Section 15.3 and Section 15.4.
The 32 bit Connection Memory has 32,768 locations. Each 32 bit long-word is used to program the desired source
data and any other per-channel characteristics of one output time-slot.
The memory map for the Connection Memory is sub-divided into 32 blocks, each corresponding to one of the
possible 32 output stream group numbers. The address ranges for these blocks are illustrated in Table 13.
Start
Address
(Hex)
Start
Address
(Hex)
Output
Group
Address Range
(Hex)
Output
Group
Address Range
(Hex)
0
1
000000
001000
002000
003000
004000
005000
006000
007000
008000
009000
00A000
00B000
00C000
00D000
00E000
00F000
000000 - 000FFF
001000 - 001FFF
002000 - 002FFF
003000 - 003FFF
004000 - 004FFF
005000 - 005FFF
006000 - 006FFF
007000 - 007FFF
008000 - 008FFF
009000 - 009FFF
00A000 - 00AFFF
00B000 - 00BFFF
00C000 - 00CFFF
00D000 - 00DFFF
00E000 - 00EFFF
00F000 - 00FFFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
010000
011000
012000
013000
014000
015000
016000
017000
018000
019000
01A000
01B000
01C000
01D000
01E000
01F000
010000 - 010FFF
011000 - 011FFF
012000 - 012FFF
013000 - 013FFF
014000 - 014FFF
015000 - 015FFF
016000 - 016FFF
017000 - 017FFF
018000 - 018FFF
019000 - 019FFF
01A000 - 01AFFF
01B000 - 01BFFF
01C000 - 01CFFF
01D000 - 01DFFF
01E000 - 01EFFF
01F000 - 01FFFF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 13 - Connection Memory Stream Control Mapping
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
The control of each output stream group, SToAn, SToBn, SToCn and SToDn depends on the programmed Global
Bit Rate Register. The address offset range for each group is illustrated in Table 14.
Output Group Data Rate
Timeslot Range
Output Stream
Stream Address Offset Range (Hex)
65 Mbps
0 - 1023
SToAn
SToBn, Cn, Dn
SToAn
00000 - 00FFF
N/A
32 Mbps
16 Mbps
0 - 511
0 - 255
00000 - 007FF
00800 - 00FFF
N/A
SToBn
SToCn, Dn
SToAn
00000 - 003FF
00400 - 007FF
00800 - 00BFF
00C00 - 00FFF
00000 - 001FF
00200 - 003FF
00400 - 005FF
00600 - 007FF
00800 - 00FFF
SToBn
SToCn
SToDn
8 Mbps
0 - 127
SToAn
SToBn
SToCn
SToDn
N/A
BERR
Table 14 - Output Control at Various Output Rates
The address range for a particular stream is given by adding the group start address, as indicated in Table 14, to
the appropriate stream offset range, as indicated in Table 15. For example, the Connection Memory address range
for SToB12 operating at 32 Mbps, is 00C800-00CFFF.
Control of each channel timeslot within each stream, offset timeslot number, timeslot address offset, range of 4
addresses is shown in the table below.
Timeslot
Address
Offset hex
SToAn
SToBn
SToCn
SToDn
0
1
0
1
0
1
0
1
000
004
008
-
2
2
2
2
-
-
-
-
126
127
128
129
-
126
127
128
129
-
126
127
128
129
-
126
127
128
129
-
1F8
1FC
200
204
-
254
255
256
254
255
256
254
255
254
255
3F8
3FC
400
Table 15 - Stream Offset Range
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Timeslot
Address
Offset hex
SToAn
SToBn
SToCn
SToDn
257
-
257
-
404
-
-
-
510
511
512
513
-
510
511
7F8
7FC
800
804
-
1021
1022
1023
FF4
FF8
FFC
Table 15 - Stream Offset Range (continued)
12.1 Connection Memory Bit Functions
The bit functions of the connection memory are illustrated in Table 16.
External Read/Write Address: 000000H
Reset Value: 0000H
31
30
29
28
V/D
12
27
26
25
24
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
PCF
2
PCF
1
PCF
0
ICL
1
ICL
0
OCL
1
OCL
0
15
0
14
13
11
10
9
8
7
6
5
4
3
2
1
0
GR
4
GR
3
GR
2
GR
1
GR
0
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH 1
ST1
CH 0
ST0
Bit
Name
PCF2 - 0
Description
31 - 29
Per Channel Function
PCF2 - 0
Function
Description
000
001
010
011
100
101
110
111
OT
FH
Output is tri-stated
Output drives high always
Output is in message mode
MSG
VAR
CD
Connection is in variable delay mode
Connection is in constant delay mode
PRBS Generator
PRBS
OT
Output is tri-stated
OT
Output is tri-stated
28 - 15
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
Table 16 - Connection Memory Bits (CMB)
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 000000H
Reset Value: 0000H
31
30
29
28
V/D
12
27
26
25
24
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
PCF
2
PCF
1
PCF
0
ICL
1
ICL
0
OCL
1
OCL
0
15
0
14
13
11
10
9
8
7
6
5
4
3
2
1
0
GR
4
GR
3
GR
2
GR
1
GR
0
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH 1
ST1
CH 0
ST0
Bit
Name
Description
14 - 10
9 - 0
GR4 - 0
CH9 - 0
Group Selection. These bits define the input/source serial stream number (31 - 0).
Channel Selection. These bits define the input/source channel number, depending on
the data rate. For 65.536 Mbps bits 9 - 0 are used to access the 1024 channels.
For 32.768 Mbps bits 9 - 1 are used to access the 512 channels. Bit 0 is used to select
stream ‘A’ (0) or stream ‘B’ (1)
For 16.869 Mbps bits 9 - 2 are used to access the 256 channels. Bits 1 - 0 are used to
select stream ‘A’ (00), ‘B’ (01), ‘C’ (10) or ‘D’ (11)
For 8.192 Mbps bits 9 - 3 are used to access the 128 channels. Bit 2 MUST be set to 0.
Bits 1 - 0 are used to select stream ‘A’ (00), ‘B’ (01), ‘C’ (10) or ‘D’ (11)
Table 16 - Connection Memory Bits (CMB) (continued)
13.0 Connection Memory LSB
The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the
output data for a stream in message mode. In this memory address range, all of the connection memory least
significant bytes (bits 7 - 0) are available for read/write in consecutive address locations. This feature is provided for
programming convenience. It can allow higher programming bandwidth on message mode streams. For example,
one longword access to this memory space can read or set the message bytes in four consecutive connection
memory locations. Access to this memory space is big-endian, with the most significant bytes on the data bus
accessing the lower address of the connection memory. Addressing into each of the streams is illustrated in Table
17.
Start
Address
(Hex)
Start
Address
(Hex)
Output
Group
Address Range
(Hex)
Output
Group
Address Range
(Hex)
0
1
2
3
4
5
6
7
8
9
020000
020400
020800
020C00
021000
021400
021800
021C00
022000
022400
020000 - 0203FF
020400 - 0207FF
020800 - 020BFF
020C00 - 020FFF
021000 - 0213FF
021400 - 0217FF
021800 - 021BFF
021C00 - 021FFF
022000 - 0223FF
022400 - 0227FF
16
17
18
19
20
21
22
23
24
25
024000
024400
024800
024C00
025000
025400
025800
025C00
026000
026400
024000 - 0243FF
024400 - 0247FF
024800 - 024BFF
024C00 - 024FFF
025000 - 0253FF
025400 - 0257FF
025800 - 025BFF
025C00 - 025FFF
026000 - 0263FF
026400 - 0267FF
Table 17 - Connection Memory LSB Stream Control Mapping
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Start
Address
(Hex)
Start
Address
(Hex)
Output
Group
Address Range
Output
Group
Address Range
(Hex)
(Hex)
10
11
12
13
14
15
022800
022C00
023000
023400
023800
023C00
022800 - 022BFF
022C00 - 022FFF
023000 - 0233FF
023400 - 0237FF
023800 - 023BFF
023C00 - 023FFF
26
27
28
29
30
31
026800
026C00
027000
027400
027800
027C00
026800 - 026BFF
026C00 - 026FFF
027000 - 0273FF
027400 - 0277FF
027800 - 027BFF
027C00 - 027FFF
Table 17 - Connection Memory LSB Stream Control Mapping
Output Group Data Rate
Timeslot Range
Output Stream
Stream Address Offset Range (Hex)
65 Mbps
0 - 1023
SToAn
SToBn, Cn, Dn
SToAn
00000 - 003FF
N/A
32 Mbps
16 Mbps
0 - 511
0 - 255
00000 - 001FF
00200 - 003FF
N/A
SToBn
SToCn, Dn
SToAn
00000 - 000FF
00100 - 001FF
00200 - 002FF
00300 - 003FF
00000 - 0007F
00080 - 000FF
00100 - 0017F
00180 - 001FF
00200 - 003FF
SToBn
SToCn
SToDn
8 Mbps
0 - 127
SToAn
SToBn
SToCn
SToDn
N/A
BERR
Table 18 - Connection Memory LSB Output Group Control
Within each stream group, the control of each of the actual output groups depends on the output rate programmed
into the Group Control Registers. The address offsets to these control areas for each of the four output groups are
illustrated in Table 18.
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
14.0 Data Memory
The data memory field is a read only address range used to monitor the data being received by the input streams.
Addressing into each of the streams is illustrated in Table 19.
Start
Address
(Hex)
Start
Address
(Hex)
Input
Address Range
(Hex)
Input
Address Range
(Hex)
Group
Group
0
1
028000
028400
028800
028C00
029000
029400
029800
029C00
02A000
02A400
02A800
02AC00
02B000
02B400
02B800
02BC00
028000 - 0283FF
028400 - 0287FF
028800 - 028BFF
028C00 - 028FFF
029000 - 0293FF
029400 - 0297FF
029800 - 029BFF
029C00 - 029FFF
02A000 - 02A3FF
02A400 - 02A7FF
02A800 - 02ABFF
02AC00 - 02AFFF
02B000 - 02B3FF
02B400 - 02B7FF
02B800 - 02BBFF
02BC00 - 02BFFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
02C000
02C400
02C800
02CC00
02D000
02D400
02D800
02DC00
02E000
02E400
02E800
02EC00
02F000
02F400
02F800
02FC00
02C000 - 02C3FF
02C400 - 02C7FF
02C800 - 02CBFF
02CC00 - 02CFFF
02D000 - 02D3FF
02D400 - 02D7FF
02D800 - 02DBFF
02DC00 - 02DFFF
02E000 - 02E3FF
02E400 - 02E7FF
02E800 - 02EBFF
02EC00 - 02EFFF
02F000 - 02F3FF
02F400 - 02F7FF
02F800 - 02FBFF
02FC00 - 02FFFF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 19 - Data Memory Stream Control Mapping
Within each stream group, the mapping of each of the actual input groups, STiA, STiB, STiC and STiD, depends on
the device data rate programmed into the Global Control Register. The address offsets to these data areas for each
of the input groups is illustrated in Table 20.
Input Group Data Rate Time-slot Range
Output Streams
Address Offset Range (Hex)
65 Mbps
0 - 1023
SToAn
SToBn
SToCn
SToDn
SToAn
SToBn
SToCn
SToDn
00000 - 003FF
N/A
N/A
N/A
32 Mbps
0 - 511
00000 - 001FF
00200 - 003FF
N/A
N/A
Table 20 - Data Memory Stream Access
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Input Group Data Rate Time-slot Range
Output Streams
Address Offset Range (Hex)
16 Mbps
0 - 255
0 - 127
N/A
SToAn
SToBn
SToCn
SToDn
SToAn
SToBn
SToCn
SToDn
BERR
00000 - 000FF
00100 - 001FF
00200 - 002FF
00300 - 003FF
00000 - 0007F
00080 - 000FF
00100 - 0017F
00180 - 001FF
00200 - 003FF
8 Mbps
Table 20 - Data Memory Stream Access
The address ranges for the data memory portion corresponding to each of the actual input groups, STiA, STiB,
STiC and STiD for any particular input stream number is calculated by adding the Start Address for the particular
stream, as indicated in Table 19, to the appropriate Address Offset Range, as indicated in Table 20. The time-slots
map linearly into the appropriate address offset range. (i.e. timeslots 0, 1, 2, ... map into addresses 00000, 00001,
00002, ...)
The entire data memory is a read only structure. Any write attempts will result in a bus error. BERR is driven active
low to terminate the bus cycle.
15.0 Group Control Registers
The ZL50074 addresses the issues of a simple programming model and automatic stream configuration, by
defining a basic switching bit rate of 65.536 Mbps, and by grouping the I/O streams depending on the rate they are
programmed.
The Group Control Registers are provided for setting the operating characteristics of the TDM input and output
streams. All of the Group Control Registers are mapped long-word aligned on 32 bit boundaries in the memory
space. Each of the 32 registers is used to control one stream. The mapping of the Group Control Registers to the
I/O stream numbers is illustrated in Table 21. The bit functions of each of the Group Control Registers are illustrated
in Table 22.
TDM Group
Group Control Register Address (Hex)
0
1
40200-40203
40204-40207
40208-4020B
4020C-4020F
:
2
3
:
:
:
29
30
31
40274-40277
40278-4027B
4027C-4027F
Table 21 - Group Control Register Addressing
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
OSI
6
21
20
19
18
17
16
OSBA
1
OSBA
0
OSBR
1
OSBR
0
OSSCR
1
OSSCR
0
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD1
ISPD0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
Bit
Name
Description
31 - 23
22
Unused
OSI
Reserved. In normal functional mode, these bits MUST be set to zero.
Output Stream Invertion
For normal operation, this bit is set low.
To invert the output stream, set this bit high.
21 - 20
OSBA1 - 0
Output Stream Bit Advancement
OSBA1 - 0
Non-65 Mbps
65 Mbps
00
01
10
11
0 ns
0 ns
3.8 ns
7.6 ns
11.4 ns
7.6 ns
15.2 ns
22.8 ns
19 - 18
17 - 16
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
OSSRC1 - 0 Output Stream Clock Source Select
OSSRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
15 - 10
9
Unused
ISI
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream Invertsion
For normal operation, this bit is set low.
To invert the input stream, set this bit high.
8 - 4
3 - 2
ISPD4 - 0
Unused
Input Sampling Point Delay
Default Sampling Point is 3/4. Adjust according to Figure 2 on page 16.
Reserved. In normal functional mode, these bits MUST be set to zero.
Table 22 - Group Control Register
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40200H - 4027FH
Reset Value: 000C000CH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
OSI
6
21
20
19
18
17
16
OSBA
1
OSBA
0
OSBR
1
OSBR
0
OSSCR
1
OSSCR
0
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
5
4
3
2
1
0
ISI
ISPD
4
ISPD
3
ISPD
2
ISPD1
ISPD0
ISBR
1
ISBR
0
ISSRC
1
ISSRC
0
Bit
Name
Description
1 - 0
ISSRC1 - 0
Input Stream Clock Source Select
ISSRC1 - 0
Input Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
Table 22 - Group Control Register (continued)
The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected
port for a maximum of 2 frames.
15.1 Input Clock Control Register
The Input Clock Control Register is used to select the logic sense of the input clock.
External Read/Write Address: 40280H
Reset Value: 0DBH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
GCIS
EL2
FPIPO
L2
CKIP
OL2
GCIS
EL1
FPIP
OL1
CKIP
OL1
GCIS
EL0
FPIP
OL0
CKIP
OL0
Bit
Name
Description
31 - 9
31 - 9
8
Unused
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
Reserved. In normal functional mode, these bits MUST be set to zero.
GCISEL2 GCI-Bus Selection
When this bit is low, FPi2 is set for ST-BUS mode.
When this bit is high, FPi2 is set for GCI-Bus mode.
Table 23 - Input Clock Control Register
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Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40280H
Reset Value: 0DBH
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
GCIS
EL2
FPIPO
L2
CKIP
OL2
GCIS
EL1
FPIP
OL1
CKIP
OL1
GCIS
EL0
FPIP
OL0
CKIP
OL0
Bit
Name
FPIPOL2 Frame Pulse Polarity Selection
Description
7
When this bit is low, FPi2 is set for positive.
When this bit is high, FPi2 is set for negative.
6
5
4
3
2
1
0
CKIPOL2 Clock Polarity Selection
When this bit is low, CKi2 is set for the positive clock edge.
When this bit is high, CKi2 is set for negative.
GCISEL1 GCI-Bus Selection
When this bit is low, FPi1 is set for ST-BUS mode.
When this bit is high, FPi1 is set for GCI-Bus mode.
FPIPOL1 Frame Pulse Polarity Selection
When this bit is low, FPi1 is set for the positive clock edge.
When this bit is high, FPi1 is set for negative.
CKIPOL1 Clock Polarity Selection
When this bit is low, CKi1 is set for the positive clock edge.
When this bit is high, CKi1 is set for negative.
GCISEL0 GCI-Bus Selection
When this bit is low, FPi0 is set for ST-BUS mode.
When this bit is high, FPi0 is set for GCI-Bus mode.
FPIPOL2 Frame Pulse Polarity Selection
When this bit is low, FPi0 is set for the positive clock edge.
When this bit is high, FPi0 is set for negative.
CKIPOL2 Clock Polarity Selection
When this bit is low, CKi0 is set for the positive clock edge.
When this bit is high, CKi0 is set for negative.
Table 23 - Input Clock Control Register (continued)
37
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
15.2 Output Clock Control Register
The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output
clocks. The bit functions of the Output Clock Control Register are illustrated in Table 24.
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
26
25
24
23
22
21
20
19
18
17
16
GCOSE FPOPOL CKOP CKO3RA
CKO3
RATE0
CKO3S CKO3S GCOSE FPOPOL CKOPO CKO2 CKO2R
L3
11
3
OL3
9
TE1
8
RC1
6
RC0
5
L2
4
2
3
L2
2
RATE1 ATE0
15
14
13
12
10
7
1
0
GCOS FPOPO CKOPO
CKO2S CKO2S GCOSE FPO CKOPO CKO1RA CKO1 CKO1SR
CKO1
SRC0
CKO0R CKO0R CKO0S CKO0S
ATE1 ATE0 RC1 RC0
EL0
L0
L0
RC1
RC0
L1
POL1
L1
TE1
RATE0
C1
Bit
Name
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
GCOSEL GCI-Bus Selection
31 - 28
27
Unused
3
When this bit is low, FPo3 is set for ST-BUS mode.
When this bit is high, FPo3 is set for GCI-Bus mode.
26
25
FPOPOL Frame Pulse Polarity Selection
When this bit is low, FPo3 is set for the positive clock edge.
When this bit is high, FPo3 is set for the negative clock edge.
3
CKOPOL Clock Polarity Selection
When this bit is low, CKo3 is set for the positive clock edge.
When this bit is high, CKo3 is set for the negative clock edge.
3
24 - 23
CKO3RA Output Clock Rate for CKo3 and FPo3
TE1 - 0
The output clock rate can not exceed the selected input clock rate. All rates are available
when the internal system clock is selected.
CKO3RATE1 - 0
CKo3
FPo3
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
Table 24 - Output Clock Control Register
38
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
26
25
24
23
22
21
20
19
18
17
16
GCOSE FPOPOL CKOP CKO3RA
CKO3
RATE0
CKO3S CKO3S GCOSE FPOPOL CKOPO CKO2 CKO2R
L3
11
3
OL3
9
TE1
8
RC1
6
RC0
5
L2
4
2
3
L2
2
RATE1 ATE0
15
14
13
12
10
7
1
0
GCOS FPOPO CKOPO
CKO2S CKO2S GCOSE FPO CKOPO CKO1RA CKO1 CKO1SR
CKO1
SRC0
CKO0R CKO0R CKO0S CKO0S
ATE1 ATE0 RC1 RC0
EL0
L0
L0
RC1
RC0
L1
POL1
L1
TE1
RATE0
C1
Bit
Name
Description
22 - 21
CKO3SR Output Clock Source for CKo3 and FPo3
C1 - 0
CKO3SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
20
19
GCOSEL GCI-Bus Selection
2
When this bit is low, FPo2 is set for ST-BUS mode.
When this bit is high, FPo2 is set for GCI-Bus mode.
FPOPOL Frame Pulse Polarity Selection
2
When this bit is low, FPo2 is set for the positive clock edge.
When this bit is high, FPo2 is set for the negative clock edge.
18
CKOPOL Clock Polarity Selection
When this bit is low, CKo2 is set for the positive clock edge.
When this bit is high, CKo2 is set for the negative clock edge.
2
17 - 16
CKO2RA Output Clock Rate for CKo2 and FPo2
TE1 - 0
The output clock rate can not exceed the selected input clock rate. All rates are available
when the internal system clock is selected.
CKO2RATE1 - 0
CKo2
FPo2
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
Table 24 - Output Clock Control Register (continued)
39
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
26
25
24
23
22
21
20
19
18
17
16
GCOSE FPOPOL CKOP CKO3RA
CKO3
RATE0
CKO3S CKO3S GCOSE FPOPOL CKOPO CKO2 CKO2R
L3
11
3
OL3
9
TE1
8
RC1
6
RC0
5
L2
4
2
3
L2
2
RATE1 ATE0
15
14
13
12
10
7
1
0
GCOS FPOPO CKOPO
CKO2S CKO2S GCOSE FPO CKOPO CKO1RA CKO1 CKO1SR
CKO1
SRC0
CKO0R CKO0R CKO0S CKO0S
ATE1 ATE0 RC1 RC0
EL0
L0
L0
RC1
RC0
L1
POL1
L1
TE1
RATE0
C1
Bit
Name
Description
15 - 14
CKO2SR Output Clock Source for CKo2 and FPo2
C1 - 0
CKO2SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
13
12
GCOSEL GCI-Bus Selection
1
When this bit is low, FPo1 is set for ST-BUS mode.
When this bit is high, FPo1 is set for GCI-Bus mode.
FPOPOL Frame Pulse Polarity Selection
1
When this bit is low, FPo1 is set for the positive clock edge.
When this bit is high, FPo1 is set for the negative clock edge.
11
CKOPOL Clock Polarity Selection
When this bit is low, CKo1 is set for the positive clock edge.
When this bit is high, CKo1 is set for the negative clock edge.
1
10 - 9
CKO1RA Output Clock Rate for CKo1 and FPo1
TE1 - 0
The output clock rate can not exceed the selected input clock rate. All rates are available
when the internal system clock is selected.
CKO1RATE1 - 0
CKo1
FPo1
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
Table 24 - Output Clock Control Register (continued)
40
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
26
25
24
23
22
21
20
19
18
17
16
GCOSE FPOPOL CKOP CKO3RA
CKO3
RATE0
CKO3S CKO3S GCOSE FPOPOL CKOPO CKO2 CKO2R
L3
11
3
OL3
9
TE1
8
RC1
6
RC0
5
L2
4
2
3
L2
2
RATE1 ATE0
15
14
13
12
10
7
1
0
GCOS FPOPO CKOPO
CKO2S CKO2S GCOSE FPO CKOPO CKO1RA CKO1 CKO1SR
CKO1
SRC0
CKO0R CKO0R CKO0S CKO0S
ATE1 ATE0 RC1 RC0
EL0
L0
L0
RC1
RC0
L1
POL1
L1
TE1
RATE0
C1
Bit
Name
Description
8 - 7
CKO1SR Output Clock Source for CKo1 and FPo1
C1 - 0
CKO1SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
6
5
GCOSEL GCI-Bus Selection
0
When this bit is low, FPo0 is set for ST-BUS mode.
When this bit is high, FPo0 is set for GCI-Bus mode.
FPOPOL Frame Pulse Polarity Selection
0
When this bit is low, FPo0 is set for the positive clock edge.
When this bit is high, FPo0 is set for the negative clock edge.
4
CKOPOL Clock Polarity Selection
When this bit is low, CKo0 is set for the positive clock edge.
When this bit is high, CKo0 is set for the negative clock edge.
0
3 - 2
CKO0RA Output Clock Rate for CKo0 and FPo0
TE1 - 0
CKO0RATE1 - 0
CKo0
FPo0
00
01
10
11
8.192 MHz
16.384 MHz
32.768 MHz
65.536 MHz
120 ns
60 ns
30 ns
15 ns
Table 24 - Output Clock Control Register (continued)
41
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
External Read/Write Address: 40284H
Reset Value: 060D1C3CH
31
0
30
0
29
0
28
0
27
26
25
24
23
22
21
20
19
18
17
16
GCOSE FPOPOL CKOP CKO3RA
CKO3
RATE0
CKO3S CKO3S GCOSE FPOPOL CKOPO CKO2 CKO2R
L3
11
3
OL3
9
TE1
8
RC1
6
RC0
5
L2
4
2
3
L2
2
RATE1 ATE0
15
14
13
12
10
7
1
0
GCOS FPOPO CKOPO
CKO2S CKO2S GCOSE FPO CKOPO CKO1RA CKO1 CKO1SR
CKO1
SRC0
CKO0R CKO0R CKO0S CKO0S
ATE1 ATE0 RC1 RC0
EL0
L0
L0
RC1
RC0
L1
POL1
L1
TE1
RATE0
C1
Bit
Name
Description
1 - 0
CKO0SR Output Clock Source for CKo0 and FPo0
C1 - 0
CKO0SRC1 - 0
Output Timing Source
00
01
10
11
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
Table 24 - Output Clock Control Register (continued)
15.3 Block Init Register
The Block Init Register is a 32 bit read/write register at address 040288 - 04028B .
H
The Block Init Register is used during block initialization of the connection memory. A block initialization
automatically occurs at power-up. However, it is possible to perform a block initialization at any time. During Block
Initialization, the value of the Block Init Register is copied to all connection memory locations in an operation that
runs in about 120 µs. If the Block Init Register is modified during a block initialization, the new value used is
ignored.
15.4 Block Init Enable Register
The Block Init Enable Register is a 32 bit read/write register at address 04028C - 04028F .
H
The Block Init Enable Register is used to initiate a block initialization of the connection memory. A block initialization
automatically occurs at power-up. Since the Block Init Register is cleared at power-up this automatic block
initialization will write all zeros to all Connection Memory Bits. However, it is possible to perform a block initialization
at any time. To begin a block initialization, 31415926 must be written to the Block Init Enable Register. If a block
H
initialization is signaled while one is in progress, the signal is ignored, and the currently active block initialization is
allowed to complete.
The value read back from the Block Init Enable Register is different than the value written. It represents both the
block initialization status, and the power-up reset initialization status. The meaning of the initialization status bits is
illustrated in Table 25. The bits 31 - 2 always read back 0.
42
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
Bit
Name
Description
0
Block Init Status
0 if Block initialization is completed;
1 if Block initialization is in progress.
1
Reset Init Status
0 if Reset initialization is completed;
1 if Reset initialization is in progress.
Table 25 - Block and Power-up Initialization Status Bits
Any access to the connection memory or the data memory during a block initialization or a reset initialization will
result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization.
15.5 Global Rate Control Register
On power-up, the GBR bits are both set to 0, corresponding to a rate of 8.192 Mbps.
External Read/Write Address: 040290 - 040293H
Reset Value: 0000H
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 1
GR1
CH 0
GR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
31 - 2
1 - 0
Unused
GBR
Reserved. In normal functional mode, these bits MUST be set to zero.
Global Bit Rate Selection
GBR 1 - 0
Input and Output Data Rate
00
01
10
8 Mbps - Group A, B, C and D
16 Mbps - Group A, B, C and D
32 Mbps - Group A and B, groups C and D outputs
are tristated
11
65 Mbps - Group A. group B outputs are tristated
43
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
Absolute Maximum Ratings - Voltages are with respect to ground (VSS) unless otherwise stated.
2
Characteristics
Sym
Min
Typ
Max
Unit
1
2
3
Chip I/O Supply Voltage
V
-0.5
-0.5
-0.5
5.0
5.0
V
V
V
DD_IO
Chip Core Supply Voltage
V
DD_CORE
Input Voltage (non-5 V tolerant inputs)
V
V
+
DD_IO
I_3V
0.5
4
5
6
7
Input Voltage (5 V tolerant inputs)
Continuous Current at digital outputs
Package power dissipation
Storage temperature
V
-0.5
7.0
15
V
mA
W
I_5V
I
o
P
2.1
D
T
- 55
+125
°C
S
Note 1: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 2: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
1
Characteristics
Operating Temperature
Sym
Min
Typ
Max
Unit
1
2
3
4
5
T
-40
1.71
3.0
0
25
1.8
3.3
+85
1.89
3.6
°C
V
OP
V
DD_CORE
Positive Supply Core
Positive Supply I/O
V
V
DD_IO
Input Voltage (non-5V tolerant inputs)
Input Voltage (5V tolerant inputs)
V
V
V
I_3V
DD_IO
V
0
5.5
I_5V
Note 1: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not
subject to production testing.
44
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
1
Characteristics
Sym
Min
Typ
Max
Unit
Test Conditions
2
1
2
Core Supply Current
I
500
62
mA
mA
uA
W
DD_CORE
I/O Supply Current
Leakage Current
I
Outputs unloaded
Outputs Unloaded
DD_IO
3
I
105
DDQ
4
Dynamic Power Dissipation
Input High Voltage
Input Low Voltage
P
1.2
DD
5
V
2.0
V
IH
6
V
0.8
5
V
IL
IL
3
7
Input Leakage (input pins)
I
µA
uA
µA
µA
pF
V
0≤<V ≤V
I
DD_IO
DD_IO
8
Input Leakage (bi-directional pins
Weak Pull-up Current
Weak Pull-down Current
Input Pin Capacitance
Output High Voltage
I
5
0≤<V ≤V
I
BL
9
I
I
-33
33
3
Input at 0V
Input at V
PU
PD
10
11
12
13
DD_IO
C
I
V
2.4
I
I
= 8mA
OH
OH
Output Low Voltage
V
0.4
V
= 8mA
OL
OL
1. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to
production testing.
2. SToA = 65 Mbps with random patterns. CKo0 = 65 MHz, CKo1 = 32 MHz
3. Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin).
1
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground
(VSS) unless otherwise stated.
Characteristics
CMOS Threshold
Sym
Level
Unit
Test Conditions
1
2
3
V
0.5 V
V
V
V
CT
DD_IO
DD_IO
DD_IO
Rise/Fall Threshold Voltage High
Rise/Fall Threshold Voltage Low
V
0.7 V
0.3 V
HM
V
LM
1. Characteristics are over recommended operating conditions unless otherwise stated.
45
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
AC Electrical Characteristics - FPi and CKi Timing
2
No.
Characteristic (Figure 7)
Sym
Min
Typ
Max
Units
Notes
1
2
3
FPi Input Frame Pulse Setup Time
FPi Input Frame Pulse Hold Time
t
3
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
FPIS
FPIH
CKIP
t
t
CKi Input Clock Period (average
value, does not consider the
effects of jitter)
15
30
60
120
4
15.26
30.5
61
15.5
31
65.536 MHz
32.768 MHz
16.384 MHz
8.192 MHz
62
122
124
4
5
6
CKi Input Clock High Time
CKi Input Clock Low Time
CKi Input Clock Rise/Fall Time
t
t
CKIH
t
4
CKIL
,
0
6
2
rCKI
t
fCKI
3
3
3
3
7
CKi Input Clock Cycle to Cycle
Variation
t
ns p-p Standard rating
STi at 65 Mbps
CVC
4
ns p-p Standard rating
STi at 32 Mbps
10
ns p-p Standard rating
STi at 16 Mbps
20
ns p-p Standard rating
STi at 8 Mbps
20%of
p-p
Extended rating.
With alternate
t
CKIP
4
clock source or
5
high CKi0 rate
1. Characteristics are over recommended operating conditions unless otherwise stated.
2. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to
production testing.
3. When using internal APLL clock source and the CKi0 frequency is less than or equal to the data rate.
4. When using input clock source CKi2-0 instead of the internal APLL clock source.
5. When using internal APLL clock source and the CKi0 frequency is higher than or equal to twice the data rate.
FPi
tFPIS
tFPH
tCKIP
tCKIH
tCKIL
CKi
trCKI
tfCKI
Input Frame Boundary
Figure 7 - Frame Pulse Input and Clock Input
46
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
AC Electrical Characteristics - FPi and CKi Skew
2
No.
Characteristic (Figure 8)
Sym
Min
Typ
Max
Units
Notes
1
CKi0 to CKi1, 2 Skew
t
-30
+30
ns
C 50pF
L
CKSK
Assume no jitter on input
clocks
1. Characteristics are over recommended operating conditions unless otherwise stated.
2. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to
production testing.
FPo
Note: FPo<k>/CKo<k> Clock Source = Internal
CKi0
Frame Boundary
tCKSK
tCKSK
CKi1, 2
Figure 8 - Frame Skew Timing Diagram
47
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
2
AC Electrical Characteristics - Serial Data Timing to CKi
3
4
No.
Characteristic (Figure 9)
Sym
Min
Typ
Max
Units
Notes
1
CKi to CKo Propagation Delay
t
3
12
ns
CKo clock source =
CKi
CKD
3
12
ns
CKo Clock source =
Internal 131MHz
APLL output
2
3
4
5
6
STi to posedge CKi setup
STi to posedge CKi hold
t
0
7.5
0
ns
ns
ns
ns
ns
SIPS
SIPH
SINS
SINH
t
t
STi to negedge CKi setup
STi to negedge CKi hold
Posedge CKi to Output Data Valid
t
7.5
3
5
t
12.5
SToA
SIPV
5
3
3
3
13
14
16
14
15
14
15
10
ns
ns
ns
ns
ns
ns
ns
ns
SToB, C, D
5
7
8
Negedge CKi to Output Data Valid
t
SToA
SINV
5
SToB, C, D
5
Posedge CKi to Output Data
tri-state
t
SToA
SIPZ
5
SToB, C, D
5
9
Negedge CKi to Output Data
tri-state
t
SToA
SINZ
5
SToB, C, D
10
ODE to Output Data tri-state
t
SToA
SOZ
5
C = 30pF, R = 1K
L
L
11
ns
SToB, C, D
5
C = 30pF, R = 1K
L
L
5
11
ODE to Output Data Enable
t
4.5
6
15
20
ns
ns
SToA
SOE
5
SToB, C, D
1. Characteristics are over recommended operating conditions unless otherwise stated.
2. Data Capture points vary with respect to CKi edge depending on clock rates & fractional delay settings.
3. All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi.
4. Loads on all serial outputs set to 30 pF
5. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to
production testing.
48
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
CKi
tCKD
CKo
tSIPS
tSIPH
STin
tSINS
tSINH
VALID DATA
STin
tSIPV
STon
STon
tSIPZ
tSINV
STon
tSINZ
STon
tSOE
tSOZ
ODE
Figure 9 - Serial Data Timing to CKi
49
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
2
AC Electrical Characteristics - Serial Data Timing to CKo
3
No.
Characteristic (Figure 10)
STi to posedge CKo setup
Sym
Min
Typ
Max
Units
Notes
1
2
3
4
5
tSOPS
tSOPH
tSONS
tSONH
tSOPV
7.5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STi to posedge CKo hold
STi to negedge CKo setup
STi to negedge CKo hold
7.5
0
Posedge CKo to Output Data Valid
SToA4
1
5
5
4
1
SToB, C, D
4
6
7
8
Negedge CKo to Output Data Valid
Posedge CKo to Output Data tri-state
Negedge CKo to Output Data tri-state
tSONV
tSOPZ
tSONZ
1
5
SToA
4
4
4
1
5
SToB, C, D
4
9
SToA
11
9
SToB, C, D
4
SToA
11
SToB, C, D
1. Data Capture points vary with respect to CKo edge depending on clock rates & fractional delay settings.
2. CKo output set to internal clock source.
3. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to
production testing
4. Loads on all serial outputs set to 30 pF
CKo
tSOPS
tSOPH
STin
STin
tSONS
tSONH
VALID DATA
tSOPV
STon
STon
tSOPZ
tSONV
STon
tSONZ
STon
Figure 10 - Serial Data Timing to CKo
50
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
AC Electrical Characteristics - Microprocessor Bus Interface
1
No
Characteristics (Figure 11, & Figure 12)
Sym
Min Typ
Max Units
Notes
tDSRE
tCSRE
tCSS
1
2
3
4
5
6
DS Recovery
5
0
0
0
0
0
ns
ns
ns
ns
ns
ns
CS Recovery
CS asserted setup to DS asserted
Address, SIZ0-1, R/W setup to DS asserted
CS hold from DS deasserted
tADS
tCSH
tADH
Address, SIZ0-1, R/W hold from DS
deasserted
tDSR
7
8
Data valid to DTA asserted on read
0
ns
C = 50pF,
L
2
R = 1k
L
tDZ
CS deasserted to Data tri-stated on read
5
ns
C = 50pF,
L
2
R = 1k
L
tWDS
tDHW
tWDD
9
Data setup to DS asserted on write
Data hold from DTA asserted on write
DS asserted to WAIT Asserted
0
0
ns
ns
ns
10
11
9
10
155
75
7
C = 50pF,
L
2
R = 1k
L
tAKS
12
13
WAIT deasserted to DTA/BERR asserted
skew
ns
ns
ns
ns
ns
ns
C = 50pF,
L
2
R = 1k
L
tAKD
DS asserted to DTA Asserted
35
50
Connection
Memory
All other
registers
tAKH
14
15
DS deasserted to DTA Deasserted
CS deasserted to DTA tri-stated
C = 30pF,
L
2
R = 1K
L
tDTHZ
13
20
C = 30pF,
L
2
R = 1K
L
tDSK
16
17
BE or UDS/LDS skew
tBEDS
BE or UDS/LDS to DS set-up
0
1. Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject
to production testing
2. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
51
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
tDSRE
DS
(SIZ0-1)
tCSRE
tCSS
tCSH
CS
tADH
tADS
VALID
A18-A1
R/W,SIZ0-1
tDZ
D15-D0
READ
VALID READ DATA
tWDS
VALID WRITE DATA
tDSR
D15-D0
WRITE
tDTHZ
Hi-Z
tDHW
Hi-Z
DTA
BERR
tAKD
tAKH
tWDD
tAKS
WAIT
Note: Motorola MC68000 and Intel i960 or similar processors are depicted in this diagram.
Figure 11 - Microprocessor Bus Interface Timing
tDSR
DS
tBEDS
(BE1-0 or
UDS, LDS)
tDSK
Figure 12 - Intel Mode Timing
52
Zarlink Semiconductor Inc.
ZL50074
Data Sheet
1
AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing
No.
Characteristic (Figure 13)
TCK Clock Period
Sym
Min
Typ
Max
Units
Notes
1
2
t
100
ns
MHz
ns
TCKP
TCK Clock Frequency
TCK Clock Pulse Width High
TCK Clock Pulse Width Low
TMS Set-up Time
t
10
TCKF
TCKH
3
t
20
20
10
10
20
60
4
t
ns
TCKL
5
t
ns
TMSS
TMSH
6
TMS Hold Time
t
ns
7
TDi Input Set-up Time
TDi Input Hold Time
TDo Output Delay
t
ns
TDIS
TDIH
8
t
ns
9
t
20
ns
CL = 30pF
TDOD
10
11
TRST pulse width
t
20
20
ns
TRSTW
PWR pulse width
t
ns
TPWR
1. Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
TMS
tTMSH
tTMSS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
tTPWR
PWR
Figure 13 - JTAG Test Port & PWR Reset Timing
53
Zarlink Semiconductor Inc.
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