AS4LC1M16ECJ-8/883C [MICROSS]
EDO DRAM, 1MX16, 80ns, CMOS, CDSO44, 0.450 INCH, CERAMIC, SOJ-50/44;
| 型号： | AS4LC1M16ECJ-8/883C |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | EDO DRAM, 1MX16, 80ns, CMOS, CDSO44, 0.450 INCH, CERAMIC, SOJ-50/44 动态存储器 CD 内存集成电路 |
| 文件： | 总22页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
1 MEG x 16PDRERLIMIANARMY
3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH
AVAILABLE AS MILITARY
SPECIFICATIONS
PIN ASSIGNMENT (Top View)
•
MIL-STD 883
44/50-Pin SOJ/LCC/Gull Wing
•
SMD Planned
450mil
FEATURES
•
JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
High-performance CMOS silicon-gate process
Single +3.3V ±0.3V power supply
All device pins are TTL-compatible
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
•
•
•
•
9
10
11
•
•
•
•
•
BYTE WRITE access cycles
NC
1,024-cycle refresh (10 row-, 10 column-addresses)
Low power, 0.3mW standby; 180mW active, typical
Extended Data-Out (EDO) PAGE access cycle
5V-tolerant I/ Os (5.5V maximum VIH level)
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
OPTIONS
•
MARKING
Timing
60ns access (Contact Factory)
70ns access
80ns access
-6
-7
-8
A4
Vss
•
•
Refresh Rate
Standard 16ms period
None
Packages
Ceramic SOJ
Ceramic Gull Wing
Ceramic LCC
ECJ No. 506
ECG No. 604
EC No. 213
an internal CAS.
The AS4LC1M16 CAS function and timing are deter-
mined by the first CAS (CASL or CASH) to transition LOW
and the last CAS to transition back HIGH. Use of only one
ofthetworesultsin a BYTEWRITEcycle.CASLtransitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and CASH transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
KEY TIMING PARAMETERS
SPEED
-6
tRC
tRAC
60ns
70ns
80ns
tPC
tAA
30ns
35ns
40ns
tCAC
15ns
20ns
20ns
tCAS
12ns
12ns
20ns
105ns
125ns
150ns
25ns
30ns
40ns
-7
-8
GENERAL DESCRIPTION
Each bit is uniquely addressed through the 20address bits
during READ or WRITE cycles. These are entered 10 bits
(A0-A9) at a time. RAS is used to latch the first 10 bits and
CAS the latter 10 bits. The CAS function also determines
whether the cycle will be a refresh cycle (RAS ONLY) or an
active cycle (READ, WRITE or READ WRITE) once RAS
goes LOW.
The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two CAS pins (CASL and
CASH). These function in a similar manner to a single CAS
of other DRAMs in that either CASL or CASH will generate
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-93
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
GENERAL DESCRIPTION (continued)
The CASL and CASH inputs internally generate a CAS
signal functioning in a similar manner to the single
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address-
defined page boundary.The PAGEcycle is always initiated
with a row -address strobed-in by RAS followed by a col-
umn-address strobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different column-
addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the PAGE MODE of operation.
?C?A/S input of other DRAMs. The key difference is each
CAS input ( CASL and CASH ) controls its corresponding
8 DQ inputs during WRITE accesses. CASL controls DQ1
through DQ8 and CASH controls DQ9 through DQ16. The
two CAS controls give the MT4LC1M16E5(S) both BYTE
READ and BYTE WRITE cycle capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS
(CASLor CASH),whichever occurs last.An EARLYWRITE
occurs when WE is taken LOW prior to either CAS falling.
A LATE WRITE or READ-MODIFY-WRITE occurs when
WE falls after CAS (CASL or CASH) was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of OE. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE must be
taken HIGH to disable the data-outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping OE LOW, no write will occur, and
the data-outputs will drive read data from the accessed
location.
EDO PAGE MODE
The AS4LC1M16 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS returns HIGH. EDO provides for CAS precharge time
t
( CP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODEDRAMs,except data willremain valid
or become valid after CAS goes HIGH during READs,
provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CASgoes HIGH while RASremains LOW,data
will transition to and remain High-Z (refer to Figure 1).
The 16data inputs and 16data outputs are routed through
16 pins using common I/ O. Pin direction is controlled by
OE and WE.
V
V
IH
IL
RAS
CASL/CASH
V
V
IH
IL
V
V
IH
IL
ADDR
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (A)
VALID DATA (B)
VALID DATA (C)
VALID DATA (D)
t
t
OD
t
OD
OD
t
OES
t
OEHC
V
V
IH
IL
OE
t
OE
t
OEP
The DQs go back to
Low-Z if OES is met.
The DQs remain High-Z
until the next CAS cycle
if OEHC is met.
The DQs remain High-Z
until the next CAS cycle
if OEP is met.
t
t
t
DON’T CARE
UNDEFINED
Figure 1
OUTPUT ENABLE AND DISABLE
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-94
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO PAGE MODE (continued)
WE can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WEto the idle banks during CASHIGH time
will also High-Z the outputs. Independent of OE control,
the outputs will disable after OFF, which is referenced
t
from the rising edge of RAS or CAS, whichever occurs last.
V
IH
RAS
CASL/CASH
ADDR
V
IL
V
V
IH
IL
V
V
IH
IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (B)
INPUT DATA (C)
t
t
WHZ
WHZ
t
V
IH
WE
OE
WPZ
V
IL
V
V
IH
IL
t
The DQs go to High-Z if WE falls, and if WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
WE CONTROL OF DQs
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-95
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
BYTE ACCESS CYCLE
WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a CAS precharge has been
satisfied, a LATE WRITE on the other byte is permissable.
The BYTE WRITEs and BYTE READs are determined by
the use of CASL and CASH. Enabling CASL will select a
lower BYTE access (DQ1-DQ8). Enabling CASH will select
an upper BYTE access (DQ9-DQ16). Enabling both CASL
and CASH selects a WORD WRITE cycle.
The AS4LC1M16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep-
tion ofthe CASinputs. Figure 3illustrates the BYTEWRITE
and WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode ofoperation ifboth bytes are active. A CASprecharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes.For example,an EARLY
REFRESH
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
16ms, regardless ofsequence. The CBRREFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
WORD WRITE
LOWER BYTE WRITE
RAS
CASL
CASH
WE
STORED
INPUT
INPUT
DATA
STORED STORED
INPUT
INPUT
DATA
STORED
DATA
DATA
DATA
DATA
DATA
DATA
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
LOWER BYTE
(DQ1-DQ8)
OF WORD
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE
(DQ9-DQ16)
OF WORD
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
ADDRESS 1
Figure 3
WORD AND BYTE WRITE EXAMPLE
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-96
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
WE
CASL
CASH
DATA-IN BUFFER
CAS
DQ1
16
NO. 2 CLOCK
GENERATOR
DQ16
DATA-OUT
BUFFER
COLUMN-
ADDRESS
BUFFER
OE
COLUMN
DECODER
10
10
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024
REFRESH
CONTROLLER
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
1024 x 16
10
ROW-
ADDRESS
BUFFERS (10)
1024 x 1024 x 16
MEMORY
10
10
1024
ARRAY
NO. 1 CLOCK
GENERATOR
Vcc
Vss
RAS
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-97
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
TRUTH TABLE
ADDRESSES
t
t
FUNCTION
RAS
H
CASL CASH WE
OE
X
R
C
DQs
NOTES
Standby
H>X H>X
X
H
H
X
X
High-Z
Data-Out
READ: WORD
READ: LOWER BYTE
L
L
L
L
L
ROW COL
ROW COL
L
H
L
Lower Byte,
Upper Byte, Data-Out
READ: UPPER BYTE
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
X
X
X
ROW COL Lower Byte, Data-Out
Upper Byte
WRITE: WORD
(EARLY WRITE)
ROW COL
ROW COL
ROW COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
H
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
L
L
H>L L>H ROW COL
Data-Out, Data-In
Data-Out
1, 2
2
EDO-PAGE-MODE 1st Cycle
L
H>L H>L
H>L H>L
L>H L>H
H>L H>L
H>L H>L
H
H
H
L
L
L
ROW COL
READ
2nd Cycle
Any Cycle
L
n/a
n/a
COL
n/a
Data-Out
2
L
L
Data-Out
2
EDO-PAGE-MODE 1st Cycle
WRITE 2nd Cycle
EDO-PAGE-MODE 1st Cycle
L
X
X
ROW COL
n/a COL
Data-In
1
L
L
Data-In
1
L
L
H>L H>L H>L L>H ROW COL
H>L H>L H>L L>H n/a COL
Data-Out, Data-In
Data-Out, Data-In
Data-Out
1, 2
1, 2
2
READ-WRITE
HIDDEN
2nd Cycle
READ
L>H>L
L>H>L
L
L
L
L
L
H
L
L
X
X
X
ROW COL
ROW COL
REFRESH
WRITE
Data-In
1, 3
RAS-ONLY REFRESH
CBR REFRESH
H
L
H
L
X
H
ROW
X
n/a
X
High-Z
H>L
High-Z
4
NOTE: 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
3. EARLY WRITE only.
4. Only one CAS must be active (CASL or CASH).
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-98
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC pin Relative to VSS .............. -1.0V to +4.6V
Voltage on NC, Inputs or I/ O pins
Relative to Vss ................................................. -1.0V to +5.5V
Operating Temperature, T (ambient) ..... T (MIN)=-55°C
A
A
...................................................................... T (MAX)=125°C
C
Storage Temperature ................................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL MIN
MAX UNITS NOTES
Supply Voltage
VCC
VIH
VIL
3.0
2.0
3.6
VCC+1
0.8
V
V
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
Input Low (Logic 0) Voltage, all inputs (including NC pins)
INPUT LEAKAGE CURRENT
-1.0
Any input 0V ≤ VIN ≤ 5.5V
VCC = 3.6V
II
-2
2
µA
4
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) VCC=3.6V
IOZ
-10
2.4
10
µA
OUTPUT LEVELS
VOH
V
Output High Voltage (IOUT = -2.0mA)
Output Low Voltage (IOUT = 2.0mA)
VOL
0.4
V
MAX
-7
PARAMETER/CONDITION
SYMBOL
-6
2
-8
2
UNITS NOTES
STANDBY CURRENT: (TTL) (RAS = CAS = VIH)
STANDBY CURRENT: (CMOS)
ICC1
ICC2
2
1
mA
mA
1
1
(?R?A/S = CAS = other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(?R?A/S, CAS address cycling: RC = RC [MIN])
ICC3
ICC4
ICC5
ICC6
170 155
130 120
160 145
150 140
140
110
130
130
mA
mA
mA
mA
5, 6
5, 6
5, 6
5, 7
t
t
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
t
t
(?R?A/S = VIL, CAS, address cycling: PC = PC [MIN])
REFRESH CURRENT: RAS ONLY
Average power supply current
t
t
(?R?A/S cycling, CAS=VIH: RC = RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
t
t
(R
?
AS, CAS address cycling: RC = RC [MIN])
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-99
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
CAPACITANCE
PARAMETER
SYMBOL
MAX UNITS NOTES
Input Capacitance: Addresses
Input Capacitance: RAS, CASL,CASH, WE, OE
Input/Output Capacitance: DQ
CI1
CI2
CIO
7
7
8
pF
pF
pF
8
8
8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 2, 3, 6, 9, 10, 11, 12,) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
-6
-7
-8
PARAMETER
SYM
tAA
tACH
tAR
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Access time from column-address
Column-address set-up to CAS precharge
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
30
35
40
ns
ns
ns
ns
ns
ns
15
45
0
15
50
0
25
60
0
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLCH
tCLZ
tCOH
tCP
25
25
13
0
0
0
Column-address to WE delay time
Access time from CAS
55
60
65
15
20
20
ns 14, 26
Column-address hold time
10
12
10
10
0
12
13
12
10
0
15
15
15
15
0
ns
10,000 ns
25
27
C
A
/
10,000
10,000
C
A
/
ns 7, 28
Last CAS going LOW to first CAS to return HIGH
?C?A/S to output in Low-Z
ns
ns
ns
29
26
Data output hold after next CAS LOW
CAS precharge time
3
3
3
10
10
10
ns 15, 30
Access time from CAS precharge
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
35
40
40
ns
ns
ns
26
28
28
C
A
/
5
50
5
5
55
5
5
C
A
/
60
10
45
20
15
60
0
C
A
/
ns 7, 25
ns 13, 25
C
A
/
35
15
10
45
0
40
15
12
55
0
Write command to CAS lead time
Data-in hold time
ns
28
ns 16, 26
ns
Data-in hold time (referenced to RAS)
Data-in setup time
ns 16, 26
ns
Output disable
0
15
15
0
15
20
0
15
20
Output Enable
tOE
ns 17, 26
OE hold time from WE during READ-MODIFY-WRITE cycle tOEH
12
10
10
12
10
10
15
10
10
ns
ns
ns
18
18
O
/
tOEHC
tOEP
?O/
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-100
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 2, 3, 6, 9, 10, 11, 12, 20) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
-6
-7
-8
PARAMETER
SYM
tOES
tOFF
MIN
5
MAX
MIN
5
MAX
MIN
10
0
MAX UNITS
NOTES
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
ns
0
15
0
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20, 26
OE setup prior to RAS during HIDDEN REFRESH cycle tORD
0
0
0
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
tPC
tPRWC
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRC
tRCD
tRCH
tRCS
tREF
tRP
30
75
35
85
40
90
31
31
19
21
60
30
70
35
80
40
RAS to column-address delay time
12
10
30
60
60
110
14
0
12
10
35
70
70
130
14
0
15
10
40
80
80
150
16
0
Row-address hold time
Column-address to RAS lead time
RAS pulse width
10,000
10,000
10,000
RAS pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS delay time
100,000
100,000
100,000
45
50
60
22, 25
23, 28
25
Read command hold time (referenced to CAS)
Read command setup time
0
0
0
Refresh period (1,024 cycles)
16
16
16
R
A
/
40
5
50
5
60
5
R
A
/
tRPC
tRRH
tRSH
tRWC
tRWD
tRWL
tT
Read command hold time (referenced to RAS)
RAS hold time
0
0
0
23
32
13
150
80
15
2
15
180
90
18
2
20
200
105
20
2
READ WRITE cycle time
RAS to WE delay time
13
Write command to RAS lead time
Transition time (rise or fall)
50
13
50
15
50
20
Write command hold time
tWCH
tWCR
tWCS
tWHZ
tWP
10
45
0
12
55
0
15
60
0
32
Write command hold time (referenced to RAS)
WE command setup time
13, 25
Output disable delay from WE
Write command pulse width
0
0
0
10
10
10
10
12
12
10
10
15
15
10
10
W
/
tWPZ
tWRH
tWRP
?W/
?W/
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-101
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
NOTES
1. All voltages referenced to VSS.
17. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE
must be pulsed during CAS HIGH time in order to
place I/ O buffers in High-Z.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is assured.
3. An initial pause of 100µs is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
18. LATE WRITE and READ-MODIFY-WRITE cycles
t
t
must have both OD and OEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
t
repeated any time the REF refresh requirement is
exceeded.
t
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = +3.0V; f = 1 MHz.
remains LOW and OE is taken back LOW after OEH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
t
t
t
19. Assumes that RCD < RCD (MAX). If RCD is greater
than the maximum recommended value shown in this
t
t
table, RAC will increase by the amount that RCD
exceeds the value shown.
20. OFF (MAX) defines the time at which the output
t
t
9. AC characteristics assume T = 2.5ns.
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS or CAS, whichever occurs last.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
t
21. Operation within the RAD (MAX) limit ensures that
t
t
t
RAC (MIN) and CAC (MIN) can be met. RAD
t
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
(MAX) is specified as a reference point only; if RAD
is greater than the specified RAD (MAX) limit, then
t
t
access time is controlled exclusively by AA, provided
t
RCD is not exceeded.
t
22. Operation within the RCD (MAX) limit ensures that
t
t
t
t
t
t
13. WCS, RWD, AWD and CWD are not restrictive
RAC (MAX) can be met. RCD (MAX) is specified as
t
t
operating parameters. WCS applies to EARLY
WRITE cycles. RWD, AWD and CWD apply to
READ-MODIFY-WRITE cycles. If WCS ≥ WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
a reference point only; if RCD is greater than the
specified RCD (MAX) limit, then access time is
controlled exclusively by CAC, provided RAD is not
exceeded.
t
t
t
t
t
t
t
t
t
t
23. Either RCH or RRH must be satisfied for a READ
cycle.
t
t
t
the entire cycle. If WCS < WCS (MIN) and RWD ≥
t
t
t
t
t
RWD (MIN), AWD ≥ AWD (MIN) and CWD ≥
CWD (MIN), the cycle is a READ-MODIFY-WRITE
24. The first CASx edge to transition LOW.
25. Output parameter (DQx) is referenced to correspond-
ing CAS input; DQ1-DQ8 by CASL and DQ9-DQ16
by CASH.
26. Each CASx must meet minimum pulse width.
27. The last CASx edge to transition HIGH.
28. Last falling CASx edge to first rising CASx edge.
29. Last rising CASx edge to first falling CASx edge.
30. Last rising CASx edge to next cycle’s last rising CASx
edge.
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE held HIGH
and WE taken LOW after CAS goes LOW results in a
t
t
LATE WRITE (OE-controlled) cycle. WCS, RWD,
t
t
CWD and AWD are not applicable in a LATE
WRITE cycle.
t
t
14. Assumes that RCD ≥ RCD (MAX).
15. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
31. Last CASx to go LOW.
32. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
t
pulsed HIGH for CP.
16. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-102
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
t
RRH
RSH
t
t
t
CLCH
t
RCD
CAS
CRP
V
V
IH
IL
CASL/CASH
t
AR
t
t
t
t
t
RAD
RAH
RAL
CAH
ACH
t
t
ASC
ASR
V
V
IH
IL
ROW
t
ROW
ADDR
COLUMN
t
t
t
RCH
WRP
WRH
RCS
V
V
WE
IH
IL
NOTE 1
t
t
t
t
AA
NOTE 2
OFF
RAC
CAC
CLZ
t
V
V
OH
OL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. OFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
tRAC
MAX
60
MIN
MAX
70
MIN
MAX
80
UNITS
ns
30
35
40
15
45
0
15
50
0
20
60
0
ns
tRAD
tRAH
tRAL
tRAS
tRC
12
10
30
30
12
10
35
35
15
10
40
40
ns
tAR
ns
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
ns
0
0
0
ns
60 10,000
110
70 10,000 80 10,000
ns
15
20
20
ns
130
14
0
150
20
0
ns
10
12
15
ns
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
14
0
45
50
60
ns
12 10,000
13 10,000 20 10,000
ns
ns
tCLCH 10
10
0
10
0
ns
0
0
0
ns
tCLZ
tCRP
tCSH
tOD
0
5
ns
40
0
50
0
60
0
ns
5
5
ns
ns
50
0
55
0
60
0
ns
13
10
10
15
10
10
15
10
10
ns
15
15
15
15
20
15
20
20
20
ns
ns
tOE
ns
ns
tOFF
0
0
0
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-103
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
t
CRP
RCD
CAS
CLCH
CASL/CASH
V
V
IH
IL
t
AR
t
t
t
t
RAD
RAH
RAL
CAH
t
t
ASC
ASR
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
t
t
WRH
WRP
WE
V
V
IH
IL
NOTE 1
t
t
DHR
DH
t
DS
V
IOH
IOL
DQ
OE
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
MIN MAX
10
-8
MIN MAX
10
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
MIN
15
45
0
MAX
MIN MAX
MIN MAX
UNITS
ns
SYM
tRAH
tRAL
tRAS
tRC
MIN
10
MAX
UNITS
ns
15
20
50
60
ns
30
35
40
ns
0
0
ns
60 10,000
110
70 10,000
130
80 10,000
150
ns
0
0
0
ns
ns
10
12
15
ns
tRCD
tRP
14
40
13
15
10
45
0
45
14
50
15
15
12
55
0
50
20
60
0
60
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
5
10
5
ns
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
ns
tCRP
tCSH
tCWL
tDH
tDHR
tDS
5
ns
20
15
60
0
ns
50
15
10
45
0
55
15
12
55
0
60
20
15
55
0
ns
ns
ns
ns
ns
ns
ns
10
10
10
12
10
10
15
10
10
ns
ns
tWRH
tWRP
ns
tRAD
12
30
12
35
15
40
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-104
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
t
RP
RAS
V
V
IH
IL
RAS
CASL/CASH
ADDR
t
CSH
t
RSH
t
t
t
t t
CAS, CLCH
CRP
RCD
V
V
IH
IL
t
AR
t
t
RAL
RAD
t
t
t
t
ASC
RCS
CAH
ASR
RAH
t
ACH
V
V
IH
IL
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
t
WRH
t
WRP
AWD
V
V
IH
IL
WE
NOTE 1
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
IOH
IOL
VALID D
VALID D
DQ
OE
OPEN
OPEN
V
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
tOE
tOEH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
30
35
40
15
20
20
15
45
0
15
50
0
20
60
0
12
12
15
ns
tAR
tRAC
tRAD
tRAH
tRAL
tRAS
tRCD
tRCS
tRP
60
30
70
35
80
40
ns
tASC
tASR
tAWD
tCAC
tCAH
tCAS
12
10
30
12
10
35
15
10
40
ns
0
0
0
ns
55
60
65
ns
15
20
20
60 10,000
70 10,000 80 10,000
ns
10
12
15
14
0
45
14
0
50
20
0
60
ns
12 10,000
13 10,000 20 10,000
ns
tCLCH 10
10
0
10
0
40
13
50
15
180
90
15
12
10
10
60
15
200
105
20
15
10
10
ns
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
0
5
tRSH
ns
5
5
tRWC 150
ns
50
35
15
10
0
55
40
15
12
0
60
45
20
15
0
tRWD
tRWL
tWP
tWRH
tWRP
80
15
10
10
10
ns
ns
ns
ns
tDS
ns
tOD
0
15
0
15
0
20
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-105
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS
t
t
t
t
RSH
CSH
PC
CP
t
t
t
t
t
t
t
t
t
t
CP
CAS, CLCH
CAS, CLCH
CAS, CLCH
CRP
RCD
CP
V
V
CASL/CASH
IH
IL
t
AR
t
t
t
ACH
ACH
ACH
t
t
t
RAD
RAH
RAL
t
t
t
t
t
t
t
t
ASR
ASC
RCS
CAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
WRH
WRP
t
RCH
V
V
IH
IL
t
t
t
t
RRH
AA
NOTE 1
t
t
t
t
AA
AA
CPA
CAC
t
RAC
CPA
CAC
t
t
CAC
CLZ
t
OEHC
t
OFF
t
COH
t
CLZ
V
OH
OL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OE
OPEN
OPEN
V
t
t
t
OE
OE
t
OD
OD
t
OES
t
V
V
OES
IH
IL
t
OEP
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
MAX
MIN
10
5
MAX
MIN
10
5
MAX
UNITS
ns
ns
30
35
40
tOEP
tOES
tOFF
tPC
10
5
15
45
0
15
50
0
20
60
0
tAR
3
15
3
15
0
20
ns
tASC
tASR
tCAC
tCAH
tCAS
30
35
40
ns
0
0
0
tRAC
tRAD
tRAH
tRAL
60
30
70
35
80
40
ns
ns
ns
ns
15
20
20
12
10
30
12
10
35
15
10
40
10
12
12
15
10,000 13 10,000 20 10,000
tCLCH 10
10
0
10
0
tRASP 60
100,000 70 100,000 80 100,000
ns
tCLZ
tCOH
tCP
0
3
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
14
0
45
14
0
50
20
0
60
ns
3
5
ns
10
10
10
0
0
0
ns
tCPA
tCRP
tCSH
tOD
35
40
40
40
0
50
0
60
0
ns
5
50
0
5
55
0
5
60
0
ns
13
10
10
15
10
10
15
10
10
ns
ns
15
15
15
20
20
20
tOE
tOEHC 10
ns
10
10
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-106
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS
t
t
t
t
CSH
PC
CP
RSH
t
t
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS, CLCH
CAS, CLCH
CP
CAS, CLCH
V
V
IH
IL
CASL/CASH
t
t
AR
ACH
t
t
t
t
t
RAD
ACH
RAL
ACH
ASC
t
t
t
t
t
t
t
ASC
ASR
RAH
CAH
ASC
CAH
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
t
t
WRH
WRP
V
V
IH
IL
WE
NOTE 1
t
t
t
t
WCR
DHR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
IOH
IOL
DQ
OE
VALID DATA
VALID DATA
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
MAX
MIN
15
50
0
MAX
MIN
20
60
0
MAX
UNITS
ns
SYM MIN
MAX
MIN
12
MAX
MIN
15
MAX
UNITS
ns
tACH
tAR
tASC
tASR
tCAH
tCAS
15
45
0
tRAD
tRAH
tRAL
12
10
30
30
35
40
ns
10
10
ns
ns
35
40
ns
0
0
0
ns
tRASP 60 125,000 70 125,000 80 100,000
ns
10
12
15
ns
tRCD
tRP
14
40
13
15
10
45
0
45
14
50
15
15
12
55
0
50
20
60
15
20
15
60
0
60
ns
12 10,000
13 10,000 20 10,000
ns
ns
tCLCH 10
10
10
5
10
10
5
ns
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
ns
tCP
10
5
ns
ns
tCRP
tCSH
tCWL
tDH
tDHR
tDS
ns
ns
50
15
10
45
0
55
15
12
55
0
60
20
15
55
0
ns
ns
ns
ns
ns
10
10
10
12
10
10
15
10
10
ns
ns
tWRH
tWRP
ns
ns
ns
tPC
25
30
40
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-107
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
t
RP
RASP
V
V
IH
IL
RAS
t
t
t
NOTE 1
t
CSH
PC
PRWC
t
RSH
t
t
t
t
t
t
CP
t
t
t
t
CRP
RCD
CP
CP
CAS, CLCH
CAS, CLCH
CAS, CLCH
CASL/CASH
V
V
IH
IL
t
AR
t
t
t
RAD
RAH
RAL
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
CWL
t
RCS
t
t
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
t
AWD
AWD
AWD
CWD
t
t
WRH
t
WRP
CWD
CWD
WE
V
V
IH
IL
NOTE 2
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
IOH
IOL
VALID VALID
VALID VALID
VALID VALID
D D
DQ
OE
OPEN
OPEN
V
D
D
D
D
OUT
IN
OUT
IN
OUT
IN
t
t
t
OD
OD
OD
t
OEH
t
t
t
OE
OE
OE
V
V
IH
IL
DON’T CARE
UNDEFINED
t
NOTE:
1. PC is for LATE WRITE cycles only.
2. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
tOE
tOEH
tPC
tPRWC 75
tRAC
MAX
MIN
MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
35
40
15
20
20
tAR
45
0
50
0
60
0
12
25
12
30
85
15
40
90
tASC
tASR
tAWD
tCAC
tCAH
tCAS
0
0
0
55
60
65
60
30
70
35
80
40
15
20
20
tRAD
tRAH
tRAL
12
10
30
12
10
35
15
10
40
10
12
15
12 10,000
13 10,000
20 10,000
tCLCH 10
10
0
10
0
tRASP 60
125,000
45
70 125,000
80 100,000
tCLZ
tCP
0
tRCD
tRCS
tRP
tRSH
tRWD
tRWL
tWP
14
0
14
0
50
20
0
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
40
5
10
40
5
tCPA
tCRP
tCSH
tCWD
tCWL
tDH
35
15
40
13
80
15
10
10
10
50
15
90
15
12
10
10
60
15
105
20
15
10
10
5
50
35
15
10
0
55
40
15
12
0
60
45
20
15
0
tWRH
tWRP
tDS
tOD
0
0
15
0
20
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-108
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
t
t
t
CP
CRP
RCD
CAS, CLCH
CP
CAS, CLCH
CP
CAS, CLCH
V
V
IH
IL
CASL/CASH
t
t
t
RAL
AR
t
t
t
RAD
ACH
CAH
t
ASR
t
t
t
t
t
ASC
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE
ROW
t
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
t
RCH
t
t
WRP
WRH
t
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
t
NOTE 1
AA
t
CPA
RAC
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
VALID
COH
V
V
IOH
IOL
DQ
OE
OPEN
VALID DOUT
VALID DIN
DOUT
t
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
tACH
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ns
30
35
40
tPC
25
30
40
15
45
0
15
50
0
20
60
0
ns
tRAC
tRAD
tRAH
tRAL
60
30
70
35
80
40
ns
tAR
ns
12
10
30
12
10
35
15
10
40
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
ns
0
0
0
ns
ns
15
20
20
ns
tRASP 60
125,000
45
70 125,000
80 100,000
ns
10
12
15
ns
tRCD
tRCH
tRCS
tRP
tRSH
tWCH
tWCS
tWHZ
tWRH
tWRP
14
0
14
0
50
15
20
0
60
20
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
3
10
5
ns
0
0
0
ns
tCOH
tCP
3
ns
40
13
10
0
50
15
12
0
60
15
15
0
ns
10
10
40
5
10
40
5
ns
ns
tCPA
tCRP
tCSH
tDH
35
15
ns
ns
5
50
10
0
ns
ns
55
12
0
60
15
0
ns
0
13
0
0
ns
ns
10
10
10
10
10
10
ns
tDS
ns
ns
tOE
20
20
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-109
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
READ CYCLE
(with WE-controlled disable)
V
IH
RAS
CASL/CASH
ADDR
V
IL
t
CSH
t
t
t
t
t
t
RCD
CAS, CLCH
CRP
CP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
ASR
ASC
CAH
ASC
V
V
IH
IL
ROW
t
COLUMN
COLUMN
t
t
WRP
WRH
RCS
t
t
t
RCH
WPZ
RCS
V
V
WE
IH
IL
NOTE 1
t
t
t
t
AA
RAC
CAC
CLZ
t
t
WHZ
CLZ
V
V
OH
OL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
MAX
15
MIN
MAX
15
MIN
MAX
15
UNITS
ns
30
35
40
tOD
0
0
0
tAR
45
0
50
0
60
0
ns
tOE
15
20
20
ns
tASC
tASR
tCAC
tCAH
tCAS
ns
tRAC
tRAD
tRAH
tRCD
tRCH
tRCS
tWHZ
tWPZ
tWRH
tWRP
60
70
80
ns
0
0
0
ns
12
10
14
0
30
12
10
14
0
35
15
10
20
0
40
ns
15
20
20
ns
ns
10
12
15
ns
45
13
50
15
60
20
ns
12 10,000
13 10,000
20 10,000
ns
ns
tCLCH 10
10
0
10
0
ns
0
0
0
ns
tCLZ
tCP
tCRP
tCSH
0
10
5
ns
0
0
0
ns
10
5
10
5
ns
10
10
10
12
10
10
15
10
10
ns
ns
ns
50
55
60
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-110
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
RAS-ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
t
RPC
CRP
V
V
IH
IL
CASL/CASH
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
V
OH
OL
Q
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE
NOTE 1
CBR REFRESH CYCLE
(Addresses and OE = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS
t
RPC
t
t
t
t
t
t
CHR
RPC
CP
CSR
CHR
CSR
V
V
IH
IL
CASL and CASH
DQ
V
V
OH
OL
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE
NOTE 2
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should
implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
t
2. WRP and tWRH are for system design reference only. The WE signal is actually a “don’t care” at RAS time during a CBR
REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other
DRAMs that require WE HIGH at RAS time during a CBR REFRESH.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
MAX
MIN
0
MAX
MIN
0
MAX
UNITS
ns
SYM MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ns
tASR
tCHR
tCP
tCRP
tCSR
tRAH
0
10
10
5
tRAS
tRC
tRP
tRPC
tWRH
tWRP
60 10,000
70 10,000 80 10,000
12
10
5
15
10
5
ns
105
40
5
125
50
5
150
60
5
ns
ns
ns
ns
ns
5
5
10
10
ns
10
10
10
10
10
10
ns
10
10
ns
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-111
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
HIDDEN REFRESH CYCLE 32
(WE = HIGH; OE = LOW)
t
RC
t
t
t
RAS
RAS
RP
V
V
IH
IL
RAS
t
t
t
t
CRP
RCD
RSH
CHR
V
V
IH
IL
CASL/CASH
t
t
AR
t
t
RAD
RAL
t
t
t
ASR
RAH
ASC
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
t
t
t
t
AA
RAC
CAC
CLZ
t
OFF
V
IOH
IOL
DQx
OE
OPEN
VALID DATA
OPEN
V
t
t
OD
OE
V
V
t
IH
IL
ORD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM MIN
tAA
MAX
MIN
MAX
MIN
MAX
UNITS
ns
SYM MIN
MAX
MIN
3
MAX
MIN
MAX
UNITS
ns
30
35
40
tOFF
tORD
tRAC
tRAD
tRAH
tRAL
tRAS
tRC
3
0
15
15
3
0
15
tAR
45
0
50
0
60
0
ns
0
ns
tASC
tASR
tCAC
tCAH
tCHR
tCLZ
tCRP
tOD
ns
60
30
70
35
80
40
ns
0
0
0
ns
12
10
30
60
105
14
40
13
12
10
35
15
10
40
ns
15
20
20
ns
ns
10
10
0
12
12
0
15
15
0
ns
ns
ns
10,000 70 10,000 80
10,000
60
ns
ns
125
14
145
20
ns
5
5
5
ns
tRCD
tRP
45
50
ns
0
15
15
0
15
20
0
20
20
ns
50
60
ns
tOE
ns
tRSH
15
15
ns
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-112
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883TESTREQUIREMENTS
(perMethod5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
*
PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-113
AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-114
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