AS5SP128K36DQ-40XT [MICROSS]
Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, MS-026-D/BHA, TQFP-100;
| 型号： | AS5SP128K36DQ-40XT |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, MS-026-D/BHA, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
DQPc
1
80
79
78
77
76
DQPb
DQb
2
3
DQc
Features
DQb
DQc
VDDQ
VSSQ
4
VDDQ
VSSQ
DQb
5
•
•
•
•
•
•
•
•
•
•
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
6
DQc
75
74
73
72
7
DQb
DQc
8
DQb
DQc
9
DQb
DQc
VSSQ
VDDQ
DQb
10
11
12
13
14
15
16
VSSQ
VDDQ
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
DQc
NC
DQb
VSS
NC
Global Write support
VDD
NC
SSRAM [SPB]
VDD
ZZ
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without Data
Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
17
18
19
20
21
22
23
24
25
VSS
DQd
DQd
VDDQ
VSSQ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa
•
•
•
•
•
•
•
DQd
DQd
DQd
DQd
26
27
28
29
30
VSSQ
VDDQ
DQd
DQd
JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
DQPd
Fast Access Times
Parameter
Symbol 200Mhz 166Mhz 133Mhz
Units
Cycle Time
Clock Access Time
Output Enable Access Time
tCYC
tCD
tOE
5.0
3.0
3.0
6.0
3.5
3.5
7.5
4.0
4.0
ns
ns
ns
General Description
Block Diagram
ASI’s AS5SP128K36DQ is
a 4.5Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High Performance
CMOS technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
OE\
ZZ
CLK
CE1\
CE2
I/O Gating and Control
CE3\
Memory Array
Output Output
Register Driver
BWE\
CONTROL
BLOCK
x36
SBP
ASI’s AS5SP128K36DQ includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
BWx\
GW\
❑ Synchronous Pipeline
Burst
❑ Two (2) cycle load
❑ One (1) cycle
de-select
BURST CNTL.
ADV
DQx, DQPx
ADSC\
ADSP\
MODE
Address
Registers
Input
Register
❑ One (1) cycle latency
on Mode change
Row
Decode
Column
Decode
A0-Ax
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
Pin Description/Assignment Table
Signal Name
Symbol
CLK
Type
Pin
Description
Clock
Input
89
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Address
Address
A0, A1
A
Input
37, 36
Input(s)
35, 34, 33, 32, 31, 100, Synchronous Address Inputs
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
Chip Enable
Chip Enable
CE1\, CE3\
CE2
Input
Input
98, 92
97
Active Low True Chip Enables
Active High True Chip Enable
Global Write Enable
Byte Enables
GW\
Input
Input
88
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
93, 94, 95, 96
Byte Write Enable
Output Enable
Address Strobe Controller
Input
Input
Input
87
86
85
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Address Strobe from Processor
ADSP\
Input
84
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted HIGH, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Address Advance
Power-Down
ADV
ZZ
Input
Input
83
64
Data Parity Input/Outputs
DQPa, DQPb
DQPc, DQPd
Input/
Output
51, 80, 1, 30
Data Input/Outputs
DQa, DQb, DQc Input/
52, 53, 56, 57, 58, 59, Bidirectional I/O Data lines. As inputs they reach the memory
DQd
Output
62, 63, 68, 69, 72, 73, array via an input register, the address stored in the register on the
74, 75, 78, 79, 2, 3, 6, rising edge of clock. As and output, the line delivers the valid data
7, 8, 9, 12, 13, 18, 19, stored in the array via an output register and output driver. The data
22, 23, 24, 25, 28, 29 delieverd is from the previous clock period of the READ cycle.
Burst Mode
Power Supply [Core]
Ground [Core]
MODE
VDD
VSS
Input
Supply
Supply
31
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
91, 15, 41, 65
90, 17, 40, 67
Power Supply I/O
VDDQ
VSSQ
NC
Supply
Supply
NA
4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply
70, 77
I/O Ground
5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground
71, 76
No Connection(s)
14, 16, 38, 39, 66
38,39,42,43
No connections to internal silicon
Logic Block Diagram
A0, A1, Ax
ADDRESS
REGISTER
MODE
2
A0, A1
ADV\
CLK
Burst
Counter
and
Q1
Q0
CLR
Logic
ADSC\
ADSP\
Byte Write
Register
DQd, DQPd
Byte Write
Driver
DQd, DQPd
BWd\
BWc\
Memory
Array
Sense
Amps
Byte Write
Register
DQc, DQPc
Byte Write
Driver
DQc, DQPc
Output
Registers
Output
Buffers
DQx,
DQPx
Byte Write
Register
DQb, DQPb
Byte Write
Driver
DQb, DQPb
BWb\
Byte Write
Register
DQa, DQPa
Byte Write
Driver
DQa, DQPa
BWa\
BWE\
GW\
Input
Registers
Pipeline
Enable
Enable
Register
CE1\
CE2
CE3\
OE\
Sleep
Control
ZZ
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
2
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
cycle READS are supported. Once the READ operation has been
completed and deselected by use of the Chip Enable(s) and either
ADSP\ or ADSC\, its outputs will tri-state immediately.
Functional Description
Austin Semiconductor’s AS5SP128K36DQ Synchronous SRAM
is manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including those
A Single ADSP\ controlled WRITE operation is initiated when
both of the following conditions are satisfied at the time of Clock
(CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
Enable(s) are asserted ACTIVE. The address presented to the
address bus is registered and loaded on CLK HIGH, then
presented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
ignored on the first machine cycle. ADSP\ triggered WRITE
accesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the data
presented to the array via the Data bus will be written into the
array at the corresponding address location specified by the
Address bus. If GW\ is HIGH (inactive) then BWE\ and one or
more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\)
controls the write operation. All WRITES that are initiated in this
device are internally self timed.
of Intel and Motorola.
The AS5SP128K36DQ supports
Synchronous SRAM READ and WRITE operations as well as
Synchronous Burst READ/WRITE operations. All inputs with
the exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices input
clock (CLK). The type, start and the duration of Burst Mode
operations is controlled by MODE, ADSC\, ADSP\ and ADV as
well as the Chip Enable pins CE1\, CE2, and CE3\. All
synchronous accesses including the Burst accesses are enabled via
the use of the multiple enable pins and wait state insertion is
supported and controlled via the use of the Advance control
(ADV).
The ASI AS5SP128K36DQ supports both Interleaved as well as
Linear Burst modes therefore making it an architectural fit for
either the Intel or Motorola CISC processor elements available on
the Market today.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satisfied: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combination
of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s) or
the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of clock
HIGH will be the location that the WRITE occurs. The ADV pin
is ignored during this cycle, and the data WRITTEN to the array
will either be a BYTE WRITE or a GLOBAL WRITE depending
on the use of the WRITE control functions GW\ and BWE\ as
well as the individual BYTE CONTOLS (BWx\).
The AS5SP128K36DQ supports Byte WRITE operations and
enters this functional mode with the Byte Write Enable (BWE\)
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\).
Global Writes are supported via the Global Write Enable (GW\)
and Global Write Enable will override the Byte Write inputs and
will perform a Write to all Data I/Os.
The AS5SP128K36DQ provides ease of producing very dense
arrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1]
ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all
Deep Power-Down Mode (SLEEP)
asserted active, and [3] the WRITE signals (GW\, BWE\) are in The AS5SP128K36DQ has a Deep Power-Down mode and is
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. controlled by the ZZ pin. The ZZ pin is an Asynchronous input
The address presented to the Address inputs is stored within the and asserting this pin places the SSRAM in a deep power-down
Address Registers and Address Counter/Advancement Logic and mode (SLEEP). White in this mode, Data integrity is guaranteed.
then passed or presented to the array core. The corresponding For the device to be placed successfully into this operational
data of the addressed location is propagated to the Output mode the device must be deselected and the Chip Enables, ADSP\
Registers and passed to the data bus on the next rising clock via and ADSC\ remain inactive for the duration of tZZREC after the
the Output Buffers. The time at which the data is presented to the ZZ input returns LOW. Use of this deep power-down mode
Data bus is as specified by either the Clock to Data valid conserves power and is very useful in multiple memory page
specification or the Output Enable to Data Valid spec for the designs where the mode recovery time can be hidden.
device speed grade chosen. The only exception occurs when the
device is recovering from a deselected to select state where its
outputs are tristated in the first machine cycle and controlled by
its Output Enable (OE\) on following cycle. Consecutive single
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
3
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
Synchronous Truth Tables
CE1\
CE2
CE3\
ADSP\
ADSC\
ADV
WT / RD
CLK
Address Accessed
Operation
H
X
X
X
L
X
X
NA
Not Selected
L
L
L
L
L
L
X
L
X
H
X
H
L
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
X
L
L
X
L
X
X
X
X
X
X
X
L
L
L
L
H
H
H
X
X
X
X
X
WT
RD
RD
RD
WT
WT
RD
RD
WT
NA
NA
NA
NA
Not Selected
Not Selected
Not Selected
X
H
H
H
X
X
X
X
X
X
X
Not Selected
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
L
L
L
L
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
X
X
X
H
H
WT
Current Address
Suspend Burst, WRITE
Notes:
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
Burst Sequence Tables
Capacitance
Interleaved Burst
Case 2
Parameter
Symbol
Max.
Units
Burst Control
Pin [MODE]
First Address
State
HIGH
Case 1
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
CI
CIO
CCLK
5.0
5.0
5.0
pF
pF
pF
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
Linear Burst
Burst Control
Pin [MODE]
State
LOW
Case 1
Case 2
A1
Case 3
Case 4
A1
A0
A0
A1
A0
A1
A0
First Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
Write Table
Asynchronous Truth Table
GW\
BW\
BWa\
BWb\
BWc\
BWd\
Operation
Operation
ZZ
OE\
I/O Status
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
H
L
H
H
L
X
H
H
L
H
L
X
H
H
H
L
X
H
H
H
L
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
Power-Down (SLEEP)
H
L
X
L
High-Z
DQ
READ
L
L
L
H
X
X
High-Z
Din, High-Z
High-Z
WRITE
De-Selected
L
X
L
X
X
X
Absolute Maximum Ratings*
AC Test Loads
Parameter
Symbol
Min.
Max.
Units
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
VDD
VDDQ
VIN
VIO
PD
tSTG
/CT
/IT
-0.3
VDD
-0.3
-0.3
4.6
V
V
Output
VDD+0.3
VDDQ+0.3
1.6
V
Rt = 50 ohm
Zo=50 ohm
Diagram [A]
V
W
οC
οC
οC
οC
οC
30 pF
-65
0
150
70
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
Vt= Termination Voltage
Rt= Termination Resistor
-40
-40
-55
85
/ET
/XT
105
125
R= 317 ohm@3.3v
R= 1667 ohm@2.5v
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum conditions for any duration or segment of time may affect
device reliability.
Output
5 pF
3.3/2.5v
R= 351 ohm@3.3v
R= 1538 ohm@2.5v
Diagram [B]
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
4
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
DC Electrical Characteristics (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Symbol
Parameter
Test Conditions
Min
Max
3.630
VDD
Units
Notes
VDD
VDDQ
VoH
Power Supply Voltage
I/O Supply Voltage
Output High Voltage
3.135
2.375
2.4
V
V
V
V
V
V
V
V
V
1
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
2
VoL
VIH
VIL
Output Low Voltage
Input High Voltage
Input Low Voltage
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
2
1.7
-0.3
-0.3
-5
-30
-5
V
IIL
Input Leakage (except ZZ)
Input Leakage, ZZ pin
Output Leakage
VDD=Max., VIN=VSS to VDD
uA
uA
uA
mA
mA
mA
IZZL
IOL
IDD
3
Output Disabled, VOUT=VSSQ to VDDQ
VDD=Max., f=Max.,
Operating Current
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
265
240
225
IOH=0mA
ISB1
Automatic CE. Power-down
Current -TTL inputs
Max. VDD, Device De-Selected,
VIN>/=VIH or VIN</=VIL
f=fMAX=1/tCYC
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
110
100
90
mA
mA
mA
mA
ISB2
ISB4
ISB3
Automatic CE. Power-down
Current - CMOS Inputs
Automatic CE. Power-down
Current -TTL inputs
Automatic CE. Power-down
Current - CMOS Inputs
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
40
f=fMAX=1/tCYC
Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0
45
mA
Max. VDD, Device De-Selected, or
VIN</=0.3v or VIN >/=VDDQ-0.3v,
f-Max=1/tCYC
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
95
85
75
mA
mA
mA
Thermal Resistance
Symbol
θJA
Description
Conditions
Typical
Units
Notes
Thermal Resistance
(Junction to Ambient)
Test Conditions follow standard test methods and
procedures for measuring thermal impedance, as
per EIA/JESD51
1-Layer
42
0C/W
6
Thermal Resistance
θJC
(Junction to Top of Case, Top)
9
0C/W
6
Notes:
[1]
[2]
All Voltages referenced to VSS (Logic Ground)
Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
[3]
[4]
MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
This parameter is sampled
[5]
[6]
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
5
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
AC Switching Characteristics (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
-26 [250Mhz]
Min. Max.
-30 [200Mhz]
-35 [166Mhz]
-40 [133Mhz]
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Units
Notes
Clock (CLK) Cycle Time
Clock (CLK) High Time
Clock (CLK) Low Time
Clock Access Time
Clock (CLK) High to Output Low-Z
Clock High to Output High-Z
Output Enable to Data Valid
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Address Set-up to CLK High
tCYC
tCH
tCL
4.00
1.70
1.70
-
1.25
1.25
-
1.25
0.00
-
1.00
0.50
1.00
0.50
1.00
0.50
1.00
0.50
1.00
0.50
1.00
0.50
-
-
5.00
2.00
2.00
-
-
6.00
2.50
2.50
-
-
7.50
3.00
3.00
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
cycles
1
1
2
-
2.60
-
2.60
2.60
-
-
3.00
-
3.00
3.00
-
-
3.50
-
3.50
3.50
-
-
4.00
-
3.50
4.00
-
tCD
tCLZ
tCHZ
tOE
1.25
1.25
-
1.25
0.00
-
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
1.25
1.25
-
1.25
0.00
-
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.25
1.25
-
1.25
0.00
-
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
2,3,4,5
2,3,4,5
6
tOH
tOELZ
tOEHZ
tAS
-
-
-
-
2,3,4,5
2,3,4,5
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
2.60
3.00
3.50
3.50
Address Hold from CLK High
tAH
Address Status Set-up to CLK High
Address Status Hold from CLK High
Address Advance Set-up to CLK High
Address Advance Hold from CLK High
Chip Enable Set-up to CLK High (CEx\, CE2)
Chip Enable Hold from CLK High (CEx\, CE2)
Data Set-up to CLK High
tASS
tASH
tADVS
tADVH
tCES
tCEH
tDS
Data Hold from CLK High
tDH
Write Set-up to CLK High (GW\, BWE\, BWx\)
Write Hold from CLK High (GW\, BWE\, BWX\)
ZZ High to Power Down
tWES
tWEH
tPD
7,8
2
2
2
2
ZZ Low to Power Up
tPU
2
2
2
2
Notes to Switching Specifications:
1.
2.
3.
4.
5.
6.
7.
8.
Measured as HIGH when above VIH and Low when below VIL
This parameter is measured with the output loading shown in AC Test Loads
This parameter is sampled
Transition is measured +500mV from steady state voltage
Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention
OE\ is a Don't Care when a Byte or Global Write is sampled LOW
A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times
This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either
ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times
with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid
at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled.
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
6
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
AC Switching Waveforms
Write Cycle Timing
Single Write
tCYC
Burst Write
tCH
Pipelined Write
CLK
tASS
tASH
tCL
ADSP\
ADSP\ Ignored with CE1\ inactive
ADSC\
ADV\
Ax
tASS
tASH
tADVS
A1
ADV\ Must be Inactive for ADSP\ Write
tADVH
A2
A3
tAS
tAH
GW\
tWES
tWEH
tWEH
tWES
BWE\, BWx\
CE1\
tCES
tCEH
CE1\ Masks ADSP\
CE2
CE3\
OE\
tDS
tDH
W1
W2a
W2d
W3
W2b
W2c
DQx,DQPx
DON'T CARE
UNDEFINED
AS5SP128K36DQ
Revision 1.0 03/22/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
7
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
AC Switching Waveforms
Read Cycle Timing
Single Read
tCYC
Burst Read
Pipelined Read
tCH
tCL
CLK
tASS
ADSP\ Ignored with CE1\ Inactive
tASH
ADSP\
ADSC\ Initiated Read
ADSC\
ADV\
Ax
Suspend Burst
tADVS
A1
tADVH
A2
A3
tAS
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
CE1\ Masks ADSP\
tCEH
CE1\
CE2
CE3\
OE\
Unselected with CE2
tOEHZ
tOE
tCD
tOH
R2b
R2a
R2c
R1
R2d
R3a
DQx,DQPx
DON'T CARE
UNDEFINED
AS5SP128K36DQ
Revision 1.0 03/22/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
8
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
AC Switching Waveforms
Read/Write Cycle Timing
Pipelined Read
Burst Read
tCH
tCYC
tCL
CLK
tASS
tASH
ADSP\
ADSC\
ADV\
Ax
tADVS
A1R
tADVH
A2W
tAS
A3W
A4R
A5R
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
tCEH
CE1\
CE2
CE3\
OE\
tCES
tCEH
tOEHZ
A2I
tOE
tOH
A4O
A4O
[a]
A4O
[b]
A4O
[c]
A1O
A3I
DQx,DQPx
[d]
tOELZ
DON'T CARE
tCD
UNDEFINED
AS5SP128K36DQ
Revision 1.0 03/22/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
9
COTS PEM
AS5SP128K36DQ
SSRAM
Austin Semiconductor, Inc.
Power Down (SNOOZE MODE)
Ordering Information
tCD
(ns)
Clock
(Mhz)
Power Down or Snooze is a Power conservation mode which
when building large/very dense arrays, using multiple devices in a
multi-banked or paged array, can greatly reduce the Operating
current requirements of your total memory array solution.
ASI Part Number
Industrial Operating Range (-400C to +850C)
AS5SP128K36DQ-30IT
AS5SP128K36DQ-35IT
AS5SP128K36DQ-40IT
Configuration
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
3.0
3.5
4.0
200
166
133
Enhanced Operating Range (-400C to +1050C)
The device is placed in this mode via the use of the ZZ pin, an
asynchronous control pin which when asserted, places the array
into the lower power or Power Down mode. Awakening the array
or leaving the Power Down (SNOOZE) mode is done so by de-
asserting the ZZ pin .
AS5SP128K36DQ-30ET
128Kx36, 3.3vCore/3.3,2.5vIO
3.0
3.5
4.0
200
166
133
AS5SP128K36DQ-35ET
AS5SP128K36DQ-40ET
128Kx36, 3.3vCore/3.3,2.5vIO
128Kx36, 3.3vCore/3.3,2.5vIO
Extended Operating Range (-550C to +1250C)
AS5SP128K36DQ-35XT
128Kx36, 3.3vCore/3.3,2.5vIO
3.5
4.0
166
133
AS5SP128K36DQ-40XT
128Kx36, 3.3vCore/3.3,2.5vIO
While in the Power Down or Snooze mode, Data integrity is
guaranteed. Accesses pending when the device entered the mode
are not considered valid nor is the completion of the operation
guaranteed. The device must be de-selected prior to entering the
Power Down mode, all Chip Enables, ADSP\ and ADSC\ must
remain inactive for the duration of ZZ recovery time (tZZREC).
ZZ Mode Electrical Characteristics
Parameter
Symbol
IDDzz
Test Conditon
Min.
Max.
Units
Power Down (SNOOZE) Mode
ZZ Active (Signal HIGH) to Power Down tZZS
ZZ Inactive (Signal Low) to Power Up
ZZ >/- VDD - 0.2V
ZZ >/- VDD - 0.2V
ZZ </- 0.2V
10
2 tCYC
mA
ns
ns
tZZR
2 tCYC
ZZ Mode Timing Diagram
Mechanical Diagram
16.00 +/- 0.20mm
1.40 +/- 0.05mm
14.00 +/- 0.10mm
1.60mm Max.
0.30 +/- 0.08
CLK
ADSP\
100 Pin TQFP
14mm x 20mm
JEDEC MS026-D/BHA
ADSC\
CEx\
CE2
ZZ
0.65mm TYP.
See Detail A
tZZS
tZZREC
IDDzz
1.00mm TYP.
0.10 +0.10/-0.05mm
Detail A
IDD
0.10
Seating Plane
Standoff
0.15 MAX
12 +/- 1
0.60 +/- 0.15mm
0.05 MIN
AS5SP128K36DQ
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
Revision 1.0 03/22/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
10
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