AS5SS128K36DQCR-7.5L/XT [MICROSS]
Standard SRAM;
| 型号： | AS5SS128K36DQCR-7.5L/XT |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Standard SRAM 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSRAM
AS5SS128K36
128K x 36 4Mb FLOW THROUGH ‘NO WAIT’
STATE BUS SYNCHRONOUS SRAM
FEATURES
• Available in Mil-Temp*, Enhanced* & Industrial Ranges
• 100 percent bus utilization
• No wait cycles between Read and Write1
• Internal self-timed write cycle
• Individual Byte Write Control
GENERAL DESCRIPTION
TheAS5SS128K36 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
“no wait” state device for networking and communication ap-
plications. It is organized as 128K words by 36 bits fabricated
with Micross’ advanced CMOS technology.
• Single Read / Write control pin
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control using
MODE input
Incorporating a ‘no wait’state feature, wait cycles are eliminated
when the bus switches from read to write, or write to read.
This device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.
• Three chip enables for simple depth expansion
and address pipelining
• Power down mode
• Common data inputs and data outputs
• CKE\ pin to enable clock and suspend operation
• Power Supply: VDD 3.3V ± 5%, VDDQ 3.3V/2.5V ± 5%
• JEDEC 100-Pin TQFP
• TQFP in copper lead frame for superior thermal
performance
All synchronous inputs pass through registers are controlled by
a positive-edge-triggered single clock input. Operations may
be suspended and all synchronous inputs ignored when Clock
Enable, CKE\ is HIGH. In this state the internal device will hold
their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter is
incremented. New external addresses can be loaded when
ADV is LOW.
• RoHs compliant options available
Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when WE\ is LOW. Separate
byte enables allow individual bytes to be written. A burst mode
pin (MODE) defines the order of the burst sequence. When tied
HIGH, the interleaved burst sequence is selected. When tied
LOW, the linear burst sequence is selected.
*Consult factory for /XT and /ET products.
FAST ACCESS TIME
Symbol
Parameter
ClockꢀAccessꢀTime
CycleꢀTime
Ͳ7.5
7.5
Ͳ8.5
8.0
10
Units
ns
tKQ
tKC
8.5
ns
fMAX
Frequency
117
100
MHz
NOTE 1: Otherwise known as (ZBL) Zero Bus Latency.
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
1
SSRAM
AS5SS128K36
BLOCK DIAGRAM
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
2
SSRAM
AS5SS128K36
PIN CONFIGURATIONS
100-pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
DQPc
DQc
DQc
VDDQ
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
Vss
DQc
DQc
DQb
DQb
DQc
DQc
Vss
DQb
DQb
Vss
VDDQ
DQc
VDDQ
DQb
DQc
NC
DQb
Vss
NC
VDD
NC
Vss
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQd
DQd
VDDQ
Vss
DQd
DQa
DQa
DQd
DQd
DQd
Vss
DQa
DQa
Vss
VDDQ
VDDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SynchronousꢀAddressꢀInputs.ꢀThese
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀthe
addressꢀbus.
SynchronousꢀAddressꢀInputs.ꢀꢀ
SynchronousꢀClock
A0,ꢀA1
CE\,ꢀCE2,ꢀCE2\ SynchronousꢀChipꢀEnable
OE\ OutputꢀEnable
DQaꢀͲꢀDQd SynchronousꢀDataꢀInputꢀ/ꢀOutput
DQPaͲDQPd ParityꢀDataꢀI/O
Aꢀ
CLK
ADV
SynchronousꢀBurstꢀAddressꢀAdvance
BWa\ꢀ,ꢀBWd\ SynchronousꢀByteꢀWriteꢀEnable
MODE
VDD
BurstꢀSequenceꢀModeꢀSelection
ꢀ+3.3Vꢀ/ꢀ2.5VꢀPowerꢀSupply
Ground
WE\
CKE\
WriteꢀEnable
ClockꢀEnable
VSS
VDDQ
ZZ
VSS
NC
Ground
IsolatedꢀOutputꢀBufferꢀSupply:ꢀ3.3V/2.5V
SnoozeꢀEnable
NotꢀConnetcted
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
3
SSRAM
AS5SS128K36
STATE DIAGRAM
READ
WRITE
BEGIN
BEGIN
WRITE
WRITE
READ
READ
DS
DS
READ
WRITE
DESELECT
READ
BURST
BURST
WRITE
BURST
DS
DS
DS
WRITE
BURST
BURST
BURST
WRITE
BURST
READ
READ
SYNCHRONOUS TRUTH TABLE 1
Operation
NotꢀSelected
NotꢀSelected
AddressꢀUsed
N/A
OE\
H
X
X
X
L
X
L
X
L
X
L
X
CE2
X
H
X
X
H
X
H
X
H
X
H
X
X
CE2\
X
X
H
X
L
X
L
X
L
ADV
L
L
L
H
L
H
L
H
L
H
L
H
X
WE\
X
X
X
X
H
X
H
X
L
X
BWx\
OE\
X
X
X
X
L
L
H
H
X
CKE\
CLK
ј
ј
ј
ј
ј
ј
ј
ј
ј
ј
ј
ј
ј
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
N/A
N/A
N/A
NotꢀSelected
NotꢀSelectedꢀContinue
BeginꢀBurstꢀRead
ContinueꢀBurstꢀRead
NOP/DummyꢀRead
DummyꢀRead
BeginꢀBurstꢀWrite
ContinueꢀBurstꢀWrite
NOP/WriteꢀAbort
WriteꢀAbort
ExternalꢀAddress
NextꢀAddress
ExternalꢀAddress
NextꢀAddress
ExternalꢀAddress
NextꢀAddress
N/A
X
L
X
X
L
X
X
X
X
L
X
X
H
H
X
NextꢀAddress
CurrentꢀAddress
IgnoreꢀClock
X
Notes:
1.ꢀXꢀmeansꢀ“Don’tꢀCare.”ꢀ
2.ꢀTheꢀrisingꢀedgeꢀofꢀclockꢀisꢀsymbolizedꢀbyꢀј.
3.ꢀAꢀcontinueꢀdeselectꢀcycleꢀcanꢀonlyꢀbeꢀenteredꢀifꢀaꢀdeselectedꢀcycleꢀisꢀexcecutedꢀfirst.
4.ꢀWE\ꢀ=ꢀLꢀmeansꢀwriteꢀoperationꢀinꢀwriteꢀtruthꢀtable.ꢀꢀWE\=Hꢀmeansreadꢀoperationꢀinꢀwriteꢀtruthꢀtable.
5.ꢀOperationꢀfinallyꢀdependsꢀonꢀstatusꢀofꢀasynchronousꢀpinsꢀ(ZZꢀandꢀOE\)
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
4
SSRAM
AS5SS128K36
ASYNCHRONOUS TRUTH TABLE 1
Function
SleepꢀMode
ZZ
H
L
OE\
X
L
I/OꢀStatus
HighͲZ
DQ
HighͲZ
Read
L
H
Writeꢀꢀ
Deselected
Notes:
L
L
X
X
Din,ꢀHighͲZ
HighͲZ
1.ꢀXꢀmeansꢀ“Don’tꢀCare.”ꢀ
2.ꢀForꢀwriteꢀcyclesꢀfollowingꢀreadꢀcycles,ꢀtheꢀoutputꢀbuffersꢀmustꢀbeꢀdisabledꢀwithꢀOE\,ꢀotherwiseꢀdataꢀbusꢀcontentionꢀwillꢀoccur.
3.ꢀSleepꢀModeꢀmeansꢀpowerꢀSleepꢀModeꢀwhereꢀstandͲbyꢀcurrentꢀdoesꢀnotꢀdependꢀonꢀcycleꢀtime.
4.ꢀDeselectedꢀmeansꢀpowerꢀSleepꢀModeꢀwhereꢀstandͲbyꢀcurrendꢀdependsꢀonꢀcycleꢀtime.
WRITE TRUTH TABLE
Operation
WE\
Bwa\
BWb\
BWc\
BWd\
Read
H
L
L
L
L
L
L
X
L
H
H
H
L
X
H
L
H
H
L
X
H
H
L
H
L
X
H
H
H
L
WRITEꢀBYTEꢀa
WRITEꢀBYTEꢀb
WRITEꢀBYTEꢀc
WRITEꢀBYTEꢀd
WRITEꢀALLꢀBYTEs
L
H
WRITEꢀABORTꢀ/ꢀNOP
Notes:
H
H
H
1.ꢀXꢀmeansꢀ“Don’tꢀCare.”ꢀ
2.ꢀAllꢀinputsꢀinꢀthisꢀtableꢀmustꢀbeetꢀsetupꢀandꢀholdꢀtimeꢀaroundꢀtheꢀrisingꢀedgeꢀofꢀCLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
ExternalꢀAddress 1stꢀBurstꢀAddress 2ndꢀBurstꢀAddress 3rdꢀBurstꢀAddress
A1ꢀA0
00
A1ꢀA0
01
A1ꢀA0
10
A1ꢀA0
11
01
00
11
10
10
11
00
01
11
10
01
00
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
5
SSRAM
AS5SS128K36
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAxIMUM RATINGS1
Symbol
TSTG
Parameter
StorageꢀTemperature
Value
Unit
oC
ꢀͲ55ꢀtoꢀ+150
1.6
PD
PowerꢀDissipation
W
mA
V
IOUT
OutputꢀCurrentꢀ(perꢀI/O)
100
VIN,ꢀVOUT
VINꢀ
–0.5ꢀtoꢀVDDꢀ+ꢀ0.3
ꢀͲ0.3ꢀtoꢀ4.6
VoltageꢀRelativeꢀtoꢀVssꢀforꢀI/OꢀPins
VoltageꢀRelativeꢀtoꢀVssꢀforꢀAddressꢀandꢀControlꢀInputs
V
Notes:
1.ꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀ
onlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀ
specificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.
2.ꢀThisꢀdeviceꢀcontainsꢀcircuityꢀtoꢀprotectꢀtheꢀinputsꢀagainstꢀdamageꢀdueꢀtoꢀhighꢀstaticꢀvoltagesꢀorꢀelectricꢀfields;ꢀhowever,ꢀprecautionsꢀmayꢀ
beꢀtakenꢀtoꢀavoidꢀapplicationꢀofꢀanyꢀvoltageꢀhigherꢀthanꢀmaximumꢀratedꢀvoltagesꢀtoꢀthisꢀhighͲimpedanceꢀcircuit.
3.ꢀThisꢀdeviceꢀcontainsꢀcircuitryꢀthatꢀwillꢀensureꢀtheꢀoutputꢀdevicesꢀareꢀinꢀHighͲZꢀatꢀpowerꢀup.
OPERATING RANGE
VDD
VDDQ
Range
Industrial
Enhanced
Military
AmbientꢀTemperature
ꢀͲ40oCꢀtoꢀ+85oC
3.3V±5% 3.3V/2.5V±5%
3.3V±5% 3.3V/2.5V±5%
3.3V±5% 3.3V/2.5V±5%
ꢀͲ40oCꢀtoꢀ+105oC
ꢀͲ55oCꢀtoꢀ+125oC
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
6
SSRAM
AS5SS128K36
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
VOH
Parameter
TestꢀConditions
IOHꢀ=ꢀ–4.0ꢀmA
Min
2.4
ꢀͲ
Max
ꢀͲ
Unit
V
OutputꢀHIGHꢀVoltage
OutputꢀLOWꢀVoltage
InputꢀHIGHꢀVoltage
InputꢀLOWꢀVoltage
VOL
VIH
VIL
ILI
IOLꢀ=ꢀ8.0ꢀmA
0.4
V
VDDꢀ+ꢀ0.3
ꢀ2.0
Ͳ0.3
V
0.8
5
V
1
VSSꢀчꢀVINꢀчꢀVDD
InputꢀLeakageꢀCurrent
OutputꢀLeakageꢀCurrent
Ͳ5
Ͳ5
μA
μA
ILO
VSSꢀчꢀVOUTꢀчꢀVDDQ,ꢀOE\ꢀ=ꢀVIH
5
POWER SUPPLY CHARACTERISTICS1 (Over Operating Range)
Symbol
Parameter
TestꢀCondition
Max
Unit
DeviceꢀSelected,ꢀOE\ꢀ=ꢀ
VIH,ꢀZZꢀчꢀVIL,ꢀAllꢀInputsꢀчꢀ
0.2VꢀorꢀшꢀVDDꢀͲ0.2V,ꢀCycleꢀ
TimeꢀшꢀtKCꢀmin.
ACꢀOperatingꢀSupplyꢀ
ICC
225
mA
Current
DeviceꢀDeselected,ꢀ
VDD=Max,ꢀAllꢀInputsꢀчꢀVILꢀ
orꢀшꢀVIH,ꢀZZꢀꢀчꢀVIL,ꢀf=Max
StandbyꢀCurrentꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
TTLꢀInputs
ISB
100
mA
DeviceꢀDeselected,ꢀ
VDD=Max,ꢀVINꢀꢀчꢀVSSꢀorꢀшꢀ
VDDꢀͲꢀ0.2Vꢀf=0
StandbyꢀCurrentꢀꢀꢀꢀꢀꢀꢀꢀꢀ
CMOSꢀInput
ISB1
ISB2
75
60
mA
mA
ZZ>VIH
SleepꢀMode
Note:
1.ꢀMODEꢀpinꢀhasꢀanꢀinternalꢀpullupꢀandꢀshouldꢀbeꢀtiedꢀtoꢀVddꢀorꢀVss.ꢀItꢀexhibitsꢀ±100ꢀʅAꢀmaximumꢀleakageꢀcurrentꢀwhenꢀtiedꢀtoꢀчꢀVssꢀ+ꢀ
0.2VꢀorꢀшꢀVddꢀ–ꢀ0.2V.
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
7
SSRAM
AS5SS128K36
CAPACITANCE1,2
Symbol
Parameter
InputꢀCapacitance
Conditions
VINꢀ=ꢀ0V
Max
6
8
Min
pF
CIN
CI/O
VOUTꢀ=ꢀ0V
Input/OutputꢀCapacitance
pF
Notes:
1.ꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀTestꢀconditions:ꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
THERMAL RESISTANCE
100ꢀTQFPꢀ
Package
Parameter
ȺꢀJA
Description
ThermalꢀResistanceꢀ
(JunctionꢀtoꢀAmbient)
ThermalꢀResistanceꢀ
(JunctionꢀtoꢀCase)
TestꢀConditions
Unit
Testꢀconditionsꢀfollowꢀstandardꢀtestꢀ
methodsꢀandꢀproceduresꢀforꢀ
measuringꢀthermalꢀimpedance,ꢀperꢀ
EIA/JESD51
oC/W
35.25
oC/W
ȺꢀJC
7.96
3.3V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevel
InputꢀRiseꢀandꢀFallꢀTimes
Unit
0Vꢀtoꢀ3V
1.5ꢀns
InputꢀandꢀOutputꢀTimingꢀandꢀ
1.5V
ReferenceꢀLevelꢀ(VREF
OutputꢀLoad
)
SeeꢀFiguresꢀ1ꢀ&ꢀ2
AC TEST LOADS
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
5 pF
50Ω
Including
jig and
scope
351 Ω
1.5V
Figure 1
Figure 2
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
8
SSRAM
AS5SS128K36
2.5V I/O AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevel
InputꢀRiseꢀandꢀFallꢀTimes
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ
OutputꢀLoad
Unit
0Vꢀtoꢀ2.5V
1.5ꢀns
1.25V
SeeꢀFiguresꢀ3&4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
9
SSRAM
AS5SS128K36
READ/WRITE CYCLE SWITCHING CHARACTERISTICS1 (OverOperating Range)
Ͳ7.5 Ͳ8
Symbol
Parameter
Min
Max
Min
Max
Unit
fMAX
ClockꢀFrequency
ꢀͲ
117
ꢀͲ
100
ꢀͲ
MHz
tKC
tKH
tKL
CycleꢀTime
ClockꢀHighꢀTime
8.5
2.5
2.5
ꢀͲ
ꢀͲ
ꢀͲ
10
4.0
4.0
ꢀͲ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
ꢀͲ
ClockꢀLowꢀTime
ꢀͲ
ꢀͲ
tKQ
ClockꢀAccessꢀTime
7.5
ꢀͲ
8.0
ꢀͲ
2
tKQX
ClockꢀHighꢀtoꢀOutputꢀInvalid
ClockꢀHighꢀtoꢀOutputꢀLowͲZ
ClockꢀHighꢀtoꢀOutputꢀHighͲZ
OutputꢀEnableꢀtoꢀOutputꢀValid
OutputꢀEnableꢀtoꢀOutputꢀLowͲZ
OutputꢀEnableꢀtoꢀOutputꢀHighͲZ
AddressꢀSetupꢀTime
2
2.5
2.5
ꢀͲ
2,3
tKQLZ
2
ꢀͲ
ꢀͲ
2,3
tKQHZ
ꢀͲ
4.0
3.4
ꢀͲ
4.2
3.6
ꢀͲ
tOEQ
ꢀͲ
ꢀͲ
2,3
tOELZ
0
0
2,3
tOEHZ
ꢀͲ
3.5
ꢀͲ
ꢀͲ
3.5
ꢀͲ
tAS
tWS
tCES
tSE
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
ꢀͲ
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
ꢀͲ
Read/WriteꢀSetupꢀTime
ChipꢀEnableꢀSetupꢀTime
ClockꢀEnableꢀSetupꢀTime
AddressꢀAdvanceꢀSetupꢀTime
DataꢀSetupꢀTime
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
tADVS
tDS
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
tAH
AddressꢀHoldꢀTime
ꢀͲ
ꢀͲ
tHE
ClockꢀEnableꢀHoldꢀTime
WriteꢀHoldꢀTime
ꢀͲ
ꢀͲ
tWH
tCEH
tADVH
tDH
ꢀͲ
ꢀͲ
ChipꢀEnableꢀHoldꢀTime
AddressꢀAdvanceꢀHoldꢀTime
DataꢀHoldꢀTime
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
ꢀͲ
tPDS
ZZꢀHighꢀtoꢀPowerꢀDown
ZZꢀLowꢀtoꢀPowerꢀDown
2
2
tPUS
ꢀͲ
2
ꢀͲ
2
Notes:
1.ꢀConfigurationꢀsignalꢀMODEꢀisꢀstaticꢀandꢀmustꢀnotꢀchangeꢀduringꢀnormalꢀoperation.
2.ꢀGuaranteedꢀbutꢀnotꢀ100%ꢀtested.ꢀThisꢀparameterꢀisꢀperiodicallyꢀsampled
3.ꢀTestedꢀwithꢀloadꢀinꢀFigureꢀ2.
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
10
SSRAM
AS5SS128K36
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
CurrentꢀduringꢀSNOOZEꢀMODE
ZZꢀactiveꢀtoꢀinputꢀignored
Conditions
ZZшVih
Min
ꢀͲ
Max Unit
ISB2
60
2
mA
cycle
cycle
cycle
ns
tPDS
tPUS
tZZI
ꢀͲ
ZZꢀinactiveꢀtoꢀinputꢀsampled
ZZꢀactiveꢀtoꢀSNOOZEꢀcurrent
ZZꢀinactiveꢀtoꢀexitꢀSNOOZEꢀcurrent
2
ꢀͲ
2
ꢀͲ
tRZZI
0
ꢀͲ
SLEEP MODE TIMING
CLK
t
PDS
t
ZZ setup cycle
ZZ recovPeUryS cycle
ZZ
t
ZZI
Isupply
I
SB2
t
RZZI
All Inputs
Deselect or Read Only
Deselect or Read Only
(except ZZ)
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
11
SSRAM
AS5SS128K36
READ CYCLE TIMING
tKH
tKL
CLK
tKC
tADVS tADVH
ADV
t
AS tAH
Address
A1
A2
A3
tWS
tWH
WRITE
CKE
tSE tHE
tCES
tCEH
CE
OE
t
DS
KQ
t
OEQ
t
OEHZ
t
t
KQHZ
Q3-4
t
OEHZ
Data Out
Q1-1
Q2-1
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
12
SSRAM
AS5SS128K36
WRITE CYCLE TIMING
tKH
t
KL
CLK
ADV
tKC
Address
WRITE
CKE
A1
A3
A2
tSE
t
HE
CE
OE
tDS
tDH
Data In
Data Out
D1-1
D2-1
D2-2
D2-4
D3-1
D3-2
D3-3
D3-4
D2-3
t
OEHZ
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
Don't Care
Undefined
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
13
SSRAM
AS5SS128K36
SINGLE READ / WRITE CYCLE TIMING
tKH
tKL
CLK
t
SE tHE
tKC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ADV
OE
tOEQ
t
OELZ
Data Out
Data In
Q1
Q3
Q4
Q6
Q7
tDS tDH
D2
D5
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
14
SSRAM
AS5SS128K36
CKE\ OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
Address
WRITE
CE
A1
A2
A3
A4
A5
A6
ADV
OE
t
KQ
t
KQHZ
t
KQLZ
Q4
Data Out
Data In
Q1
Q3
t
DS
t
DH
D5
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
Don't Care
Undefined
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
15
SSRAM
AS5SS128K36
CE\ OPERATION TIMING
t
KH
tKL
CLK
t
SE tHE
t
KC
CKE
A1
A2
A3
A4
A5
Address
WRITE
CE
ADV
OE
t
OEQ
t
KQHZ
t
KQ
tOELZ
tKQLZ
Q1
Q2
Q4
Data Out
Data In
t
DS
tDH
D3
D5
Don't Care
Undefined
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
16
SSRAM
AS5SS128K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQ)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
1.00 REF.
0.20 MIN.
DETAIL
A
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
17
SSRAM
AS5SS128K36
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQC & DQCR)
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
ThinꢀQuadꢀFlatꢀPack
Millimeters
Inches
Notes:
Symbol
Ref.ꢀStd.
Min
Max
Min
Max
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
No.ꢀLeadsꢀ(N)ꢀ100
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
A
ꢀͲ
1.60
0.15
1.45
ꢀͲ
0.063
0.006
0.057
0.015
A10.05
0.002
0.053
0.009
A2
1.35
0.22
b
0.38
3. Controlling dimension:
millimeters.
D
21.90
22.10
0.852
0.870
D1
19.9
0
2
0.
1
0
0.783
0.791
E
15.90
16.10
14.10
0.626
0.547
0.634
E1
13.90
0.555
e
0.65ꢀBSC
0.026ꢀBSC
L
0.45
0.750.018
0.030
L1
1.00ꢀREF
0.039ꢀREF
C
0O
7O
0O
7O
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
18
SSRAM
AS5SS128K36
ORDERING INFORMATION
TQFP
Example:ꢀAS5SS128K36DQͲ7.5/IT
Packageꢀ
Speedꢀꢀꢀꢀ
tKQꢀ(ns)
Type
DeviceꢀNumber
Process
AS5SS128K36
AS5SS128K36
DQ
DQ
Ͳ7.5
Ͳ8
/*
/*
TQFPͲCopperꢀLeadꢀFrameꢀͲꢀPb/SnꢀLeadꢀFinish
Example:ꢀAS5SS128K36DQCͲ8/XT
Packageꢀ
DeviceꢀNumber
AS5SS128K36
AS5SS128K36
Type
DQC
DQC
Speedꢀ(ns) Process
Ͳ7.5
Ͳ8
/*
/*
TQFPͲCopperꢀLeadꢀFrameꢀͲꢀNiPdAuꢀLeadꢀFinishꢀ(RoHSꢀCompliant)
Example:ꢀAS5SS128K36DQCRͲ7.5/IT
Packageꢀ
DeviceꢀNumber
AS5SS512K18
AS5SS128K36
Type
DQCR
DQCR
Speedꢀ(ns) Process
Ͳ7.5
Ͳ8
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
ET = Enhanced Temperature Range
XT = Military Temperature Range
-40oC to +85oC
-40oC to +105oC (Consult Factory)
-55oC to +125oC (Consult Factory)
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
19
SSRAM
AS5SS128K36
DOCUMENT TITLE
Rev #
History
Release Date
Status
2.6
Updated Micross Information
October 2010
Release
2.7
Added -7.5 & -8 speeds, deleted
-11 & -12 speeds, added copper lead
frame and RoHS compliant options,
complete redo per ISSI source
datasheet.
May 2011
Release
Release
2.8
Added Thermal Resistance table,
page 8.
September 2011
Micross Components reserves the right to change products or specifications without notice.
AS5SS128K36
Rev. 2.8 09/11
20
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