MT42C4256CZ-12/883 [MICROSS]
Video DRAM,;
| 型号： | MT42C4256CZ-12/883 |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Video DRAM, 动态存储器 |
| 文件： | 总58页 (文件大小：4989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VRAM
SMJ44C251B
MT42C4256
256K X 4 VRAM
256K x 4 DRAM
PIN ASSIGNMENT
(Top View)
with 512K x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89497
• MIL-STD-883
28-Pin DIP (C)
(400 MIL)
28-Pin SOJ (DCJ)
28-Pin LCC (EC)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
1
2
3
4
5
6
Vss
SDQ4
SDQ3
Vss
28
27
26
1
2
3
4
5
6
7
8
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
28
27
26
25
24
23
22
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
25 SE\
24 DQ4
23 DQ3
DQ2
7
8
ME\/WE\
NC
22
DSF
FEATURES
21 CAS\
21 CAS\
20 QSF
19 A0
9
20
19
18
17
16
15
RAS\
A8
A6
A5
A4
QSF
A0
A1
A2
A3
A7
9
• Class B High-Reliability Processing
10
11
12
13
10
11
12
13
14
• DRAM: 262144 Words × 4 Bits
SAM: 512 Words × 4 Bits
18
17
16
15
A1
A2
A3
A7
• Single 5-V Power Supply (±10% Tolerance)
• Dual Port Accessibility–Simultaneous and Asynchronous Access
From the DRAM and SAM Ports
• Bidirectional-Data-Transfer Function Between the DRAM and the
Serial-Data Register
• 4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many
as Four Memory Address Locations Written per Cycle From an
On-Chip Color Register
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden Refresh Modes
• All Inputs/Outputs and Clocks Are TTL Compatible
• Long Refresh Period: Every 8 ms (Max)
• Up to 33-MHz Uninterrupted Serial-Data Streams
• 3-State Serial I/Os Allow Easy Multiplexing of Video-Data
Streams
Vcc 14
Vcc
28-Pin ZIP (CZ)
1
3
5
7
DSF
DQ3
SDQ2
Vss
SDQ0
TRG\
DQ1
GND
A8
A5
Vcc
A3
A1
DQ2
SE\
SDQ3
SC
SDQ1
DQ0
W\
RAS\
A8
2
4
6
8
9
10
12
14
16
18
20
22
11
13
15
17
19
21
23
25
27
A4
A7
24 A2
26 A0
28 CAS\
QSF
28-Pin FP (F)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
1
2
3
4
5
6
7
8
Vss
28
• 512 Selectable Serial-Register Starting
• Split Serial-Data Register for Simplified Real-Time Register Reload
27
26
25
24
23
22
21
20
19
18
17
16
15
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
OPTIONS
• Timing
MARKING
9
100ns, 30ns/27ns
120ns, 35ns/35ns
-10
-12
RAS\
A8
A6
A5
A4
10
11
12
13
14
• Package(s)
MT Prefix
SMJ Prefix
Vcc
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic ZIP
Ceramic LCC
DCJ
C
EC
CZ
---
F
---
PIN NAME
(SMJ)
A0 - A8
CAS\
DQ0 - DQ3
SE\
PIN NAME
(MT)
A0 - A8
CAS\
JDM
HMM
SVM
HJM
---
DESCRIPTION
Address Inputs
Column Enable
DQ1 - DQ4 DRAM Data In-Out/Write-Mask Bit
SE\
RAS\
SC
Serial Enable
Row Enable
Serial Data Clock
RAS\
SC
Ceramic Flat Pack
SDQ0 - SDQ3 SDQ1 - SDQ4 Serial Data In-Out
TRG\
W\
DSF
QSF
Vcc
TR\ /OE\
ME\ /WE\
DSF
QSF
Vcc
Transfer Register/Q Output Enable
Write-Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5V Supply
For more products and information
please visit our web site at
www.micross.com
Vss
Vss
Ground
Ground (Important: Not Connected to
internal Vss, Pin should be left open or
tied to ground.
GND
NC
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
1
VRAM
SMJ44C251B
MT42C4256
DESCRIPTION
The SMJ44C251B/MT42C4256 multiport video RAM is a
high-speed, dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262144 words
of 4 bits each interfaced to a serial-data register or serial-access
memory (SAM) organized as 512 words of 4 bits each. The
SMJ44C251B/MT42C4256 supports three types of operation:
random access to and from the DRAM, serial access to and from
the serial register, and bidirectional transfer of data between any
row in the DRAM and the serial register. Except during transfer
operations, the SMJ44C251B/MT42C4256 can be accessed
simultaneously and asynchronously from the DRAM and SAM
ports.
applications not requiring real-time register reload (for example,
reloads done during CRT retrace periods), the single-register
mode of operation is retained to simplify design. The SAM can
also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is loaded,
its contents can be transferred to the corresponding column posi-
tions in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data
can be input to or accessed from the SAM at serial rates up to
33 MHz. During the split-register mode of operation, internal
circuitry detects when the last bit position is accessed from the
active half of the register and immediately transfers control to the
During a transfer operation, the 512 columns of the DRAM
are connected to the 512 positions in the serial data register. The
512 × 4-bit serial-data register can be loaded from the memory
row (transfer read), or the contents of the 512 × 4-bit serial-data
register can be written to the memory row (transfer write).
The SMJ44C251B/MT42C4256 is equipped with several
features designed to provide higher system-level bandwidth and
to simplify design integration on both the DRAM and SAM ports.
On the DRAM port, greater pixel draw rates can be achieved
by the device’s 4 × 4 block-write mode. The block-write mode
allows four bits of data (present in an on-chip color-data register)
to be written to any combination of four adjacent column-address
locations. As many as 16 bits of data can be written to memory
during each CAS cycle time. Also on the DRAM port, a write
mask or a write-per-bit feature allows masking any combina-
tion of the four input/outputs on any write cycle. The persistent
write-per-bit feature uses a mask register that, once loaded, can
be used on subsequent write cycles. The mask register eliminates
having to provide mask data on every mask-write cycle.
The SMJ44C251B/MT42C4256 offers a split-register
transfer read (DRAM to SAM) feature for the serial tester
(SAM port). This feature enables real-time register reload
implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high
half and a low half. While one half is being read out of the SAM
port, the other half can be loaded from the memory array. For
opposite half. A separate output, QSF, is included to
dicate which half of the serial register is active at any given time
in the split-register mode.
in-
All inputs, outputs, and clock signals on the SMJ44C251B/
MT42C4256 are compatible with Series 54 TTL devices. All
address lines and data-in lines are latched on-chip to simplify
system design. All data-out lines are unlatched to allow greater
system flexibility.
Enhanced page-mode operation allows faster memory ac-
cess by keeping the same row address while selecting random
column addresses. The time for row-address setup, row-address
hold, and address multiplex is eliminated, and a memory cycle
time reduction of up to 3× can be achieved, compared to mini-
mum RAS cycle times. The maximum number of columns that
can be accessed is determined by the maximum RAS low time
and page-mode cycle time used. The SMJ44C251B/MT42C4256
allows a full page (512 cycles) of
information to be accessed in
read, write, or read-modify-write mode during a single RAS-low
period using relatively conservative page-mode cycle times.
The SMJ44C251B/MT42C4256 employs state-of-the-art
technology for very high performance combined with improved
reliability.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
2
VRAM
SMJ44C251B
MT42C4256
FUNCTIONAL BLOCK DIAGRAM
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
3
VRAM
SMJ44C251B
MT42C4256
FUNCTION TABLE
CAS\
FALL
RAS\ FALL
ADDRESS
RAS\ CAS\
DQ0 - DQ3
TYPE3
FUNCTION
CAS\2
W\1
X
CAS\ TRG\
DSF
SE\
DSF
RAS\
W\
CBR Refresh
Register-to-memory transfer
(transfer write)
L
X
L
X
X
X
L
X
X
X
Row
Addr
Row
Addr
Refresh
Addr
Row
Addr
Row
Addr
Row
Addr
X
Tap
Point
Tap
Point
Tap
Point
Tap
Point
Tap
Point
Col
Addr
X
X
X
R
T
H
L
X
X
X
X
Alternate transfer write
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(transfer read)
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
T
T
L
H
H
L
L
T
Split-register-transfer read
(must reload tap)
L
H
L
X
X
T
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
DQ
Mask Data
DQ Col
Valid
L
R
R
R
R
R
R
R
R
Row Blk Addr
H
H
H
H
H
H
H
L
L
H
L
Addr
Row
Addr
A2-A8
Col
Addr
Mask Mask
Valid
Data
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
L
H
H
L
X
Row Blk Addr
L
H
L
X
Addr
Row
Addr
A2-A8
Col
Addr
H
H
H
H
X
Block write to DRAM
(nonmasked)
Row Blk Addr
L
H
L
X
Addr
Refresh
Addr
Refresh
Addr
A2-A8
Load write mask
H
H
X
X
Load color register
H
X
X
NOTES:
1. In persistent write-per-bit function, W\ must be high during the refresh cycle.
2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled.
3. R = random access operation, T = transfer operation.
LEGEND
H = HIGH
L = LOW
X = Don’t Care
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
4
VRAM
SMJ44C251B
MT42C4256
DETAILED SIGNAL DESCRIPTION VS. OPERATIONAL MODE
PIN
A0 - A8
DRAM
Row, column address
TRANSFER
Row, tap address
SAM
CAS\
DQi
Column enable, output enable
DRAM data I/O, write mask bits
Block-write enable
Persistent write-per-bit enable
Color-register load enable
Row enable
Tap-address strobe
Split-register enable
Alternative write-transfer enable
DSF
RAS\
SE\
Row enable
Serial-in mode enable
Serial enable
Serial clock
SC
SDQ
TRG\
W\
Serial-data I/O
Q output enable
Write enable, write-per-bit select
Transfer enable
Transfer-write enable
Split register
Active status
QSF
Make no external connection or tie
to system Vss
NC/GND
Vcc
Vss
5V supply (typical)
Device ground
ROW-ADDRESS STROBE (RAS\)
OPERATION
RAS\ is similar to a chip enable because all DRAM cycles
and transfer cycles are initiated by the falling edge of RAS\.
RAS\ is a control input that latches the states of row address,
W\, TRG\, SE\, CAS\, and DSF onto the chip to invoke DRAM
and transfer functions.
Depending on the type of operation chosen, the signals of
the SMJ44C251B/MT42C4256 perform different functions.
The “Detailed Signal Description vs. Operational Mode” table
summarizes the signal descriptions and the operational modes
they control.
The SMJ44C251B/MT42C4256 has three kinds of
operations: random-access operations typical of a DRAM,
transfer operations from memory arrays to the SAM, and
serial-access operations through the SAM port. The signals
used to control these operations are described here, followed
by discussions of the operations themselves.
COLUMN-ADDRESS STROBE (CAS\)
CAS\ is a control input that latches the states of column
address and DSF to control DRAM and transfer functions.
When CAS\ is brought low during a transfer cycle, it latches
the new tap point for the serial-data input or output. CAS\ also
acts as an output enable for the DRAM outputs DQ0–DQ3.
ADDRESS (A0–A8)
OUTPUT ENABLE/TRANSFER SELECT (TRG\)
TRG\ selects either DRAM or transfer operation as RAS\
falls. For DRAM operation, TRG\ must be held high as RAS\
falls. During DRAM operation, TRG\ functions as an out-
put enable for the DRAM outputs DQ0–DQ3. For transfer
operation, TRG\ must be brought low before RAS\ falls.
For DRAM operation, 18 address bits are required to
decode one of the 262144 storage cell locations. Nine row- ad-
dress bits are set up onA0–A8 and latched onto the chip on the
falling edge of RAS\. Nine column-address bits are set up on
A0–A8 and latched onto the chip on the falling edge of CAS\.
All addresses must be stable on or before the falling edges of
RAS\ and CAS\.
WRITE-MASK SELECT, WRITE ENABLE (W\)
In DRAM operation, W\ enables data to be written to the
DRAM. W\ is also used to select the DRAM write-per-bit
mode. Holding W\ low on the falling edge of RAS\ invokes
the write-per-bit operation. The SMJ44C251B/MT42C4256
supports both the normal write-per-bit mode and the persistent
write-per-bit mode.
During the transfer operation, the states of A0–A8 are
latched on the falling edge of RAS\ to select one of the 512
rows where the transfer occurs. To select one of 512 tap points
(starting positions) for the serial-data input or output, the
appropriate 9-bit column address (A0–A8) must be valid when
CAS\ falls.
CONTINUED
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
5
VRAM
SMJ44C251B
MT42C4256
WRITE-MASK SELECT, WRITE ENABLE (W\)
(continued)
For transfer operation, W\ selects either a read-transfer op-
eration (DRAM to SAM) or a write-transfer operation (SAM to
DRAM). During a transfer cycle, if W is high when RAS\ falls,
a read transfer occurs; if W is low, a write transfer occurs.
in serial-output mode, data in SAM is accessed from the least
significant bit to the most significant bit. The data registers oper-
ate modulo 512; so after bit 511 is accessed, the next bits to be
accessed are 00, 01, 02, etc. If the previous transfer cycle was
either a write transfer or a pseudo transfer, the data register is in
serial-input mode and signal data can be input to the register.
SPECIAL FUNCTION SELECT (DSF)
SERIAL CLOCK (SC)
DSF is latched on the falling edge of RAS\ or CAS\, similar
to an address. DSF determines which of the following functions
are invoked on a particular cycle:
Serial data is accessed in or out of the data register on the
rising edge of SC. The SMJ44C251B/MT42C4256 is designed
to work with a wide range of clock-duty cycles to simplify
system design. There is no refresh requirement because the
data registers that comprise the SAM are static. There is also
no minimum SC clock operating frequency.
• Persistent write-per-bit
• Block write
• Split-register transfer read
• Mask-register load for the persistent write-per-bit mode
• Color-register load for the block-write mode
SERIAL ENABLE (SE\)
During serial-access operations SE\ is used as an enable/
disable for SDQ in both the input and output modes. If SE\
is held as RAS\ falls during a write-transfer cycle, a pseudo-
transfer write occurs. There is no actual transfer, but the data
register switches from the output mode to the input mode.
DRAM DATA I/O, WRITE-MASK DATA (DQ0–DQ3)
DRAM data is written via DQ terminals during a write or
read-modify-write cycle. In an early-write cycle, W\ is brought
low prior to CAS\ and the data is strobed in by CAS\ with data
setup and hold times referenced to this signal. In a delayed-write
or read-modify-write cycle, W\ is brought low after CAS\ and the
data is strobed in by W\ with data setup and hold times referenced
to this signal.
The 3-state DQ output buffers provide direct TTL
compatibility (no pullup resistors) with a fanout of two Series 54
TTL loads. Data out is the same polarity as data in. The outputs
are in the high-impedance (floating) state as long as CAS\ and
TRG\ are held high. Data does not appear at the outputs until
both CAS\ and TRG\ are brought low. Once the outputs are valid,
they remain valid while CAS\ and TRG\ are low. CAS\ or TRG\
going high returns the outputs to the high-impedance state. In a
register-transfer operation, the DQ outputs remain in the high-
impedance state for the entire cycle.
NO CONNECT/GROUND (NC/GND)
NC/GND is reserved for the manufacturer’s test opera-
tion. It is an input and should be tied to system ground or left
floating for proper device operation.
SPECIAL FUNCTION OUTPUT (QSF)
During split-register operation the QSF output indicates
which half of the SAM is being accessed. When QSF is low,
the serial-address pointer is accessing the lower (least signifi-
cant) 256 bits of SAM. When QSF is high, the serial-address
pointer is accessing the higher (most significant) 256 bits of
SAM. QSF changes state upon crossing the boundary between
the two SAM halves in the split-register mode.
During normal transfer operations QSF changes state upon
completing a transfer cycle. This state is determined
by the tap point being loaded during the transfer cycle.
The write-per-bit mask is latched into the device via the
random DQ terminals by the falling edge of RAS\. This mask
selects which of the four random I/Os are written.
POWER UP
SERIAL DATA I/O (SDQ0–SDQ3)
To achieve proper device operation, an initial pause of
200ms is required after power-up, followed by a minimum of
eight RAS\ cycles or eight CBR cycles, a memory-to-register
transfer cycle, and two SC cycles.
Serial inputs and serial outputs share common I/O
terminals. Serial-input or serial-output mode is determined by
the previous transfer cycle. If the previous transfer cycle was a
read transfer, the data register is in serial-output mode. While
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
6
VRAM
SMJ44C251B
MT42C4256
RANDOM-ACCESS-OPERATION FUNCTIONS
CAS\
RAS\ FALL
ADDRESS
DQ0 - DQ3
FALL
DSF
FUNCTION
CAS\2
W\
W\1
X
CAS\ TRG\
DSF
SE\
RAS\
CAS\
RAS\
CBR Refresh
L
X
H
X
L
X
X
X
L
X
X
X
X
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Row
Addr
Col
Addr
DQ
Valid
H
L
Mask Data
DQ Col
Mask Mask
Row Blk Addr
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
X
X
X
X
X
X
X
H
L
Addr
Row
Addr
A2-A8
Col
Addr
Valid
Data
X
Row Blk Addr
Col
Mask
L
H
L
X
Addr
Row
Addr
A2-A8
Col
Addr
Valid
Data
H
H
H
H
X
Block write to DRAM
(nonmasked)
Row Blk Addr
Col
Mask
L
H
L
X
Addr
Refresh
Addr
A2-A8
DQ
Mask
Load write mask
H
H
X
X
Refresh
Addr
Color
Data
Load color register
H
X
X
NOTES:
1. In persistent write-per-bit function, W must be high during the refresh cycle.
2. DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled
LEGEND:
H = High
L = Low
X = Don’t care
Avalid column address can be presented immediately after row-
address hold time has been satisfied, usually well in advance
of the falling edge of CAS\. In this case, data can be obtained
RANDOM-ACCESS OPERATION
The random-access operation functions are summarized in
the “Random-Access-Operation Function” table and described
in the following sections.
after ta(C) max (access time from CAS low), if ta(CA) max (access
time from column address) has been satisfied.
ENHANCED PAGE-MODE
Enhanced page-mode operation allows faster memory ac-
cess by keeping the same row address while selecting random
column addresses. This mode eliminates the time required for
REFRESH
There are three types of refresh available on the
SMJ44C251B/MT42C4256: RAS\-only refresh, CBR refresh,
and hidden refresh.
row address setup-and-hold and address
multiplex. The
maximum RAS\ low time and the CAS\ page cycle time used
determine the number of columns that can be
cessed.
Unlike conventional page-mode operation, the enhanced
page mode allows the SMJ44C251B/MT42C4256 to operate
at a
ac-
RAS\-ONLY REFRESH
Arefresh operation must be performed to each row at least
once every 8 ms to retain data. Unless CAS\ is applied, the out-
put buffers are in the high-impedance state, so the RAS\-only
refresh sequence avoids any output during refresh. Externally
generated addresses must be supplied during RAS-only refresh.
Strobing each of the 512 row addresses with RAS causes
higher data bandwidth. Data retrieval begins as soon as the
column address is valid rather than when CAS\ transitions low.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
7
VRAM
SMJ44C251B
MT42C4256
(continued)
BLOCK WRITE
The block-write mode allows data (present in an on-
chip color register) to be written into four consecutive
column-address locations. The 4-bit color register is loaded
by the color-register-load cycle. Both write-per-bit modes can
be applied in the block-write cycle. The block-write mode also
offers the 4 × 4 column-mask capability.
RAS\-ONLY REFRESH (continued)
all bits in each row to be refreshed. CAS\ can remain high
(inactive) for this refresh sequence to conserve power.
CAS\-BEFORE-RAS\ (CBR) REFRESH
CBR refresh is accomplished by bringing CAS\ low earlier
than RAS\. The external row address is ignored and the refresh
row address is generated internally when using CBR refresh.
Other cycles can be performed in between CBR cycles without
disturbing the internal address generation.
LOAD COLOR REGISTER
The load-color-register cycle is performed using normal
DRAM write-cycle timing except that DSF is held high on the
falling edges of RAS\ and CAS\. A 4-bit code is input to the
color register via the random I/O terminals and latched on the
later of the falling edge of CAS\ or W\. After the color register
is loaded, it retains data until power is lost or until another
load-color-register cycle is executed.
HIDDEN REFRESH
A hidden refresh is accomplished by holding CAS\ low in
the DRAM-read cycle and cycling RAS\. The output data of
the DRAM-read cycle remains valid while the refresh is being
carried out. Like the CBR refresh, the refreshed row addresses
are generated internally during the hidden refresh.
BLOCK WRITE CYCLE
After the color register is loaded, the block-write cycle can
begin as a normal DRAM write cycle with DSF held high on
the falling edge of CAS\ (see Figures 2, 3, and 4). When the
block-write cycle is invoked, each data bit in the 4-bit color
register is written to selected bits of the four adjacent columns
of the corresponding random I/O.
WRITE-PER-BIT
The write-per-bit feature allows masking of any
com-
bination of the four DQs on any write cycle (see Figure 1). The
write-per-bit operation is invoked only when W\ is held low on
the falling edge of RAS\. If W\ is held high on the falling edge
During block-write cycles, only the seven most significant
column addresses (A2–A8) are latched on the falling edge of
CAS\. The two least significant addresses (A0–A1) are replaced
by four DQ bits (DQ0–DQ3), which are also latched on the
later of the falling edge of CAS\ or W\. These four bits are
used as a column mask, and they indicate which of the four
column-address locations addressed byA2–A8 are written with
the contents of the color register during the block-write cycle.
DQ0 enables a write to column-address A1 = 0 (low), A0 = 0
(low); DQ1 enables a write to column-address A1 = 0 (low),
A0 = 1 (high); DQ2 enables a write to column-address A1 = 1
(high), A0 = 0 (low); DQ3 enables a write to column-address
A1 = 1 (high),A0 = 1 (high).Ahigh logic level enables a write,
and a low logic level disables the write. A maximum of 16 bits
(4 × 4) can be written to memory during each CAS\ cycle in
the block-write mode.
of RAS\, write-per-bit is not enabled and the write
operation
is performed to all four DQs. The SMJ44C251B/MT42C4256
offers two write-per-bit modes: the nonpersistent write-per-bit
mode and the persistent write-per-bit mode.
NONPERSISTENT WRITE-PER-BIT
When DSF is low on the falling edge of RAS\, the write
mask is reloaded. A 4-bit code (the write-per-bit mask) is input
to the device via the random DQ terminals and latched on the
falling edge of RAS\. The write-per-bit mask selects which of
the four random I/Os are written and which are not. After RAS\
has latched the on-chip write-per-bit mask, input data is driven
onto the DQ terminals and is latched on the later falling edge of
CAS\ or W\. When a data low is strobed into a particular I/O on
the falling edge of RAS\, data is not written to that I/O. When a
data high is strobed into a particular I/O on the falling edge of
RAS\, data is written to that I/O.
PERSISTENT WRITE-PER-BIT
When DSF is high on the falling edge of RAS\, the write-
per-bit mask is not reloaded: it retains the value stored during
the last write-per-bit mask reload. This mode of operation is
known as persistent write-per-bit because the write-per-bit
mask is persistent over an arbitrary number of write cycles. The
write-per-bit mask reload can be done during the nonpersistent
write-per-bit cycle or by the mask-register-load cycle.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
8
VRAM
SMJ44C251B
MT42C4256
FIGURE 1: EXAMPLE OF WRITE-PER-BIT OPERATIONS
DQ Mask = H: Write to I/O enable
= L: Write to I/O disable
FIGURE 2: EXAMPLE BLOCK-WRITE DIAGRAM OPERATIONS
NOTES:
* W\ must be low during the block-write cycle.
DQ0–DQ3 are latched on the later of W\ or CAS\ falling edge except in block 6 (see legend).
LEGEND:
1. Refresh address
2. Row address
3. Block address (A2 –A8)
4. Color-register data
5. Column-mask data
6. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS\.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
9
VRAM
SMJ44C251B
MT42C4256
FIGURE 3: BLOCK-WRITE CIRCUIT BLOCK DIAGRAM
FIGURE 4: EXAMPLE OF BLOCK WRITE OPERATION WITH DQ
MASK AND ADDRESS MASK
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
10
VRAM
SMJ44C251B
MT42C4256
Switches serial port from serial-out mode to serial-in
mode. No actual data transfer takes place between the
DRAM and the SAM.
• Memory-to-register transfer (normal-read transfer,
transfer entire contents of DRAM row to SAM)
• Split-register-read transfer (divides the SAM into a low
and a high half. Only one half is transferred to the
SAM while the other half is read from the serial I/O
port.)
TRANSFER OPERATION
Transfer operations between the memory arrays (DRAM)
and the data registers (SAM) are invoked by bringing TRG\ low
before RAS\ falls. The states of W\, SE\, and DSF, which are also
latched on the falling edge of RAS\, determine which transfer
operation is invoked. Figure 5 shows an overview of data flow
between the random and the serial interfaces.
As shown in the “Transfer-Operation Functions” table,
the SMJ44C251B/MT42C4256 supports five basic modes of
transfer operation:
• Register-to-memory transfer (normal write transfer,
SAM to DRAM)
• Alternate-write transfer (independent of the state of SE\)
• Memory-to-register transfer (pseudo-transfer write).
FIGURE 5: BLOCK DIAGRAM SHOWING ONE RANDOM AND ONE
SERIAL-I/O INTERFACE
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
11
VRAM
SMJ44C251B
MT42C4256
TRANSFER-OPERATION FUNCTIONS
CAS\
FALL
RAS\ FALL
FUNCTION
ADDRESS
DQ0 - DQ3
CAS\
CAS\
TRG\
W\
DSF
X
SE\
L
DSF
X
RAS\
CAS\
RAS\
W\
Register-to-memory transfer
(normal write transfer)
Alternate-write transfer
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(normal read transfer)
Split-register-read transfer
(must reload tap)
Row
Addr
Row
Addr
Refresh
Addr
Row
Addr
Row
Addr
Tap
Point
Tap
Point
Tap
Point
Tap
Point
Tap
H
L
L
L
L
L
L
X
X
X
X
X
X
H
L
H
X
X
X
X
X
X
H
L
L
H
X
H
H
H
L
X
X
H
H
X
X
Point
LEGEND:
H = High
L = Low
X = Don’t Care
PSEUDO-WRITE TRANSFER
(write-mode control) (refer to Figure 28)
To invoke the pseudo-write transfer (write-mode control
cycle), SE\ is brought high and latched at the falling edge of
RAS\. The pseudo-write transfer does not actually invoke any
data transfer but switches the mode of the serial port from the
serial-out (read) mode to the serial-in (write) mode.
Before serial data can be clocked into the serial port via the
SDQ terminals and the SC input, the SDQ terminals must be
switched into input mode. Because the transfer does not occur
during the pseudo-transfer write, the row address (A0–A8) is in
the don’t care state and the column address (A0–A8), which is
latched on the falling edge of CAS\, selects one of the 512 tap
points in the SAM that are available for the next serial input.
WRITE TRANSFER
All write-transfer cycles (except the pseudo write transfer)
transfer the entire content of SAM to the selected row in the
DRAM. To invoke a write-transfer cycle, W\ must be low when
RAS\ falls. There are three possible write-transfer operations:
normal-write transfer, alternate-write transfer, and pseudo-write
transfer. All write-transfer cycles switch the serial port to the
serial-in mode.
NORMAL-WRITE TRANSFER
(SAM-to-DRAM transfer)
A normal-write transfer cycle loads the contents of the
serial-data register to a selected row in the memory array. TRG\,
W\, and SE\ are brought low and latched at the falling edge of
RAS\. Nine row-address bits (A0–A8) are also latched at the
falling edge of RAS\ to select one of the 512 rows available as
the destination of the data transfer. The nine column-address bits
(A0–A8) are latched at the falling edge of CAS\ to select one of
the 512 tap points in SAM that are available for the next serial
input.
READ TRANSFER
(DRAM-to-SAM transfer) (refer to Figure 7)
During a read-transfer cycle, data from the selected row
in DRAM is transferred to SAM. There are two read-transfer
operations: normal-read transfer and split-register-read
transfer.
During a write-transfer operation before RAS\ falls, the
serial-input operation must be suspended after a minimum
delay of td(SCRL) but can be resumed after a minimum delay of
td(RHSC) after RAS goes high (see Figure 6).
NORMAL-READ TRANSFER
(refer to Figure 7)
The normal-read-transfer operation loads data from
ALTERNATE-WRITE TRANSFER
(refer to Figure 30)
When DSF is brought high and latched at the falling edge
of RAS\ in the normal-write-transfer cycle, the alternate-write
transfer occurs.
a
selected row in DRAM into SAM. TRG\ is brought low
and latched at the falling edge of RAS\. Nine row-address
bits (A0–A8) are also latched at the falling edge of RAS\
to select one of the 512 rows available for transfer. The
nine column-
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
12
VRAM
SMJ44C251B
MT42C4256
(continued)
serial data is read out.
A normal-read transfer can be performed in three ways:
early-load read transfer, real-time or midline-load read transfer,
and late-load read transfer. Each of these offers the flexibility
of controlling the TRG\ trailing edge in the read-transfer cycle
(see Figure 7).
NORMAL-READ TRANSFER
(refer to Figure 7)
address bits (A0– A8) are latched at the falling edge of CAS\
to select one of the SAM’s 512 available tap points where the
FIGURE 6: NORMAL-WRITE-TRANSFER-CYCLE TIMING
FIGURE 7: NORMAL-READ-TRANSFER TIMINGS
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
13
VRAM
SMJ44C251B
MT42C4256
Anormal-read transfer must precede the split-register-read
transfer to ensure proper operation. After the normal-read-
transfer cycle, the first split-register read transfer can follow
immediately without any minimum SC requirement. However,
there is a minimum requirement of a rising edge of SC between
split-register read-transfer cycles.
SPLIT-REGISTER-READ TRANSFER
In split-register-read-transfer operation, the serial-data
register is split into halves. The low half contains bits 0–255, and
the high half contains 256–511. While one half is being read out
of the SAM port, the other half can be loaded from the memory
array.
QSF indicates which half of the SAM is being accessed dur-
ing serial-access operation. When QSF is low, the serial-address
pointer is accessing the lower (least significant) 256 bits of the
SAM. When QSF is high, the pointer is accessing the higher
(most significant) 256 bits of the SAM. QSF changes state upon
completing a normal-read-transfer cycle. The tap point loaded
during the current transfer cycle determines the state of QSF.
In split-register read-transfer mode, QSF changes state when a
boundary between the two register halves is reached (see Figure
8 and Figure 9).
To invoke a split-register read-transfer cycle, DSF is brought
high, TRG\ is brought low, and both are latched at the falling
edge of RAS\. Nine row-address bits (A0–A8) are also latched
at the falling edge of RAS\ to select one of the 512 rows avail-
able for the transfer. The nine column-address bits (A0–A8)
are latched at the falling edge of CAS\, where address bits A0
–A7 select one of the 255 tap points in the specified half of SAM
and address bit A8 selects which half is to be transferred. If A8
is a logic low, the low half is transferred. If A8 is a logic high,
the high half is transferred. SAM locations 255 and 511 cannot
be used as tap points.
FIGURE 8: EXAMPLE OF A SPLIT-REGISTER READ-TRANSFER
CYCLE AFTER A NORMAL READ-TRANSFER CYCLE
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
14
VRAM
SMJ44C251B
MT42C4256
FIGURE 9: A SPLIT-REGISTER READ-TRANSFER CYCLE AFTER
A SPLIT-REGISTER READ-TRANSFER CYCLE
SERIAL-ACCESS OPERATION
transfer operation is a write- or pseudo-write-transfer operation,
the SAM port is in the input mode.
Serial data can be read out of or written into SAM by
clocking SC starting at the tap point loaded by the preceding
transfer cycle, proceeding sequentially to the most significant
bit (bit 511), then wrapping around to the least
The serial-read and serial-write operations can be performed
through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. The preced-
ing transfer operation determines the input or output state of the
SAM port. If the preceding transfer operation is a read-transfer
operation, the SAM port is in the output mode. If the preceding
significant bit (bit 0) (see Figure 10).
FIGURE 10: SERIAL POINTER DIRECTION FOR SERIAL READ/WRITE
inactive half during this period, the serial pointer points next to
the tap-point location loaded by that split register (see
Figure 11, Case I). If there is no split-register read transfer to
the inactive half during this period, the serial pointer points next
to bit 256 or bit 0, respectively (see Figure 11, Case II).
For split-register read-transfer operation, serial data can be read
out from the active half of SAM by clocking SC starting at the tap
point loaded by the preceding split-register-transfer cycle, then
proceeding sequentially to the most significant bit of the half,
bit 255 or bit 511. If there is a split-register-read transfer to the
FIGURE 11: SERIAL POINTER FOR SPLIT-REGISTER READ
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
15
VRAM
SMJ44C251B
MT42C4256
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Supply voltage range, VCC1.......................................-1V to 7V
Voltage range on any pin1.........................................-1V to 7V
Short-circuit output current.............................................50mA
Power dissipation................................................................1W
Operating free-air temperature range, TA........-55°C to 125°C
Storage temperature range, TSTG......................-65°C to 150°C
NOTE: 1. All voltage values are with respect to Vss.
RECOMMENDED OPERATING CONDITIONS
SYM
PARAMETER
MIN
NOM
MAX
UNIT
V
V
Supply Voltage
4.5
5
5.5
V
CC
SS
Supply Voltage
0
V
V
V
High-level input voltage
Low-level input voltage**
Operating free-air temperature
Operating case temperature
2.9
-1
6.5
0.6
125
125
IH
IL
V
V
T
-55
°C
°C
A
T
C
NOTE: **The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
16
VRAM
SMJ44C251B
MT42C4256
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANG-
ES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPER-
ATURE (UNLESS OTHERWISE NOTED)
PARAMETER
SYM
CONDITIONS
MIN
MAX
UNIT
High-level output voltage
VOH
IOH = -5mA
2.4
V
Low-level output voltage1
VOL
II
IOL = 4.2mA
0.4
±10
±10
V
VCC = 5V, VI = 0V to 5.8V,
All others open
Input leakage current
μA
μA
Output leakage current2
IO
VCC = 5.5V, VO = 0V to VCC
-10
-12
SAM
CONDITIONS
3
SYM
MIN MAX MIN MAX UNITS
PARAMETER
PORT
Operating current
I
t
t
and t = MIN Standby
c(W)
100
110
15
90
100
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC1
c(rd)
Operating current
I
t
= MIN
Active
Standby
Active
CC1A
c(SC)
Standby current
I
All clocks = V
CC
CC2
Standby current
I
t
= MIN
35
35
CC2A
c(SC)
RAS\-only refresh current
RAS\-only refresh current
Page-mode current
Page-mode current
CAS\-before-RAS\ current
CAS\-before-RAS\ current
Data-transfer current
Data-transfer current
I
and t = MIN Standby
c(W)
100
110
65
90
CC3
c(rd)
I
t
= MIN
Active
Standby
Active
100
60
CC3A
c(SC)
I
t
= MIN
= MIN
CC4
c(P)
I
t
70
65
CC4A
c(SC)
I
t
t
and t = MIN Standby
c(W)
90
80
CC5
c(rd)
I
t
= MIN
Active
and t = MIN Standby
c(W)
110
100
110
100
90
CC5A
c(SC)
I
CC6
c(rd)
I
t
= MIN
Active
100
CC6A
c(SC)
NOTES:
1. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designer’s Handbook. This
phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ terminals are switched. This may
cause VOL and VOH to exceed the data-book limit for a short period of time, depending upon output loading and temperature. Care should be taken to provide
proper termination, decoupling, and layout of the device to minimize simultaneous switching effects.
2. SE\ is disabled for SDQ output leakage tests.
3.
ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2).
ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for ICC2).
ICC is measured with no load on DQ or SDQ.
4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
17
VRAM
SMJ44C251B
MT42C4256
CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGES AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz1
PARAMETER
SYM
MIN
MAX
UNIT
Input capacitance, A0 - A8
C
7
pF
i(A)
Input capacitance, CAS\ and RAS\
Output capacitance, SDQs and DQs
Output capacitance, SQSF
C
7
9
9
pF
pF
pF
i(RC)
C
o(O)
C
o(QSF)
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANG-
ES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR
TEMPERATURE2
-10
-12
4
PARAMETER
Access time from CAS\
SYM/ALT. SYM CONDITIONS
MIN MAX
MIN MAX UNIT
t
/t
t
t
t
t
= MAX
= MAX
= MAX
= MAX
25
30
60
65
120
30
35
25
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
a(C) CAC
d(RLCL)
d(RLCL)
d(RLCL)
d(RLCL)
Access time from column address
Access time from CAS\ high
t
/t
50
55
a(CA) CAA
t
/t
a(CP) CPA
Access time from RAS\
t
/t
100
25
a(R) RAC
Access time of DQ0 - DQ3 from TRG\ low
Access time of SDQ0 - SDQ3 from SC high
Access time of SDQ0 - SDQ3 from SE\ low
t
/t
a(G) OEA
t
/t
C = 30pF
30
a(SQ) SCA
L
t
/t
C = 30pF
20
a(SE) SEA
L
3
t
/t
C = 100pF
0
0
0
20
20
20
0
0
0
dis(CH) OFF
L
Disable time, random output from CAS\ high
3
t
/t
C = 100pF
L
dis(G) OEZ
Disable time, random output from TRG\ high
3
t
/t
C = 30pF
L
dis(SE) SEZ
Disable time, random output from SE\ high
NOTES:
1. Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the terminal
under test. All other terminals are open.
2. Switching times assume CL = 100 pF unless otherwise noted (see Figure 12).
3. tdis(CH), tdis(G), and tdis(SE) are specified when the output is no longer driven.
4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
18
VRAM
SMJ44C251B
MT42C4256
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE1
-10
-12
PARAMETER
SYM/ALT. SYM MIN
/t
MAX
MIN
MAX
UNIT
2
t
190
190
250
60
105
190
190
30
20
25
80
100
25
25
10
10
35
35
30
100
0
220
ns
c(rd) RC
Cycle time, read
2
t
/t
220
290
70
125
220
220
35
30
30
90
120
25
30
12
12
40
40
20
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(W) WC
Cycle time, write
2
t
/t
c(rdW) RMW
Cycle time, read-modify-write
2
t
/t
c(P) PC
Cycle time, page-mode read or write
2
t
/t
c(rdWP) PRMW
Cycle time, page-mode read-modify-write
2
t
t
/t
c(TRD) RC
Cycle time, read transfer
2
/t
c(TW) WC
Cycle time, write transfer
2
t
/t
c(SC) SCC
Cycle time, serial clock
Pulse duration, CAS\ high
t
/t
w(CH) CPN
4
t
/t
75000
75000
75000
75000
w(CL) CAS
Pulse duration, CAS\ low
Pulse duration, RAS\ high
t
/t
w(RH) RP
5
t
/t
w(RL) RAS
Pulse duration, RAS\ low
Pulse duration,W\ low
t
/t
w(WL) WP
Pulse duration, TRG\ low
t
w(TRG)
Pulse duration, SC high
t
/t
w(SCH) SC
Pulse duration, SC low
t
/t
w(SCL) SCP
Pulse duration, SE\ low
t
/t
w(SEL) SE
Pulse duration, SE\ high
t
/t
w(SEH) SEP
Pulse duration, TRG\ high
Pulse duration, RAS\ low (page mode)
Setup time, column address
Setup time, DSF before CAS\ low
Setup time, row address
t
/t
w(GH) TP
t
75000
75000
w(RL)P
t
/t
su(CA) ASC
t
/t
0
0
su(SFC) FSC
t
/t
0
0
su(RA) ASR
Setup time, W\ before RAS\ low
Setup time, DQ before RAS\ low
Setup time, TRG\ before RAS\ low
t
/t
0
0
su(WMR) WSR
t
/t
0
0
su(DQR) MS
t
/t
0
0
su(TRG) THS
6
t
/t
0
0
su(SE) ESR
Setup time, SE\ before RAS\ low
Setup time, serial write disable
t
/t
10
0
15
0
su(SESC) SWIS
Setup time, DSF before RAS\ low
Setup time, data before CAS\ low
Setup time, data before W\ low
t
/t
su(SFR) FSR
t
/t
0
0
su(DCL) DSC
t
/t
0
0
su(DWL) DSW
Setup time, read command
t
/t
0
0
su(rd) RCS
Setup time, early write command before CAS\ low
Setup time, write before CAS\ high
t
t
/t
0
0
su(WCL) WCS
/t
25
30
su(WCH) CWL
Setup time, write before RAS\ high with
TRG\ = W\ = low
t
/t
25
30
ns
su(WRH) RWL
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
19
VRAM
SMJ44C251B
MT42C4256
TIMING REQUIREMENTS (continued)1
-10
-12
PARAMETER
SYM/ALT. SYM MIN
MAX
MIN
MAX
UNIT
Setup time, SDQ before SC high
t
/t
0
0
ns
su(SDS) SDS
Hold time, column address after CAS\ low
Hold time, DSF after CAS\ low
t
/t
20
20
15
15
20
20
15
15
ns
ns
ns
ns
h(CLCA) CAH
t
/t
h(SFC) CFH
Hold time, row address after RAS\ low
t
/t
h(RA) RAH
Hold time, TRG\ after RAS\ low
t
/t
h(TRG) TLH
Hold time, SE\ after RAS\ low with
t
/t
15
15
ns
h(SE) REH
6
TRG\ = W\ = low
Hold time, write mask, transfer enable
after RAS\ low
Hold time, DQ after RAS\ low
(write-mask operation)
t
/t
15
15
15
15
ns
ns
h(RWM) RWH
t
/t
h(RDQ) MH
Hold time, DSF after RAS\ low
t
/t
15
45
20
45
20
0
15
45
25
50
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(SFR) RFH
7
t
/t
h(RLCA) AR
Hold time, column address after RAS\ low
Hold time, data after CAS\ low
t
/t
h(CLD) DH
7
t
/t
h(RLD) DHR
Hold time, data after RAS\ low
Hold time, data after W\ low
t
/t
h(WLD) DH
8
t
/t
h(CHrd) RCH
Hold time, read after CAS\ high
8
t
/t
10
30
50
25
5
10
35
55
30
5
h(RHrd) RRH
Hold time, read after RAS\ high
Hold time, write after CAS\ low
t
t
/t
h(CLW) WCH
7
/t
h(RLW) WCR
Hold time, write after RAS\ low
9
t
/t
h(WLG) OEH
Hold time, TRG\ after W\ low
Hold time, SDQ after SC high
Hold time, SDQ after SC high
Hold time, DSF after RAS\ low
Hold time, serial-write disable
Delay time, RAS\ low to CAS\ high
Delay time, CAS\ high to RAS\ low
Delay time, CAS\ low to RAS\ high
t
/t
h(SDS) SDH
t
/t
5
5
h(SHSQ) SOH
t
/t
45
20
100
0
45
20
120
0
h(RSF) FHR
t
/t
h(SCSE) SWIH
t
/t
d(RLCH) CSH
t
t
/t
d(CHRL) CRP
/t
25
55
25
50
130
85
25
10
10
30
65
25
60
155
100
25
10
10
d(CLRH) RSH
10,11
t
/t
d(CLWL) CWD
Delay time, CAS\ low to W\ low
12
t
/t
75
90
d(RLCL) RCD
Delay time, RAS\ low to CAS\ low
Delay time, column address to RAS\ high
t
/t
d(CARH) RAL
10
t
/t
d(RLWL) RWD
Delay time, RAS\ low to W\ low
10
t
/t
d(CAWL) AWD
Delay time, column address to W\ low
13
t
/t
d(RLCH)RF CHR
Delay time, RAS\ low to CAS\ high
13
t
/t
d(CLRL)RF CSR
Delay time, CAS\ low to RAS\ low
13
t
/t
d(RHCL)RF RPC
Delay time, RAS\ high to CAS\ low
Delay time, CAS\ low to TRG\ high for DRAM read
cycles
t
25
30
ns
d(CLGH)
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
20
VRAM
SMJ44C251B
MT42C4256
TIMING REQUIREMENTS (continued)1
-10
-12
PARAMETER
SYM/ALT. SYM MIN
MAX
MIN
MAX
UNIT
Delay time, TRG\ high before data applied at DQ
t
/t
25
30
ns
d(GHD) OED
Delay time, RAS\ low to TRG\ high
(real-time-reload read-transfer cycle only)
Delay time, RAS\ low to first SC high after
t
/t
90
95
ns
ns
d(RLTH) RTH
t
t
/t
130
40
140
d(RLSH) RSD
14
TRG\ high
Delay time, CAS\ low to first SC high after TRG\
/t
45
ns
d(CLSH) CSD
14
high
14,15,16
t
/t
15
20
ns
ns
d(SCTR) TSL
Delay time, SC high to TRG\ high
15,16
t
t
/t
-10
-10
d(THRH) TRD
Delay time, TRG\ high to RAS\ high
Delay time, SC high to RAS\ low with
/t
10
20
ns
ns
d(SCRL) SRS
6, 17, 18
TRG\ = W\ = low
Delay time, SC high to SE\ high in serial-input
mode
t
20
25
20
30
d(SCSE)
6
t
/t
ns
ns
ns
ns
d(RHSC) SRD
Delay time, RAS\ high to SC high
19
t
/t
t
t
d(THRL) TRP
w(RH)
35
w(RH)
40
Delay time, TRG\ high to RAS\ low
15, 16
t
/t
d(THSC) TSD
Delay time, TRG\ high to SC high
20
t
/t
10
15
d(SESC) SWS
Delay time, SE\ low to SC high
Delay time, RAS\ high to last (most significant)
rising edge of SC before boundary switch during
split-register read-transfer cycles
t
15
20
ns
d(RHMS)
Delay time, CAS\ low to TRG\ high in real-time
read-transfer cycles
Delay time, column address to first SC in early-
load read-transfer cycles
Delay time, column address to TRG\ high in real-
time read-transfer cycles
t
/t
5
5
ns
ns
ns
d(CLGH) CTH
t
t
/t
45
10
50
10
d(CASH) ASD
/t
d(CAGH) ATH
12
t
/t
15
0
50
15
0
60
ns
ns
ns
ns
ns
d(RLCA) RAD
Delay time, RAS\ low to column address
Delay time, data to CAS\ low
t
/t
d(DCL) DZC
Delay time, data to TRG\ low
t
/t
0
0
d(DGL) DZO
Delay time, RAS\ low to serial-input data
Delay time, TRG\ low to RAS\ high
t
/t
50
25
50
30
d(RLSD) SDD
t
/t
d(GLRH) ROH
Delay time, last (most significant) rising edge of
SC to RAS\ low before boundary switch during
split-register read-transfer cycles
Delay time, last (255 or 511) rising edge of SC to
QSF switching a the boundary during split-register
t
25
25
ns
ns
d(MSRL)
t
/t
40
40
d(SCQSF) SQD
21
read transfer cycles
Delay time, CAS\ low to QSF switching in read-
t
/t
35
30
75
35
30
75
ns
ns
ns
d(CLQSF) CQD
21
transfer or write-transfer cycles
Delay time, TRG\ high to QSF switching in read-
t
/t
d(GHQSF) TQD
21
transfer or write-transfer cycles
Delay time, RAS\ low to QSF switching in read-
t
/t
d(RLQSF) RQD
21
transfer or write-transfer cycles
Refresh time interval, memory
Transition time
t /t
8
8
ms
ns
rf REF
t /t
t
3
50
3
50
T
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
21
VRAM
SMJ44C251B
MT42C4256
NOTES:
1. Timing measurements are referenced to VIL max and VIH min.
2. All cycle times assume tt = 5 ns.
3. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data out cycle needs to be 70 ns
minimum.
4. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this may require additional CAS\ low time
[tw(CL)].
5. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this may require additional RAS\ low time
[tw(RL)].
6. Register-to-memory (write) transfer cycles only
7. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
8. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
9. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
10. Read-modify-write operation only
11. TRG\ must disable the output buffers prior to applying data to the DQ terminals.
12. The maximum value is specified only to assure RAS\ access time.
13. CAS\-before-RAS\ refresh operation only
14. Early-load read-transfer cycle only
15. Real-time-reload read-transfer cycle only
16. Late-load read-transfer cycle only
17. In a read-transfer cycle, the state of SC when RAS\ falls is a don’t care condition. However, to assure proper sequencing of the internal clock circuitry, there
can be no positive transitions of SC for at least 10 ns prior to when RAS\ goes low.
18. In a memory-to-register (read) transfer cycle, td(SCRL) applies only when the SAM was previously in serial-input mode.
19. Memory-to-register (read) and register-to-memory (write) transfer cycles only
20. Serial data-in cycles only
21. Switching times assume CL = 100 pF unless otherwise noted (see Figure 12).
FIGURE 12: LOAD CIRCUIT
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
22
VRAM
SMJ44C251B
MT42C4256
FIGURE 13: Read-Cycle Timing
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
23
VRAM
SMJ44C251B
MT42C4256
FIGURE 14: Early-Write-Cycle Timing
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
24
VRAM
SMJ44C251B
MT42C4256
FIGURE 15: Delayed-Write-Cycle Timing
(Output-Enable-Controlled Write)
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
25
VRAM
SMJ44C251B
MT42C4256
FIGURE 16: Read-Write/Read-Modify-Write-Cycle Timing
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
26
VRAM
SMJ44C251B
MT42C4256
FIGURE 17: Enhanced-Page-Mode Read-Cycle Timing
NOTES:
1. Access time is ta(CP) or ta(CA) dependent.
2. Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are
not violated and the proper polarity of DSF is selected on the falling edges of RAS\ and CAS\ to select the desired write mode (normal,
block
write, etc.)
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
27
VRAM
SMJ44C251B
MT42C4256
FIGURE 18: Enhanced-Page-Mode Write-Cycle Timing
NOTES:
1. Referenced to CAS or W, whichever occurs last
NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications. TRG\
must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write feature is used. If the early-write-cycle timing is
used, the state of TRG\ is a don’t care after the minimum period th(TRG) from the falling edge of RAS\.
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
28
VRAM
SMJ44C251B
MT42C4256
FIGURE 19: Enhanced-Page-Mode
Read-Modify-Write-Cycle Timing
NOTES:
1. Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE C: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
L
H
H
2
L
L
L
L
3
H
L
L
H
4
5
Write Operation
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
Don't Care Write Mask
Write-mask load/use, Write DQs to I/Os
Use previous write mask, Write DQs to I/Os
Load write mask on later of W\ fall and CAS\ fall
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
29
VRAM
SMJ44C251B
MT42C4256
FIGURE 20: Load-Color-Register-Cycle Timing
(Early-Write Load)
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
30
VRAM
SMJ44C251B
MT42C4256
FIGURE 21: Load-Color-Register-Cycle Timing
(Delayed-Write Load)
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
31
VRAM
SMJ44C251B
MT42C4256
FIGURE 22: Block-Write-Cycle Timing (Early Write)
BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
H
L
2
L
L
3
4
Write-mask load/use, Block write
Use previous write mask, Block write
Write mask disable, Block write to all I/Os
Write Mask Column Mask
Don't Care Column Mask
Don't Care Column Mask
H
Write mask data 0: I/O write disable
1: I/O write enable
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
DQ0 — column 0 (address A1 = 0, A0 = 0)
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
Micross Components reserves the right to change products or specifications without notice.
32
VRAM
SMJ44C251B
MT42C4256
FIGURE 23: Block-Write-Cycle Timing (Delayed-Write)
BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
H
L
2
L
L
3
4
Write-mask load/use, Block write
Use previous write mask, Block write
Write mask disable, Block write to all I/Os
Write Mask Column Mask
Don't Care Column Mask
Don't Care Column Mask
H
Write mask data 0: I/O write disable
1: I/O write enable
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
33
VRAM
SMJ44C251B
MT42C4256
FIGURE 24: Enhanced-Page-Mode
Block-Write-Cycle Timing
NOTES:
1. Referenced to CAS\ or W\, whichever occurs last
NOTE D: TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If
the early-write-cycle timing is used, the state of TRG\ is a don’t care after the minimum period th(TRG) from the falling edge of RAS\.
ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
L
H
L
2
L
L
3
4
Write-mask load/use, Block write
Use previous write mask, Block write
Write mask disable, Block write to all I/Os
Write mask data 0: I/O write disable
1: I/O write enable
Column mask data DQn =
Write Mask Column Mask
Don't Care Column Mask
Don't Care Column Mask
H
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Micross Components reserves the right to change products or specifications without notice.
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
34
VRAM
SMJ44C251B
MT42C4256
FIGURE 25: RAS\-Only Refresh-Cycle Timing
NOTES:
NOTE E: In persistent write-per-bit function, W\ must be high at the falling edge of RAS\ during the refresh cycle.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
35
VRAM
SMJ44C251B
MT42C4256
FIGURE 26: CBR-Refresh-Cycle Timing
NOTES:
NOTE F: In persistent write-per-bit operation, W\ must be high at the falling edge of RAS\ during the refresh cycle.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
36
VRAM
SMJ44C251B
MT42C4256
FIGURE 27: Hidden-Refresh-Cycle Timing
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
37
VRAM
SMJ44C251B
MT42C4256
FIGURE 28: Write-Mode-Control Pseudo-Transfer Timing
NOTES:
NOTE G: The write-mode-control cycle is used to change the SDQs from the output mode to the input mode. This allows serial data to be written into the data
register. This figure assumes that the device was originally in the serial-read mode.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
38
VRAM
SMJ44C251B
MT42C4256
FIGURE 29: Data-Register-to-Memory Transfer Timing,
Serial Input Enable
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
39
VRAM
SMJ44C251B
MT42C4256
FIGURE 30: Alternate Data-Register-to-Memory
Transfer-Cycle Timing
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
40
VRAM
SMJ44C251B
MT42C4256
FIGURE 31: Memory-to-Data-Register Transfer-Cycle Timing,
Early-Load Operation
NOTES:
NOTE H: Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min.
NOTE I: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is
used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of the
selected row. The data that is transferred into the data registers can be either shifted out or transferred back into another row.
NOTE J: Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers.
Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
41
VRAM
SMJ44C251B
MT42C4256
FIGURE 32: Memory-to-Data-Register Transfer-Cycle Timing,
Real-Time-Reload Operation/Late-Load Operation
NOTES:
NOTE K: Late-load operation is defined as td(THRH) < 0 ns.
NOTE L: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is
used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of the
selected row. The data that is transferred into the data registers can be either shifted out or transferred back into another row.
NOTE M: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers.
Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
42
VRAM
SMJ44C251B
MT42C4256
FIGURE 33: Memory-to-Data-Register Transfer-Cycle Timing,
SDQ Ports Previously in Serial-Input Mode
NOTES:
NOTE N: Late-load operation is defined as td(THRH) < 0 ns.
NOTE O: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is
used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of
the selected row. The data that is transferred into the data registers may be either shifted out or transferred back into another row.
NOTE P: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers.
Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
43
VRAM
SMJ44C251B
MT42C4256
FIGURE 34: Split-Register-Mode Read-Transfer-Cycle Timing
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
44
VRAM
SMJ44C251B
MT42C4256
FIGURE 35: Split-Register-Transfer Operating Sequence
NOTES:
NOTE Q: In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer cycle. This is
necessary to initialize the data register and the starting tap location. First serial access can then begin either after the normal read-transfer cycle (CASE I), during
the first split-register cycle (CASE II), or even after the first split-register transfer cycle (CASE III). There is no minimum requirement of SC clock between
the normal read-transfer cycle and the first split-register cycle.
NOTE R: A split register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of the
serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register transfer cycle into the inactive half. After td(MSRL) is met, the split-
register transfer into the inactive half must also satisfy the td(RHMS) requirement. td(RHMS) is the minimum delay time between the rising edge of RAS\ of the
split-register transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). There is a minimum requirement of one
rising edge of SC clock between two split-register transfer cycles.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
45
VRAM
SMJ44C251B
MT42C4256
FIGURE 36: Serial-Write-Cycle Timing (SE\ = VIL)
NOTES:
NOTE S: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals,
the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other write-transfer cycle. A read-transfer cycle
is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the
location specified by the input address loaded on the previous transfer cycle.
NOTE T: While accessing data in the serial-data registers, the state of TRG\ is a don’t care as long as TRG\ is held high when RAS\ goes low to prevent data
transfers between memory and data registers.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
46
VRAM
SMJ44C251B
MT42C4256
FIGURE 37: Serial-Write-Cycle Timing (SE\-Controlled Write)
NOTES:
NOTE U: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals,
the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other write-transfer cycle. A read-transfer cycle
is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the
location specified by the input address loaded on the previous transfer cycle.
NOTE V: While accessing data in the serial-data registers, the state of TRG\ is a don’t care as long as TRG\ is held high when RAS\ goes low to prevent data
transfers between memory and data registers.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
47
VRAM
SMJ44C251B
MT42C4256
FIGURE 38: Serial-Read-Cycle Timing (SE\ = VIL)
NOTES:
NOTE W: While reading data through the serial-data register, the state of TRG\ is a don’t care as long as TRG\ is held high when RAS\ goes low. This is to
avoid the initiation of a register-to-memory-to-register data-transfer operation.
NOTE X: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put into the read mode
by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subsequent shifting out of data take the device
out of the read mode and put it in the write mode, not allowing the reading of data.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
48
VRAM
SMJ44C251B
MT42C4256
FIGURE 39: Serial-Read-Cycle Timing (SE\-Controlled Read)
NOTES:
NOTE Y: While reading data through the serial-data register, the state of TRG\ is a don’t care as long as TRG\ is held high when RAS\ goes low. This is to
avoid the initiation of a register-to-memory-to-register data-transfer operation.
NOTE Z: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put into the read mode
by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subsequent shifting out of data take the
device out of the read mode and put it in the write mode, not allowing the reading of data.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
49
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Micross Case #500 (Package Designator DCJ)
SMD 5962-89497, Case Outline T
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
50
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Micross Case #109 (Package Designator C or JDM)
SMD 5962-89497, Case Outline X
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
51
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Package Designator HJM
SMD 5962-89497, Case Outline Y
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
52
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Micross Case #203 (Package Designator EC or HMM)
SMD 5962-89497, Case Outline Z
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
53
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Package Designator CZ or SVM
SMD 5962-89497, Case Outline M
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
54
VRAM
SMJ44C251B
MT42C4256
MECHANICAL DEFINITIONS*
Micross Case #302 (Package Designator F)
SMD 5962-89497, Case Outline U
SMD SPECIFICATIONS
SYMBOL
MIN
0.090
0.015
0.004
---
0.380
---
0.180
0.030
MAX
0.130
0.022
0.009
0.740
0.420
0.440
---
A
b
c
D
E
E1
E2
E3
e
---
0.050 BSC
L
Q
S1
0.250
0.026
0.000
0.370
0.045
---
*All measurements are in inches.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
55
VRAM
SMJ44C251B
MT42C4256
ORDERING INFORMATION
EXAMPLE: MT42C4256DCJ-12/883C
EXAMPLE: MT42C4256C-12/IT
Device
Number
MT42C4256
MT42C4256
Package
Type
Device
Number
MT42C4256
MT42C4256
Package
Type
C
Speed ns Process
Speed ns Process
DCJ
DCJ
-10
-12
/*
/*
-10
-12
/*
/*
C
EXAMPLE: MT42C4256CZ-12/883C
EXAMPLE: MT42C4256F-12/IT
Device
Number
MT42C4256
MT42C4256
Package
Type
CZ
Device
Number
MT42C4256
MT42C4256
Package
Type
Speed ns Process
Speed ns Process
-10
-12
/*
/*
F
F
-10
-12
/*
/*
CZ
EXAMPLE: MT42C4256EC-10/883C
Device
Number
MT42C4256
MT42C4256
Package
Type
EC
Speed ns Process
-10
-12
/*
/*
EC
EXAMPLE: SMJ44C251B 10HJM
EXAMPLE: SMJ44C251B 12JDM
Device
Number
SMJ44C251B
SMJ44C251B
Package
Device
Number
SMJ44C251B
SMJ44C251B
Package
Speed ns
Process
Speed ns
Process
Type
HJM
HJM
Type
JDM
JDM
10
12
See Note
See Note
10
12
See Note
See Note
EXAMPLE: SMJ44C251B 12HMM
EXAMPLE: SMJ44C251B 10SVM
Device
Number
SMJ44C251B
SMJ44C251B
Package
Type
HMM
Device
Number
SMJ44C251B
SMJ44C251B
Package
Speed ns
Process
Speed ns
Process
Type
SVM
SVM
10
12
See Note
See Note
10
12
See Note
See Note
HMM
*OPERATING TEMPERATURE
XT = Military Temperature Range
IT = Industrial Temperature Range
883C = MIL-STD-883C process
-55oC to +125oC
-40°C to +85°C
-55oC to +125oC
NOTE: SMJ prefix denotes MIL-STD-883C process, temperature
range -55oC to +125oC.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
56
VRAM
SMJ44C251B
MT42C4256
MICROSS TO DSCC PART NUMBER
CROSS REFERENCE*
Package Designator C or JDM
Package Designator CZ or SVM
Micross Part Number
SMD Part Number
5962-8949704MXA
5962-8949703MXA
5962-8949704MXA
5962-8949703MXA
Micross Part Number
SMD Part Number
5962-8949704MMA
5962-8949703MMA
5962-8949704MMA
5962-8949703MMA
MT42C4256C-10/883C
MT42C4256C-12/883C
SMJ44C251B-10JDM**
SMJ44C251B-12JDM**
MT42C4256CZ-10/883C
MT42C4256CZ-12/883C
SMJ44C251B-10SVM**
SMJ44C251B-12SVM**
Package Designator EC or HMM
Package Designator DCJ
Micross Part Number
MT42C4256EC-10/883C 5962-8949704MZA
MT42C4256EC-12/883C 5962-8949703MZA
SMD Part Number
Micross Part Number
MT42C4256DCJ-10/883C
MT42C4256DCJ-12/883C
SMD Part Number
5962-8949704MYA
5962-8949703MYA
SMJ44C251B-10HMM**
SMJ44C251B-12HMM**
5962-8949704MZA
5962-8949703MZA
Package Designator F
Package Designator HJM
Micross Part Number
MT42C4256F-10/883C
MT42C4256F-12/883C
SMD Part Number
5962-8949704MYA
5962-8949703MYA
Micross Part Number
SMJ44C251B-10HJM**
SMJ44C251B-12HJM**
SMD Part Number
5962-8949704MYA
5962-8949703MYA
* Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
** Parts are listed on SMD under the old Texas Instruments part number. Micross purchased this product line in November of 1999.
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
57
VRAM
SMJ44C251B
MT42C4256
DOCUMENT TITLE
128 Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory
Rev #
History
Release Date
Status
0.5
Removed F & DCJ package- pg 1,
56, 57
April 2010
Release
Deleted package diagrams (old page
50 & 55)
0.6
Added F & DCJ package information
back into datasheet
June 2010
Release
Micross Components reserves the right to change products or specifications without notice.
SMJ44C251B/MT42C4256
Rev. 0.6 06/10
58
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