SMJ55161AGB-70 [MICROSS]
Memory Circuit, 256KX16, PPGA68;
| 型号： | SMJ55161AGB-70 |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Memory Circuit, 256KX16, PPGA68 内存集成电路 |
| 文件： | 总64页 (文件大小：1234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VRAM
SMJ55161A
Production
Austin Semiconductor, Inc.
262144 x 16 BIT VRAM
PIN ASSIGNMENT
MULTIPORT VIDEO RAM
(Top View)
AVAILABLE AS MILITARY
64-Pin Ceramic Flatpack (HKC)
SPECIFICATIONS
•SMD5962-94549(TBD)
•MIL-STD-883 Methods -55C to 125C temp (SM prefix)
FEATURES
• Organization:
– DRAM: 262 144 by 16 Bits
– SAM: 512 by 16 Bits
• Dual-Port Accessibility – Simultaneous and Asynchronous
Access From the DRAM and SAM Ports
• Bidirectional Data-Transfer Function From the DRAM to
the Serial-Data Register, and from Serial Data Register to DRAM
• (8 x 8) x 2 Block Write feature for fast area fill
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
• Byte-Write Control (CASL, CASU) Provides Flexibility
• Extended Data Output for Faster System Cycle Time
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden-Refresh Modes
• Long Refresh Period: Every 8 ms (Maximum)
• Up to 50-MHz Uninterrupted Serial-Data Streams
• 512 Selectable Serial-Register Starting Locations
• SE-Controlled Register-Status QSF
• Split-Register-Transfer Read for Simplified Real-Time Register
Load
PIN DESCRIPTIONS
PIN
DESCRIPTION
Address inputs
• Programmable Split-Register Stop Point
A0-A8
• 3-State Serial Outputs Allow Easy Multiplexing of Video-Data
Streams
CASL\, CASU\ Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Special Function Select
DQ0-DQ15
• Pin-out Compatible upgrade from SMJ55161
DSF
Special-Function Select
No Connect/Ground (NOTE: Not
• Compatible With JEDEC Standards
NC/GND
connected internally to V
)
SS
QSF
RAS\
SC
SE\
SQ0-SQ15
TRG\
Special-Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial-Data Output
OPTIONS
• Timing
70ns access
75ns access
80ns access
MARKING
-70
-75
-80
Output Enable, Transfer Select
V
5V Supply (TYP)
CC
• Package
68 pin PGA
64 pin Flatpack
V
Ground
GB
HKC
SS
WE\
DRAM Write-Enable Select
• Operating Temperature Ranges
- Military (-55oC to +125oC)
-Industrial (-40oC to +85oC)
For more products and information
please visit our web site at
www.austinsemiconductor.com
XT suffix
IT suffix
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PERFORMANCE RANGES
-70
-75
-80
MAX UNITS
DESCRIPTION
SYM
MIN
MAX
MIN
MAX
MIN
Access Time Row Enable
t
70
75
80
25
ns
a(R)
Access Time Serial Data
DRAM Cycle Time
DRAM Page Mode
Serial Cycle Time
t
20
23
ns
ns
ns
ns
a(SQ)
t
130
45
140
48
150
50
c(W)
t
c(P)
t
22
24
30
c(SC)
Operating Current,
Serial Port Stand-by
Operating Current,
Serial Port Active
I
165
210
165
210
210
195
mA
mA
CC1
I
CC1A
GB PACKAGE (Bottom View) & PIN ASSIGNMENTS
PIN No.
NAME
PIN No.
NAME
V
J1
DQ1
E8
SS1
J2
J3
SQ3
DQ3
E9
D1
A4
SE\
V
J4
J5
J6
DQ4
DQ5
DQ6
D2
D3
D7
SS1
V
DD1
V
SS1
J7
J8
J9
SQ7
CASL\
A8
D8
D9
C1
A3
A2
SQ15
V
H1
H2
H3
H4
H5
DQ0
SQ2
DQ2
SQ4
SQ5
C2
C3
C4
C6
C7
SS1
V
DD2
V
SS2
V
DD2
V
SS2
H6
H7
H8
H9
G1
G2
SQ6
DQ7
WE\
A7
SQ0
SQ1
C8
C9
B1
B2
B3
B4
CASU\
A1
DQ15
DQ14
DQ13
DQ12
V
G3
G4
G6
G7
B5
B6
B7
B8
DQ11
DQ10
SQ8
DD2
V
SS2
V
DD2
V
DSF
SS2
G8
G9
F1
RAS\
A6
TRG
B9
A1
A2
A0
SQ14
SQ13
V
F2
F3
F7
F8
A3
A4
A5
A6
SQ12
SQ11
SQ10
SQ9
SS1
V
DD1
V
DD1
V
DD1
F9
E1
A5
SC
A7
A8
DQ9
DQ8
V
E2
A9
QSF
DD1
SMJ55161A
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GENERAL DESCRIPTION
The SMJ55161A, a multiport-video random-access memory
The SMJ55161A offers a split-register-transfer read
(RAM), is a high-speed, dual-port memory device. It consists (DRAM-to-SAM) feature for the serial register (SAM port) that
of a dynamic RAM (DRAM) module organized as 262 144 words enables real-time-register-load implementation for continuous
of 16 bits each interfaced to a serial-data register (serial-access serial-data streams without critical timing requirements. The
memory [SAM]) organized as 512 words of 16 bits each. The register is divided into a high half and a low half. While one half
SMJ55161A supports three basic types of operation: random is being read out of the SAM port, the other half can be loaded
access to and from the DRAM, serial access to/from the serial from the memory array. For applications not requiring real-time
register, and transfer of data from any row in the DRAM to the register load (for example, loads done during CRT-retrace
serial register and vice versa. Except during transfer operations, periods), the full-register mode of operation is retained to
the SMJ55161A can be accessed simultaneously and simplify system design.
asynchronously from the DRAM and SAM ports.
The SAM port is designed for maximum performance. Data
The SMJ55161A is equipped with several features designed can be accessed from the SAM at serial rates up to 50 MHz.
to provide higher system-level bandwidth and to simplify design During the split-register-transfer read operations, internal
integration on both the DRAM and SAM ports. On the DRAM circuitry detects when the last bit position is accessed from the
port, greater pixel-draw rates are achieved by the device’s active half of the register and immediately transfers control to
(8 × 8) × 2 block-write feature. The block-write mode allows 16 the opposite half. A separate output, QSF, is included to
bits of data (present in an on-chip color-data register) to be indicate which half of the serial register is active.
written to any combination of eight adjacent column-address
All inputs, outputs, and clock signals on the SMJ55161 are
locations. As many as 128 bits of data can be written to memory compatible with Series 54/74 TTL. All address lines and data-in
during each CAS\ cycle time. Also, on the DRAM port and lines are latched on-chip to simplify system design. All data-
SAM port, a write mask or a write-per-bit feature allows out lines are unlatched to allow greater system flexibility.
masking of any combination of the 16 inputs/outputs on any
The SMJ55161A is offered in a 68-pin ceramic pin-grid-
write cycle. The persistent write-per-bit feature uses a mask array package (GB suffix) and a 64-pin ceramic flatpack (HKC
register that, once loaded, can be used on subsequent write suffix).
cycles without reloading. The SMJ55161A also offers byte
The SMJ55161A is supported by a broad line of graphic
control which can be applied in read cycles, write cycles, block- processors and control devices from Texas Instruments. See
write cycles, load-write-mask-register cycles, and load-color- Table 2 and Table 4 for additional information.
register cycles. The SMJ55161A also offers extended-data-
Additional features of the 55161A include MASKED
output (EDO) mode. The EDO mode is effective in both the FLASH WRITE which allows for data in color register to be
page-mode and standard DRAM cycles.
written into all the memory locations of a selected row.
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FUNCTIONAL BLOCK DIAGRAM
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TABLE 1: DRAM & SAM FUNCTIONS
CASx\
DQ0-DQ151
RAS\ FALL
ADDRESS
FALL
MNE
CODE
FUNCTION
CASL\
RAS\ CASU\
WE\
2
3
TRG\
WE\
DSF
DSF
RAS\
CASx\
CASX\
Reserved (do not use)
CBR refresh (no reset) and stop-
L
L
L
L
L
L
X
X
X
Stop
X
X
X
X
---
X
H
X
X
CBRS
4
5
point set
point
X
6
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
CBR
CBR refresh (option reset)
7
H
X
CBRN
CBR refresh (no reset)
Row
Tap
Full-register-transfer read
Split-register-transfer read
H
H
H
L
L
H
H
L
L
H
L
X
X
L
X
X
X
X
RT
Address Point
Row Tap
Address Point
Row
SRT
RWM
DRAM write
(nonpersistent write-per-bit)
Column Write
Valid
Data
H
Address Address Mask
Block
Address
A3-A8
DRAM block write
(nonpersistent write-per-bit)
Row
Address
Write Column
Mask Mask
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
BWM
RWM
BWM
RW
DRAM write
(persistent write-per-bit)
Row
Column
Address Address
Valid
Data
X
Block
Row
DRAM block write
(persistent write-per-bit)
Column
Mask
L
H
L
Address
Address
A3-A8
X
Row
Column
Address Address
Valid
Data
DRAM write (nonmasked)
H
H
X
Block
Row
Column
Mask
DRAM block write (nonmasked)
H
Address
Address
A3-A8
X
BW
Refresh
X
Write
Mask
8
H
H
H
H
H
H
H
L
H
H
L
H
H
L
L
H
X
X
X
X
LMR
LCR
Load write-mask register
Address
Refresh
X
Color
Data
Load color register
X
Address
Row
Tap
Write
X
9
MWT
MSWT
FWM
Masked Write Transfer
Address Point
Mask
Row Tap
Address Point
Write
X
9
L
L
H
H
Masked Split Write Transfer
Mask
Row
X
Write
---
9
H
L
Masked Flash Write Transfer
Address
Mask
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Don’t Care
NOTES:
1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the power-up initialization cycle.
5. A0–A3, A8: don’t care; A4–A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
SMJ55161A
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TABLE 2: PIN DESCRIPTIONS VS. OPERATIONAL MODE
PIN
DRAM
TRANSFER
SAM
A0-A8 Row, column address
CASL\,
Row address, Tap point
Column-address strobe, DQ output enable
Tap-address strobe
CASU\
DQ
DRAM data I/O, write mask
Block-write enable
Split-register-transfer enable
Write-mask-register load enable
Color-register load enable
CBR (option reset)
DSF
RAS\
SE\
Row-address strobe
Row-address strobe
Transfer enable
SQ output enable,
QSF output enable
Serial clock
SC
SQ
Serial-data output
TRG\ DQ output enable
WE\
QSF
Write enable, write-pre-bit enable
Special-function output
Serial-register status
Either make no external connection or tie to
NC/GND
system GND (V
)
SS
1
CC
5V supply
V
1
Ground
V
SS
NOTES: 1. For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground.
address (A0–A8)
row-address strobe (RAS\)
Eighteen address bits are required to decode each one of
RAS\ is similar to a chip enable so that all DRAM cycles
the 262 144 storage cell locations. Nine row-address bits are set and transfer cycles are initiated by the falling edge of RAS\.
up on pins A0–A8 and latched onto the chip on the falling edge RAS\ is a control input that latches the states of the row
of RAS\. Nine column-address bits are set up on pins A0–A8 address, WE\, TRG\, CASL\, CASU\, and DSF onto the chip to
and latched onto the chip on the first falling edge of CASx\. All invoke DRAM and transfer-read/write functions of the
addresses must be stable on or before the falling edge of RAS\ SMJ55161A.
and the first falling edge of CASx\.
During the full-register-transfer read operation, the states
of A0–A8 are latched on the falling edge of RAS\ to select one
column-address strobe (CASL, CASU)
CASL\ and CASU\ are control inputs that latch the states
of the 512 rows where the transfer occurs. At the first falling
of the column address and DSF to control DRAM and transfer
edge of CASx\, the column-address bits A0–A8 are latched.
functions of the SMJ55161A. CASx\ also acts as output enable
The most significant column-address bit (A8) selects which
for the DRAM output pins DQ0–DQ15. In DRAM operation,
half of the row is transferred to the SAM. The appropriate 8-bit
CASL\ enables data to be written to or read from the lower byte
column address (A0–A8) selects one of 512 tap points (starting
(DQ0–DQ7), and CASU\ enables data to be written to or from
positions) for the serial-data output.
the upper byte (DQ8–DQ15). In transfer operations, address
During the split-register-transfer read operation, an
bits A0–A8 are latched at the first falling edge of CASx\ as the
internal counter selects which half of the register is used. If the
start position (tap) for the serial-data output (SQ0–SQ15).
high half of the SAM is currently in use, the low half of the
SAM is loaded with the low half of the DRAM half row and vice
versa. Column address (A8) selects the DRAM half row. The
remaining eight address bits (A0–A7) are used to select one of
256 possible starting locations within the SAM.
SMJ55161A
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serial-data outputs (SQ0 –SQ15)
output enable/transfer select (TRG\)
TRG\ selects either DRAM or transfer operation as RAS\
Serial data is read from the SQ pins. The SQ output buffers
falls. For DRAM operation, TRG\ must be held high as RAS\ provide direct TTL compatibility (no pullup resistors) with a
falls. During DRAM operation, TRG functions as an output fanout of one Series 54 TTL load. The serial outputs are in the
enable for the DRAM output pins DQ0–DQ15. For transfer high-impedance (floating) state as long as the serial-enable pin,
operation, TRG\ must be brought low before RAS\ falls.
SE\, is high. The serial outputs are enabled when SE\ is brought
low.
write-mask select, write enable (WE)
In DRAM operation, WE\ enables data to be written to the
DRAM. WE\ is also used to select the DRAM write-per-bit
mode. Holding WE\ low on the falling edge of RAS\ invokes
the write-per-bit operation. The SMJ55161A supports both the
nonpersistent write-per-bit mode and the persistent write-per-
bit mode.
serial clock (SC)
Serial data is accessed out of the data register during the
rising edge of SC. The SMJ55161A is designed to work with a
wide range of clock duty cycles to simplify system design.
There is no refresh requirement because the data registers that
comprise the SAM are static. There is also no minimum SC-
clock operating frequency.
special-function select (DSF)
The DSF input is latched on the falling edge of RAS\ or the
first falling edge of CASx\, similar to an address. DSF deter-
mines which of the following functions are invoked on a par-
ticular cycle:
serial enable (SE)
During serial-access operations, SE\ is used as an enable/
disable for the SQ outputs. SE\ low enables the serial-data out-
put while SE\ high disables the serial-data output. SE\ is also
used as an enable/disable for output pin QSF.
IMPORTANT: While SE\ is held high, the serial clock is
not disabled. External SC pulses increment the internal serial-
address counter regardless of the state of SE\. This ungated
serial-clock scheme minimizes access time of serial output from
SE\ low because the serial-clock input buffer and the serial-
address counter are not disabled by SE\.
• CBR refresh with reset (CBR)
• CBR refresh with no reset (CBRN)
• CBR refresh with no reset and stop-point set (CBRS)
• Block write
• Loading write-mask register for the persistent
write-per-bit mode (LMR)
• Loading color register for the block-write mode
• Split-register-transfer read
special-function output (QSF)
QSF is an output pin that indicates which half of the SAM
is being accessed. When QSF is low, the serial-address pointer
is accessing the lower (least significant) 256 bits of the serial
register (SAM). When QSF is high, the pointer is accessing the
higher (most significant) 256 bits of the SAM.
During full-register-transfer operations, QSF can change
state upon completing the cycle. This state is determined by
the tap point loaded during the transfer cycle. QSF is enabled
by SE\; therefore, if SE\ is high, the QSF output is in the high-
impedance state.
DRAM data I/O, write mask data (DQ0–DQ15)
DRAM data is written or read through the common I/O DQ
pins. The 3-state DQ-output buffers provide direct TTL
compatibility (no pullup resistors) with a fanout of one Series
54 TTL load. Data out is the same polarity as data in. During a
normal access cycle, the outputs remain in the high-impedance
state until TRG\ is brought low. Data appears at the outputs
until TRG\ returns high, CASx\ returns high following RAS\
returning high, or RAS\ returns high following CASx\ returning
high. The write mask is latched into the device through the
random DQ pins by the falling edge of RAS\ and is used on all
write-per-bit cycles. In a transfer operation, the DQ outputs
remain in the high-impedance state for the entire cycle.
no connect / ground (NC/GND)
NC/GND must be tied to system ground or left floating for
proper device operation.
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TABLE 3: DRAM FUNCTIONS
CASx\
DQ0-DQ151
RAS\ FALL
ADDRESS
RAS\
FALL
MNE
CODE
FUNCTION
CASL\
RAS\ CASU\
2
3
TRG\
WE\
DSF
DSF
CASx\
CASX\
WE\
Reserved (do not use)
CBR refresh (no reset) and stop-
L
L
L
L
L
L
X
X
X
Stop
X
X
X
X
---
X
H
X
X
CBRS
4
5
point set
point
X
6
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
CBR
CBR refresh (option reset)
7
H
X
CBRN
CBR refresh (no reset)
DRAM write
(nonpersistent write-per-bit)
Row
Column Write
Valid
Data
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
RWM
BWM
RWM
BWM
RW
Address Address Mask
Block
Address
A3-A8
DRAM block write
(nonpersistent write-per-bit)
Row
Address
Write Column
Mask Mask
DRAM write
(persistent write-per-bit)
Row
Address Address
Column
Valid
Data
L
X
Block
Row
DRAM block write
(persistent write-per-bit)
Column
Mask
L
H
L
Address
Address
A3-A8
X
Row
Address Address
Column
Valid
Data
DRAM write (nonmasked)
H
H
X
Block
Row
Column
Mask
DRAM block write (nonmasked)
H
Address
Address
A3-A8
X
BW
Refresh
X
Write
Mask
8
H
H
H
H
H
H
H
H
L
X
LMR
LCR
Load write-mask register
Address
Refresh
X
Color
Data
Load color register
H
X
Address
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Don’t Care
NOTES:
1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the powerup initialization cycle.
5. A0–A3, A8: don’t care; A4–A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
7. CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
SMJ55161A
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need to be refreshed consecutively as long as the entire refresh
enhanced page mode
is completed within the required time period, trf(MA). The
output buffers remain in the high-impedance state during the
CBR refresh cycles regardless of the state of TRG\.
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting ran-
dom column addresses. This mode eliminates the time required
for row-address setup, row-address hold, and address multi-
plex. The maximum RAS\ low time and CAS\ page cycle time
used determine the number of columns that can be accessed.
Unlike conventional page-mode operations, the enhanced
page mode allows the SMJ55161A to operate at a higher data
bandwidth. Data retrieval begins as soon as the column
address is valid rather than when CASx\ transitions low. A
valid column address can be presented immediately after the
row-address hold time has been satisfied, usually well in
advance of the falling edge of CASx\. In this case, data is
hidden refresh
A hidden refresh is accomplished by holding both CASL\
and CASU\ low in the DRAM read cycle and cycling RAS\. The
output data of the DRAM read cycle remains valid while the
refresh is carried out. Like the CBR refresh, the refreshed row
addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS\-only refresh is accomplished by cycling RAS\ at
every row address. Unless CASx\ and TRG\ are low, the output
buffers remain in the high-impedance state to conserve power.
Externally-generated addresses must be supplied during RAS\-
only refresh. Strobing each of the 512 row addresses with RAS\
causes all bits in each row to be refreshed.
obtained after ta(C) MAX (access time from CASx\ low) if ta(CA)
MAX (access time from column address) has been satisfied.
REFRESH
CAS-before-RAS (CBR) refresh
extended data output
CBR refreshes are accomplished by bringing either or both
CASL\ and CASU\ low earlier than RAS\. The external row
address is ignored, and the refresh row address is generated
internally. Three types of CBR refresh cycles are available. The
CBR refresh (option reset) ends the persistent write-per-bit mode
and the stop-point mode. The CBRN and CBRS refreshes (no
reset) do not end the persistent write-per-bit mode or the stop-
point mode. The 512 rows of the DRAM do not necessarily
The SMJ55161A features EDO during DRAM accesses. While
RAS\ and TRG\ are low, the DRAM output remains valid. The
output remains valid even when CASx\ returns high until WE\
is low, TRG\ is high, or both CASx\ and RAS\ are high (see
Figure 1 and Figure 2). The EDO mode functions during all read
cycles including DRAM read, page-mode read, and read-
modify-write cycles (see Figure 3).
FIGURE 1: DRAM Read Cycle With RAS\-Controlled Output
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FIGURE 2: DRAM Read Cycle With CASx\-Controlled Output
FIGURE 3: DRAM Page-Read Cycle with Extended Output
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byte operation
Byte operation can be applied in DRAM-read cycles, write written to the upper byte (DQ8–DQ15). In an early write cycle,
cycles, block-write cycles, load-write-mask-register cycles, and WE is brought low prior to both CASx\ signals, and data setup
load-color-register cycles. In byte operation, the column and hold times for DQ0 –DQ15 are referenced to the first falling
address (A0–A8) is latched at the first falling edge of CASx\. In edge of CASx\ (see Figure 5).
read cycles, CASL\ enables the lower byte (DQ0–DQ7) and
CASU\ enables the upper byte (DQ8–DQ15) (see Figure 4).
For late-write or read-modify-write cycles, WE\ is brought
low after either or both CASL\ and CASU\ fall. The data is
In byte-write operation, CASL enables data to be written strobed in with data setup and hold times for DQ0 –DQ15
to the lower byte (DQ0–DQ7), and CASU\ enables data to be referenced to WE\ (see Figure 6).
FIGURE 4: Example of a Byte-Read Cycle
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FIGURE 5: Example of an Early-Write Cycle
FIGURE 6: Example of a Late-Write Cycle
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edge of RAS\. The write-per-bit mask selects which of the 16
I/Os are to be written and which are not. After RAS\ has latched
the on-chip write-per-bit mask, input data is driven onto the DQ
pins and is latched on either the first falling edge of CASx\ or
the falling edge of WE\, whichever occurs later. CASL\ enables
the lower byte (DQ0–DQ7) to be written through the mask and
CASU\ enables the upper byte (DQ8–DQ15) to be written
through the mask. If a data low (write mask = 0) is strobed into
a particular I/O pin on the falling edge of RAS\, data is not
written to that I/O. If a data high (write mask = 1) is strobed into
a particular I/O pin on the falling edge of RAS\, data is written
to that I/O (see Figure 7).
write-per-bit
The write-per-bit feature allows masking any combination of
the 16 DQs on any write cycle. The write-per-bit operation is
invoked when WE\ is held low on the falling edge of RAS\. If
WE\ is held high on the falling edge of RAS\, the write opera-
tion is performed without any masking. The SMJ55161A offers
two write-per-bit modes: nonpersistent write-per-bit and per-
sistent write-per-bit.
nonpersistent write-per-bit
When WE\ is low on the falling edge of RAS\, the write mask is
reloaded. A 16-bit binary code (the write-per-bit mask) is input
to the device through the DQ pins and latched on the falling
FIGURE 7: Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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the write-mask register via the random I/O pins and latched on
either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later. Byte write control can be applied to the
write mask during the LMR cycle. The persistent write-per-bit
mode can then be used in exactly the same way as the
nonpersistent write-per-bit mode except that the input data on
the falling edge of RAS\ is ignored. When the device is set to
the persistent write-per-bit mode, it remains in this mode and is
reset only by a CBR refresh (option-reset) cycle (see Figure 8).
persistent write-per-bit
The persistent write-per-bit mode is initiated by
performing a load-write-mask-register (LMR) cycle. In the
persistent write-per-bit mode, the write-per-bit mask is
overwritten but remains valid over an arbitrary number of write
cycles until another LMR cycle is performed or power is
removed.
The LMR cycle is performed using DRAM write-cycle
timing with DSF held high on the falling edge of RAS\ and held
low on the first falling edge of CASx\. A binary code is input to
FIGURE 8: Example of a Persistent Write-Per-Bit Operation
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data. Nonpersistent write-per-bit or persistent write-per-bit
functions can be applied to the block-write operation to
provide write-masking options. The DQ data is provided by 8
bits from the on-chip color register. Bits 0–7 from the 16-bit
write-mask register, bits 0 –7 from the 16-bit column-mask
register, and bits 0 –7 from the 16-bit color-data register
configure the block write for the first half, while bits 8 - 15 of the
corresponding register control the other half in a similar
fashion (see Figure 10).
block write
The block-write feature allows up to 128 bits of data to be
written simultaneously to one row of the memory array. This
function is implemented as eight columns by eight DQs and
repeated in two halves. In this manner, each of the two 2M-bit
halves can have up to eight consecutive columns written at a
time with up to eight DQs per column (see Figure 9).
Each 2M-bit half has a 8-bit column mask to mask off and
prevent any or all of the eight columns from being written with
FIGURE 9: Block-Write Operation
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FIGURE 10: Block-Write With Masks
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Column-address bits A0 and A2 are ignored. Block 0 (columns
0 –7) is selected for each 2M-bit half. The first half has
DQ0–DQ2 written with bits 0–2 from the color-data register
(101) to first four columns of block 0. DQ3 is not written and
retains its previous data due to write-mask-register-bit 3
being 0. DQ4–DQ7 has all four columns masked off due to
column-mask bits 4–7 being 0 so that no data is written.
The second half (DQ8–DQ11 ) has its four DQs written
with bits 8 –11 from the color-data register (1100) to columns
1–3 of its block 0. Column 0 is not written and retains its previ-
ous data on all four DQs due to column-mask-register-bit 8
being 0.
DQ12–DQ15 has DQ12, DQ14, and DQ15 written with bits
12, 14, and 15 from the color-data register to column 0 and
column 2 of its block 0. DQ13 retains its previous data on all
columns due to the write mask. Columns 1 and 3 retain their
previous data on all DQs due to the column mask. If the previ-
ous data for DQ12-DQ15 is all 0s, the upper half (DQ12-DQ15)
contains the data pattern shown in Figure 12 after the block-
write operation shown in the previous example.
block write (continued)
A set of eight columns makes a block, resulting in 64 blocks
along one row. Block 0 comprises columns 0 –7,
block 1 comprises columns 7 –15, block 2 comprises columns 16
–23, etc., as shown in Figure 11.
During block-write cycles, only the six most significant
column addresses (A3–A8) are latched on the first falling edge
of CASx to decode one of the 64 blocks. Address bits A0–A2
are ignored. Each 2M-bit half has the same block selected.
A block-write cycle is entered in a manner similar to a DRAM
write cycle except DSF is held high on the first falling edge of
CASx\. As in a DRAM write operation, CASL\ and CASU\
enable the corresponding lower and upper DRAM DQ bytes to
be written. The column-mask data is input via the DQs and is
latched on either the first falling edge of CASx\ or the falling
edge of WE\, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as
described below. Refer to the write-per-bit section for details on
use of the write-mask capability, allowing additional performance
options.
Example of block write:
Block-write column address = 110000000
(A0–A8 from left to right)
FIGURE 12: Example of Upper
DQ12-DQ15 After A Block-Write
Operation With Previous Data Of 0
bit 0
Color-data register = 1011
Write-mask register = 1110
Column-mask register = 1111
1st
bit 15
0111
1011
1010
4th
1011
1111
0000
2nd
1100
1111
0111
3rd
Quad Quad Quad Quad
FIGURE 11: Block Columns Organization
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falling edge of CASx\ or the falling edge of WE\, whichever
occurs later. If only one CASx\ is low, only the corresponding
byte of the color register is loaded. When the color register is
loaded, it retains data until power is lost or until another load-
color-register cycle is performed (see Figure 13 and Figure 14).
load color register
The load-color-register cycle is performed using normal DRAM
write-cycle timing except that DSF is held high on the falling
edges of RAS\, CASL\, and CASU\. The color register is loaded
from pins DQ0 –DQ15, which are latched on either the first
FIGURE 13: Example of Block Writes
FIGURE 14: Example Of A Persistent Block Write
Legend:
1. Refresh address
2. Row address
3. Block address (A3–A8) is latched on the first falling edge of CASx\.
4. Color-register data
5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS\.
6. Column-mask data: DQi–DQi+7 (i = 0, 8) are latched on either the first falling edge of CASx\ or the falling edge of WE\,
whichever occurs later.
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DRAM-to-SAM transfer operation
full-register-transfer read
During the DRAM-to-SAM transfer operation, one row
A full-register-transfer read operation loads data from a
(512 columns) in the DRAM array is selected to be transferred selected half of a row in the DRAM into the SAM. TRG\ is
to the 512-bit serial-data register. The transfer operation is brought low and latched at the falling edge of RAS\. Nine row-
invoked by TRG\ being brought low and WE\ being held high address bits (A0–A8) are also latched at the falling edge of
on the falling edge of RAS\. The state of DSF, which is latched RAS\ to select one of the 512 rows available for the transfer.
on the falling edge of RAS\, determines whether the full- The nine column-address bits (A0– A8) are latched at the first
register-transfer read operation or the split-register-transfer read falling edge of CASx\. Address bits A0–A8 select one of the
operation is performed (see Table 4).
SAM’s 512 available tap points from which the serial data is
read out.
A full-register-transfer read can be performed in three ways:
early load, real-time load (or midline load), or late load. Each of
these offers the flexibility of controlling the TRG\ trailing edge
in the full-register-transfer read cycle (see Figure 15).
TABLE 4: SAM Fuction Table
CASx\
FALL
RAS\ FALL
ADDRESS
DQ0-DQ15
MNE
FUNCTION
CASx\ CODE
WE\
1
TRG\
WE\
DSF
DSF
RAS\
Row
CASX\ RAS\
CASx\
Tap
X
Full-register-transfer Read
Split-register-transfer Read
H
L
H
L
X
X
X
X
RT
Address Point
Row
Address Point
Tap
H
L
H
H
X
SRT
LEGEND:
X = Don’t Care
NOTES:
1. Logic L is selected when either CASL\ or CASU\ are low.
FIGURE 15: Example of Full-Register-Transfer Read Operations
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output mode (Read transfer), or output to input mode (Write
transfer). It remains unchanged during split transfer operation
(Split read transfer or Split write transfer).
split-register-transfer read
The SMJ55161A features two types of bidirectional data
transfer capability between DRAM and SAM.
Both DRAM and SAM are divided by the most significant
row address (AX8), as shown in Figure 16. Therefore, no data
transfer between AX8=0 side DRAM and AX8=1 side DRAM
can be provided through the SAM. Care must be taken if the
split read transfer on AX8=1 side (or AX8=0 side) is provided
after the read transfer or the split read transfer, is provided on
AX8=0 side (or AX8=1 side).
QSF indicates which half of the register is being accessed
during serial-access operation. When QSF is low, the serial-
address pointer is accessing the lower (least significant) 256
bits of the SAM. When QSF is high, the pointer is accessing
the higher (most significant) 256 bits of the SAM. QSF changes
state upon completing a full-register-transfer-read cycle. The
tap point loaded during the current transfer cycle determines
the state of QSF. QSF also changes state when a boundary
between two register halves is reached.
1) Conventional (non split) transfer: 512 words by 16 bits of
data can be loaded from DRAM to SAM (Read transfer), or
from SAM to DRAM (write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from
the lower/upper half of the DRAM to the lower/uppper half of
the SAM (Split read transfer), or from the lower/upper half to
SAM to the lower/upper half of DRAM (Split write transfer).
The conventional transfer and split transfer modes are
controlled by the DSF input signal. Data transfer is invoked by
holding the TRG\ signal “low” at the falling edge of RAS\.
The SMJ55161A supports 4 types of transfer operations:
Read transfer, Split read transfer, Write transfer and Split write
transfer as shown in the truth table. The type of transfer
operation is determined by the state of CAS\, WE\, and DSF
latched at the falling edge of RAS\. During conventional
transfer operations, the SAM port is switched from input to
FIGURE 16: DRAM and SAM Configuration
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FIGURE 17: Example Of A Split-Register-Transfer Read After A Full-
Register-Transfer Read
FIGURE 18: Example Of Successive Split-Register-Transfer-Read
Operations
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If there is no split-register-transfer read to the inactive half
during this period, the serial pointer points next to bit 256 or bit
0, respectively (see Figure 21).
serial-read operation
The serial-read operation can be performed through the
SAM port simultaneously and asynchronously with DRAM
operations except during transfer operations. Serial data can be
read from the SAM by clocking SC starting at the tap point
loaded by the preceding transfer cycle, proceeding
sequentially to the most significant bit (bit 255), and then
wrapping around to the least significant bit (bit 0), as shown in
Figure 19.
split-register programmable stop point
The SMJ55161A offers a programmable stop-point mode
for split-register-transfer read operations. This mode can be
used to improve two-dimensional drawing performance in a
nonscanline data format.
For split-register-transfer-read operation, serial data can
be read out from the active half of the SAM by clocking SC
starting at the tap point loaded by the preceding split-
register-transfer cycle. The serial pointer then proceeds
sequentially to the most significant bit of the half, bit 255 or bit
511. If there is a split-register-transfer read to the inactive half
during this period, the serial pointer points next to the tap point
location loaded by that split-register transfer (see Figure 20).
For a split-register-transfer-read operation, the stop point
is defined as a register location at which the serial output stops
coming from one half of the SAM and switches to the opposite
half of the SAM. While in stop-point mode, the SAM is divided
into partitions whose length is programmed via row addresses
A4–A7 in a CBR set (CBRS) cycle. The last serial-address
location of each partition is the stop point (see Figure 22).
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In stop-point mode, the tap point loaded during the split-
register-transfer read cycle determines the SAM partition in
which the serial output begins and at which stop point the
serial output stops coming from one half of the SAM and
switches to the opposite half of the SAM (see Figure 23).
The stop-point mode of the previous revision 55161 is
designed to be compatible with both 256-bit SAM and 512-bit
SAM devices like the 55161A.
split-register programmable stop point
(continued)
Stop-point mode is not active until the CBRS cycle is
initiated. The CBRS operation is enabled by holding CASx\ and
WE\ low and DSF high on the falling edge of RAS\. The falling
edge of RAS\ also latches row addresses A4–A7 which are
used to define the SAM’s partition length. The other row-
address inputs are don’t cares. Stop-point mode should be
initiated after the initialization cycles are performed
(see Table 5).
IMPORTANT: For proper device operation, a stop-point-
mode (CBRS) cycle should be initiated immediately after the
power-up initialization cycles are performed.
TABLE 5: Programming Code for Stop-Point Mode
MAX
PARTITION
LENGTH
NUMBER OF
PARTITIONS
ADDRESS AT RAS\ IN CBRS CYCLE
STOP-POINT LOCATIONS
A8
A7
A6
A5
A4 A0 - A3
31, 63, 95, 127, 159, 191, 223, 255, 287,
319, 351, 383, 415, 447, 479, 511
63, 127, 191, 255, 319, 383, 447, 511
127, 255, 383, 511
255, 511
255
16
X
L
L
L
L
X
16
32
64
128
256
X
X
X
X
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
X
X
X
X
8
4
2
1
H
FIGURE 23: Example of Split-Register Operation With Programmable
Stop Points
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register-transfer-read cycle and two SC cycles are required to
initialize the SAM port.
After initialization, the internal state of the SMJ55161A is
as shown in Table 6.
power up
To achieve proper device operation, an initial pause of 200 ms is
required after power up followed by a minimum of eight RAS\
cycles or eight CBR cycles to initialize the DRAM port. A full-
TABLE 6: Internal State of SMJ55161A
STATE
STATE AFTER INITIALIZATION
Defined by the transfer cycle during initialization
Nonpersistent Mode
QSF
Write Mode
Write-mask Register
Color Register
Undefined
Undefined
Serial-Register Tap Point Defined by the transfer cycle during initialization
SAM Port Output Mode
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
Supply voltage range, VCC**........................................-1V to +7 V
Voltage range on any pin................................................-1Vto +7 V
Short-circuit output current.......................................................50mA
Power dissipation.........................................................................1.1W
Operating free-air temperature range, TA...................-55°C to 125°C
Storage temperature range, Tstg..................................-65°C to 150°C
**All voltage values are with respect to VSS.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Supply Voltage
SYMBOL
MIN
NOM
MAX
UNIT
V
4.5
5
5.5
V
CC
Supply Voltage
V
0
V
V
SS
High-level input voltage
V
2.4
-0.5
-55
V
+0.5
IH
CC
1
V
0.8
125
V
Low-level input voltage
IL
A
Operating free-air temperature
T
°C
NOTES:
1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)
SAM
PORT MIN MAX MIN MAX MIN MAX UNIT
-70
-75
-80
PARAMETER
SYMBOL
CONDITIONS
= -1 mA
High-level output voltage
V
V
V
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
V
= 2 mA
0.4
10
0.4
10
0.4
10
OL
OL
V
= 5.5V,
CC
I
V = 0V to 5.8V,
µA
I
I
All other pins at 0V to V
CC
3
I
V
= 5.5V, V = 0V to V
CC
10
140
180
12
10
130
170
12
10
120
160
12
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Output current (leakage)
O
CC
O
2
I
See note 4
t = MIN
c(SC)
Standby
Active
Operating current
CC1
2
I
I
I
I
I
I
Operating current
CC1A
All clocks = VCC
tc(SC) = MIN
See note 4
Standby current
I
Standby
Active
CC2
Standby current
60
55
50
CC2A
RAS\-only refresh current
RAS\-only refresh current
I
Standby
Active
130
175
140
190
110
150
120
170
120
165
130
180
100
140
120
160
115
155
120
170
95
CC3
5
tc(SC) = MIN
CC3A
2
5
I
Standby
Active
Page-mode current
tc(P) = MIN
CC4
5
Page-mode current2
CBR current
tc(SC) = MIN
CC4A
I
See note 4
Standby
Active
CC5
5
CBR current
130
110
150
tc(SC) = MIN
CC5A
Data-transfer current
Data-transfer current
I
See note 4
Standby
Active
CC6
tc(SC) = MIN
CC6A
NOTES:
1. For conditions shown as MAX/MIN, use the appropriate value specified in the timing requirements.
2. Measured with outputs open.
3. SE\ is disabled for SQ output leakage tests.
4. Measured with one address change while RAS\ = VIL; tc(rd), tc(W), tc(TRD) = MIN.
5. Measured with one address change while CASx\ = VIH
.
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CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Input capacitance, address inputs
C
5
10
pF
i(A)
Input capacitance, address-strobe inputs
Input capacitance, write-enable input
Input capacitance, serial clock
C
8
7
10
10
10
10
10
10
15
12
pF
pF
pF
pF
pF
pF
pF
pF
i(RC)
C
i(W)
i(SC)
i(SE)
C
C
6
Input capacitance, serial enable
Input capacitance, special function
Input capacitance, transfer-register input
Output capacitance, SQ and DQ
Output capacitance, QSF
7
C
7
i(DSF)
i(TRG)
C
7
C
12
10
O(O)
C
O(QSF)
NOTES: *VCC = 5V ±0.5V, and the bias on pins under test is 0V.
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1
-70
-75
-80
PARAMETER
Access time from CASx\
SYMBOL CONDITIONS2 MIN MAX MIN MAX MIN MAX UNIT
t
17
35
40
70
17
20
17
17
17
17
17
15
20
38
43
75
20
23
18
20
20
20
25
18
20
40
45
80
20
25
20
20
20
20
25
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
a(C)
Access time from column address
Access time from CASx\ high
Access time from RAS\
t
t
a(CA)
a(CP)
t
= MAX
d(RLCL)
t
a(R)
Access time of DQ from TRG\ low
Access time of SQ from SC high
Access time of SQ from SE\ low
t
a(G)
t
C = 30 pF
L
a(SQ)
t
C = 30 pF
a(SE)
L
3
t
t
C = 50 pF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Disable time, random output from CASx\ high
dis(CH)
dis(RH)
L
3
C = 50 pF
Disable time, random output from RAS\ high
L
3
t
C = 50 pF
Disable time, random output from TRG\ high
Disable time, random output from WE\ low
dis(G)
L
t
C = 50 pF
L
dis(WL)
Disable time, serial output from SE\ high
t
C = 30 pF
L
dis(SE)
NOTES:
1. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50pF. Data-out reference level: VOH/VOL = 2V/0.8V.
Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30pF. Serial-data out reference level: VOH/VOL
=
2V/0.8V.
2. For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
3. tdis(CH), tdis(RH), tdis(G), tdis(WL), and tdis(SE) are specified when the output is no longer driven.
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TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1
-70
-75
-80
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNIT
Cycle time, read
Cycle time, write
t
124
124
170
35
140
140
188
48
150
150
200
50
ns
ns
ns
ns
ns
ns
ns
ns
c(rd)
t
c(W)
Cycle time, read-modify-write
t
c(rdW)
Cycle time, page-mode read, write
Cycle time, page-mode read-modify-write
Cycle time, transfer read
t
c(P)
c(RDWP)
t
74
88
90
t
130
20
140
24
150
30
c(TRD)
2
t
Cycle time, serial clock
c(SC)
Pulse duration, CASx\ high
t
10
10
10
w(CH)
3
t
15 10,000 20 10,000 20 10,000 ns
50 55 60 ns
70 10,000 75 10,000 80 10,000 ns
Pulse duration, CASx\ low
w(CL)
w(RH)
Pulse duration, RAS\ high
t
4
t
Pulse duration, RAS\ low
w(RL)
Pulse duration, WE\ low
t
10
17
7
13
20
9
15
20
10
10
20
ns
ns
ns
ns
ns
w(WL)
Pulse duration, TRG\ low
t
w(TRG)
t
w(SCH)
Pulse duration, SC high
Pulse duration, SC low
t
7
9
w(SCL)
Pulse duration, TRG\ high
t
20
20
w(GH)
Pulse duration, RAS\ low (page mode)
Setup time, column address before CASx\ low
Setup time, DSF before CASx\ low
Setup time, row address before RAS\ low
Setup time, WE\ before RAS\ low
Setup time, DQ before RAS\ low
Setup time, TRG\ high before RAS\ low
Setup time, DSF low before RAS\ low
Setup time, data valid before CASx\ low
Setup time, data valid before WE\ low
t
70 100,000 75 100,000 80 100,000 ns
w(RL)P
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(CA)
t
su(SFC)
t
su(RA)
t
su(WMR)
t
su(DQR)
t
su(TRG)
t
su(SFR)
su(DCL)
t
t
su(DWL)
Setup time, read command, WE\ high before CASx\ low
Setup time, early-write command, WE\ low before CASx\ low
t
0
0
0
0
0
0
ns
ns
su(rd)
t
su(WCL)
Setup time, WE\ low before CASx\ high, write
Setup time, WE\ low before RAS\ high, write
Hold time, column address after CASx\ low
Hold time, DSF after CASx\ low
t
t
15
17
10
12
10
12
12
12
18
20
13
15
10
15
15
15
20
20
15
15
10
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
su(WCH)
su(WRH)
t
h(CLCA)
t
h(SFC)
Hold time, row address after RAS\ low
Hold time, TRG\ after RAS\ low
t
h(RA)
t
h(TRG)
Hold time, write mask after RAS\ low
Hold time, DQ after RAS\ low (write-mask operation)
t
h(RWM)
t
h(RDQ)
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TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1
-70
-75
-80
PARAMETER
Hold time, DSF after RAS\ low
SYMBOL MIN MAX
MIN MAX MIN MAX UNIT
t
10
30
12
30
12
0
10
33
15
35
15
0
10
35
15
35
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(SFR)
5
t
Hold time, column address valid after RAS\ low
Hold time, data valid after CASx\ low
h(RLCA)
t
t
h(CLD)
5
Hold time, data valid after RAS\ low
h(RLD)
Hold time, data valid after WE\ low
t
h(WLD)
h(CHrd)
h(RHrd)
6
t
t
Hold time, read, WE\ high after CASx\ high
6
0
0
0
Hold time, read, WE\ high after RAS\ high
Hold time, write, WE\ low after CASx\low
t
t
t
12
30
10
2
15
35
10
2
15
35
10
2
h(CLW)
5
Hold time, write, WE\ low after RAS\ low
h(RLW)
7
Hold time, TRG\ high after WE\ low
h(WLG)
Hold time, SQ valid after SC high
Hold time, DSF after RAS\ low
t
h(SHSQ)
t
30
0
35
0
35
0
h(RSF)
Hold time, output valid after CASx\ low
t
h(CLQ)
t
t
t
t
t
70
10
7
75
13
5
80
15
5
d(RLCH)
d(RLCH)
d(CHRL)
d(CLRH)
Delay time, RAS\ low to CASx\ high
ns
See Note 8
Delay time, CASx\ high to RAS\ low
Delay time, CASx\ low to RAS\ high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
40
15
35
35
90
55
5
20
48
20
38
38
100
63
5
20
50
20
40
40
105
65
5
9,10
Delay time, CASx\ low to WE\ low
d(CLWL)
11
t
50
50
60
Delay time, RAS\ low to CASx\ low
d(RLCL)
d(CARH)
d(CACH)
d(RLWL)
Delay time, column address valid to RAS\ high
t
t
t
t
Delay time, column address valid to CASx\ high
9
Delay time, RAS\ low to WE\ low
9
Delay time, column address valid to WE\ low
d(CAWL)
8
t
Delay time, CASx\ low to RAS\ low
d(CLRL)
d(RHCL)
d(CLGH)
8
t
0
0
0
Delay time, RAS\ high to CASx\ low
Delay time, CASx\ low to TRG\ high for DRAM read cycles
t
20
15
55
70
12
15
20
5
20
15
58
75
15
20
23
5
20
15
Delay time, TRG\ high before data applied at DQ
t
d(GHD)
12
t
Delay time, RAS\ low to TRG\ high
d(RLTH)
13
t
Delay time, RAS\ low to first SC high after TRG\ high
d(RLSH)
d(RLCA)
d(GLRH)
Delay time, RAS\ low to column address valid
Delay time, TRG\ low to RAS\ high
t
35
35
15
20
25
5
40
t
13
t
Delay time, CASx\ low to first SC high after TRG\ high
d(CLSH)
12, 13
t
Delay time, SC high to TRG\ high
d(SCTR)
d(THRH)
12
t
-10
50
15
-10
55
18
-10
60
20
Delay time, TRG\ high to RAS\ high
14
t
Delay time, TRG\ high to RAS\ low
d(THRL)
d(THSC)
12
t
Delay time, TRG\ high to SC high
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TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)1
-70
-75
-80
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNIT
Delay time, RAS\ high to last (most significant) rising edge of SC
before boundary switch during split-register-transfer read cycles
t
t
20
20
20
ns
d(RHMS)
Delay time, CASx\ low to TRG\ high in read-time-transfer read
cycles
Delay time, column address to first SC in early-load-transfer read
cycles
Delay time, column address to TRG\ high in real-time-transfer read
cycles
t
17
25
20
15
28
20
15
30
20
ns
ns
ns
d(CLTH)
d(CASH)
d(CAGH)
t
Delay time, data to CASx\ low
Delay time, data to TRG\ low
t
0
0
0
0
0
0
ns
ns
d(DCL)
t
d(DGL)
Delay time, last (most significant) rising edge of SC to RAS\ low
before boundary switch during split-register-transfer read cycles
Delay time, last (127 or 255) rising edge of SC to QSF switching at
t
20
20
20
ns
ns
d(MSRL)
t
25
30
28
33
30
35
15
d(SCQSF)
the boundary during split-register-transfer read cycles
15
t
ns
Delay time, CASx\ low to QSF switching in transfer-read cycles
d(CLQSF)
15
t
25
70
8
28
73
8
30
75
8
ns
ns
Delay time, TRG\ high to QSF switching in transfer-read cycles
d(GHQSF)
15
t
Delay time, RAS\ lwo to QSF switching in transfer-read cycles
d(RLQSF)
Refresh time interval, memory
Transition time
t
ms
ns
rf(MA)
t
3
25
3
25
3
25
t
NOTE:
1. Timing measurements are referenced to VIL MAX and VIH MIN.
2. Cycle time assumes tt = 3 ns.
3. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional CASx\
low time [tw(CL)].
4. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional RAS\
low time [tw(RL)].
5. The minimum value is measured when td(RLCL) is set to td(RLCL) MIN as a reference.
6. Either th(RHrd) or td(CHrd) must be satisfied for a read cycle.
7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
8. CBR refresh operation only.
9. Read-modify-write operation only.
10. TRG\ must disable the output buffers prior to applying data to the DQ pins.
11. The maximum value is specified only to assure RAS\ access time.
12. Real-time-load transfer read or late-load-transfer read cycle only.
13. Early-load-transfer read cycle only.
14. Full-register-(read) transfer cycles only.
15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
VOH / VOL = 2 V/0.8 V.
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SAM TO DRAM WRITE TRANSFER & SERIAL IN TIMINGS
PARAMETER
SYMBOL
-70
-75
-80
UNITS
Last SC to RAS\ set-up time (serial input)
t
25
25
25
ns
SRS
RAS\ to serial input delay time
Serial input set-up time
t
35
0
40
0
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDD
t
SDS
SDH
Serial input hold time
t
0
0
0
Serial input to SE\ delay time
Serial input to first SC delay time
Serial write enable to set-up time
Serial write enable to hold time
Serial write disable to set-up time
Serial write disable to hold time
t
t
0
0
0
SZE
0
0
0
SZS
t
0
0
0
SWS
SWH
t
10
0
12
0
12
0
t
t
SWiS
SWiH
10
12
12
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FIGURE 24: READ-CYCLE TIMING WITH CASx\-CONTROLLED OUTPUT
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FIGURE 25: READ-CYCLE TIMING WITH RAS\-CONTROLLED OUTPUT
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FIGURE 26: EARLY-WRITE-CYCLE TIMING
TABLE 7: EARLY-WRITE-CYCLE STATE TABLE
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
H
L
2
3
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
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FIGURE 27: LATE-WRITE-CYCLE TIMING (OUTPUT-ENABLE-CONTROLLED WRITE)
TABLE 8: LATE-WRITE-CYCLE STATE TABLE
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
H
L
2
3
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
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FIGURE 28: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD)
NOTES:
1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
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FIGURE 29: LOAD-WRITE-MASK-REGISTER-CYCLE TIMING (LATE-WRITE LOAD)
NOTES:
1. Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.
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FIGURE 30: READ-WRITE/READ-MODIFY-WRITE-CYCLE TIMING
TABLE 9: READ-WRITE/READ-MODIFY-WRITE-CYCLE STATE TABLE
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
H
L
2
3
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
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FIGURE 31: ENHANCED-PAGE-MODE READ-CYCLE TIMING
NOTES:
A. Access time is ta(CP) or ta(CA) dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write
mode (normal, block write, etc.).
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FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING
NOTES:
A. Referenced to the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG\ must remain high throughout the entire page-mode operation if the late write
feature is used. If the early write-cycle timing is used, the state of TRG\ is a don’t care after the minimum period th(TRG) from the falling
edge of RAS\..
TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
L
L
L
2
L
L
L
3
H
L
4
5
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
Load-write mask on either the first falling edge of CASx\
H
L
H
Don't Care Write Mask
1
or the falling edge of WE\, whichever occurs later.
NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a don’t care during this cycle.
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FIGURE 33: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
TABLE 11: ENHANCED-PAGE-MODE READ-MODIFY-WRITE-CYCLE STATE TABLE
STATE
CYCLE
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
1
L
L
L
2
L
L
L
3
H
L
4
5
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
Load-write mask on either the first falling edge of CASx\
H
L
H
Don't Care Write Mask
1
or the falling edge of WE\, whichever occurs later.
NOTES: 1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
a don’t care during this cycle.
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FIGURE 34: ENHANCED-PAGE-MODE READ-/WRITE-CYCLE TIMING
NOTES:
A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS\ and CASx\ to select the desired write
mode (normal, block write, etc.).
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FIGURE 35: LOAD-COLOR-REGISTER-CYCLE TIMING (EARLY-WRITE LOAD)
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FIGURE 36: LOAD-COLOR-REGISTER-CYCLE TIMING (LATE-WRITE LOAD)
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FIGURE 37: BLOCK-WRITE-CYCLE TIMING (EARLY WRITE)
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TABLE 12: BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
H
L
2
3
Block-write operation (nonmasked)
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
Write-mask data 0: I/O write disable
1: I/O write enable DQ
Column-mask data DQi – DQi + 7 0: column-write disable
(i = 0,8) 1: column-write enable
COLUMN MASK DATA
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN MASK DATA
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Low: Mask
High: No Mask
Lower Byte
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Low: Mask
High: No Mask
Upper Byte
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FIGURE 38: BLOCK-WRITE-CYCLE TIMING (LATE WRITE)
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TABLE 13: BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
H
L
2
3
Block-write operation (nonmasked)
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
Write-mask data 0: I/O write disable
1: I/O write enable DQ
Column-mask data DQi – DQi + 7 0: column-write disable
(i = 0,8) 1: column-write enable
COLUMN MASK DATA
DQ0-15
DQ0
COLUMN MASK DATA
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
Low: Mask
High: No Mask
Lower Byte
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Low: Mask
High: No Mask
Upper Byte
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FIGURE 39: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE TIMING
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TABLE 14: ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE
STATE
CYCLE
1
H
L
2
3
Block-write operation (nonmasked)
Block-write operation with nonpersistent write-per-bit
Block-write operation with persistent write-per-bit
Don't Care Valid Data
Write Mask Valid Data
Don't Care Valid Data
L
Write-mask data 0: I/O write disable
1: I/O write enable DQ
Column-mask data DQi – DQi + 7 0: column-write disable
(i = 0,8) 1: column-write enable
COLUMN MASK DATA
DQ0-15
DQ0
COLUMN MASK DATA
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
Column 0 (A0 = 0, A1 = 0, A2 = 0)
Column 1 (A0 = 1, A1 = 0, A2 = 0)
Column 2 (A0 = 0, A1 = 1, A2 = 0)
Column 3 (A0 = 1, A1 = 1, A2 = 0)
Column 4 (A0 = 0, A1 = 0, A2 = 1)
Column 5 (A0 = 1, A1 = 0, A2 = 1)
Column 6 (A0 = 0, A1 = 1, A2 = 1)
Column 7 (A0 = 1, A1 = 1, A2 = 1)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
Low: Mask
High: No Mask
Lower Byte
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Low: Mask
High: No Mask
Upper Byte
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FIGURE 40: RAS\-ONLY REFRESH-CYCLE TIMING
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FIGURE 41: CBR-REFRESH-CYCLE TIMING
TABLE 15: CBR-CYCLE STATE TABLE
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset
1
2
L
H
H
3
H
H
L
Don't Care
Don't Care
Stop Address
CBR refresh with stop-point set and no reset
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FIGURE 42: HIDDEN-REFRESH-CYCLE TIMING
TABLE 16: HIDDEN-REFRESH-CYCLE STATE TABLE
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset
1
2
L
H
H
3
H
H
L
Don't Care
Don't Care
Stop Address
CBR refresh with stop-point set and no reset
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FIGURE 43: FULL-REGISTER TRANSFER-READ TIMING, EARLY-LOAD OPERATIONS
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0 – A8.
D. Early-load operation is defined as th(TRG) MIN < th(TRG) < td(RLTH) MIN.
E. There must be no rising transitions.
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FIGURE 44: FULL-REGISTER TRANSFER READ-TIMING, REAL-TIME
LOAD OPERATION/LATE-LOAD OPERATION
NOTES:
A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
to from the 512 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be
shifted out of the registers. Also, the first bit to read from the data register after TRG\ has gone high must be activated by a positive
transition of SC.
C. A0–A8.
D. Late load operation is defined as td(THRH) < 0 ns.
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FIGURE 45: SPLIT-REGISTER-TRANSFER-READ TIMING
NOTES:
A. A0–A7: tap point of the given half; A8: identifies the DRAM row half
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FIGURE 46: SERIAL-READ-CYCLE TIMING (SE\ = VIL)
NOTES:
A. While the data is being read through the serial-data register, TRG\ is a don’t care; however, TRG\ must be held high when RAS\ goes low.
This is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the
read mode by performing a transfer-read cycle.
FIGURE 47: SERIAL-WRITE-CYCLE TIMING
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FIGURE 48: SERIAL-READ TIMING (SE\-CONTROLLED READ)
NOTES:
A. While the data is being read through the serial-data register, TRG\ is a don’t care; however, TRG\ must be held high when RAS\ goes low. This
is to avoid the initiation of a register-data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read
mode by performing a transfer-read cycle.
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FIGURE 49: SPLIT-REGISTER OPERATING SEQUENCE
NOTES:
A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is
necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle
(CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no
minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle.
B. A split-register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of
the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register-transfer cycle into the inactive half. After the
td(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. td(RHMS) is the
minimum delay time between the rising edge of RAS\ of the split-register-transfer cycle into the inactive half and the rising edge of the serial
clock of the last bit (bit 255 or 511).
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FIGURE 50: MASKED WRITE TRANSFER
NOTES:
1. SE\ = “L”
2. There must be no rising transitions.
3. QSF = “L” - Lower SAM (0-255) is active.
QSF = “H” - Upper SAM (256-511) is active.
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FIGURE 51: MASKED SPLIT WRITE TRANSFER
NOTES:
1. SE\ = “L”
2. QSF = “L” - Lower SAM (0-255) is active.
QSF = “H” - Upper SAM (256-511) is active.
3. Si is the SAM start address in before SWT.
4. STOP i and STOP j are programmable stop addresses.
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MECHANICAL DEFINITIONS*
Package Designator GB
SMD 5962-94549, Case Outline X
NOTES:
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. Index mark may appear on top or bottom depending on package vendor.
4. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38)
radius relative to the center of the ceramic.
5. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
6. The pins can be gold plated or solder dipped.
7. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively
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MECHANICAL DEFINITIONS*
Package Designator HKC
SMD 5962-94549, Case Outline Y
NOTES:
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. This package can be hermetically sealed with a metal lid.
4. The terminals are gold plated.
5. All leads not shown for clarity purposes.
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ORDERING INFORMATION
EXAMPLE: SM55161AGB-75
Part
Prefix*
Package
Speed
Number
55161A
55161A
55161A
55161A
55161A
55161A
SM
SMJ
SM
SMJ
SM
GB
GB
GB
GB
GB
GB
-70
-70
-75
-75
-80
-80
SMJ
EXAMPLE: SMJ55161AHKC-80
Part
Prefix*
Package
Speed
Number
55161A
55161A
55161A
55161A
55161A
55161A
SM
SMJ
SM
SMJ
SM
HKC
HKC
HKC
HKC
HKC
HKC
-70
-70
-75
-75
-80
-80
SMJ
*AVAILABLE PROCESSES
SM = IndustrialTemperature Range
SMJ = Full Military Processing
-40oC to +85oC
-55oC to +125oC
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ASI TO DSCC PART NUMBER
CROSS REFERENCE
Package Designator GB
Package Designator HKC
ASI Part #
SMD Part #
ASI Part #
SMD Part #
TO BE COMPLETED WHEN SMD LISTING IS RELEASED
TO BE COMPLETED WHEN SMD LISTING IS RELEASED
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