SP5658SKGMP2T [MITEL]
2.7GHz 3-Wire Bus Controlled Frequency Synthesiser; 2.7GHz的3线总线控制频率合成器
| 型号： | SP5658SKGMP2T |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 2.7GHz 3-Wire Bus Controlled Frequency Synthesiser |
| 文件： | 总14页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5658
2.7GHz 3-Wire Bus Controlled Frequency Synthesiser
Advance Information
Supersedes October 1996 Media IC Handbook HB3923-2
DS4064 - 4.1 March 1998
The SP5658 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz.
The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.
Comparison frequencies are obtained either from a crystal
controlled on–chip oscillator or from an external source.
The device contains two switching ports, in the 14 pin
version and four in the 16 pin, together with an ‘‘in–lock” flag
output. The device also contains a varactor line disable and
charge pump disable facility.
CHARGE PUMP
CRYSTAL
DISABLE
ENABLE
1
14
DRIVE
V
EE
RF INPUT
RF INPUT
V
DATA
CC
CLOCK
LOCK
PORT P1/OC
PORT P0/OP
MP14
FEATURES
CHARGE PUMP
CRYSTAL
DISABLE
ENABLE
DATA
1
16
DRIVE
■ Complete 2.7GHz single chip system
■ Optimised for low phase noise
■ Selectable divide by two prescaler
■ Selectable reference division ratio
■ Charge pump disable
V
EE
RF INPUT
RF INPUT
V
CC
■ Varactor line disable
■ ‘In–lock’ flag
■ Two switching ports in 14 pin version
■ Four switching ports in 16 pin version
■ Pin compatible with SP5659 I 2 C bus low
phase noise synthesiserPP
CLOCK
LOCK
PORT P3
PORT P2
PORT P0/OP
PORT P1/OC
MP16
■ ESD protection (Normal ESD handling procedures
should be observed)
Fig. 1 Pin connections – top view
APPLICATIONS
■ SAT, TV, VCR and Cable tuning systems
■ Communications systems
ORDERING INFORMATION
SP5658F/KG/MP1S (Tubes, 14 lead SO)
SP5658S/KG/MP2S (Tubes, 16 lead SO)
SP5658F/KG/MP1T (Tape and Mounted)
SP5658S/KG/MP2T (Tape and Mounted)
SP5658
PHASE
COMP
PROGRAMMABLE
DIVIDER
F
F
REFERENCE
DIVIDER
See Table 1
CRYSTAL
2
pd
comp
OSC
13
14
13 BIT
COUNT
RF
INPUTS
:
-16/17
:- 2/1
CHARGE
PUMP
1
4 BIT
COUNT
DE
16
CHARGE
PUMP
DRIVE
CO
1 BIT OS
LATCH
3 BIT LATCH
(R0,R1,R2)
1 BIT
LATCH
18 BIT LATCH
DISABLE
15
12
VEE
3
4
5
6
DISABLE
4 BIT
1 BIT
LATCH
T0
LATCH AND
PORT
ENABLE
DATA
FLOCK
DATA
INTERFACE
VCC
INTERFACE
CLOCK
7
8
9
10
11
P3
P2 P1/0C P0/OP
LOCK
Fig. 2 SP5658S block diagram
2
SP5658
ELECTRICAL CHARACTERISTICS
T amb = –20°C to + 80°C, VCC = + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
eitherproductiontestordesign. Theyapplywithinthespecifiedambienttemperatureandsupplyvoltagerangesunlessotherwise
stated.
Value
Characteristics
Pin
Units
Conditions
(SP5658S)
Min
Typ
Max
Supply current, ICC
12
59
52
74
65
mA
mA
VCC =5V Prescaler enabled, DE=1
VCC =5V Prescaler disabled, DE=0
RF input voltage
13, 14
13,14
13, 14
13,14
40
100
40
300
300
300
300
mVrms
mVrms
mVrms
mVrms
300MHz to 2.7GHz Prescaler
enabled, DE=1, See Fig. 5b
80MHz Prescaler enabled,
DE=1, See Fig. 5b.
100MHz to 2.0GHz Prescaler
disabled, DE=0, See Fig. 5a
50
80MHz Prescaler disabled,
DE=0, See Fig. 5a.
RF input impedance
RF input capacitance
Data, Clock, Enable & Disable
Input high voltage
Input low voltage
13, 14
13, 14
3,4,5,6
50
Ω
Refer to Fig. 4
Refer to Fig. 4
2
pF
3
0
VCC
0.7
10
V
V
Input high current
Input low current
µA
µA
kHz
V
Input voltage = VCC
Input voltage = VEE
–10
500
Clock Rate
6
Clock data & enable input
hysteresis
4,5,6
0.4
3
SP5658
ELECTRICAL CHARACTERISTICS
T amb = –20°C to + 80°C, VCC = + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed
by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristics
Pin
(SP5658S)
Value
Typ
Units
Conditions
Min
Max
Bus Timing
4,5,6
Data set up, tSU
Data hold, tHD
300
600
300
600
300
ns
ns
ns
ns
ns
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
See Fig. 3
Enable set up, tES
Enable hold, tEH
Clock to enable, tCE
Charge pump output current
Charge pump output leakage
1
1
See Table 3, V PIN1 = 2V
V PIN1 = 2V
± 3
± 10
nA
Charge pump drive output
current
16
1
mA
V PIN16 = 0.7V
Oscillator temperature stability
2
2
2
2
ppm/°C
Oscillator supply voltage
stability
ppm/V
External reference input
frequency
2
2
2
200
4
20
500
12
MHz
AC coupled sinewave
AC coupled sinewave
External reference input
amplitude
mVPP
Crystal frequency
2
2
MHz
mVPP
Ω
Crystal oscillator drive level
45
Recommended crystal series
resistance
100
400
200
Applies to 4MHz crystal only.
‘‘Parallel resonant” crystal. Figure
quoted is under all conditions
including start up.
Crystal oscillator negative
resistance
2
Ω
Includes temperature and process
tolerances.
Comparison frequency
2
MHz
Phase noise at phase detector
–142
dBC/
Hz
6kHz loop BW, phase comparator
freq 250kHz. Figure measured @
1kHz offset, DSB (within loop band
width).
RF division ratio
240
480
131071
262142
Prescaler disabled, DE=0
Prescaler enabled, DE=1
See Table 1
Reference division ratio
Output ports P0–P3 #
Sink current
7,8,9,10
10
1
mA
V PORT =0.7V
Leakage current
10
10
µA
V PORT =13.2V
Lock output
11
Sink current
mA
V LOCK =0.7V, ‘out of lock’
‘in lock’
Leakage current
µA
4
# Ports P2 and P3 are not available on the SP5658F.
SP5658
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V EE at 0V
Characteristics
Pin
Min
Max
Units
Conditions
(SP5658S)
Supply voltage, VCC
RF input voltage
RF input DC offset
Port voltage
12
13, 14
13, 14
7 – 10
7 – 10
7 – 10
11
1
16
2
3 – 6
–0.3
7
2.5
VCC +0.3
14
V
Vp–p
V
V
V
mA
V
V
V
V
AC coupled as per application
–0.3
–0.3
–0.3
Port in off state
Port in on state
6
50
Total port current
Lock output DC offset
Charge pump DC offset
Drive DC offset
Crystal DC offset
Data, Clock, Enable & Disable DC
offset
–0.3
–0.3
–0.3
–0.3
–0.3
VCC +0.3
VCC +0.3
VCC +0.3
VCC +0.3
VCC +0.3
V
Storage temperature
Junction temperature
MP14 Thermal Resistance
Chip to ambient 123 °C/W
Chip to case 45 °C/W
MP16 Thermal Resistance
Chip to ambient
Chip to case
Power consumption at VCC =5.5V
ESD protection
–55
+125
150
°C
°C
111
41
407
°C/W
°C/W
mW
kV
All ports off, prescaler enabled
MIL–STD 883 TM 3015
ALL
2
FUNCTIONAL DESCRIPTION
The output of the preamplifier is fed to the 2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
Acounter4.IfbitDEissettoa0theprescalerisdisabled;Note
that the control function DE cannot be used dynamically.
Theoutputoftheprogrammabledividerisfedtothephase
comparatorwhereitiscomparedinbothphaseandfrequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.
TheSP5658containsalltheelementsnecessary,withthe
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high
comparison frequency and is fabricated in high speed logic,
which enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable
divide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.
The SP5658 is controlled by a standard 3–wire bus
The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
currentpulsesintothevaractorlinevoltage. Thechargepump
can be disabled to a high impedance state by the DISABLE
input.ThevaractordriveoutputcanalsobedisabledbytheOS
bit within the data word, so switching the external transistor
‘OFF’ and allowing an external voltage to be written to the
varactor line for tuner alignment purposes.
The phase comparator also drives the lock detect circuit
which generates a lock flag. ‘In–lock’ is indicated by a high
impedance state on the lock output.
The programmable divider output divided by 2, F pd /2 and
the comparison frequency, F comp can be switched to ports P0
and P1 respectively by switching the device into test mode.
The test modes are described in Table 2.
comprising data, clock and enable inputs. The programming
word for the 16 pin variant contains 28 bits, four of which are
used for port selection, 18 to set the programmable divider
ratio and enable/disable the prescaler, bit DE, three bits to
select the reference division ratio, bits R0–R2, one bit to set
charge pump current, bit C0, and the remaining two bits to
access test modes, bit T0, and to disable the varactor drive,
bit OS. The data word for 14 pin variant is identical to 16 pin
except 26 bits only are required, two of which are used for port
selection. The programming format is shown in Fig. 3.
The clock input is disabled by an enable low signal, data
is therefore only clocked into the internal shift registers during
an enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
5
SP5658
CLOCK
ENABLE
0
MSB 227 226 225 224 223 222 221 220 219 218 217 216
P3 P2 P1 P0 TO OS CO R2 R1 R0 DE
2
LSB
LSB
DATA
16 PIN VARIANT
FREQUENCY DATA
MSB IS TRANSMITTED
FIRST
0
MSB 225 224 223 222 221 220 219 218 217 216
P1 P0 TO OS CO R2 R1 R0 DE
2
DATA
14 PIN VARIANT
FREQUENCY DATA
tEH
tCE tES
3V
0.7V
CLOCK
t
ES =Enable set up time
SU =Data set up time
HD =Data hold time
CE =Clock–to–enable time
EH =Enable hold time
t
t
t
t
3V
0.7V
ENABLE
DATA
3V
0.7V
tSU
tHD
216
DE
20
to
: Programmable divider ratio control bits
:- 2 Prescaler (Enable = 1, Disable = 0)
:
R2, R1 ,R0
P3, P2, P1, P0
: Reference divider ratio control bits (see Table1)
: Port control bits
CO
OS
T0
: Charge Pump current select (see Table 3)
: Drive output disable switch
: Test mode enable (see Table 2)
Fig. 3 Data format and timing
R2
R1
R0
RATIO
Comparison Frequency with a 4MHz
external reference.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
2MHz
1MHz
500kHz
250kHz
125kHz
62.5kHz
31.25kHz
15.625kHz
Table 1 Reference division ratios
6
SP5658
TO
OS
DIS
P0/OP
P1/0C
FUNCTIONAL DESCRIPTION
0
0
1
0
0
0
0
0
1
1
0
1
0
0
1
#
#
#
#
NORMAL OPERATION
CHARGE PUMP DISABLE
NORMAL OPERATION
VARACTOR LINE DISABLE
CHARGE PUMP AND
F pd/2
#
#
F comp
#
#
VARACTOR LINE DISABLE
NOT PERMITTED
1
X
1
–
–
# CONTROLLED BY BITS P0 AND P1 WITHIN DATA WORD
Table 2 Test modes
C0
CURRENT IN mA
MIN
0.23
0.68
TYP
0.3
0.9
MAX
0.37
1.12
0
1
Table 3 Charge pump current
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
1
2
5
X
X
–j5
–j0.2
X
S :Z = 50
11 0
–j2
–j0.5
X
NORMALISED TO 50
FREQUENCY MARKERS AT 100MHz,
500MHz, 1GHz AND 2.7GHz
–j1
Fig. 4 Typical input impedance
300
300
VIN
(mV RMS
INTO 50
VIN
(mV RMS
)
INTO 50
)
OPERATING
WINDOW
OPERATING
WINDOW
100
40
100
50
40
10
10
3000 3500
100
1000
2000
300
80
1000
2000
3000 3500
2700
80
FREQUENCY (MHz)
FREQUENCY (MHz)
Fig. 5a Typical input sensitivity (Prescaler disabled, DE=0)
Fig. 5b Typical input sensitivity (Prescaler enabled, DE=1)
7
SP5658
DOUBLE CONVERSION TUNER SYSTEMS
The high 2.7GHz maximum operating frequency and
excellent noise characteristics of the SP5658 enables the
construction of double conversion high IF tuners.
A typical system shown in Fig.7 will use the SP5658 as the
first LO control for full band upconversion to an IF of greater
than 1GHz. The wide range of reference division ratios allows
theSP5658tobeusedbothfortheupconverterLOwithahigh
phasecomparatorfrequency(hencelowphasenoise)andthe
down converter which utilises the device in a lower
comparison frequency mode (which offers a fine step size).
1.6GHz
50–900MHz
38.9MHz
1650–2700MHz
First LO
Second LO
SP5658
SP5658
Fig. 6 Example of double conversion from VHF/UHF frequencies to TV IF
+5V
+30V
+12V
68pF
4MHz 18pF
22k
15nF
16k
47k
2n2
13k3
2N3904
Optional application utilising
on–board crystal controlled
oscillator
1
2
3
4
5
6
7
14
13
12
11
10
9
10n
REF
DIS
TUNER
1n
1n
ENABLE
DATA
OSCILLATOR
OUTPUT
CONTROL
MICRO
CLOCK
10n
P1
8
P0
LOCK
Fig. 7 Typical application, SP5658F
APPLICATION NOTES
A generic set of application notes AN168 for designing
with synthesisers such as the SP5658 has been written. This
coversaspectssuchasloopfilterdesignanddecoupling.This
application note is also featured in the Media IC Handbook.
The board can be used for the following purposes:
(A) measuring RF sensitivity performance.
(B) Indicating port function.
(C) Synthesising a voltage controlled oscillator.
(D) Testing of external reference sources.
A generic test/demo board has been produced which can
be used for the SP5658. A circuit diagram and layout for the
board is shown in Figs. 8 and 9.
8
SP5658
P2
C8
+30V
+5V
+12V
C9
EXTERNAL REFERENCE
SKT2
C7/C8/C9 = 100nF
C3
68pF
C7
R9
R7
C6
10nF*
22K
*(NOT FITTED)
R8
C2
R6 13K3
VAR
GND
15nF
16K
47K
C12
2n2F
1
2
14
X1 4MHz C1
18pF
T1
2N3904
13
12
P1
DISABLE / REF
ENABLE
3
4
5
RF INPUT
SKT1
C4
C5
1nF
11
10
1nF
DATA / SDA
C10
1nF
6
7
9
8
CLOCK / SCL
C13
100pF
C14
100pF
NC NC
D1 D2 D3 D4 D5
PIN NO : 7 LOCK
8
C11
1nF
Fig. 8 Test board
Fig. 9 Test board (layout)
9
SP5658
LOOP BANDWIDTH
REFERENCE SOURCE
The majority of applications for which the SP5658 is
intended require a loop filter bandwidth of between 2kHz and
10kHz.
The SP5658 offers optimal LO phase noise performance
whenoperatedwithalargestepsize.Thisisduetothefactthat
the LO phase noise within the loop bandwidth is:
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange the
loop filter bandwidth such that the 1kHz figure lies within the
loop bandwidth. Thus the phase noise depends on the
synthesiser comparator noise floor, rather than the VCO.
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
phase comparator
noise floor
+ 20 log 10
LO frequency
phase comparator frequency
(
)
Assuming the phase comparator noise floor is flat irrespective
of sampling frequency, this means that the best performance
will be achieved when the overall LO to phase comparator
division ratio is a minimum.
There are two ways of achieving a higher phase
comparator sampling frequency:–
A) Reduce the division ratio between the reference source
and the phase comparator
B) use a higher reference source frequency.
Approach B) may be preferred for best performance since it is
possible that the noise floor of the reference oscillator may
degrade the phase comparator performance if the reference
division ratio is very small.
10
SP5658
V
REF
V
CC
500
500
CHARGE
PUMP
RF INPUTS
200
DRIVE
OUTPUT
OS
(Output disable)
RF inputs
Loop amplifier
V
CC
PORT/LOCK
25K
BIAS
Output Ports and Lock Output
Disable, Enable, Data and Clock inputs
V
CC
CRYSTAL
Reference oscillator
11
Fig. 10 Input/Output interface circuits
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