M30623MWP-XXXGP [MITSUBISHI]
Microcontroller, 16-Bit, MROM, M16C CPU, 24MHz, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128;
| 型号： | M30623MWP-XXXGP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 16-Bit, MROM, M16C CPU, 24MHz, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128 时钟 微控制器 外围集成电路 |
| 文件： | 总348页 (文件大小：4168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview
The M16C/62P group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin and 128-pin plastic
molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high
level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at
high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast
instruction processing capability, makes it suitable for control of various OA, communication, and industrial
equipment which requires high-speed arithmetic/logic operations.
Applications
Audio, cameras, office/communications/portable/industrial equipment, etc
------Table of Contents------
Overview ......................................................... 1
Central Processing Unit (CPU) ..................... 12
Special Function Registers (SFR)................. 14
Reset............................................................. 20
Processor Mode ............................................ 29
Clock Generation Circuit ............................... 51
Protection ...................................................... 74
Interrupts ....................................................... 75
Watchdog Timer............................................ 95
DMAC ........................................................... 97
Timers ......................................................... 107
Timer A .................................................... 109
Timer B .................................................... 123
Three-phase Motor Control Timer Function 129
Serial I/O ..................................................... 139
Clock Synchronous serial I/O Mode ........ 148
UART Mode............................................. 155
Special Mode 1 (I2C mode) ..................... 162
Special Mode 2........................................ 172
Special Mode 3 (IE mode) ....................... 177
Special Mode 4 (SIM mode) (UART2)..... 179
SI/O3 and SI/O4.......................................... 184
A-D Converter ............................................. 189
D-A Converter ............................................. 206
CRC Calculation ......................................... 208
Programmable I/O Ports ............................. 210
Electrical Characteristics............................. 223
Flash Memory ............................................. 261
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
1
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 lists performance outline of M16C/62P group.
Table 1.1.1. Performance outline of M16C/62P group
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
41.7 ns (f(BCLK)= 24MHZ, VCC1= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V)
(See the product list)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
100-pin version
P0 to P10 (except P85)
128-pin version
P0 to P14 (except P85)
P85
8 bits x 10, 7 bits x 1
P0 to P5: VCC2 ports
P6 to P10: VCC1 ports
8 bits x 13, 7 bits x 1,
P0 to P5, P12, P13: VCC2 ports
P6 to P10, P11, P14: VCC1 ports
2 bits x 1
_______
Input port
1 bit x 1 (NMI pin level judgment): VCC1 ports
Multifunction timer
Output
Input
16 bits x 5 channels (TA0, TA1, TA2, TA3, TA40)
16 bits x 6 channels (TB0, TB1, TB2, TB3, TB4, TB5)
3 channels (UART0, UART1, UART2)
UART, clock synchronous, I C bus (option ), or IE bus (option )
2 channels (SI/O3, SI/O4)
Clock synchronous
Serial I/O
2
1
3
2
3
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
10 bits x (8 x 3 + 2) channels
8 bits x 2
2 channels (trigger: 25 sources)
CRC-CCITT
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Interrupt
Clock generation circuit
• Main clock
• Sub-clock
(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
•
Ring oscillator (for main-clock oscillation stop detect function)
• PLL frequency synthesizer
3
Voltage detection circuit
Power supply voltage
Present (option )
VCC1=3.0V to 5.5V, VCC2=3.0V to VCC1(f(BCLK)=24MHZ)
VCC1=VCC2=2.7V to 5.5V (f(BCLK)=10MHZ)
3.3V ± 0.3V or 5.0V ± 0.5V
Flash memory Program/erase voltage
Number of program/erase
100 times
Power consumption
14mA (VCC1=VCC2=5V, f(BCLK)=24MHZ)
8mA (VCC1=VCC2=3V, f(BCLK)=10MHZ)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHZ, when wait mode)
I/O
I/O withstand voltage
5.0V
characteristics Output current
Memory expansion
Operating ambient temperature
5mA
Available (to 4M bytes)
-20 to 85°C
-40 to 85°C (option )
3
Device configuration
Package
CMOS high performance silicon gate
100-pin and 128-pin plastic mold QFP
Notes:
2
1. I C Bus is a registered trademark of PHILIPS.
2. IE Bus is a registered trademark of NEC.
3. If you desire this option, please so specify.
2
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.1.1 is a block diagram of the M16C/62P group.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC1 ports>
<VCC2 ports>
Internal peripheral functions
Timer (16-bit)
System clock generator
IN-XOUT
CIN-XCOUT
A-D converter
(10 bits
X 8 channels
X
X
Expandable up to 26 channels)
Output (timer A): 5
Input (timer B): 6
PLL frequency synthesizer
Ring oscillator
UART or
clock synchronous serial I/O
Three-phase motor
control circuit
Clock synchronous serial I/O
(8 bits
X 3 channels)
(8 bits
X
2 channels)
CRC arithmetic circuit (CCITT )
16
12
5
(Polynomial : X +X +X +1)
Memory
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
SB
ROM
(Note 1)
USP
R2
R3
DMAC
(2 channels)
ISP
RAM
(Note 2)
INTB
PC
FLG
A0
A1
FB
D-A converter
(8 bits X 2 channels)
Multiplier
<VCC1 ports>
<VCC2 ports>
Port P12 Port P13
Port P11
Port P14
(Note 3)
(Note 3)
(Note 3)
(Note 3)
Note 1: ROM size depends on microcomputer type.
Note 2: RAM size depends on microcomputer type.
Note 3: Ports P11 to P14 exist only in 128-pin version.
8
2
8
8
Figure 1.1.1. Block Diagram
3
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Product List
Tables 1.1.2 and 1.1.3 list the M16C/62P group products and Figure 1.1.2 shows the type numbers,
memory sizes and packages.
Table 1.1.2. Product List (1)
As of January 2003
RAM capacity
4K bytes
Package type
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
Type No.
ROM capacity
48K bytes
Remarks
M30622M6P-XXXFP
M30622M6P-XXXGP
**
**
**
**
**
**
**
**
**
M30622M8P-XXXFP
M30622M8P-XXXGP
64K bytes
96K bytes
128K bytes
4K bytes
5K bytes
10K bytes
M30622MAP-XXXFP
M30622MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP
M30623MEP-XXXGP
192K bytes
12K bytes
12K bytes
**
**
**
**
**
**
**
M30622MGP-XXXFP
M30622MGP-XXXGP
100P6Q-A
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
128P6Q-A
100P6S-A
256K bytes
100P6Q-A
128P6Q-A
100P6S-A
20K bytes
16K bytes
MASK ROM version
M30622MWP-XXXFP **
**
M30622MWP-XXXGP
100P6Q-A
**
M30623MWP-XXXGP
128P6Q-A
100P6S-A
**
M30624MWP-XXXFP
**
M30624MWP-XXXGP **
100P6Q-A
24K bytes
31K bytes
320K bytes
M30625MWP-XXXGP **
128P6Q-A
100P6S-A
M30626MWP-XXXFP
M30626MWP-XXXGP **
100P6Q-A
**
M30627MWP-XXXGP **
128P6Q-A
100P6S-A
M30622MHP-XXXFP
M30622MHP-XXXGP
**
100P6Q-A
128P6Q-A
100P6S-A
16K bytes
24K bytes
**
M30623MHP-XXXGP
**
M30624MHP-XXXFP
**
M30624MHP-XXXGP
384K bytes
100P6Q-A
128P6Q-A
100P6S-A
**
M30625MHP-XXXGP
**
M30626MHP-XXXFP
**
M30626MHP-XXXGP
31K bytes
100P6Q-A
128P6Q-A
**
M30627MHP-XXXGP
**
: Under planning
** : Under development
*
4
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.1.3. Product List (2)
As of January 2003
RAM capacity
4K bytes
Package type
Type No.
M30622F8PFP
ROM capacity
64K bytes
Remarks
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
**
**
**
**
**
**
**
**
**
**
*
M30622F8PGP
M30620FCPFP
M30620FCPGP
M30624FGPFP
M30624FGPGP
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
M30626FJPFP
M30626FJPGP
M30627FJPGP
10K bytes
20K bytes
128K bytes
256K bytes
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
128P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
Flash memory version
384K bytes
512K bytes
31K bytes
31K bytes
*
*
M30620SPFP
M30620SPGP
M30622SPFP
M30622SPGP
10K bytes
4K bytes
**
**
**
**
External ROM version
: Under planning
** : Under development
*
Type No.
M 3 0 6 2 6 M H P– X X X F P
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 128P6Q-A
ROM No.
Omitted for flash memory version and
external ROM version
ROM capacity:
6: 48K bytes
8: 64K bytes
A: 96K bytes
C: 128K bytes
E: 192K bytes
G: 256K bytes
W: 320K bytes
H: 384K bytes
J: 512K bytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: External ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/62 Group
M16C Family
Figure 1.1.2. Type No., Memory Size, and Package
5
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figures 1.1.3 to 1.1.5 show the pin configurations (top view).
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
4
/CS0
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
/BCLK
/HLDA
/HOLD
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P0
P0
P0
P0
P0
P0
7
6
5
4
3
2
/AN07/D
/AN06/D
/AN05/D
/AN04/D
/AN03/D
/AN02/D
7
6
5
4
3
2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P45
P46
P47
P50
P51
P52
P0
1
/AN01/D
/AN00/D
7
6
5
1
P00
0
P5
P5
P5
P5
P5
3
P10
P10
P10
/AN
/AN
/AN
7
6
5
/KI
/KI
/KI
3
2
1
0
3
2
1
4
M16C/62P Group
5
6
/ALE
/RDY/CLKOUT
P10
4
/AN4/KI
7
P10
P10
P10
3/AN
2/AN
1
/AN
P60
/CTS
/CLK
/RxD
/T
/CTS
/CLK
/RxD
/T
0
/RTS
0
P6
1
0
P6
P6
P6
2
0/SCL
0
0
3
4
X
D0
/SDA
1
AVSS
P10
0/AN
0
/RTS
1
/CTS
0
/CLKS
1
P6
5
1
VREF
P66
1
/SCL
/SDA
1
AVCC
/ADTRG/SIN
P6
7
X
D1
1
P9
7
4
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Package: 100P6S-A
Note: P70 and P71 are N channel open-drain output pins.
Figure 1.1.3. Pin Configuration (Top View)
6
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P12/D10
P4
P4
P4
2
/A18
/A19
/CS0
P1
1
/D
/D
9
3
P10
8
4
P0
P0
P0
P0
7
6
5
4
/AN07/D
/AN06/D
/AN05/D
/AN04/D
7
6
5
4
P4
P4
P4
5/CS1
6
/CS2
/CS3
7
P5
P5
P5
P5
0
/WRL/WR
/WRH/BHE
/RD
P0
3
/AN03/D
/AN02/D
3
2
1
2
3
P02
P01
/AN01/D
/AN00/D
1
0
/BCLK
P00
P5
P5
P5
P5
P6
P6
4/HLDA
5
P10
P10
P10
7
6
5
/AN
/AN
/AN
7/KI
6/KI
5/KI
3
2
1
/HOLD
/ALE
/RDY/CLKOUT
M16C/62P Group
6
7
0
1
P10
4
/AN4/KI
0
/CTS
/CLK
/RxD
/T
/CTS
0/RTS0
0
P103/AN
3
P10
2
/AN
2
1
P6
P6
2
0
/SCL
0
3
X
D
0/SDA0
P10
1
/AN
AVSS
P6
P6
P6
P6
4
5
6
7
1/RTS1/CTS0/CLKS1
1
31
30
/CLK
/RxD
P100/AN
0
1
/SCL
1
VREF
29
28
/T
XD
1
/SDA
1
AVcc
/ADTRG/SIN
/ANEX1/SOUT
/ANEX0/CLK4
P7
0
/T
1
X
D
2
/SDA
2
/TA0OUT(Note)
/TA0IN/TB5IN(Note)
/TA1OUT/V
P9
P9
P9
7
4
4
27
26
P7
/RxD
2/SCL2
6
5
P7
2
/CLK
2
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package: 100P6Q-A
Note: P70 and P71 are N channel open-drain output pins.
Figure 1.1.4. Pin Configuration (Top View)
7
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Overview
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (top view)
102 101
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P1
0
/D
8
7
6
5
4
3
2
1
0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P12
P12
P12
5
6
7
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P0
P0
P0
P0
P0
P0
7
6
5
4
3
2
/AN07/D
/AN06/D
/AN05/D
/AN04/D
/AN03/D
/AN02/D
/AN01/D
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P0
1
P130
P131
P132
P133
P0
0
/AN00/D
P11
P11
P11
P11
7
6
5
P5
4
/HLDA
/HOLD
P5
5
4
M16C/62P Group
P5
P5
6
/ALE
P11
P11
P11
P11
3
2
1
0
7
/RDY/CLKOUT
P13
P13
P13
P13
4
5
6
7
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
6
5
/KI
/KI
/KI
3
2
1
0
3
2
1
P6
0
/CTS
0
0
/RTS
0
P6
1
/CLK
P104/AN4/KI
P6
P6
P6
P6
2
/RxD
0/SCL0
P103
P102
P101
/AN
/AN
/AN
3
/T
/CTS
/CLK
X
D
0/SDA
0
4
1
/RTS1/CTS0/CLKS1
5
1
AVSS
/AN
VSS
P100
0
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Package: 128P6Q-A
Note: P70 and P71 are N channel open-drain output pins.
Figure 1.1.5. Pin Configuration (Top View)
8
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview
Table 1.1.4 Pin Description (100-pin and 128-pin Packages) (Continued)
Pin name Signal name
I/O type
Function
Power supply
V
V
CC1, VCC2, Power supply
Apply 2.7V to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
SS
input
pin. The Vcc apply condition is that VCC2 ≤ VCC1
(Note)
This pin switches between processor modes. Connect this pin to
V
CC1
CNVSS
CNVSS
Input
V
SS pin when after a reset you want to start operation in single-
chip mode (memory expansion mode) or the VCC1 pin when
starting operation in microprocessor mode.
Reset input
Clock input
Input
Input
V
CC1
CC1
“L” on this input resets the microcomputer.
RESET
These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the XIN
and the XOUT pins. To use an externally derived clock, input it to
the XIN pin and leave the XOUT pin open.
XIN
V
XOUT
Clock output Output
BYTE
Input
External data
bus width
select input
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. Connect
this pin to the VSS pin when operating in single-chip mode.
AVCC
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect
this pin to VCC1
This pin is a power supply input for the A-D converter. Connect
this pin to VSS
.
Analog power
supply input
.
VREF
Input
This pin is a reference voltage input for the A-D converter.
Reference
voltage input
P0
0
to P0
7
I/O port P0
Input/output VCC2
This is an 8-bit CMOS I/O port. This port has an input/output select
direction register, allowing each pin in that port to be directed for
input or output individually.
If any port is set for input, selection can be made for it in a program
whether or not to have a pull-up resistor in 4 bit units. This selection
is unavailable in memory extension and microprocessor modes.
This port can function as input pins for the A-D converter when so
selected in a program.
When set as a separate bus, these pins input and output data (D
–D ).
0
D
0
to D
7
Input/output
7
This is an 8-bit I/O port equivalent to P0. P1
as INT interrupt input pins as selected by a program.
When set as a separate bus, these pins input and output data (D8
5
to P1
7
also function
P1
0
to P1
7
7
I/O port P1
I/O port P2
Input/output VCC2
Input/output
D
8
to D15
to P2
–D15).
This is an 8-bit I/O port equivalent to P0. This port can function as
input pins for the A-D converter when so selected in a program.
P2
0
Input/output VCC2
A
0
to A
7
Output
These pins output 8 low-order address bits (A
If the external bus is set as an 8-bit wide multiplexed bus, these
pins input and output data (D to D ) and output 8 low-order
address bits (A to A ) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these
pins input and output data (D to D ) and output address (A to A
).
0 to A7).
A
A
0
/D
/D
0
7
to
Input/output
7
0
7
0
7
A
A
A
0
1
7
Output
Input/output
/D
/D
0
6
to
0
6
1
7)
separated in time by multiplexing. They also output address (A
This is an 8-bit I/O port equivalent to P0.
0
P3
0
to P3
to A15
/D
to A15
7
7
I/O port P3
I/O port P4
Input/output VCC2
Output
A
8
These pins output 8 middle-order address bits (A
If the external bus is set as a 16-bit wide multiplexed bus, these
pins input and output data (D ) and output address (A
8 to A15).
Input/output
Output
A
A
8
9
7,
7
8)
separated in time by multiplexing. They also output address (A
to A15).
9
P4
16 to A19
CS to CS
0
to P4
Input/output VCC2
Output
This is an 8-bit I/O port equivalent to P0.
A
,
3
These pins output A16 to A19 and CS
0
to CS
3 signals. A16 to A19
0
are 4 high- order address bits. CS
0
to CS are chip select signals
3
Output
used to specify an access space.
Note: In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
9
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview
Table 1.1.5 Pin Description (100-pin and 128-pin Packages) (Continued)
Power supply
Pin name Signal name
I/O type
Function
P5
0
to P5
7
I/O port P5
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5
in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program.
7
V
CC2
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output
Output
Output
Output
Output
Input
Output WRL/WR, WRH/BHE, RD, BCLK, HLDA, and ALE signals.
WRL/WR and WRH/BHE are switchable in a program. Note that
WRL and WRH are always used as a pair, so as WR and BHE.
WRL, WRH, and RD selected
If the external data bus is 16 bits wide, data are written to even
addresses when the WRL signal is low, and written to odd
addresses when the WRH signal is low. Data are read out when the
RD signal is low.
Output
Input
WR, BHE, and RD selected
Data are written when the WR signal is low, or read out when the
RD signal is low. Odd addresses are accessed when the BHE
signal is low. Use this mode when the external data bus is 8 bits
wide.
The microcomputer goes to a hold state when input to the HOLD
pin is held low. While in the hold state, HLDA outputs a low
level. ALE is used to latch the address. While the input level of the
RDY pin is low, the bus of the microcomputer goes to a wait state.
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as UART0 and UART1 I/O pins as selected by program.
P6
P7
0
to P6
to P7
7
I/O port P6
I/O port P7
Input/output VCC1
Input/output VCC1
This is an 8-bit I/O port equivalent to P0 (P70 and P71 are N
0
7
channel open-drain output). This port can function as input/output
pins for timers A0 to A3 when so selected in a program.
Furthermore, P70 to P75, P71, and P72 to P75 can also function as
input/output pins for UART2, an input pin for timer B5, and output
pins for the three-phase motor control timer, respectively.
P8
0
to P8
4
, P8
6
, and P8
7
are I/O ports with the same functions as
to P8 and P8 to P8 can
P8
P8
0
6
to P8
4
, I/O port P8
Input/output VCC1
Input/output
P0. When so selected in a program, P8
function as input/output pins for timer A4 or output pins for the
three-phase motor control timer and INT interrupt input pins,
0
1
2
4
,
P8
P8
7,
Input/output
Input
respectively. P8
can function as input/output pins for the subclock oscillator circuit.
In that case, connect a crystal resonator between P8 (XCOUT pin)
and P8 (XCIN pin).
P8 is an input-only port shared with NMI. An NMI interrupt is
6 and P87, when so selected in a program, both
5
I/O port P85
6
7
5
generated when input on this pin changes state from high to low.
The NMI function cannot be disabled in a program.
A pull-up cannot be set for this pin.
P90
to P9
7
I/O port P9
Input/output VCC1
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as SI/O3 and SI/O4 I/O pins, Timer B0 to B4 input pins, D-
A converter output pins, A-D converter input pins, or A-D trigger
input pins as selected by program.
P10
P10
0
7
to
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as A-D converter input pins as selected by program.
I/O port P10 Input/output VCC1
Furthermore, P10
4 to P107 also function as input pins for the key
input interrupt function.
Table 1.1.6 Pin Description (3) (128-pin Package) (Continued)
Power supply
circuit block
Pin name
I/O type
Function
Signal name
P11
P12
P13
P14
0
0
0
0
to P11
to P12
to P13
7
7
7
I/O port P11 Input/output
I/O port P12 Input/output
I/O port P13 Input/output
I/O port P14 Input/output
This is an 8-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0.
This is an 2-bit I/O port equivalent to P0.
V
CC1
V
CC2
V
V
CC2
CC1
, P14
1
10
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Memory
Figure 1.2.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from
address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,
a 64-Kbyte internal ROM is allocated to the addresses from F000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 10-Kbytes internal RAM is allocated to the addresses from 0040016 to 02BFF16. In addition to storing
data, the internal RAM also stores the stack used when calling subroutines and when interrupts are gener-
ated.
The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
0000016
SFR
FFE0016
0040016
Internal RAM
XXXXX16
1000016
Special page
vector table
Reserved area
(Note 1)
Internal ROM
Internal RAM
External area
Size
Address XXXXX16
013FF16
Size
Address YYYYY16
2700016
2800016
4K bytes
5K bytes
48K bytes
64K bytes
F400016
F000016
Reserved area
FFFDC16
Undefined instruction
Overflow
017FF16
96K bytes
128K bytes
192K bytes
E800016
E000016
D000016
10K bytes
12K bytes
16K bytes
02BFF16
033FF16
043FF16
External area
BRK instruction
Address match
Single step
8000016
Reserved area
(Note 2)
20K bytes
053FF16
256K bytes
320K bytes
384K bytes
512K bytes
YYYYY16
C000016
B000016
Watchdog timer
24K bytes
31K bytes
063FF16
07FFF16
DBC
NMI
Internal ROM
A000016
8000016
Reset
FFFFF16
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Note 3: Shown here is a memory map for the case where the PM10 bit in the PM1
register is “1” and the PM13 bit in the PM1 register is “1”.
Figure 1.2.1. Memory Map
11
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 1.3.1. Central Processing Unit Register
(1) Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
12
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
(3) Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”
.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
• Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
13
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416
Processor mode register 0
(Note 2)
PM0
00000000
2
2
(CNVSS pin is “L”)
(CNVSS pin is “H”)
00000011
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
000010002
000516
000616
000716
000816
000916
000A16
000B16
01001000
00100000
00000001
2
2
2
XXXXXX00
2
XX000000
2
Data bank register
0016
000C16 Oscillation stop detection register
(Note 3)
0000X000
??16
2
000D16
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
00??????
0016
2(Note 4)
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Power supply detection register 1
001A16 Power supply detection register 2
001B16 Chip select expansion control register
(Note 5)
(Note 5)
VCR1
VCR2
CSE
00001000
0016
2
0016
PLL control register 0
PLC0
0001X0102
001C16
001D16
001E16
Processor mode register 2
Power supply down detection interrupt register
PM2
D4INT
SAR0
XXX00000
0016
2
001F16
002016
DMA0 source pointer
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
??16
??16
X?16
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
DAR0
??16
??16
X?16
TCR0
??16
??16
DM0CON
00000?002
DMA1 source pointer
SAR1
DAR1
??16
??16
X?16
DMA1 destination pointer
??16
??16
X?16
DMA1 transfer counter
DMA1 control register
TCR1
??16
??16
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 4: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage
at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable
Note 5: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Nothing is mapped to this bit
? : Undefined
14
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
After reset
INT3 interrupt control register
INT3IC
TB5IC
XX00?000
XXXX?000
XXXX?000
XXXX?000
2
2
Timer B5 interrupt control register
Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register
TB4IC, U1BCNIC
2
Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register
TB3IC, U0BCNIC
2
SI/O4 interrupt control register (S4IC), INT5 interrupt control register S4IC, INT5IC
XX00?0002
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00?000
XXXX?000
XXXX?0002
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
2
2
DMA1 interrupt control register
2
2
2
Key input interrupt control register
A-D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
2
2
2
2
2
2
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
2
2
2
2
2
2
XXXX?000
XXXX?000
2
2
XX00?000
XX00?000
2
2
INT1 interrupt control register
INT2 interrupt control register
XX00?0002
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
15
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
008016
008116
008216
008316
008416
008516
008616
Register
Symbol
After reset
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash identification register
Flash memory control register 1
(Note 2)
(Note 2)
FIDR
FMR1
XXXXXX002
0?00??0?2
Flash memory control register 0
Address match interrupt register 2
(Note 2)
FMR0
??0000012
RMAD2
0016
0016
X016
XXXXXX002
0016
0016
X016
Address match interrupt enable register 2
Address match interrupt register 3
AIER2
RMAD3
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Peripheral clock select register
PCLKR
000000112
~
~
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: This register is included in the flash memory version.
X : Nothing is mapped to this bit
? : Undefined
16
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
Register
Symbol
TBSR
After reset
000XXXXX
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
Timer B3, 4, 5 count start flag
2
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
??16
??16
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 interrupt occurrence frequency set counter
ICTB2
Timer B3 register
Timer B4 register
Timer B5 register
TB3
TB4
TB5
??16
??16
??16
??16
??16
??16
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 2
Interrupt cause select register
TB3MR
00??00002
00?X0000
00?X0000
TB4MR
TB5MR
IFSR2A
IFSR
2
2
00XXXXXX
0016
2
SI/O3 transmit/receive register
S3TRR
??16
SI/O3 control register
S3C
01000000
2
036316 SI/O3 bit rate generator
036416 SI/O4 transmit/receive register
036516
S3BRG
S4TRR
??16
??16
SI/O4 control register
SI/O4 bit rate generator
S4C
01000000
2
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
S4BRG
??16
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
0016
000X0X0X
X0000000
X0000000
0016
000X0X0X
X0000000
X0000000
0016
000X0X0X
2
2
2
U1SMR3
U1SMR2
2
2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
2
037516 UART2 special mode register 3
2
2
2
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
X0000000
X0000000
0016
??16
037616
037716
037816
U2MR
U2BRG
037916 UART2 bit rate generator
037A16
UART2 transmit buffer register
U2TB
????????2
037B16
XXXXXXX?
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
U2C0
U2C1
U2RB
00001000
00000010
2
2
037C16
037D16
037E16
037F16
UART2 receive buffer register
????????
2
?????XX?
2
Note : The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
17
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
Register
Symbol
TABSR
After reset
0016
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
CPSRF
ONSF
TRGSR
UDF
0XXXXXXX
0016
0016
2
0016
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
TA0
TA1
TA2
TA3
TA4
TB0
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
Timer B1 register
Timer B2 register
TB1
TB2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer B2 special mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
0016
00??0000
00?X0000
00?X0000
2
2
2
XXXXXX00
2
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
??16
????????
2
XXXXXXX?
2
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
2
2
????????
2
?????XX?
2
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
U1MR
U1BRG
U1TB
0016
??16
????????
2
XXXXXXX?
2
03AC16 UART1 transmit/receive control register 0
03AD16 UART1 transmit/receive control register 1
U1C0
U1C1
U1RB
00001000
00000010
????????
?????XX?
X00000002
2
2
2
03AE16
UART1 receive buffer register
03AF16
2
03B016
UART transmit/receive control register 2
UCON
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
DMA0 request cause select register
DM0SL
DM1SL
0016
0016
03B916
03BA16 DMA1 request cause select register
03BB16
03BC16
CRC data register
CRCD
CRCIN
??16
??16
??16
03BD16
03BE16
CRC input register
03BF16
Note : The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
18
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Address
Register
Symbol
After reset
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
????????
XXXXXX??
2
2
2
2
2
2
2
2
2
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
2
2
2
2
2
2
2
XXXXXX??
A-D control register 2
ADCON2
0016
03D616 A-D control register 0
03D716 A-D control register 1
03D816 D-A register 0
03D916
ADCON0
ADCON1
DA0
00000???
0016
??16
2
03DA16 D-A register 1
03DB16
DA1
??16
0016
03DC16
D-A control register
DACON
03DD16
03DE16 Port P14 control register
03DF16 Pull-up control register 3
PC14
PUR3
P0
XX00XXXX
0016
??16
2
03E016
Port P0 register
03E116
03E216
03E316
03E416
03E516
Port P1 register
P1
??16
0016
0016
??16
Port P0 direction register
Port P1 direction register
Port P2 register
PD0
PD1
P2
Port P3 register
P3
??16
03E616 Port P2 direction register
PD2
0016
03E716
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
PD3
P4
P5
PD4
PD5
P6
0016
??16
03E816
03E916
03EA16
??16
0016
0016
??16
??16
0016
0016
??16
??16
00X00000
0016
??16
??16
0016
0016
??16
??16
0016
0016
0016
03EB16 Port P5 direction register
03EC16
Port P6 register
03ED16 Port P7 register
03EE16 Port P6 direction register
P7
PD6
PD7
P8
03EF16
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
2
Port P11 register
Port P10 direction register
Port P11 direction register
Port P12 register
Port P13 register
03FA16 Port P12 direction register
03FB16 Port P13 direction register
03FC16 Pull-up control register 0
03FD16 Pull-up control register 1
00000000
00000010
0016
2
(Note 2)
2
Pull-up control register 2
Port control register
PUR2
PCR
03FE16
03FF16
0016
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: At hardware reset 1 or hardware reset 2, the register is as follows:
• “00000000
• “00000010
2
” where “L” is inputted to the CNVSS pin
” where “H” is inputted to the CNVSS pin
2
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “00000000
• “00000010
2
” where the PM01 to PM00 bits in the PM0 register are “00
” where the PM01 to PM00 bits in the PM0 register are “01
2
” (single-chip mode)
” (memory expansion mode) or
2
2
“112” (microprocessor mode)
X : Nothing is mapped to this bit
19
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-
tion stop detection reset.
Hardware Reset
There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.
Hardware Reset 1
____________
____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
Table 1.5.1). The oscillation circuit is initialized and the main clock starts oscillating. When the input
____________
level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized, and the program
is executed starting from the address indicated by the reset vector. The internal RAM is not initialized.
____________
If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM becomes indetermi-
nate.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1
____________
shows the statuses of the other pins while the RESET pin is “L”. Figure 1.5.3 shows the CPU register
status after reset. Refer to “SFR” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Supply a clock for 20 cycles or more to the XIN pin.
____________
(3) Apply an “H” signal to the RESET pin.
2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Supply a clock for 20 cycles or more to the XIN pin.
____________
(5) Apply an “H” signal to the RESET pin.
Hardware Reset 2
This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-
tion circuit monitors the voltage supplied to the VCC1 pin.
If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-
puter is reset when the voltage at the VCC1 input pin drops below Vdet3.
Similarly, if the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit en-
abled), the microcomputer is reset when the voltage at the VCC1 input pin drops below Vdet2.
Conversely, when the input voltage at the VCC1 pin rises to Vdet3 or more, the pins and the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
vector. It takes about td(S-R) before the program starts running after Vdet3 is detected. The initialized
pins and registers and the status thereof are the same as in hardware reset 1.
Set the CM10 bit in the CM1 register to “1” (stop mode) after setting the VC25 bit to “1” (RAM retention
limit detection circuit enabled), and the microcomputer will be reset when the voltage at the VCC1
input pin drops below Vdet2 and comes out of reset when the voltage at the VCC1 input pin rises above
Vdet3. During stop mode, the value set in the VC26 bit has no effect. Therefore, no reset is generated
even when the input voltage at the VCC1 pin drops to Vdet3 or less.
20
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Recommended
operating
voltage
V
CC1
0V
V
CC1
RESET
RESET
0V
Equal to or less
than 0.2VCC1
Equal to or less
than 0.2VCC1
More than 20 cycles of XIN + td(P-R)
are needed.
Note : When the microcomputer is used under the condition VCC1 ≥ VCC2, make sure the VCC2 voltage does not
exceed the VCC1 voltage when powering up, or powering down the microcomputer.
Figure 1.5.1. Example Reset Circuit
Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.
Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcom-
puter initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00
bits in the PM0 register are not initialized, the processor mode remains unchanged.
Oscillation Stop Detection Reset
Where the CM27 bit in the CM2 register is “0” (reset at oscillation stop detection), the microcomputer
initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to
the section “oscillation stop, re-oscillation detection function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”. Also, since
the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.
21
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
V
CC1, VCC2
X
IN
td(P-R)
More than
20 cycles
are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
BCLK 28cycles
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
CS0
Single chip
mode
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 1.5.2. Reset Sequence
22
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.5.1. Pin Status When RESET Pin Level is “L”
Status
CNVSS = VCC1
BYTE = VCC
Data input
Pin name
CNVSS = VSS
BYTE = VSS
P0
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Input port
Data input
Data input
P1
Input port
P2, P3, P4
0
to P4
3
Address output (undefined)
CS0 output (“H” is output)
Address output (undefined)
CS0 output (“H” is output)
P4
P4
P5
4
5
to P4
7
Input port (Pulled high
)
Input port (Pulled high)
0
WR output (“H” is output)
BHE output (undefined)
RD output (“H” is output)
BCLK output
WR output (“H” is output)
BHE output (undefined)
RD output (“H” is output)
BCLK output
P5
P5
P5
1
2
3
HLDA output (The output value HLDA output (The output value
P5
4
Input port
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P5
P5
P5
5
6
7
Input port
Input port
Input port
HOLD input
HOLD input
ALE output (“L” is output)
RDY input
ALE output (“L” is output)
RDY input
P6, P7, P8
0 to P84,
Input port
Input port
Input port
Input port
Input port
Input port
P8 , P8 , P9, P10
6
7
P11, P12, P13,
1 (Note)
P140, P14
Note : P11, P12, P13, P140, P141 pins exist in 128-pin version.
b15
b0
000016
000016
000016
000016
000016
000016
000016
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b19
b0
b0
0000016
Interrupt table register(INTB)
Program counter(PC)
Content of addresses FFFFE16 to FFFFC16
b15
User stack pointer(USP)
000016
000016
000016
Interrupt stack pointer(ISP)
Static base register(SB)
b15
b0
b0
Flag register(FLG)
000016
b15
b8 b7
IPL
U
I
O B S Z D C
Figure 1.5.3. CPU Register Status After Rreset
23
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Voltage Detection Circuit
The voltage detection circuit has circuits to monitor the input voltage at the VCC1 pin, each checking the
input voltage with respect to Vdet2, Vdet3, and Vdet4, respectively. Use the VC25 to VC27 bits in the VCR2
register to select whether or not to enable these circuits.
Enable the RAM retention limit detection circuit when using hardware reset 2 in stop mode, or when using
the WDC5 bit in the WDC register. The WDC5 bit indicates that the RAM is retained.
Use the reset level detection circuit for hardware reset 2.
The power supply down detection circuit can be set to detect whether the input voltage is equal to or greater
than Vdet4 or less than Vdet4 by using the VC13 bit in the VCR1 register. Furthermore, a power supply
down detection interrupt can be used.
WDC5 bit
Write to WDC register
S
R
Q
WARM/COLD
(Cold start, warm start)
Internal power on reset
VCR2 register
b7 b6 b5
RESET
Internal power supply
voltage stable time
1 shot
>T
+
td(S-R)
≥Vdet2
Half latch
E
Q
D
T
Q
+
Internal reset signal
(“L” active)
≥Vdet3
E
CM10 bit=1
(stop mode)
V
CC1
+
Power supply down
detection signal
≥Vdet4
Noise rejection
E
VCR1 register
b3
VC13 bit
Figure 1.5.4. Reset Circuit Block
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16 00XXXXXX
After reset
0
2
(Note2)
Bit symbol
Bit name
High-order bit of watchdog timer
Cold start / warm start 0 : Cold start
Function
RW
RO
(b4-b0)
WDC5
RW
RW
discrimination flag (Note 1) 1 : Warm start
Reserved bit
Set to “0”
(b6)
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Note 1: The WDC5 bit is always “1” (= warm start) no matter how it is set by writing a “0” or “1”.
Note 2: The WDC5 bit is “0” (= cold start) immediately after power-on. It can only be set to “1” in a program. It is
set to “0” when the input voltage at the VCC1 pin drops to Vdet
bit = 1 (RAM retention limit detection circuit enabled).
2 or less while the VCR2 register’s VC25
Figure 1.5.5. WDC Register
24
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Power supply detection register 1
b7
b
b
b4
b
b
b1
b
Symbol
Address
001916
After reset (Note 2)
00001000
0 0 0 0
0 0 0
VCR1
2
Bit name
Function
RW
Bit symbol
(b2-b0)
Reserved bit
Must set to “0”
RW
RO
Power supply down monitor
flag (Note 1)
0:VCC1 < Vdet4
1:VCC1 Vdet4
Must set to “0”
VC13
RW
Reserved bit
(b7-b4)
Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (power supply down detection circuit
enable). The VC13 bit is always “1” (VCC1 4 V) when the VC27 bit in the VCR2 register is set to “0” (power
supply down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Power supply detection register 2 (Note 1)
b7
b
b
b4
b
b
b1
b
Symbol
VCR2
Address
001A16
After reset (Note 6)
0016
0 0 0 0 0
Bit name
RW
RW
Bit symbol
(b4-b0)
Function
Must set to “0”
Reserved bit
0: Disable RAM retention limit
detection circuit
1: Enable RAM retention limit
detection circuit
0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
RAM retention limit
detection monitor bit
(Notes 3, 4, 7)
VC25
RW
RW
VC26
VC27
Reset level monitor bit
(Notes 2, 3, 7)
0: Disable power supply down
detection circuit
1: Enable power supply down
detection circuit
Power supply down monitor
bit (Note 5)
RW
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: To use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: To use hardware reset 2 in stop mode, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc
becomes lower than Vdet3.)
1 pin
Note 4: To use the WDC5 bit in the WDC register, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
Note 5: Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(power supply down detection interrupt enable), set the VC27 bit to “1” (power supply down detection circuit
enable).
Note 6: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 7: The detection circuit does not start operation until td(E-A) elapses after the VC25 bit, VC26 bit, or VC27 bit is
set to “1”.
Power supply down detection interrupt register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001F16
After reset
0016
Bit symbol
D40
RW
RW
Bit name
Function
Power supply down detection
interrupt enable bit (Note 5)
0 : Disable
1 : Enable
0: Disable (do not use the power
supply down detection
interrupt to get out of stop mode)
1: Enable (use the power supply
down detection interrupt to get
out of stop mode)
STOP mode deactivation
control bit
(Note 4)
D41
RW
Power supply change
detection flag (Note 2)
0: Not detected
1: Vdet4 passing detection
RW
D42
D43
DF0
DF1
(Note 3)
0: Not detected
1: Detected
RW
(Note 3)
WDT overflow detect flag
Sampling clock select bit
b5b4
RW
RW
00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
(b7-b6)
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (power supply down detection circuit enabled).
If the VC27 bit is set to “0” (power supply down detection circuit disable), the D42 bit is set to “0” (Not
detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the power supply down detection interrupt needs to be used to get out of stop mode again after once
used for that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is useful where the VC27 bit in the VCR2 register is set to “1”.
Figure 1.5.6. VCR1 Register, VCR2 Register, and D4INT Register
25
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Typical operation 1 of hardware reset 2
5.0V
5.0V
Vdet4
Vdet3r
Vdet3
VCC1
Vdet3s
VSS
RESET
Internal reset signal
VC13 bit
VC26 bit
VC27 bit
undefined
undefined
Set to “1” in a program (reset level detection circuit enable)
Set to “1” in a program
(power supply down detection circuit enable)
undefined
Typical operation 2 of hardware reset 2
5.0V
5.0V
Vdet4
Vdet3r
Vdet2
Vdet3s
VCC1
VSS
RESET
Internal reset signal
Set to “1” in a program (warm start)
Set to “1” in a program (stop mode)
WDC5 bit
undefined
CM10 bit
VC13 bit
undefined
undefined
Set to “1” in a program
(RAM retention limit detection circuit enable)
undefined
undefined
VC25 bit
VC27 bit
Set to “1” in a program
(power supply down detection circuit enable)
Figure 1.5.7. Typical Operation of Hardware Reset 2
26
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Power Supply Down Detection Interrupt
A power supply down detection interrupt request is generated when the input voltage at the VCC1 pin rises
to Vdet4 or more or drops below Vdet4 while the D40 bit in the D4INT register is set to “1” (power supply
down detection interrupt enable). The power supply down detection interrupt shares the interrupt vector
with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
To use the power supply down detection interrupt to get out of stop mode, set the D41 bit in the D4INT
register to “1” (enable).
The D42 bit in the D4INT register becomes “1” when passing through Vdet4 is detected after the voltage
inputted to the VCC1 pin is up or down.
A power supply down detection interrupt is generated when the D42 bit changes state from “0” to “1”. The
D42 bit needs to be set to “0” in a program. However, where the D41 bit is “1” and the stop mode is selected,
the power supply down detection interrupt request arises, and the microcomputer is reset from the stop
mode with no regard for the status of D42 bit if it is detected that the voltage applied to the VCC1 pin has
increased, passing through Vdet4.
Table 1.5.2 shows the power supply down detection interrupt request generation conditions.
It is possible to set the sampling clock detecting that the voltage applied to the VCC1 pin has passed through
Vdet4 with the DF1 to DF0 bits of D4INT register. Table 1.5.3 shows sampling clock periods.
Table 1.5.2. Power Supply Down Detection Interrupt Request Generation Conditions
Power supply
down detection
Interrupt
Bit, Vdet4 passing detection, operation mode condition
VC27
bit
D40
bit
Vdet4 passing
detection
D41
bit
VC13
bit
Operation mode
(Notes 1, 2)
D42 bit
request
0
1
Not generated
0
1
Not detected
Detected
0
Generated
From 0 to 1
Normal, wait
Stop
Not generated
Generated
1
0
1
Not generated
From 1 to 1
(No change)
Normal, wait
Stop
From 0 to 1
(Up)
Generated
From 1 to 0
(Down)
Not generated
Note 1: The status except the wait mode and stop mode is handled as the normal mode.(Refer to “Clock generating circuit”)
Note 2: Refer to “Limitations on stop mode”, “Limitations on wait mode”.
Table 1.5.3. Sampling Clock Periods
CPU
clock
(MHz)
Sampling clock (µs)
divided by 8 divided by 16 divided by 32 divided by 64
16
1.5
3.0
6.0
12.0
Precautions
1. Limitations on Stop Mode
If the CM10 bit in the CM1 register is set to “1” (stop mode) when the VC13 bit in the VCR1 register is “1”
(VCC1 ≥ Vdet4) while the VC27 bit in the VCR2 register is “1” (power supply down detection circuit enable)
and the D40 bit in the D4INT register is “1” (power supply down detection interrupt enable) and D41 bit in
the D4INT register is “1” (power supply down detection interrupt is used to get out of stop mode), a power
supply down detection interrupt is immediately generated, causing the microcomputer to exit stop mode.
In systems where the microcomputer enters stop mode when the input voltage at the VCC1 pin drops
below Vdet4 and exits stop mode when the input voltage rises to Vdet4 or more, make sure the CM10 bit
is set to “1” when VC13 bit is “0” (VCC1 < Vdet4).
27
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
2. Limitations on WAIT Instruction
If the WAIT instruction is executed when the VC13 bit in the VCR1 register is “1” (VCC1 ≥ Vdet4) while the
VC27 bit in the VCR2 register is “1” (power supply down detection circuit enable) and the D40 bit in the
D4INT register is “1” (power supply down detection interrupt enable), a power supply down detection
interrupt is immediately generated, causing the microcomputer to exit wait mode.
In systems where the microcomputer enters wait mode when the input voltage at the VCC1 pin drops
below Vdet4 and exits wait mode when the input voltage rises to Vdet4 or more, make sure the WAIT
instruction is executed when VC13 bit is “0” (VCC1 < Vdet4).
Power supply down detection interrupt generation circuit
DF1, DF0
Power supply down detection circuit
00
01
10
11
2
2
2
2
D42 bit is set to “0”(not detected) by
writing a “0” in a program. VC27 bit
is set to “0” (power supply down
detection circuit disabled), the D42
bit is set to “0”.
VC27
BCLK
VC13
1/8
1/2
1/2
1/2
D42
Watchdog
timer interrupt
signal
V
V
CC1
REF
+
-
Noise
rejection
Noise rejection
circuit
Digital
filter
Power supply
down
detection
signal
(Rejection wide:200 ns)
Power supply
down detection
interrupt signal
“H” when VC27
bit= 0 (disabled)
Non-maskable
interrupt signal
D41
Oscillation stop,
re-oscillation
detection
CM02
interrupt signal
WAIT instruction(wait mode)
Watchdog timer block
D43
D40
Watchdog timer
underflow signal
This bit is set to “0”(not detected) by writing a “0” in a program.
Figure 1.5.8. Power Supply Down Detection Interrupt Generation Block
V
CC1
VC13 bit
sampling
sampling
sampling
sampling
No power supply down detection interrupt signals
are generated when the D42 bit is “H”.
Output of the digital filter (Note 2)
D42 bit
Set to “0” in a
program (not
detected)
Set to “0” in a
program (not
detected)
Power supply down detection
interrupt signal
Note 1 : D40 is “1”(power supply down detection interrupt enabled)
Note 2 : Output of the digital filter shown in Figure 1.5.8.
Figure 1.5.9. Power Supply Down Detection Interrupt Generation Circuit Operation Example
28
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor Mode
(1) Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 1.6.1 shows the features of these processor modes.
Table 1.6.1. Features of Processor Modes
Processor modes
Single-chip mode
Access space
Pins which are assigned I/O ports
SFR, internal RAM, internal ROM
All pins are I/O ports or peripheral
function I/O pins
Memory expansion mode
SFR, internal RAM, internal ROM,
external area (Note)
Some pins serve as bus control pins (Note)
Microprocessor mode
Note : Refer to “Bus”.
SFR, internal RAM, external area (Note)
Some pins serve as bus control pins (Note)
(2) Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 1.6.2 shows the processor mode after hardware reset. Table 1.6.3 shows the PM01 to PM00 bit set
values and processor modes.
Table 1.6.2. Processor Mode After Hardware Reset
CNVSS pin input level
Processor mode
V
V
SS
Single-chip mode
CC1 (Note 1, Note 2)
Microprocessor mode
Note 1: If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1
or hardware reset 2), the internal ROM cannot be accessed regardless of PM10 to PM00 bits.
Note 2: The multiplexed bus cannot be assigned to the entire CS space.
Table 1.6.3. PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 bits
00
01
Processor modes
2
Single-chip mode
2
Memory expansion mode
Must not be set
102
2
11
Microprocessor mode
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regard-
less of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits
cannot be rewritten to “012” (memory expansion mode) or “112” (microprocessor mode) at the same time
the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or hard-
ware reset 2), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 1.6.1 and 1.6.2 show the registers associated with processor modes. Figure 1.6.3 show the
memory map in single chip mode.
29
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note 1)
Symbol
PM0
Address
000416
After reset (Note 4)
b7 b6 b5 b4 b3 b2 b1 b0
00000000
2
(CNVSS pin = “L”)
(CNVSS pin = “H”)
00000011
2
Bit symbol
Bit name
Function
RW
RW
b1 b0
Processor mode bit
(Note 4)
PM00
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
PM01
PM02
RW
RW
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
R/W mode select bit
(Note 2)
PM03
PM04
Software reset bit
Setting this bit to “1” resets the
microcomputer. When read, its content
is “0”.
RW
RW
b5 b4
Multiplexed bus space
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
space)
select bit
(Note 2)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space
(Note 3)
PM05
PM06
PM07
RW
RW
RW
0 : Address output
1 : Port function
(Address is not output)
Port P40 to P43 function
select bit (Note 2)
0 : BCLK is output
1 : BCLK is not output
(Pin is left high-impedance)
BCLK output disable bit
(Note 2)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: Effective when the PM01 to PM00 bits are set to “01
mode).
2
” (memory expansion mode) or “11
2
” (microprocessor
Note 3: To set the PM01 to PM00 bits are “01
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the
CNVSS pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “11 ” after reset.
If the PM05 to PM04 bits are set to “11 ” during memory expansion mode, P3 to P3 and P4
become I/O ports, in which case the accessible area for each CS is 256 bytes.
2” and the PM05 to PM04 bits are “112” (multiplexed bus assigned to
2
2
1
7
0 to P43
Note 4: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop
detection reset.
Figure 1.6.1. PM0 Register
30
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
After reset
0X001000
0
2
Bit symbol
PM10
Bit name
Function
RW
RW
0: 0800016 to 26FFF16
(block A disable)
1: 1000016 to 26FFF16
(block A enable)
CS2 area switch bit
(data block enable bit)
(Note 2)
0 : Address output
(Note 3) 1 : Port function
Port P37 to P34
function select bit
PM11
PM12
RW
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
Watchdog timer function
select bit
RW
RW
Internal reserved area
expansion bit
PM13
See Note 6
b5 b4
Memory area
0 0 : 1 Mbyte mode
(Do not expand)
0 1 : Must not be set
1 0 : Must not be set
1 1 : 4 Mbyte mode
PM14
PM15
RW
RW
expansion bit (Note 3)
Should be set to “0”.
Reserved bit
RW
RW
(b6)
0 : No wait state
1 : With wait state (1 wait)
PM17
Wait bit (Note 5)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: For the mask ROM version, this bit must be set to “0” . For the flash memory version, the PM10 bit also
controls block A by enabling or disabling it. However, the PM10 bit is automatically set to “1” when the
FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to “01
mode).
2” (memory expansion mode) or “112” (microprocessor
Note 4: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 5: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area. If the CSiW bit (i = 0 to 3) in the CSR register is “0” (with wait state), the
CSi area is always accessed with one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplex bus is used, set the CSiW bit to “0” (with wait state).
Note 6: The access area is changed by the PM13 bit as listed in the table below.
Access area
PM13=0
PM13=1
Internal RAM Up to addresses 0040016 to 03FFF16 (15 Kbytes) The entire area is usable
ROM Up to addresses D000016 to FFFFF16 (192 Kbytes) The entire area is usable
External
Addresses 0400016 to 07FFF16 are usable
Addresses 8000016 to CFFFF16 are usable
Addresses 0400016 to 07FFF16 are reserved
Addresses 8000016 to CFFFF16 are reserved
Figure 1.6.2. PM1 Register
31
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
PM13=0
Single-chip mode
Internal RAM
Internal ROM
0000016
Address XXXXX16
Capacity
Address YYYYY16
Capacity
SFR
4K bytes
48K bytes
F400016
F000016
E800016
013FF16
0040016
5K bytes 017FF16
64K bytes
96K bytes
10K bytes
02BFF16
033FF16
Internal RAM
12K bytes
128K bytes
192K bytes
E000016
XXXXX16
D000016
03FFF16(Note 2)
03FFF16(Note 2)
03FFF16(Note 2)
03FFF16(Note 2)
16K bytes
20K bytes
D000016(Note 2)
D000016(Note 2)
256K bytes
320K bytes
24K bytes
31K bytes
384K bytes
512K bytes
D000016(Note 2)
D000016(Note 2)
Can not
use
PM13=1
Capacity
Internal RAM
Internal ROM
Address XXXXX16
Capacity
48K bytes
64K bytes
96K bytes
128K bytes
192K bytes
Address YYYYY16
F400016
4K bytes
5K bytes
013FF16
017FF16
F000016
YYYYY16
FFFFF16
10K bytes
12K bytes
16K bytes
20K bytes
24K bytes
31K bytes
02BFF16
033FF16
043FF16
053FF16
063FF16
07FFF16
E800016
E000016
D000016
Internal ROM
256K bytes
320K bytes
C000016
B000016
384K bytes
512K bytes
A000016
8000016
Note 1: For the mask ROM version, set the PM10 bit to “0” (0800016 to 26FFF16 for CS2 area).
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
Figure 1.6.3. Memory Map in Single Chip Mode
32
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
_______
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0
_______ _____ ________ ______ ________ ________
________ __________ _________
to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits.
Separate Bus
In this bus mode, data and address are separate.
Multiplexed Bus
In this bus mode, data and address are multiplexed. If the data bus is 8 bits wide, D0 to D7 and A0 to
A7 are multiplexed. If the data bus is 16 bits wide, D0 to D7 and A1 to A8 are multiplexed, with D8 to D15
not multiplexed. In this case, external devices connecting to the multiplexed bus are mapped to the
even addresses of the microcomputer.
33
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 1.7.1
shows the PM06 and PM11 bit set values and address bus widths.
Table 1.7.1. PM06 and PM11 Bits Set Value and Address Bus Width
Set value(Note)
PM11=1
Pin function
to P3
to P43
Address bus wide
P3
P4
4
0
7
12 bits
PM06=1
PM11=0
PM06=1
PM11=0
PM06=0
A
12 to A15
to P43
16 bits
20 bits
P4
0
A
A
12 to A15
16 to A19
Note 1: No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address
bus is indeterminate until any external area is accessed.
(2) Data Bus
When input on the BYTE pin is high, 8 lines D0 to D7 comprise the data bus; when input on the BYTE
pin is low, 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
(3) Chip Select Signal
______
______
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins.
_____
These pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 1.7.1 shows the CSR register.
______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
______
______
from the CSi pin. During 4 Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to
______
“Memory space expansion function”. Figure 1.7.2 shows the example of address bus and CSi signal
output in 1 Mbyte mode.
Chip select control register
Symbol
CSR
Address
000816
After reset
00000001
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
RW
CS0
RW
RW
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
CS1
RW
RW
RW
CS2
CS3
CS0W
CS1W
CS2W
CS3W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : With wait state
1 : Without wait state
(Note 1, Note 2, Note 3)
RW
RW
RW
Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set
the CSiW bit to “0” (Wait state).
Note 2: If the PM17 bit in the PM1 register is set to “1” (with wait state), the external area indicated by CS0 to
CS3 is always accessed with one wait state even when the CSiW bit is “1” (without wait state).
Note 3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be
selected using the CSEi1W to CSEi0W bits in the CSE register.
Figure 1.7.1. CSR Register
34
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
Example 1
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
Example 2
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
The chip select signal changes state but the address bus does not
change state
Access to the external Access to the external
area indicated by CSi area indicated by CSj
Access to the external Access to the internal
area indicated by CSi ROM or internal RAM
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
CSi
Data
Data
Data bus
Address bus
CSi
Data
Address Address
Address
CSj
Example 3
Example 4
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
Neither the address bus nor the chip select signal changes state between
these two cycles
The address bus changes state but the chip select signal does not
change state
No access
Access to the external Access to the same
area indicated by CSi external area
Access to the external
area indicated by CSi
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
CSi
Data bus
Address bus
CSi
Data
Data
Data
Address
Address Address
Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
______
Figure 1.7.2. Example of Address Bus and CSi Signal Output in 1 Mbyte Mode
35
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(4) Read and Write Signals
_____
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
________
______
_____ ________
________
BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
_____ ______
________
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
_____ ________
_________
Table 1.7.2 shows the operation of RD, WRL, and WRH signals. Table 1.7.3 shows the operation of
_____ ______
________
operation of RD, WR, and BHE signals.
_____ ________
_________
Table 1.7.2. Operation of RD, WRL and WRH Signals
Data bus width
Status of external data bus
RD
L
WRL
H
L
WRH
H
H
L
Read data
16-bit
( BYTE pin input
= “L”)
H
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
H
H
L
H
L
_____ ______
________
Table 1.7.3. Operation of RD, WR and BHE Signals
Data bus width
A0
H
Status of external data bus
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
RD
H
L
WR
L
BHE
L
H
L
L
H
16-bit
(BYTE pin input
= “L”)
H
L
H
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
(Note)
(Note)
H or L
H or L
8-bit (BYTE pin
input = “H”)
H
Read 1 byte of data
Note : Do not use.
(5) ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin input = “H”
ALE
When BYTE pin input = “L”
ALE
A0
Address
A0/D0 to A7/D7
Address
Data
Address
Data
A
1
/D
0
to A
8/D7
A8 to A19
Address (Note)
A9 to A19
Address
Note : If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 1.7.3. ALE Signal, Address Bus, Data Bus
36
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(6) The _R__D___Y__ Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
______
______
______ ________ ________ ______ ________
__________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the
________
________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________
________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits are “00
2” (one wait state).
________
Figure 1.7.4. Example in which Wait State was Inserted into Read Cycle by RDY Signal
37
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(7) Hold Signal
This signal is used to transfer control of the bus from the CPU or DMA to an external circuit. When input
__________
on the HOLD pin is asserted “L”, the microcomputer goes to a hold state after completing the bus access
__________
then in progress. While the HOLD pin is held “L”, the microcomputer remains in a hold state, outputting a
__________
low signal from the HLDA pin.
Table 1.7.4 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.7.5. Bus-using Priorities
Table 1.7.4. Microcomputer Status in Hold State
Item
Status
BCLK
Output
_______
_______ _____ ________ _________ _______ _______
A
0
to A19, D to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE High-impedance
0
I/O ports
P0, P1, P3, P4(Note 2)
P6 to P14(Note 1)
High-impedance
Maintains status when hold signal is received
Output “L”
__________
HLDA
Internal peripheral circuits
ALE signal
ON (but watchdog timer stops)
Undefined
Note 1: P11 to P14 are included in the 128-pin version.
Note 2: When I/O port function is selected.
(8) BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to “CPU clock and pheripheral clock”.
38
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
Table 1.7.5. Pin Functions for Each Processor Mode
Memory expansion
mode
Processor mode
Memory expansion mode or microprocessor mode
01
2
(CS2 is for multiplexed bus and
others are for separate bus)
(CS1 is for multiplexed bus and
others are for separate bus)
00
2(separate bus)
112(multiplexed bus
for the entire space)
(Note 1)
PM05–PM04 bits
10
2
Data bus width
BYTE pin
16 bits
“L”
16 bits
“L”
8 bits
“H”
8 bits
“H”
8 bits
“H”
P0
0
0
to P0
to P1
7
7
D
0
to D
7
D
0
to D
7
D
0
to D
7
D
0
8
to D
7
I/O ports
I/O ports
P1
I/O ports
D
8
0
to D15
I/O ports
D
to D15
P2
0
A0
A
A
0
/D
0(Note 2)
A
0
1
A
0/D0
A
1
to A
7
/D to D
1
7
A
to A
7
/D
0
to D
6
A
1
to A
7/D1 to D7
P21
to P2
7
A
1
to A7
A1 to A7
(Note 2)
(Note 2)
P30
A8
A8
A8
A
8
/D (Note 2)
7
A8
P3
1
4
to P3
to P3
3
7
A
9
to A11
12 to A15
I/O ports
16 to A19
I/O ports
I/O ports
P3
PM11=0
PM11=1
A
P40
to P4
3
A
PM06=0
PM06=1
CS0=0
CS0=1
CS1=0
CS1=1
CS2=0
CS2=1
CS3=0
CS3=1
PM02=0
PM02=1
PM02=0
PM02=1
I/O ports
I/O ports
P4
P4
P4
P4
P5
P5
4
5
6
7
0
1
I/O ports
CS0
I/O ports
CS1
I/O ports
CS2
I/O ports
CS3
WR
(Note 3)
WRL
WRH
(Note 3)
(Note 3)
WRL
WRH
(Note 3)
(Note 3)
BHE
(Note 3)
P5
P5
P5
P5
P5
P5
2
3
4
5
6
7
RD
BCLK
HLDA
HOLD
ALE
RDY
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: To set the PM01 to PM00 bits are set to “01 ” and the PM05 to PM04 bits are set to “11
space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not rewrite the PM05
to PM04 bits to “11 ” after reset. If the PM05 to PM04 bits are set to “11 ” during memory expansion mode, P3 to P3 and P4 to P43
2
2” (multiplexed bus assigned to the entire CS
2
2
1
7
0
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3: If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
39
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(9) External Bus Status When Internal Area Accessed
Table 1.7.6 shows the external bus status when the internal area is accessed.
Table 1.7.6. External Bus Status When Internal Area Accessed
Item
SFR accessed
Address output
Internal ROM, RAM accessed
Maintain status before accessed
address of external area or SFR
High-impedance
A
0
to A19
to D15
D
0
When read
When write
High-impedance
Output data
Undefined
RD, WR, WRL, WRH
BHE
RD, WR, WRL, WRH output
BHE output
Output “H”
Maintain status before accessed
status of external area or SFR
Output “H”
CS0 to CS3
ALE
Output “H”
Output “L”
Output “L”
(10) Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0”. Figure 1.7.6 shows the CSE
register. Table 1.7.7 shows the software wait related bits and bus cycles. Figure 1.7.7 and 1.7.8 show the
typical bus timings using software wait.
Chip select expansion control register
Symbol
CSE
Address
001B16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
CSE00W
Bit name
CS0 wait expansion bit
Function
b1 b0
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
(Note)
CSE01W
RW
RW
1 1: Must not be set
b3 b2
0 0: 1 wait
CS1 wait expansion bit
(Note)
CSE10W
CSE11W
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
RW
b5 b4
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
CS2 wait expansion bit
(Note)
CSE20W
CSE21W
RW
1 1: Must not be set
b7 b6
CS3 wait expansion bit
(Note)
CSE30W
CSE31W
RW
RW
0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “
00 ” before setting it.
2
Figure 1.7.6. CSE Register
40
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
Table 1.7.7. Bit and Bus Cycle Related to Software Wait
CSR register
CSE register
CS3W bit (Note 1)
CS2W bit (Note 1)
CS1W bit (Note 1)
CS0W bit (Note 1)
CSE31W to CSE30W bit
CSE21W to CSE20W bit
CSE11W to CSE10W bit
CSE01W to CSE00W bit
PM1 register
PM17 bit
Software wait
Area
Bus mode
Bus cycle
0
1
No wait
1 wait
1 BCLK cycle (Note 3)
2 BCLK cycles
Internal
RAM, ROM
1 BCLK cycle (read)
2 BCLK cycles (write)
2 BCLK cycles (Note 3)
3 BCLK cycles
0
1
00
2
No wait
0
0
0
1
0
0
0
0
00
01
10
2
2
2
1 wait
2 waits
3 waits
1 wait
Separate bus
External area
4 BCLK cycles
1
1
2 BCLK cycles
00
00
01
10
00
2
2
2
2
2
1 wait
3 BCLK cycles
2 waits
3 waits
1 wait
3 BCLK cycles
Multiplexed bus
(Note 2)
4 BCLK cycles
3 BCLK cycles
Note 1: To use the RDY signal, set this bit to “0”.
Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
Note 3: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“0016” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
41
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(1) Separate bus, No wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Input
Output
Data bus
Address bus
Address
Address
CS
(2) Separate bus, 1-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Input
Data bus
Address bus
CS
Address
Address
(3) Separate bus, 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Input
Data bus
Address
Address bus
Address
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 1.7.7. Typical Bus Timings Using Software Wait (1)
42
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
(1) Separate bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Input
Data bus
Output
Address
Address
Address bus
CS
(2)Multiplexed bus, 1- or 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
ALE
Address
Address
Address bus
Address bus/
Data bus
Address
Data output
Input
Address
CS
(3)Multiplexed bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
ALE
Address bus
Address
Address
Address bus/
Data bus
Address
Data output
Input
Address
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 1.7.8. Typical Bus Timings Using Software Wait (2)
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Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function
Memory Space Expansion Function
The following describes a memory space extension function.
During memory expansion or microprocessor mode, the memory space expansion function allows the
access space to be expanded using the appropriate register bits.
Table 1.8.1 shows the way of setting memory space expansion function, memory spaces.
Table 1.8.1. The Way of Setting Memory Space Expansion Function, Memory Space
Memory space expansion function
1 Mbytes mode
How to set (PM15 to PM14)
Memory space
1 Mbytes (no expansion)
4 Mbytes
002
4 Mbytes mode
112
(1) 1 Mbyte Mode
In this mode, the memory space is 1 Mbytes. In 1 Mbyte mode, the external area to be accessed is
______
______
specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 1.8.2 to 1.8.3
_____
show the memory mapping and CS area in 1 Mbyte mode.
(2) 4 Mbyte Mode
In this mode, the memory space is 4 Mbytes. Figure 1.8.1 shows the DBR register. The BSR2 to BSR0
bits select a bank number which is to be accessed to read or write data. Setting the OFS bit to “1” (with
offset) allows the accessed address to be offset by 4000016.
______
In 4 Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed.
Addresses 0400016 to 3FFFF16, C000016 to FFFFF16
______
______
• The CSi signal is output from the CSi pin (same operation as 1 Mbyte mode. However the last address
_______
of CS1 area is 3FFFF16)
Addresses 4000016 to BFFFF16
______
• The CS0 pin outputs “L”
______
______
• The CS1 to CS3 pins output the value of the BSR2 to BSR0 bits (bank number)
______
Figures 1.8.4 to 1.8.5 show the memory mapping and CS area in 4 Mbyte mode. Note that banks 0 to 6
______
are data-only areas. Locate the program in bank 7 or the CSi area.
Data bank register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DBR
Address
000B16
After reset
0016
Bit symbol
Bit name
Description
RW
Nothing is assigned. When write, set to “0”. When read, its content is
“0”.
(b1-b0)
OFS
0: Not offset
1: Offset
Offset bit
RW
RW
BSR0
Bank selection bits
b5 b4 b3
0 0 0: Bank 0
0 1 0: Bank 2
1 0 0: Bank 4
1 1 0: Bank 6
b05 b04 1b3: Bank 1
0 1 1: Bank 3
1 0 1: Bank 5
1 1 1: Bank 7
BSR1
BSR2
RW
RW
Nothing is assigned. When write, set to “0”. When read, its content is
“0”.
(b7-b6)
Note : Effective when the PM01 to PM00 bits are set to “01
mode).
2” (memory expansion mode) or “112” (microprocessor
Figure 1.8.1. DBR Register
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Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function
Memory expansion mode
Microprocessor mode
SFR
0000016
SFR
0040016
Internal RAM
XXXXX16
Internal RAM
Reserved area
Reserved area
0400016
(16 Kbytes)
CS3
0800016
Reserved, External area
Reserved, external area
Reserved area
(PM10=0: 124 Kbytes)
(PM10=1: 92 Kbytes)
CS2
1000016
CS2
2700016
2800016
Reserved area
External area
(32 Kbytes)
CS1
3000016
External area
CS0(Memory expansion mode:640 Kbytes )
D000016
Reserved area
Internal ROM
CS0(Microprocessor mode:832 Kbytes)
YYYYY16
FFFFF16
PM13=0
Internal RAM
Internal ROM
External area
Address XXXXX16
Address YYYYY16
Capacity
CS0
Capacity
4 Kbytes
5 Kbytes
CS1
CS2
CS3
013FF16
F400016
F000016
E800016
2800016
2FFFF16
–
When PM10=0
0800016–26FFF16
0400016–
07FFF16
48 Kbytes
64 Kbytes
96 Kbytes
Memory expansion mode
3000016–CFFFF16
017FF16
Microprocessor mode
3000016–FFFFF16
When PM10=1
1000016–26FFF16
02BFF16
033FF16
10 Kbytes
12 Kbytes
16 Kbytes
20 Kbytes
24 Kbytes
E000016
128 Kbytes
192 Kbytes
256 Kbytes
D000016
03FFF16(Note)
03FFF16(Note)
03FFF16(Note) 320 Kbytes
D000016(Note)
D000016(Note)
D000016(Note)
D000016(Note)
31 Kbytes 03FFF16(Note)
384 Kbytes
512 Kbytes
Note : If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
______
Figure 1.8.2. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=0)
Memory expansion mode
Microprocessor mode
0000016
SFR
SFR
0040016
Internal RAM
Internal RAM
XXXXX16
Reserved area
0800016
1000016
Reserved, external area
Reserved area
Reserved, external area
(PM10=0: 124 Kbytes)
(PM10=1: 92 Kbytes)
CS2
CS2
2700016
2800016
Reserved area
External area
(32 Kbytes)
CS1
3000016
External
area
CS0(Memory expansion mode:320 Kbytes )
8000016
Reserved area
Internal ROM
CS0(Microprocessor mode:832 Kbytes)
YYYYY16
FFFFF16
PM13=1
Internal RAM
Internal ROM
External area
CS1
Address XXXXX16
Address YYYYY16
Capacity
CS0
Capacity
4 Kbytes
CS2
CS3
No area
013FF16
017FF16
02BFF16
033FF16
043FF16
053FF16
063FF16
07FFF16
F400016
F000016
2800016
–
When PM10=0
48 Kbytes
64 Kbytes
Memory expansion mode
3000016–7FFFF16
2FFFF16
0800016–26FFF16
5 Kbytes
10 Kbytes
12 Kbytes
96 Kbytes
128 Kbytes
192 Kbytes
256 Kbytes
Microprocessor mode
3000016–FFFFF16
When PM10=1
1000016–26FFF16
E800016
E000016
D000016
16 Kbytes
20 Kbytes
24 Kbytes
C000016
B000016
A000016
8000016
320 Kbytes
384 Kbytes
512 Kbytes
31 Kbytes
______
Figure 1.8.3. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=1)
45
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function
Memory expansion mode
Microprocessor mode
SFR
0000016
SFR
0040016
Internal RAM
XXXXX16
Internal RAM
Reserved area
Reserved area
0400016
(16 Kbytes)
CS3
0800016
1000016
Reserved, external area
Reserved area
Reserved, external area
Reserved area
(PM10=0: 124 Kbytes)
(PM10=1: 92 Kbytes)
CS2
CS2
2700016
2800016
(96 Kbytes)
CS1
4000016
External area
Other than the CS area (512 Kbytes X 8 banks)
External area
C000016
D000016
YYYYY16
CS0(Memory expansion mode:64 Kbytes )
CS0(Microprocessor mode:256 Kbytes)
Reserved area
Internal ROM
FFFFF16
PM13=0
External area
Internal RAM
Capacity
Internal ROM
Address XXXXX16
Address YYYYY16
Capacity
CS0
Other than the CS area (Note 1)
4000016–BFFFF16
CS1
2800016
3FFFF16
CS2
CS3
4 Kbytes
5 Kbytes
48 Kbytes
013FF16
017FF16
02BFF16
F400016
F000016
E800016
–
When PM10=0
0800016–26FFF16
Memory expansion mode
C000016–CFFFF16
0400016
07FFF16
–
64 Kbytes
96 Kbytes
10 Kbytes
Microprocessor mode
C000016–FFFFF16
When PM10=1
1000016–26FFF16
128 Kbytes
192 Kbytes
E000016
12 Kbytes 033FF16
D000016
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
03FFF16(Note2)
03FFF16(Note2)
03FFF16(Note2)
03FFF16(Note2)
D000016(Note2)
256 Kbytes
320 Kbytes D000016(Note2)
384 Kbytes D000016(Note2)
D000016(Note2)
512 Kbytes
Note 1: The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
______
Figure 1.8.4. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=0)
Memory expansion mode
Microprocessor mode
0000016
SFR
SFR
0040016
Internal RAM
Internal RAM
XXXXX16
Reserved area
Reserved area
0800016
1000016
Reserved, external area
Reserved, external area
(PM10=0: 124 Kbytes)
(PM10=1: 92 Kbytes)
CS2
CS2
2700016
2800016
Reserved area
External area
Reserved area
External area
(96 Kbytes)
CS1
4000016
Other than the CS area (Memory expansion mode:256 Kbytes X 8 banks)*
*Two 256 Kbytes X 8 banks can be used by changing the offset.
8000016
C000016
Other than the CS area(Microprocessor mode:512 Kbytes X 8 banks)
Reserved area
Internal ROM
CS0(Microprocessor mode:256 Kbytes)
YYYYY16
FFFFF16
PM13=1
Internal RAM
Address XXXXX16
Internal ROM
Capacity
External area
CS1
Address YYYYY16
Capacity
CS0
Other than the CS area (Note)
CS2
CS3
4 Kbytes
013FF16
017FF16
02BFF16
033FF16
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
192 Kbytes
F400016
F000016
2800016
3FFFF16
–
When PM10=0
0800016–26FFF16
No area
Memory expansion mode
0400016–7FFFF16
Microprocessor mode
C000016–FFFFF16
5 Kbytes
10 Kbytes
12 Kbytes
E800016
E000016
D000016
When PM10=1
1000016–26FFF16
Microprocessor mode
0400016–BFFFF16
16 Kbytes
20 Kbytes
24 Kbytes
31 Kbytes
043FF16
053FF16
063FF16
07FFF16
C000016
B000016
A000016
8000016
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
Note : The CS0 pin outputs a low signal, and the CS1–CS3 pins output a bank number.
______
Figure 1.8.5. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=1)
46
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Space Expansion Function
Figure 1.8.6 shows the external memory connect example in 4 Mbyte mode.
_____
_______
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The address
_______ _______
_______
input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer,
respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures 1.8.7 to
1.8.9 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer for the case
of a connection example in Figure 1.8.6.
In microprocessor mode, or in memory expansion mode where the PM13 bit is “0”, banks are located
every 512 Kbytes. Setting the OFS bit to “1” allows the accessed address to be offset by 4000016, so that
even the data overlapping a bank boundary can be accessed in succession.
In memory expansion mode where the PM13 bit is “1”, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them over with the OFS bit.
____
_______
Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 =“L”, CS0
_______
_____
____
and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept
_______
_______
“H” active and “L” active chip select signals, CS0 and CS2 should be decoded external to the chip.
8
D0 to D7
DQ0 to DQ7
AD0 to AD16
17
A0 to A16
A17
A19
AD17
AD18
CS1
CS2
CS3
RD
AD19
AD20
AD21
OE
CS0
CS
WR
DQ0 to DQ7
AD0 to AD16
OE
S2
(Note)
S1
W
Note: If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.
Figure 1.8.6. External Memory Connect Example in 4M Byte Mode
47
Under
development
ROM address
00000016
Microcomputer address
OFS bit of the DBR register=0
OFS bit of the DBR register=1
Memory expansion mode where PM13 =0
4000016
bank 0
bank 1
bank 2
bank 3
Output from the microcomputer pins
04000016
08000016
Bank
number
Access
area
4000016
bank 0
CS output
Address output
OFS
CS3 CS2 CS1
A
19
A18
A17
A16
A15–A0
BFFFF16
4000016
4000016
BFFFF16
0
0
0
0
0
0
0
1
0
1
0
000016
FFFF16
00000016
07FFFF16
04000016
0BFFFF16
08000016
0FFFFF16
0
1
0
1
0
1
0
1
2
BFFFF16
4000016
0
0
0
0
0
1
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
4000016
0C000016
10000016
14000016
0
0
1
0
1
0
0
000016
FFFF16
BFFFF16
4000016
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
BFFFF16
4000016
bank 1
000016
FFFF16
0C000016
13FFFF16
10000016
17FFFF16
14000016
1BFFFF16
1
0
1
BFFFF16
4000016
BFFFF16
4000016
BFFFF16
BFFFF16
4000016
000016
FFFF16
BFFFF16
4000016
000016
FFFF16
bank 2
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
0
1
18000016
1C000016
4000016
BFFFF16
4000016
BFFFF16
4000016
BFFFF16
000016
FFFF16
18000016
1FFFFF16
1C000016
23FFFF16
20000016
27FFFF16
0
1
0
BFFFF16
4000016
Data
3
4
5
000016
FFFF16
BFFFF16
4000016
bank 3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
000016
FFFF16
20000016
BFFFF16
4000016
4000016
BFFFF16
4000016
BFFFF16
4000016
BFFFF16
000016
FFFF16
24000016
2BFFFF16
28000016
2FFFFF16
2C000016
bank 4
bank 5
1
0
1
24000016
28000016
000016
FFFF16
BFFFF16
4000016
bank 4
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000016
FFFF16
33FFFF16
30000016
37FFFF16
34000016
3BFFFF16
38000016
BFFFF16
4000016
4000016
BFFFF16
4000016
BFFFF16
2C000016
30000016
000016
FFFF16
0
1
6
7
BFFFF16
4000016
000016
FFFF16
bank 5
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
000016
FFFF16
4000016
7FFFF16
BFFFF16
4000016
bank 6
bank 7
3BFFFF16
3C000016
3FFFFF16
3C000016
34000016
38000016
8000016
BFFFF16
000016
FFFF16
BFFFF16
4000016
bank 6
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
000016
FFFF16
C000016
CFFFF16
Program or data
Program or data
3CFFFF16
BFFFF16
D000016
DFFFF16
D000016
DFFFF16
Internal ROM access
3C000016
3FFFFF16
Internal ROM access
Internal ROM access
Internal ROM access
BFFFF16
Address input for 4-
Mbyte ROM
A21 A20 A19
A18 N.C. A17
A16 A15–A0
Address input for 4-Mbyte ROM
N.C.: No connected
Under
development
Memory expansion mode where PM13 =1
ROM address
00000016
Microcomputer address
OFS bit of the DBR register=0
OFS bit of the DBR register=1
Output from the microcomputer pins
Bank
number
Access
area
4000016
7FFFF16
CS output
Address output
OFS
bank 0
CS3 CS2 CS1
A
19
A
18
A17
A16
A15–A0
4000016
0
0
0
0
0
0
0
1
0
1
0
000016
FFFF16
00000016
03FFFF16
04000016
07FFFF16
08000016
0BFFFF16
4000016
bank 0
0
1
0
04000016
08000016
0
1
1
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
4000016
0
1
2
0
0
0
0
0
0
1
1
0
0
0
1
0
1
000016
FFFF16
7FFFF16
4000016
7FFFF16
bank 1
bank 2
0
0
0
0
1
1
0
0
1
1
0
1
0
1
000016
FFFF16
4000016
bank 1
0C000016
10000016
14000016
0
0
0
0
1
1
1
1
0
0
0
1
0
1
000016
FFFF16
0C000016
0FFFFF16
10000016
13FFFF16
14000016
17FFFF16
1
0
1
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
7FFFF16
4000016
7FFFF16
0
0
1
1
0
0
0
0
1
1
0
1
0
1
000016
FFFF16
0
0
1
1
0
0
1
1
0
0
0
1
0
1
000016
FFFF16
4000016
bank 2
4000016
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
0
0
1
1
1
1
0
0
1
1
0
1
0
1
000016
FFFF16
18000016
1BFFFF16
1C000016
1FFFFF16
20000016
23FFFF16
7FFFF16
0
1
0
4000016
7FFFF16
18000016
1C000016
3
4
5
bank 3
bank 4
bank 5
0
0
1
1
1
1
1
1
0
0
0
1
0
1
000016
FFFF16
Data
4000016
1
1
0
0
0
0
0
0
1
1
0
1
0
1
000016
FFFF16
bank 3
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
20000016
1
1
0
0
0
0
1
1
0
0
0
1
0
1
000016
FFFF16
24000016
27FFFF16
28000016
2BFFFF16
2C000016
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
000016
FFFF16
4000016
bank 4
24000016
28000016
1
1
0
0
1
1
1
1
0
0
0
1
0
1
000016
FFFF16
7FFFF16
4000016
7FFFF16
2FFFFF16
30000016
33FFFF16
34000016
37FFFF16
38000016
4000016
7FFFF16
4000016
7FFFF16
4000016
7FFFF16
1
1
1
1
0
0
0
0
1
1
0
1
0
1
000016
FFFF16
0
1
4000016
bank 5
2C000016
30000016
6
1
1
1
1
0
0
0
0
0
1
0
1
000016
FFFF16
1
1
7FFFF16
4000016
7FFFF16
0
0
1
1
1
1
1
1
1
1
0
1
0
1
000016
FFFF16
bank 6
bank 7
3BFFFF16
7
7
0
1
Internal ROM access
8000016
4000016
bank 6
34000016
38000016
Internal ROM access
3C000016
FFFFF16
4000016
1
1
1
1
1
1
0
0
0
1
0
1
000016
FFFF16
7FFFF16
1
1
7FFFF16
4000016
7FFFF16
3FFFFF16
Program or data
Program or data
Internal ROM access
8000016
FFFFF16
Internal ROM access
4000016
bank 7
7FFFF16
3C000016
3FFFFF16
A21 A20 A19
A18 N.C. A17
A16 A15–A0
Address input for 4-
Mbyte ROM
Address input for 4-Mbyte ROM
N.C.: No connected
Under
development
Microprocessor mode
ROM address
00000016
Microcomputer address
OFS bit of the DBR register=0
OFS bit of the DBR register=1
Output from the microcomputer pins
CS output Address output
CS3 CS2 CS1
Bank
number
Access
area
4000016
OFS
A
19
A
18
A
17
A16
A15–A0
bank 0
bank 1
bank 2
bank 3
4000016
BFFFF16
0
0
0
0
0
0
0
1
0
1
0
000016
FFFF16
00000016
07FFFF16
04000016
0BFFFF16
08000016
0FFFFF16
04000016
08000016
4000016
bank 0
0
1
0
1
0
1
BFFFF16
4000016
0
1
2
0
0
0
0
0
1
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
BFFFF16
4000016
0
0
0
0
1
1
0
1
1
0
0
1
0
1
000016
FFFF16
4000016
BFFFF16
0C000016
10000016
14000016
BFFFF16
4000016
4000016
BFFFF16
0
0
0
1
1
0
1
0
0
1
0
1
0
1
000016
FFFF16
0C000016
13FFFF16
10000016
17FFFF16
14000016
1BFFFF16
bank 1
1
0
1
BFFFF16
4000016
0
0
1
1
0
0
0
1
1
0
0
1
0
1
000016
FFFF16
4000016
BFFFF16
0
0
1
1
0
1
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
BFFFF16
4000016
bank 2
18000016
1C000016
4000016
BFFFF16
0
0
1
1
1
1
0
1
1
0
0
1
0
1
000016
FFFF16
18000016
1FFFFF16
1C000016
23FFFF16
20000016
27FFFF16
BFFFF16
4000016
Data
0
1
0
3
4
5
0
1
1
0
1
0
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
BFFFF16
4000016
bank 3
20000016
1
1
0
0
0
0
0
1
1
0
0
1
0
1
000016
FFFF16
4000016
BFFFF16
BFFFF16
4000016
bank 4
bank 5
24000016
28000016
4000016
BFFFF16
1
1
0
0
0
1
1
0
0
1
0
1
0
1
000016
FFFF16
24000016
2BFFFF16
28000016
2FFFFF16
2C000016
1
0
1
BFFFF16
4000016
bank 4
1
1
0
0
1
1
0
1
1
0
0
1
0
1
000016
FFFF16
4000016
BFFFF16
BFFFF16
4000016
2C000016
30000016
1
1
0
1
1
0
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
33FFFF16
30000016
37FFFF16
34000016
3BFFFF16
38000016
BFFFF16
4000016
bank 5
4000016
BFFFF16
1
1
1
1
0
0
0
1
1
0
0
1
0
1
000016
FFFF16
0
1
6
7
BFFFF16
4000016
bank 6
bank 7
1
1
1
1
0
1
1
0
0
1
0
1
0
1
000016
FFFF16
4000016
BFFFF16
34000016
38000016
BFFFF16
4000016
1
1
1
1
1
1
0
0
1
1
0
1
0
1
000016
FFFF16
bank 6
4000016
7FFFF16
Program or data
Program or data
3BFFFF16
3C000016
3FFFFF16
3C000016
3FFFFF16
BFFFF16
7FFFF16
C000016
8000016
BFFFF16
1
1
1
1
1
1
1
1
0
0
0
1
0
1
000016
FFFF16
0
3C000016
3FFFFF16
1
1
1
1
1
1
1
1
1
1
0
1
0
1
000016
FFFF16
FFFFF16
C000016
FFFFF16
A21 A20 A19
A18 N.C. A17
A16 A15–A0
Address input for 4-
Mbyte ROM
Address input for 4-Mbyte ROM
N.C.: No connected
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Clock Generation Circuit
The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) Ring oscillator (oscillation stop detect function)
(4) PLL frequency synthesizer
Table 1.9.1 lists the clock generation circuit specifications. Figure 1.9.1 shows the clock generation circuit.
Figures 1.9.2 to 1.9.6 show the clock-related registers.
Table 1.9.1. Clock Generation Circuit Specifications
Main clock
oscillation circuit
PLL frequency
synthesizer
Sub clock
oscillation circuit
Item
Ring oscillator
• CPU clock source •CPU clock source • CPU clock source
• CPU clock source
Use of clock
• Peripheral function • Timer A, B's clock • Peripheral function clock source • Peripheral function clock
clock source
source
• CPU and peripheral function
clock sources when the main
clock stops oscillating
source
10 to 24 MHz
Clock frequency 0 to 16 MHz
32.768 kHz
About 1 MHz
• Ceramic oscillator • Crystal oscillator
• Crystal oscillator
Usable oscillator
X
IN, XOUT
XCIN, XCOUT
Pins to connect
oscillator
Presence
Stopped
Presence
Oscillating
Presence
Stopped
Presence
Stopped
Oscillation stop,
restart function
Oscillator status
after reset
Externally derived clock can be input
Other
51
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
CM01–CM00=00
2
Sub-clock
generating circuit
I/O ports
PM01–PM00=00
2
, CM01–CM00=01
2
2
CLKOUT
PM01–PM00=00
2
, CM01–CM00=10
X
CIN
XCOUT
PM01–PM00=00
CM01–CM00=11
2,
2
fC32
1/32
CM04
f
1
2
PCLK0=1
PCLK0=0
Sub-clock
f
fC
f
8
Ring
oscillator
clock
Ring
oscillator
CM21
f
32
fAD
Oscillation
stop, re-
oscillation
detection
circuit
f
1SIO
PCLK1=1
PCLK1=0
f
2SIO
f
8SIO
CM10=1(stop mode)
S
R
Q
PLL
frequency
synthesizer
X
IN
XOUT
f
32SIO
e
b
c
CM07=0
a
d
PLL
CM21=1
CM21=0
Divider
clock
CPU clock
BCLK
Main
clock
1
0
fC
Main clock
generating circuit
CM11
CM07=1
CM05
CM02
S
R
Q
WAIT instruction
c
e
b
1/2
1/2
1/2
1/2
1/2
a
1/32
RESET
1/2
1/4
1/8
1/16
CM06=0
Software reset
NMI
CM17–CM16=11
2
CM06=1
2
CM06=0
CM17–CM16=10
Interrupt request level judgment output
d
CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
CM06=0
CM17–CM16=01
2
CM21, CM27 : CM2 register bits
CM06=0
CM17–CM16=00
2
Details of divider
Oscillation stop, re-oscillation detection circuit
Reset
generating
circuit
CM27
Pulse generation
circuit for clock
edge detection
and charge,
Oscillation stop
detection reset
0
1
Charge,
discharge
circuit
Main
clock
Oscillation stop,
re-oscillation
Oscillation stop,
re-oscillation
discharge control
detection signal
detection interrupt
generating circuit
CM21 switch signal
PLL frequency synthesizer
Programmable
counter
1/2
PLL clock
Voltage
control
oscillator
(VCO)
Charge
pump
Phase
comparator
Main clock
Internal low-
pass filter
Figure 1.9.1. Clock Generation Circuit
52
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
After reset
01001000
2
Bit symbol
CM00
Bit name
Function
RW
RW
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
CM01
CM02
RW
RW
RW
RW
RW
WAIT peripheral function
clock stop bit (Note 10)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
CM03
1 : HIGH
Port XC select bit
(Note 2)
0 : I/O port P86, P87
CM04
CM05
1 : XCIN-XCOUT generation function(Note 9)
Main clock stop bit
(Notes 3, 10, 12, 13)
0 : On
1 : Off (Note 4, Note5)
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
RW
RW
bit 0 (Notes 7, 13)
1 : Division by 8 mode
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock, PLL clock, or ring oscillator clock
1 : Sub-clock
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: The CM03 bit is set to “1” (high) when the CM04 bit is set to “0” (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode
is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to “1” (Sub-clock select) or the CM21 bit of CM2 register to “1” (Ring oscillator select) with the sub-clock
stably oscillating.
(2) Set the CM20 bit of CM2 register to “0” (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to “1” (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted.
Note 5: When CM05 bit is set to “1, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the CM06
bit is set to “1” (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to “1”. Also make sure ports P86 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to “1”, set the CM07 bit to “0”(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to “0” (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to “0”.
Note 13: If the CM05 bit is set to “1” (main clock turned off) in low speed mode, the CM06 bit is set to “1” (divide-by-8 mode) and the
CM15 bit is set to “1” (drive capability high). Avoid changing the CM06 bit in low power dissipation mode.
During ring oscillator mode, the CM06 and CM15 bits do not change even if the CM05 bit is set to “1”. During ring oscillator
low power dissipation mode, the divide-by-n value can be selected using the CM06 and CM17 to CM16 bits. To return to
high or middle speed mode, however, set the CM06 bit to “1” and the CM15 bit to “1” before selecting the desired mode.
Figure 1.9.2. CM0 Register
53
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
After reset
0
0
0
00100000
2
Bit symbol
CM10
Bit
Function
RW
RW
name
All clock stop control bit
0 : Clock on
(Notes 4, 6)
1 : All clocks off (stop mode)
System clock select bit 1
(Notes 6, 7)
CM11
0 : Main clock
1 : PLL clock (Note 5)
RW
Reserved bit
Must set to “0”
RW
RW
(b4-b2)
CM15
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
select bit (Note 2)
b7 b6
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
CM16
CM17
RW
RW
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit of CM2 register is
set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Note 5: After setting the PLC07 bit in PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
“1” (PLL clock).
Note 6: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is ring oscillator clock), writing to the CM10 bit
has no effect.
Note 7: Effective when CM07 bit is “0” and CM21 bit is “0” .
Figure 1.9.3. CM1 Register
54
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM2
Address
000C16
After reset
0 0
0X000000
2(Note 11)
Bit symbol
CM20
Bit name
Oscillation stop, re-
oscillation detection bit
(Notes 7, 9, 10, 11)
Function
RW
RW
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
0: Main clock or PLL clock (Ring
oscillator turned off)
1: Ring oscillator clock
System clock select bit 2
(Notes 2, 3, 6, 8, 11)
CM21
CM22
RW
RW
(Ring oscillator oscillating)
Oscillation stop, re-
oscillation detection flag
(Note 4)
0: Main clock stop, re-oscillation
not detected
1: Main clock stop, re-oscillation
detected
0: Main clock oscillating
1: Main clock turned off
X
IN monitor flag
RO
CM23
(Note 5)
Reserved bit
Must set to “0”
RW
(b5-b4)
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
(b6)
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(Note 11)
CM27
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to “1” (ring oscillator clock) if the main clock stop is detected.
Note 3: If the CM20 bit is “1” and the CM23 bit is “1” (main clock turned off), do not set the CM21 bit to “0”.
Note 4: This bit becomes “1” at main clock stop detection and main clock re-oscillation detection. When this bit
changes from “0” to “1”, there arise oscillation stop, re-oscillation detection interrupt. Use this register to
discriminate the causes for oscillation stop, re-oscillation detection interrupt and watchdog timer interrupt
in the interrupt processing program. By writing “0” in the program, this bit becomes “0”. (Even when “1” is
written in the program, no change is identified for the bit. Also, this bit is not set to “0” where there occur
oscillation stop, re-oscillation detection interrupt.) When the CM22 bit is “1”, no oscillation stop, re-
oscillation detection interrupt occur even if oscillation stop or re-oscillation is detected.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 6: Effective when the CM07 bit of CM0 register is “0”.
Note 7: When the PM21 bit of PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
effect.
Note 8: Where the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is “0” (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is “0”
under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to “1” (ring oscillator clock) inside the interrupt
routine.
Note 9: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to “1” (enable).
Note 10: Set the CM20 bit to “0” (disable) before setting the CM05 bit of CM0 register.
Note 11: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Figure 1.9.4. CM2 Register
55
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Peripheral clock select register (Note)
Symbol
PCLKR
Address
025E16
When reset
00000011
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0 0 0 0
Bit symbol
PCLK0
Bit name
Function
RW
RW
Timers A, B clock select bit
(Clock source for the
timers A, B, and the dead
time timer)
0 : f
1 : f
2
1
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
PCLK1
0 : f2SIO
1 : f1SIO
RW
RW
Reserved bit
Must set to “0”
(b7-b2)
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Processor mode register 2 (Note 1)
Symbol
PM2
Address
001E16
After reset
XXX00000
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0
Bit name
Function
RW
Bit symbol
PM20
Specifying wait when
accessing SFR at PLL
0 : 2 waits
1 : 1 wait
RW
RW
(Note 2)
operation
System clock protective
bit
PM21
PM22
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
(Note 3, Note 4)
WDT count source
protective bit
0 : CPU clock is used for the
watchdog timer count source
1 : Ring oscillator clock is used
for the watchdog timer count
source
RW
RW
(Note 3, Note 5)
Reserved bit
Must set to “0”
(b4-b3)
(b7-b5)
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is “0” (PLL turned off). Also, to select a 16 MHz or higher PLL
clock, set this bit to “0” (2 waits). Note that if the clock source for the CPU clock is to be changed from the PLL
clock to another, the PLC07 bit must be set to “0” before setting the PM20 bit.
Note 3: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 4: Setting the PM21 bit to “1” results in the following conditions:
• The BCLK is not halted by executing the WAIT instruction.
• Writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
CM11 bit of CM1 register (CPU clock source does not change)
CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits of PLC0 register (PLL frequency synthesizer settings do not change)
Note 5: Setting the PM22 bit to “1” results in the following conditions:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode or hold state.
Figure 1.9.5. PCLKR Register and PM2 Register
56
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
PLL control register 0 (Note 1, Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PLC0
Address
001C16
After reset
0001 X010
2
0 0
1
Bit
Bit name
Function
RW
RW
symbol
b2 b1b0
PLL multiplying factor
select bit (Note 3)
PLC00
0 0 0: Do not set
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1: Multiply by 6
1 0 0: Multiply by 8
1 0 1:
PLC01
PLC02
RW
RW
1 1 0:
1 1 1:
Do not set
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
(b3)
(b4)
RW
RW
Reserved bit
Reserved bit
Must set to “1”
Must set to “0”
(b6-b5)
0: PLL Off
1: PLL On
Operation enable bit
RW
PLC07
(Note 4)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the PM21 bit of PM2 register is “1” (clock modification disable), writing to this register has no effect.
Note 3: These three bits can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
cannot be modified.
Note 4: Before setting this bit to “1” , set the CM07 bit to “0” (main clock), set the CM17 to CM16 bits to “00
(main clock undivided mode), and set the CM06 bit to “0” (CM16 and CM17 bits enable).
2”
Figure 1.9.6. PLC0 Register
57
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
(1) Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as
the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured
by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a
feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the
amount of power consumed in the chip. The main clock oscillator circuit may also be configured by
feeding an externally generated clock to the XIN pin. Figure 1.9.7 shows the examples of main clock
connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or ring
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor. Note that if an externally generated clock is fed into
the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1”. If necessary, use an
external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.9.7. Examples of Main Clock Connection Circuit
58
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
(2) Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 1.9.8 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscilla-
tor circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 1.9.8. Examples of Sub Clock Connection Circuit
59
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
(3) Ring Oscillator Clock
This clock, approximately 1 MHz, is supplied by a ring oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (ring oscillator
clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer.
After reset, the ring oscillator clock is turned off. It is turned on by setting the CM21 bit of CM2 register to
“1” (ring oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in
place of the main clock. If the main clock stops oscillating when the CM20 bit of CM2 register is “1”
(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-
oscillation detection interrupt), the ring oscillator automatically starts operating, supplying the necessary
clock for the microcomputer.
(4) PLL Clock
The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the
clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL
frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is
used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
To enter wait or stop mode, set the CM11 bit to “0” (main clock for the CPU clock source) and then the
PLC07 bit of PLC0 register to “0” (PLL off) before entering that mode. Figure 1.9.9 shows the procedure
for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits PLC0 register
(However, 10 MHz ≤ PLL clock frequency ≤ 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 1.9.2 shows the example for setting PLL
clock frequencies.
Table 1.9.2. Example for Setting PLL Clock Frequencies
X
IN
PLC02
PLC01
PLC00
Multiplying factor
PLL clock
(MHz)(Note)
(MHz)
10
5
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
2
4
6
8
2
4
6
8
20
24
3.33
2.5
12
6
4
3
Note: 10MHz≤PLL clock frequency≤24MHz.
60
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “002”(main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled). (Note)
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz or higher PLL clock)
Set the PM20 bit to “0” (2-wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
Note : PLL operation mode can be entered from high speed mode.
Figure 1.9.9. Procedure to Use PLL Clock as CPU Clock Source
61
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or
the PLL clock.
If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “002” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, ring oscillator mode or low power
ring oscillator mode, or when the CM05 bit of CM0 register is set to “1” (main clock turned off) in low-
speed mode, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode).
(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or ring oscillator clock by
dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32
clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D
converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to
CM00 bits of CM0 register to select.
62
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
(1) Normal Operation Mode
Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
ring oscillator or ring oscillator low power dissipation mode. Nor can operation modes be changed directly
from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation
mode. Where the CPU clock source is changed from the ring oscillator to the main clock, change the
operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the
CM06 bit of CM0 register was set to “1”) in the ring oscillator mode.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• PLL Operation Mode
The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (ring oscillator turned off), and the ring oscillator clock is
used when the CM21 bit is set to “1” (ring oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B. fC32 is the only
peripheral function clock available when the CM21 bit is set to “0” (ring oscillator turned off). If the
CM21 bit is set to “1” (ring oscillator oscillating), then fC32 and the ring oscillator clock can be used.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
63
Preliminary Specifications Rev.1.0
Under
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
• Ring Oscillator Mode
The ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The ring
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32
can be used as the count source for timers A and B.
• Ring Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected
as in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function
clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. When the
operation mode is returned to the high and medium speed modes, set the CM06 bit to “1” (divided by
8 mode).
Table 1.9.3. Setting Clock Related Bit and Modes
CM2 register
CM1 register
CM11 CM17, CM16
CM0 register
Modes
CM21
CM07
CM06
CM05
CM04
PLL operation mode
High-speed mode
0
0
0
0
0
0
1
0
0
0
0
0
00
00
01
10
2
2
2
2
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Midium-
speed
mode
divided by 2
divided by 4
divided by 8
divided by 16
112
Low-speed mode
1
1
Low power dissipation mode
1(Note 1) 1(Note 1)
Ring
oscillator
mode
divided by 1
divided by 2
divided by 4
divided by 8
divided by 16
1
1
1
1
1
1
002
012
102
0
0
0
0
0
0
1
0
0
1
0
112
Ring oscillator low power
dissipation mode
(Note 2)
(Note 2)
Note 1: When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode.
(2) Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit of PM2 register is “1” (ring oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock, ring oscillator
clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
If the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for the
CPU clock source) and then the PLC07 bit to “0” (PLL turned off) before entering wait mode.
• Pin Status During Wait Mode
Table 1.9.4 lists pin status during wait mode
• Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-
ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
64
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Specifications in this manual are tentative and subject to change.
development
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral func-
tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked
by external signals can be used to exit wait mode.
Table 1.9.4. Pin Status During Wait Mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
A
0
to A19, D
0
to D15, CS0 to CS3,
Retains status before wait mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
“H”
HLDA,BCLK
“H”
ALE
“H”
I/O ports
Retains status before wait mode
Retains status before wait mode
Does not stop
CLKOUT
When fC selected
When f8, f32 selected
Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is main-
tained.
Table 1.9.5. Interrupts to Exit Wait Mode
Interrupt
CM02=0
CM02=1
NMI interrupt
Serial I/O interrupt
Can be used
Can be used
Can be used when operating
with internal or external clock
Can be used when operating
with external clock
key input interrupt
Can be used
Can be used
(Do not use)
A-D conversion
interrupt
Can be used in one-shot mode
or single sweep mode
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Table 1.9.5 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
65
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Specifications in this manual are tentative and subject to change.
development
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
(3) Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc1 and Vcc2 pins is VRAM or more,
the internal RAM is retained. When applying 2.7 or less voltage to Vcc1 and Vcc2 pins, make sure
Vcc1≥Vcc2≥VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is seleted)
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disable).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
• Pin Status in Stop Mode
Table 1.9.6 lists pin status during stop mode
• Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph-
eral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
If the CPU clock before entering stop mode was derived from the ring oscillator clock: ring oscillator
clock divide-by-8
66
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Table 1.9.6. Pin Status in Stop Mode
Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
A
0
to A19, D
0
to D15, CS0 to CS3,
Retains status before stop mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
“H”
HLDA, BCLK
“H”
“H”
ALE
I/O ports
Retains status before stop mode Retains status before stop mode
CLKOUT
When fc selected
When f8, f32 selected
“H”
Retains status before stop mode
67
Preliminary Specifications Rev.1.0
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Specifications in this manual are tentative and subject to change.
development
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Figure 1.9.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure
1.9.11 shows the state transition in normal operation mode.
Table 1.9.7 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
Reset
WAIT
instruction
(Note 3)
CPU operation stopped
All oscillators stopped
CM10=1
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
Interrupt
WAIT
CM07=0
instruction
(Note 3)
CM06=1
CM05=0
CM11=0
CM10=1
(Note 5)
High-speed, medium-
speed mode
Stop mode
Wait mode
Interrupt
CM10=1
CM10=1
When
Notes 1, 2
low power
dissipation
mode
When
low-
speed
mode
PLL operation
mode
WAIT
instruction
(Note 3)
Low-speed, low power
dissipation mode
Stop mode
Stop mode
Wait mode
Wait mode
Interrupt
Interrupt
CM10=1
WAIT
instruction
(Note 3)
Ring oscillator, Ring oscillator
dissipation mode
Interrupt
Interrupt
(Note 4)
Normal mode
Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
Note 3: When the PM21 bit = 0 (system clock protective function unused).
Note 4: The ring oscillator clock divided by 8 provides the CPU clock.
Note 5: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (ring oscillator turned off).
Figure 1.9.10. State Transition to Stop Mode and Wait Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Main clock oscillation
Ring oscillator clock
oscillation
Ring oscillator low power
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
PLL operation mode
PLC07=1
Middle-speed mode
(divide by 2)
Ring oscillator mode
dissipation mode
High-speed mode
(divide by 8)
CPU clock: f(XIN)/8
CM07=0
(divide by 16)
CM11=1
(Note 6)
CPU clock: f(PLL)
CPU clock
CPU clock
CM21=0
(Note 8)
CPU clock: f(XIN
)
CPU clock: f(XIN)/2
CM05=0
CPU clock: f(XIN)/4
CPU clock: f(XIN)/16
CM07=0
f(Ring)
f(Ring)
CM07=0
CM06=0
CM17=0
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=1
CM07=0
CM06=0
CM17=1
CM16=0
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM06=0
CM17=1
CM16=1
PLC07=0
CM11=0
CM05=1
(Note 1)
CM16=0
CM06=1
CM21=1
(Note 7)
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
Ring oscillator
low power
dissipation mode
PLL operation
mode
Ring oscillator
mode
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
Middle-speed mode
(divide by 2)
High-speed mode
PLC07=1
CM11=1
(Note 6)
(divide by 8)
(divide by 16)
CM21=0
(Note 8)
CPU clock
CPU clock
CPU clock: f(PLL)
CM07=0
CM05=0
CPU clock: f(XIN
)
CPU clock: f(XIN)/2
CM07=0
CPU clock: f(XIN)/4
CM07=0
CPU clock: f(XIN)/8
CM07=0
CPU clock: f(XIN)/16
CM07=0
f(Ring)
f(Ring)
CM07=0
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM06=0
CM06=0
CM06=0
CM06=0
CM17=1
CM16=0
CM06=0
CM17=1
CM16=1
CM17=0
PLC07=0
CM11=0
(Note 7)
CM17=0
CM16=0
CM17=0
CM16=1
CM16=0
CM06=1
CM21=1
CM05=1
(Note 1)
CM07=1
(Note 3)
CM07=0
(Note 2, Note 4)
Low-speed mode
Low-speed mode
CM21=0
CM21=1
CPU clock: f(XCIN
CM07=0
)
CPU clock: f(XCIN
)
CM07=0
CM05=1
(Note 1)
CM05=1
(Note 1)
CM05=0
CM05=0
Low power
dissipation mode
Low power dissipation mode
CM21=0
CM21=1
CPU clock: f(XCIN
)
CPU clock: f(XCIN
)
CM07=0
CM07=0
CM06=1
CM15=1
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Avoid making a transition when the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Switch clock after oscillation of main clock is sufficiently stable.
3: Switch clock after oscillation of sub-clock is sufficiently stable.
4: Change CM17 and CM16 before changing CM06.
5: Transit in accordance with arrow.
6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.
To select a 16 MHz or higher PLL clock, set the PM20 bit to “0” (SFR accessed with two wait states) before setting PLC07 to “1” (PLL operation).
7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to “0” (PLL turned off)
before setting the PM20 bit to “1” (SFR accessed with one wait state).
8: Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
Figure 1.9.11. State Transition in Normal Mode
69
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Table 1.9.7. Allowed Transition and Setting
State after transition
Ring oscillator
low power
dissipation mode
Ring oscillator
mode
PLL operation
mode
High-speed mode,
middle-speed mode
1
Low power
dissipation mode
Low-speed mode
Stop mode
1
1
Wait mode
High-speed mode,
middle-speed mode
7
3
1
(9)
(13)
(16)
--
(15)
--
--
--
--
(17)
See Table A
(8)
2
Low-speed mode
1, 6
(11)
1
(16)
--
--
--
(17)
(17)
--
Low power dissipation
1
(16)
2
--
(10)
--
--
--
mode
2
PLL operation mode
3
(12)
--
--
--
Ring oscillator mode
4
1
1
(14)
(11)
(16)
--
--
--
--
--
(17)
(17)
--
See Table A
(10)
Ring oscillator
low power dissipation
mode
1
(16)
--
--
--
See Table A
Stop mode
5
5
5
(18)
(18)
(18)
(18)
(18)
(18)
(18)
Wait mode
(18)
(18)
(18)
--
--: Cannot transit
Table 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode,
Ring Oscillator Mode, and Ring Oscillator Low Power Dissipation Mode
Table B. Setting and Operation
Setting
Sub clock oscillating
Sub clock turned off
Operation
Divided Divided
Divided
by 2
Divided
by 2
Divided
by 8
Divided
by 4
Divided
by 16
No
division
Divided
by 4
No
division
CM04 = 0
CM04 = 1
Sub clock turned off
(1)
(2)
by 8
by 16
(4)
(5)
(5)
(7)
(6)
(1)
--
--
--
--
--
--
--
--
No division
Divided by 2
Sub clock oscillating
(3)
(3)
(3)
(3)
(2)
--
(7)
(7)
(6)
(6)
(6)
(1)
--
CM06 = 0,
CM17 = 0 , CM16 = 0
CM06 = 0,
CM17 = 0 , CM16 = 1
CM06 = 0,
CM17 = 1 , CM16 = 0
CM06 = 0,
CM17 = 1 , CM16 = 1
(3)
CPU clock no division mode
(4)
(4)
(4)
--
--
(1)
--
--
--
Divided by 4
Divided by 8
Divided by 16
CPU clock division by 2 mode
CPU clock division by 4 mode
CPU clock division by 16 mode
CPU clock division by 8 mode
(4)
(5)
(5)
--
--
--
(1)
--
--
(7)
--
--
--
--
(1)
(6)
(6)
(6)
(6)
(5)
--
--
(4)
(5)
(5)
(7)
(7)
(7)
No division
Divided by 2
(6)
(2)
--
--
--
(3)
(3)
(3)
(3)
CM06 = 1
CM07 = 0
CM07 = 1
CM05 = 0
CM05 = 1
(7)
Divided by 4
Divided by 8
Divided by 16
--
(2)
--
--
--
(4)
(4)
(4)
Main clock, PLL clock,
or ring oscillator clock selected
--
--
(2)
--
--
(5)
(5)
(8)
--
--
--
(2)
(7)
Sub clock selected
(9)
--: Cannot transit
Main clock oscillating
Main clock turned off
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Notes:
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Ring oscillator clock oscillates and stops in low-speed mode and low power dissipation mode. In these mode,
the ring oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function
clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
PLC07 = 0,
CM11 = 0
PLC07 = 1,
CM11 = 1
Main clock selected
PLL clock selected
CM21 = 0
CM21 = 1
Main clock or PLL clock selected
Ring oscillator clock selected
Transition to stop mode
Transition to wait mode
Exit stop mode or wait mode
CM10 = 1
wait
Hardware interrupt
70
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
System Clock Protective Function
When the main clock is selected for the CPU clock source, this function disables the clock against modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit of CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for the
CPU clock source):
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is “1”.
71
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re-
oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit of CM2
register. Table 1.9.4 lists an specification overview of the oscillation stop and re-oscillation detect function.
Table 1.9.7. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item
Specification
Oscillation stop detectable clock and
frequency bandwidth
f(XIN) ≥ 2 MHz
Enabling condition for oscillation stop, Set CM20 bit to “1”(enable)
re-oscillation detection function
Operation at oscillation stop,
re-oscillation detection
•Reset occurs (when CM27 bit =0)
•Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1)
(1) Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)
Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to “SFR”,
“Reset”).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)
(2) Operation When CM27 bit = 0 (Oscillation Stop and Re-oscillation Detect Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The ring oscillator starts oscillation, and the ring oscillator clock becomes the CPU clock and clock
source for peripheral functions in place of the main clock.
• CM21 bit = 1 (ring oscillator clock for CPU clock source)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(ring oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from
the stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
72
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
How to Use Oscillation Stop and Re-oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-
rupt. If the re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an
interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and
peripheral function clock source in the program. Figure 1.9.12 shows the procedure for switching the
clock source from the ring oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-
comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-
abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-
tion detection interrupt request is generated. At the same time, the ring oscillator starts oscillating. In
this case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred,
the peripheral function clocks now are derived from the ring oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop , re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop , re-oscillation detection function dis-
abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.
Main clock switch
Inspect the CM23 bit
1(Main clock stop)
0(Main clock oscillation)
Do this check a number of times
The main clock is confirmed to be active a number of times.
Set the CM22 bit to 0 (main clock stop,
re-oscillation not detected).
Set the CM21 bit to 0
(main clock for the CPU clock source)(Note)
All of CM21-23 are the CM2 register bits
End
Note: If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation
mode after set to high-speed mode.
Figure 1.9.12. Procedure to Switch Clock Source From Ring Oscillator to Main Clock
73
Preliminary Specifications Rev.1.0
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Under
Mitsubishi microcomputers
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 1.10.1 shows the PRCR register. The following lists the registers protected
by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0 and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by PRC2 bit: PD9, S3C and S4C registers
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
After reset
XX000000
0
0
2
Bit symbol
PRC0
Bit name
Function
RW
RW
Enable write to CM0, CM1, CM2,
PLC0 and PCLKR registers
Protect bit 0
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0 and INVC1
registers
PRC1
Protect bit 1
RW
RW
0 : Write protected
1 : Write enabled
Enable write to PD9, S3C and
S4C registers
PRC2
PRC3
Protect bit 2
Protect bit 3
Reserved bit
0 : Write protected
1 : Write enabled
Enable write to VCR2 and D4INT
registers
RW
RW
0 : Write protected
1 : Write enabled
Must set to “0”
(b5-b4)
(b7-b6)
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.
Figure 1.10.1. PRCR Register
74
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts
Type of Interrupts
Figure 1.11.1 shows types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
(Non-maskable interrupt)
INT instruction
Interrupt
_______
NMI
________
DBC (Note 2)
Special
Watchdog timer
Single step (Note 2)
Address match
(Non-maskable interrupt)
Hardware
Peripheral function (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 1.11.1. Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable I0nterrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
75
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
76
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
_______
• NMI Interrupt
_______
_______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______
about the NMI interrupt, refer to the section "NMI interrupt".
________
• DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
• Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop detection function, refer to the section "clock generating circuit".
• Power Supply Down Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the
section "voltage detection circuit".
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or
AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt en-
abled). For details about the address match interrupt, refer to the section "address match interrupt".
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 1.11.2. For details
about the peripheral functions, refer to the description of each peripheral function in this manual.
77
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Interrupts
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 1.11.2 shows the interrupt vector.
MSB
LSB
Low address
Mid address
Vector address (L)
Vector address (H)
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.11.2. Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.11.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to the section "flash memory
rewrite disabling function".
Table 1.11.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Address (L) to address (H)
Remarks
Reference
Undefined instruction FFFDC16 to FFFDF16
Interrupt on UND instruction
M16C/60, M16C/20
serise software
maual
Overflow
FFFE016 to FFFE316
FFFE416 to FFFE716
Interrupt on INTO instruction
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
BRK instruction
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Address match interrupt
Single step (Note)
Watchdog timer
Watchdog timer
Oscillation stop and
re-oscillation detection
Power supply down
Clock generating circuit
Voltage detection circuit
detection
________
DBC (Note)
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
_______
_______
NMI
NMI interrupt
Reset
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 1.11.2 lists the relocatable vector tables. Setting an even address in the INTB regis-
ter results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 1.11.2. Relocatable Vector Tables
Vector address (Note 1)
Address (L) to address (H)
Software interrupt
number
Reference
Interrupt source
(Note 5)
+0 to +3 (000016 to 000316)
M16C/60, M16C/20
series software
manual
BRK instruction
0
1 to 3
4
(Reserved)
+16 to +19 (001016 to 001316)
+20 to +23 (001416 to 001716)
INT interrupt
Timer
INT3
5
Timer B5
(Note 4)
6
7
+24 to +27 (001816 to 001B16)
+28 to +31 (001C16 to 001F16)
+32 to +35 (002016 to 002316)
Timer B4, UART1 bus collision detect
(Note 4)
Timer
Serial I/O
Timer B3, UART0 bus collision detect
(Note 2)
8
SI/O4, INT5
INT interrupt
Serial I/O
SI/O3, INT4 (Note 2)
UART 2 bus collision detection
DMA0
9
+36 to +39 (002416 to 002716)
+40 to +43 (002816 to 002B16)
10
11
Serial I/O
DMAC
+44 to +47 (002C16 to 002F16)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+48 to +51 (003016 to 003316)
+52 to +55 (003416 to 003716)
DMA1
Key input interrupt
A-D convertor
Key input interrupt
A-D
+56 to +59 (003816 to 003B16)
+60 to +63 (003C16 to 003F16)
+64 to +67 (004016 to 004316)
+68 to +71 (004416 to 004716)
+72 to +75 (004816 to 004B16)
+76 to +79 (004C16 to 004F16)
+80 to +83 (005016 to 005316)
+84 to +87 (005416 to 005716)
+88 to +91 (005816 to 005B16)
+92 to +95 (005C16 to 005F16)
+96 to +99 (006016 to 006316)
+100 to +103 (006416 to 006716)
+104 to +107 (006816 to 006B16)
+108 to +111 (006C16 to 006F16)
UART2 transmit, NACK2 (Note 3)
UART2 receive, ACK2 (Note 3)
(Note 3)
UART0 transmit, NACK0
Serial I/O
(Note 3)
UART0 receive, ACK0
UART1 transmit, NACK1(Note 3)
(Note 3)
UART1 receive, ACK1
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer
+112 to +115 (007016 to 007316)
+116 to +119 (007416 to 007716)
+120 to +123 (007816 to 007B16)
INT0
INT1
INT interrupt
+124 to +127 (007C16 to 007F16)
+128 to +131 (008016 to 008316)
INT2
32
to
M16C/60, M16C/20
series software
manual
to
Software interrupt
(Note 5)
63
+252 to +255 (00FC16 to 00FF16)
Note 1: Address relative to address in INTB.
Note 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Note 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Note 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Note 5: These interrupts cannot be disabled using the I flag.
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Interrupts
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable
the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 1.11.3 shows the interrupt control registers.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt control register (Note 2)
Symbol
TB5IC
TB4IC/U1BCNIC (Note 3)
TB3IC/U0BCNIC (Note 3)
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Address
004516
004616
004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
After reset
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
RW
RW
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(b7-b4)
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: Use the IFSR2A register to select.
Symbol
Address
004416
004816
004916
After reset
INT3IC (Note 4)
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
XX00X000
XX00X000
XX00X000
2
b7 b6 b5 b4 b3 b2 b1 b0
2
2
2
0
005D16 to 005F16 XX00X000
Bit symbol
ILVL0
Bit name
Function
RW
RW
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
RW
RW
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
RW
(Note 1)
POL
0 : Selects falling edge (Notes 3, 5)
1 : Selects rising edge
RW
RW
Reserved bit
Must always be set to “0”
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
RW
(b7-b6)
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0 "(falling
edge).
Note 4: During memory expansion and microprocessor modes, set the INT3IC register’s ILVL2 to ILVL0 bits to ‘000
(interrupt disabled).
2’
Note 5: Set the S3IC or S4IC register’s POL bit to "0" (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 1.11.3. Interrupt Control Registers
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Interrupts
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = “1”
· IR bit = “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 1.11.4. Interrupt Priority Levels
Enabled by IPL
Table 1.11.3. Settings of Interrupt Priority
Levels
Interrupt priority
level
Priority
order
ILVL2 to ILVL0 bits
IPL
Enabled interrupt priority levels
000
001
010
011
100
101
110
111
2
Level 0 (interrupt disabled)
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
000
001
010
011
100
101
110
111
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 1.11.4 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not re-
quested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
(Note 1)
temporary register
.
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(Note 1)
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address bus
Data bus
Address
000016
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
RD
Indeterminate
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the
instruction queue buffer is ready to accept instructions.
Figure 1.11.4. Time Required for Executing Interrupt Sequence
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Interrupts
Interrupt Response Time
Figure 1.11.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 1.11.5) and a time during which the interrupt
sequence is executed ((b) in Figure 1.11.5).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value 16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd
Even
Odd
18 cycles
19 cycles
19 cycles
20 cycles
20 cycles
20 cycles
20 cycles
20 cycles
Even
Odd
Odd
Figure 1.11.5. Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 1.11.5 is set in the IPL. Shown in Table 1.11.5 are the IPL values of software and special
interrupts when they are accepted.
Table 1.11.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Level that is set to IPL
_______
Watchdog timer, NMI
7
_________
Not changed
Software, address match, DBC, single-step
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
1.11.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Stack
Address
MSB
Address
MSB
LSB
LSB
[SP]
New SP value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
PC
L
PC
M
FLG
L
FLG
H
PCH
[SP]
SPvalue before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.11.6. Stack StatusBefore and After Acceptance of Interrupt Request
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
(Note)
(Note)
SP
, at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 1.11.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Sequence in which order
registers are saved
Address
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
PC
L
(2) Saved simultaneously,
all 16 bits
PCM
FLG
L
(1) Saved simultaneously,
all 16 bits
FLG
H
PCH
[SP]
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
PC
L
(3)
PCM
(4)
Saved, 8 bits at a time
FLG
L
(1)
(2)
FLG
H
PCH
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.11.7. Operation of Saving Register
86
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt re-
quest.
Return the other registers saved by a program within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.11.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > WDT > Peripheral function > Single step > Address match
Figure 1.11.8. Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 1.11.9 shows the circuit that judges the interrupt priority level.
87
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Priority level of each interrupt
Level 0 (initial value)
INT1
High
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3, UART0 bus collision
Timer B5
UART1 reception, ACK1
UART0 reception, ACK0
Priority of peripheral fucntion interrupts
(if priority levels are same)
UART2 reception, ACK2
A-D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmissionm, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
Low
SI/O3, INT4
IPL
Interrupt request level resolution output
to clock generating circuit (Fig.1.11.1)
I flag
Interrupt
request
accepted
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Power supply down detection
DBC
NMI
Figure 1.11.9. Interrupts Priority Select Circuit
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Specifications in this manual are tentative and subject to change.
development
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
______
INT Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
_______
_______
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
_______
_______
_______
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the
_______
IFSR register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested)
before enabling the interrupt.
Figure 1.11.10 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
RW
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
(Note 1)
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
RW
RW
RW
RW
(Note 1)
(Note 1)
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
0 : SI/O3
1 : INT4
(Note 3)
select bit
(Note 2)
Interrupt request cause
select bit
0 : SI/O4
1 : INT5
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: During memory expansion and microprocessor modes, set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035E16
After reset
00XXXXXX
2
Bit symbol
Bit name
Function
RW
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
(b5-b0)
IFSR26
0 : Timer B3
Interrupt request cause
select bit
1 : UART0 bus collision
detection
RW
RW
IFSR27
0 : Timer B4
1 : UART1 bus collision
detection
Interrupt request cause
select bit
Figure 1.11.10. IFSR Register and IFSR2A Register
89
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
______
NMI Interrupt
_______
_______
______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt
is a non-maskable interrupt.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
This pin cannot be used as an input port.
Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be
used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure
1.11.11 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which
has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port
are not detected as interrupts.
PUR2 register's PU25 bit
Pull-up
transistor
KUPIC register
PD10 register's
PD10_7 bit
PD10 register's PD10_7 bit
KI
3
PD10 register's
PD10_6 bit
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
KI
2
Pull-up
transistor
PD10 register's
PD10_5 bit
KI
1
PD10 register's
PD10_4 bit
Pull-up
transistor
KI
0
Figure 1.11.11. Key Input Interrupt
90
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indi-
cated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use
the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits to enable or
disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address
match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction
being executed. Figure 1.11.12 shows the instruction just before execution and address stored in the stack
when there occurs interruption.
Note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for
external area.
Figure 1.11.13 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
(1) Instructions in which the "return destination + 2" address is stored in the stack when address match
interrupt occurs
• 16-bit operation code
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
OR.B:S
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
SUB.B:S
MOV.B:S
#IMM8,dest
#IMM8,dest
AND.B:S
STZ.B:S
#IMM8,dest
#IMM8,dest
STNZ.B:S
CMP.B:S
JMPS
STZX.B:S #IMM81,#IMM82,dest
PUSHM
JSRS
src
POPM dest
#IMM8
MOV.B:S
#IMM,dest (However, dest = A0 or A1)
(2) Instructions in which the "return destination + 1" address is stored in the stack when address match
interrupt occurs
• Instructions other than the above
Figure 1.11.12. Instruction Just Before Execution and Address Stored in Stack When There
Occurs Interrupts
Table 1.11.6. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0
Address match interrupt 1
Address match interrupt 2
Address match interrupt 3
AIER0
AIER1
AIER20
AIER21
RMAD0
RMAD1
RMAD2
RMAD3
91
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
After reset
XXXXXX002
Bit symbol
AIER0
Bit name
Function
RW
Address match interrupt 0
enable bit
0 : Interrupt disabled
RW
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
RW
1 : Interrupt enabled
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
(b7-b2)
Address match interrupt enable register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER2
Address
01BB16
After reset
XXXXXX002
Bit symbol
AIER20
Bit name
Function
RW
RW
Address match interrupt 2
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER21
(b7-b2)
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
After reset
b0
001216 to 001016
001616 to 001416
01BA16 to 01B816
01BE16 to 01BC16
X0000016
X0000016
X0000016
X0000016
Function
Setting range
0000016 to FFFFF16
RW
RW
Address setting register for address match interrupt
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 1.11.13. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
92
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Precautions for Interrupts
(1) Reading Address 0000016
• Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or
an unexpected interrupt is generated.
(2) SP Setting
• Set any value in the SP before accepting an interrupt. The SP is cleared to ‘000016’ after reset. There-
fore, if an interrupt is accepted before setting any value in the SP, the program may go out of control.
_______
Especially when using NMI interrupt, set a value in the SP at the beginning of the program. For the first
_______
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
(3) _N__M___I_ Interrupt
_______
_______
• The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
_______
• The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5 bit
_______
can only be read when determining the pin level after an NMI interrupt is generated.
_______
• Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
_______
NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
_______
_______
• Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
_______
• The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.
_____
(4) INT Interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to the INT0
________
through INT5 pins regardless of the CPU clock.
________
________
• When the polarity of the INT0 to INT5 pins is changed, the IR bit is sometimes set to “1” (=interrupt
requested). After changing the polarity, set the IR bit to “0” (=interrupt not requested). Figure 1.11.13
______
shows the procedure for changing the INT interrupt generate factor.
Set the I flag to “0” (=disable interrupt)
Set the ILVL2 to ILVL0 bits to '0002' (= level 0)
(Disable INT interrupt)
Set the POL bit
Set the IR bit to “0” (=interrupt not requested)
Set the ILVL2 to ILVL0 bits to
'0012' (=level 1) to '1112' (=level 7)
(Enable the accepting of INT interrupt request)
Set the I flag to “1” (= enable interrupt)
Note: Execute the setting above individually. Do not execute two or
more settings at once (by one instruction).
______
Figure 1.11.14. Switching Procedure for INT Interrupt Request
93
Preliminary Specifications Rev.1.0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
(5) Watchdog Timer Interrupt
• Initialize the watchdog timer after the watchdog timer interrupt occurs.
(6) Modifying Interrupt Control Register
• Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to occur,
disable the interrupts before modifying the register. A sample program is shown below.
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
POPC FLG ; Enable interrupts.
Why the FSET I instruction is preceded by two NOP instructions (four when using HOLD function) in
Example 1 and why the FSET I instruction is preceded by a dummy read in Example 2
This is to prevent the I flag from being set to “1” before writing to the interrupt control register for reasons
of the instruction queue buffer.
To modify any interrupt control register after disabling interrupts, be careful with the instructions used.
Modifying other than the IR bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to “1” (= interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
Modifying the IR bit
Even when the IR bit is cleared to “0” (= interrupt not requested), it may not actually be cleared to “0”
depending on the instruction used. Therefore, use the MOV instruction to clear the IR bit.
94
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Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot be
set to “0” (watchdog timer interrupt) in a program.
The pin, CPU and SFR initialized where the monitor timer underflows when the PM12 bit is “1” are the same
as in software reset.
When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be
16 or 128. If a sub-clock is selected for CPU clock, the divide-by-N value for the prescaler is always 2 no
matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period
of watchdog timer is, however, subject to an error due to the prescaler.
With main clock chosen for CPU clock
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
With sub-clock chosen for CPU clock
Prescaler dividing (2) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is re-
sumed from the held value when the modes or state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
• Count source protective mode
In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit of PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit of PM2 register to “1” (ring oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
95
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Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting the PM22 bit to “1” results in the following conditions
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count
source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode or hold state.
Prescaler
CM07 = 0
WDC7 = 0
1/16
PM12 = 0
CM07 = 0
WDC7 = 1
Watchdog timer
interrupt request
CPU
clock
PM22 = 0
PM22 = 1
1/128
1/2
HOLD
Watchdog timer
CM07 = 1
PM12 = 1
Reset
Ring oscillator clock
Set to
“7FFF16”
Write to WDTS register
RESET
Figure 1.12.1. Watchdog Timer Block Diagram
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16 00XXXXXX
After reset
(Note2)
0
2
Bit symbol
Bit name
High-order bit of watchdog timer
Cold start / warm start 0 : Cold start
Function
RW
RO
(b4-b0)
WDC5
RW
RW
discrimination flag (Note 1) 1 : Warm start
Reserved bit
Must set to “0”
(b6)
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Note 1: The WDC5 bit is always “1” (warm start) no matter how it is set by writing a “0” or “1”.
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set
to “0” when the input voltage at the VCC1 pin drops to Vdet
is set to “1” (RAM retention limit detection circuit enable).
2
or less while the VC25 bit in the VCR2 register
Watchdog timer start register (Note)
b7
b0
Symbol
WDTS
Address
000E16
After reset
Indeterminate
RW
WO
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 1.12.2. WDC Register and WDTS Register
96
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 1.13.1 shows the block diagram of the DMAC. Table 1.13.1
shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416
)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 002916, 002816
)
)
DMA0 transfer counter TCR0 (16)
(addresses 003616 to 003416
)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.13.1. DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0–1)’s DSR bit, as well as by an interrupt
request which is generated by any function specified by the DMiSL register’s DMS and DSEL3–DSEL0 bits.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the
interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be
accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,
the interrupt control register’s IR bit does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =
“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.
97
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Under
Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Table 1.13.1. DMAC Specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
DMA request factors
(Note 1, Note 2)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
________ ________
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority
Transfer unit
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer address direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode •Single transfer Transfer is completed when the DMAi transfer counter (i = 0–1)
underflows after reaching the terminal count.
•Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
DMA shutdown •Single transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
•Repeat transfer When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (en
Reload timing for forward ad-
dress pointer and transfer
counter
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016–003F16) are accessed by the DMAC.
98
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 request cause select register
Symbol
DM0SL
Address
03B816
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
DSEL0
Function
Bit name
RW
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
RW
RW
DSEL3
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b5-b4)
DMS
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
Software DMA
request bit
DSR
DSEL3 to DSEL0 bits are “0001
2”
(software trigger).
The value of this bit when read is “0” .
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
–
–
–
–
–
–
Two edges of INT0 pin
Timer B3
Timer B4
Timer B5
–
–
–
–
–
–
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A-D conversion
UART1 transmit
Figure 1.13.2. DM0SL Register
99
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA1 request cause select register
Symbol
DM1SL
Address
03BA16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
Bit symbol
DSEL0
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
RW
RW
DSEL3
(b5-b4)
DMS
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSR
DSEL3 to DSEL0 bits are “0001
(software trigger).
2”
The value of this bit when read is “0” .
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
–
–
–
–
–
SI/O3
SI/O4
Two edges of INT1
–
–
–
–
–
–
–
–
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A-D conversion
UART1 receive/ACK1
DMAi control register(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
After reset
00000X00
00000X00
2
2
Bit symbol
Bit name
Function
RW
RW
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
RW
(Note 1)
0 : DMA not requested
1 : DMA requested
DMA request bit
DMA enable bit
0 : Disabled
1 : Enabled
RW
RW
RW
Source address direction
select bit (Note 2)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 2)
0 : Fixed
1 : Forward
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
(b7-b6)
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 1.13.3. DM1SL Register, DM0CON Register, and DM1CON Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAi source pointer (i = 0, 1) (Note)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
Function
Set the source address of transfer
RW
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
RW
Function
Set the destination address of transfer
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
After reset
Indeterminate
Indeterminate
Function
RW
Setting range
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
000016 to FFFF16
RW
Figure 1.13.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
1. Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory extension and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-
bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
_______
(d) Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area
________
________
are affected by the RDY signal. Refer to “RDY signal”.
Figure 1.13.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units using an 8-bit bus ((2) in Figure 1.13.5), two source read bus cycles and two destination write bus
cycles are required.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
CPU use
Destination
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Dummy
cycle
Address
bus
Destination
Source
CPU use
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
CPU use
Source
Source + 1
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Transfer Cycles for Source Read
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMA transfer cycles. Table 1.13.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.13.2. DMA Transfer Cycles
Single-chip mode
Memory expansion mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
(BYTE= “L”)
8-bit
Even
Odd
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
8-bit transfers
(DMBIT= “1”)
Even
Odd
—
—
1
—
—
1
(BYTE = “H”)
16-bit
Even
Odd
16-bit transfers
(DMBIT= “0”)
(BYTE = “L”)
8-bit
2
2
Even
Odd
—
—
—
—
(BYTE = “H”)
Table 1.13.3. Coefficient j, k
Internal area
External area
Internal ROM, RAM
No wait With wait
SFR
Separate bus
Multiplex bus
2
2
1
1
1-wait
2-wait
With wait
With wait
2 waits 3 waits
No wait
1 wait
2 waits
3 waits
1wait
j
1
1
2
2
2
2
3
3
1
2
2
2
3
3
4
4
3
3
3
3
4
4
k
Notes:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in PM2 register.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
3. DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
4. DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 1.13.4 shows the
timing at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 1.13.4. Timing at Which the DMAS Bit Changes State
DMAS bit of the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
• Immediately before a data transfer starts
• When set by writing “0” in a program
Software trigger
When the DSR bit of DMiCON
register is set to “1”
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiCON register
has its IR bit set to “1”
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 1.13.6 shows an example of DMA transfer effected by external factors.
In Figure 1.13.6, because DMA0 and DMA1 requests occurred at the same time, DMA0 which has higher
channel priority is accepted first and a DMA transfer on it starts. When DMA0 finishes one transfer unit, it
relinquishes control of the bus to the CPU, and when the CPU finishes one bus access, DMA1 starts a
transfer next and after completion of one transfer unit, returns control of the bus to the CPU.
Note that because there is only one DMAS bit on each channel, the number of times DMA is requested
cannot be counted. Therefore, even if multiple DMA requests occurred before gaining control of the bus
as in the case of DMA1 in Figure 1.13.6, the DMAS bit is set to “0” when control of the bus is gained and
after completion of one transfer unit, control of the bus is returned to the CPU.
An example where DMA requests for external causes are detected active at the same
BCLK
DMA0
Obtainment
of the bus
right
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.13.6. DMA Transfer by External Factors
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Timers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function
as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 1.14.1 and 1.14.2 show block diagrams of timer A and
timer B configuration, respectively.
f
2
PCLK0 bit = 0
PCLK0 bit = 1
Clock prescaler
1/2
1/8
• Main clock
• PLL clock
• Ring oscillator
clock
f
1 or f2
f1
f
C32
1/32
X
CIN
Reset
f
8
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
f
32
1/4
f8 f32 fC32
f
1 or f2
• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4
Noise
filter
• Event counter mode
Timer B2 overflow or underflow
Note: Be aware that TA0IN shares the pin with RxD2 and TB5IN.
Figure 1.14.1. Timer A Configuration
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Timers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
f
2
PCLK0 bit = 0
PCLK0 bit = 1
Clock prescaler
1/32
Reset
1/2
1/8
• Main clock
f
1 or f2
f1
fC32
• PLL clock
• Ring oscillator
clock
X
CIN
f
8
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
f
32
1/4
f1 or f2
f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B0 interrupt
Noise
filter
Timer B0
TB0IN
TB1IN
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B1 interrupt
Timer B2 interrupt
Noise
filter
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB2IN
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B3 interrupt
Noise
filter
TB3IN
TB4IN
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B4 interrupt
Timer B5 interrupt
Noise
filter
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note: Be aware that TB5IN shares the pin with RxD2 and TA0IN.
Figure 1.14.2. Timer B Configuration
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Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.14.3 shows a block diagram of the timer A. Figures 1.14.4 to 1.14.6 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1 or f2
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f32
Reload register
f
C32
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 4)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Addresses
TAj
TAk
Timer A4 Timer A1
Timer A0 Timer A2
(Note)
TB2 overflow
(Note)
TAj overflow
Timer A0 038716 038616
Timer A1 038916 038816
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
To external
trigger circuit
Down count
(j = i – 1. Note, however, that j = 4 when i = 0)
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note: Overflow or underflow
Figure 1.14.3. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
TMOD0
Bit name
Operation mode select bit
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TMOD1
RW
RW
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each
operation mode
RW
RW
RW
RW
RW
Count source select bit
Function varies with each
operation mode
Figure 1.14.4. TA0MR to TA4MR Registers
109
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (i= 0 to 4) (Note 1)
Symbol
TA0
TA1
Address
038716, 038616
038916, 038816
After reset
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
TA2
TA3
TA4
038B16, 038A16
038D16, 038C16
038F16, 038E16
Indeterminate
Indeterminate
Indeterminate
Function
RW
RW
Mode
Timer
mode
Setting range
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
Event
counter
mode
Divide the count source by FFFF16 – n + 1
where n = set value when counting up or
by n + 1 when counting down
000016 to FFFF16
RW
WO
(Note 5)
One-shot
Divide the count source by n where n = set 000016 to FFFF16
timer mode value and cause the timer to stop
(Notes 2, 4)
Modify the pulse width as follows:
PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
where n = set value, fj = count source
frequency
Pulse width
modulation
mode
000016 to FFFE16
(Note 3, 4)
WO
WO
(16-bit PWM)
Pulse width
modulation
mode
0016 to FE16
Modify the pulse width as follows:
PWM period: (28 – 1) x (m + 1)/ fj
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
(High-order address)
0016 to FF16
(Low-order address)
(8-bit PWM)
(Note 3, 4)
Note 1: The register must be accessed in 16 bit units.
Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
0 : Stops counting
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
Up/down flag (Note 1)
Symbol
UDF
Address
038416
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
Bit name
Function
RW
RW
Timer A0 up/down flag
0 : Down count
1 : Up count
RW
RW
RW
RW
Timer A1 up/down flag
Timer A2 up/down flag
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
Timer A3 up/down flag
Timer A4 up/down flag
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA2P
TA3P
TA4P
WO
WO
WO
Timer A3 two-phase pulse
signal processing select bit
(Notes 2, 3)
Timer A4 two-phase pulse
signal processing select bit
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA4I
to “0” (input mode).
N
and TA2OUT to TA4OUT pins are set
Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit
to “0”.
Figure 1.14.5. TA0 to TA4 Registers, TABSR Register, and UDF Register
110
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
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Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
Symbol
ONSF
Address
038216
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits of TAiMR register (i =
2’ (= one-shot timer
mode) and the MR2 bit of TAiMR
RW
RW
0 to 4) = ‘10
register = “0” (=TAiOS bit enabled). RW
When read, its content is “0”.
RW
0 : Z-phase input disabled
RW
TA4OS
Z-phase input enable bit
1 : Z-phase input enabled
b7 b6
TA0TGL
Timer A0 event/trigger
select bit
RW
(Note 1)
0 0 : Input on TA0IN is selected
(Note 2)
(Note 2)
(Note 2)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
TA0TGH
RW
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
Trigger select register
Symbol
TRGSR
Address
038316
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
RW
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note 1) RW
0 1 : TB2 overflow is selected(Note 2)
(Note 2)
(Note 2)
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
RW
b3 b2
Timer A2 event/trigger
select bit
RW
0 0 : Input on TA2IN is selected (Note 1)
(Note 2)
(Note 2)
(Note 2)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
RW
RW
RW
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note 1)
(Note 2)
(Note 2)
(Note 2)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
RW
RW
0 0 : Input on TA4IN is selected (Note 1)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected(Note 2)
1 1 : TA0 overflow is selected(Note 2)
(Note 2)
Note 1: Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
Note 2: Overflow or underflow
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
2
RW
RW
Bit symbol
Bit name
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
Function
(b6-b0)
CPSR
Setting this bit to “1” initializes the
prescaler for the timekeeping clock. (
When read, its content is “0”.)
Clock prescaler reset flag
Figure 1.14.6. ONSF Register, TRGSR Register, and CPSRF Register
111
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.14.1). Figure 1.14.7
shows TAiMR register in timer mode.
Table 1.14.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio
1/(n+1) n: set value of TAiMR register (i= 0 to 4)
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
000016 to FFFF16
Count start condition
Count stop condition
Interrupt request generation timing Timer underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function
• Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 0
Bit symbol
Bit name
Function
RW
RW
RW
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
RW
Gate function select bit
MR1
MR2
0 0 : Gate function not available
}
RW
RW
0 1 :
(TAiIN pin functions as I/O port)
1 0 : Counts while input on the TAiIN pin
is low (Note 2)
1 1 : Counts while input on the TAiIN pin
is high (Note 2)
RW
RW
MR3
Must be set to “0” in timer mode
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
or f2
0 1 : f
1 0 : f32
1 1 : fC32
TCK1
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 1.14.7. Timer Ai Mode Register in Timer Mode
112
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
development
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Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 1.14.2 lists specifica-
tions in event counter mode (when not processing two-phase pulse signal). Table 1.14.3 lists specifica-
tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 1.14.8 shows TAiMR register in event counter mode (when not processing two-phase pulse sig-
nal). Figure 1.14.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-
phase pulse signal with the timers A2, A3 and A4).
Table 1.14.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Count operation
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or count source input
I/O port, pulse output, or up/down-count select input
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Free-run count function
Select function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
113
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 1
Bit symbol
Bit name
Function
RW
b1 b0
TMOD0
TMOD1
MR0
RW
RW
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 2)
Pulse output function
select bit
RW
RW
(TAiOUT pin functions as pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (Note 4)
RW
RW
RW
MR3
Must be set to “0” in event counter mode
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR
registers.
Note 2: TA0OUT pin is N-channel open drain output.
Note 3: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Figure 1.14.8. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
114
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.14.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading timer A2, A3 or A4 register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Up-
count
Up-
count
Up-
count count
Down- Down- Down-
count count
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count down all edges
Count up all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
115
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
Symbol
TA2MR to TA4MR
Address
039816 to 039A16
After reset
0016
b6 b5 b4 b3 b2 b1 b0
0
1 0 0 0 1
RW
Bit name
Operation mode select bit
Function
0 1 : Event counter mode
b1 b0
TMOD0
TMOD1
RW
RW
MR0
MR1
MR2
To use two-phase pulse signal processing, set this bit to “0”.
RW
RW
RW
RW
RW
To use two-phase pulse signal processing, set this bit to “0”.
To use two-phase pulse signal processing, set this bit to “1”.
MR3
To use two-phase pulse signal processing, set this bit to “0”.
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse signal
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiGH and TAiGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 1.14.9. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
116
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
_______
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 1.14.10
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
(Note)
INT2
(Z phase)
Input equal to or greater than one clock cycle
of count source
m
m+1
1
2
3
4
5
Timer A3
Note: This timing diagram is for the case where the POL bit of INT2IC register = “1” (= rising edge).
Figure 1.14.10. Two-phase Pulse (A phase and B phase) and the Z Phase
117
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 1.14.4.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 1.14.12 shows the
TAiMR register in one-shot timer mode.
Table 1.14.4. Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
n : set value of TAi register 000016 to FFFF16
Divide ratio
1/n
However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
Count start condition
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing When the counter reaches “000016”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
Select function
The timer outputs a low when not counting and a high when counting.
118
Preliminary Specifications Rev.1.0
Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
39616 to 039A16
After reset
0016
0
1 0
Bit symbol
Bit name
RW
RW
RW
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 1)
RW
(TAiOUT pin functions as a pulse output pin)
MR1
MR2
0 : Falling edge of input signal to TAiIN pin (Note 3)
1 : Rising edge of input signal to TAiIN pin (Note 3)
External trigger select
bit (Note 2)
RW
RW
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
MR3
RW
RW
Must be set to “0” in one-shot timer mode
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
or f2
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘00
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
2’ (TAiIN pin input).
Figure 1.14.12. TAiMR Register in One-shot Timer Mode
119
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Under
Specifications in this manual are tentative and subject to change.
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Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 1.14.5). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 1.14.13 shows
TAiMR register in pulse width modulation mode. Figures 1.14.14 and 1.14.15 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 1.14.5. Specifications in PWM Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new value at a rising edge of PWM pulse and continues counting
•
• The timer is not affected by a trigger that occurs during counting
16-bit PWM
• High level width
• Cycle time (2 -1) / fj fixed
n / fj
n : set value of TAi register (i=o to 4)
fj: count source frequency (f1, f2, f8, f32, fC32)
16
8-bit PWM
•
•
High level width n x (m+1) / fj n : set value of TAiMR register high-order address
Cycle time (2 -1) x (m+1) / fj m : set value of TAiMR register low-order address
8
Count start condition
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• TAiS bit of TABSR register is set to “1” (= start counting)
TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
120
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Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
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M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
1 1
1
RW
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
RW
RW
(Note 1)
MR0
MR1
Must be set to “1” in PWM mode
External trigger select
bit (Note 2)
0: Falling edge of input signal to TAiIN pin(Note 3)
1: Rising edge of input signal to TAiIN pin(Note 3)
RW
RW
MR2
MR3
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
RW
RW
RW
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1
8
or f2
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘00
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
2’ (TAiIN pin input).
Figure 1.14.13. TAiMR Register in PWM Mode
121
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Mitsubishi microcomputers
Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
Timers (Timer A)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1 / fi X
(216 – 1)
Count source
“H”
“L”
Input signal to
TAiIN pin
Trigger is not generated by this signal
1 / f
j
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit of TAiIC
register
f
j
: Frequency of count source
(f , f , f , f32, fC32
i = 0 to 4
Note 1: n = 000016 to FFFE16
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiGH and TAiGL bits of ONSF
or TRGSR register = ‘00 ’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2
1
2
8
)
Set to “0” upon accepting an interrupt request or by writing in program
.
2
bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 1.14.14. Example of 16-bit Pulse Width Modulator Operation
1 / fj
X (m + 1) X (28 – 1)
Count source (Note1)
“H”
“L”
Input signal to
TAiIN pin
1 / fj X (m + 1)
“H”
“L”
Underflow signal of
8-bit prescaler (Note2)
1 / fj X (m + 1) X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit of TAiIC
register
f
j
: Frequency of count source
(f , f , f , f32, fC32
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
1
2
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiGH and TAiGL bits of ONSF or
TRGSR register = ‘00 ’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
.
2
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 1.14.15. Example of 8-bit Pulse Width Modulator Operation
122
Preliminary Specifications Rev.1.0
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 1.15.1 shows a block diagram of the timer B. Figures 1.15.2 and 1.15.3 show registers related to the
timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
Reload register
• Timer
f1 or f2
• Pulse period measuremnet,
pulse width measurement
f
f
8
Clock selection
32
fC32
Counter
• Event counter
TABSR register
TBSR register
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow (Note)
(j = i – 1. Note, however,
j = 2 when i = 0,
Timer B0 039116 039016 Timer B2
Timer B1 039316 039216 Timer B0
Timer B2 039516 039416 Timer B1
Timer B3 035116 035016 Timer B5
Timer B4 035316 035216 Timer B3
Timer B5 035516 035416 Timer B4
j = 5 when i = 3)
Note: Overflow or underflow.
Figure 1.15.1. Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
Symbol
Address
After reset
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16 00XX0000
TB3MR to TB5MR 035B16 to 035D16 00XX0000
2
2
Bit symbol
TMOD0
Function
Bit name
RW
RW
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
TMOD1
RW
MR0
MR1
MR2
RW
RW
Function varies with each operation
mode
RW
(Note 1)
(Note 2)
RO
MR3
TCK0
TCK1
RW
RW
Count source select bit
Function varies with each operation
mode
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.15.2. TB0MR to TB5MR Registers
123
Preliminary Specifications Rev.1.0
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Under
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
After reset
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
035116, 035016 Indeterminate
035316, 035216 Indeterminate
035516, 035416 Indeterminate
Timer Bi register (i=0 to 5)(Note 1)
(b15)
b7
(b8)
b0 b7
b0
Function
Setting range
Mode
RW
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
Event counter
mode
Divide the count source by n + 1
where n = set value (Note 2)
000016 to FFFF16
RW
RO
Pulse period
modulation mode,
Measures a pulse period or width
Pulse width
modulation mode
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Count start flag
Symbol
TABSR
Address
038016
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer B3, B4, B5 count start flag
Symbol
TBSR
Address
034016
After reset
000XXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
RW
Bit name
Function
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b4-b0)
TB3S
TB4S
TB5S
Timer B3 count start flag
Timer B4 count start flag
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
RW
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b6-b0)
CPSR
Clock prescaler reset flag
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Figure 1.15.3. TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register
124
Preliminary Specifications Rev.1.0
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Under
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.15.1). Figure 1.15.4
shows TBiMR register in timer mode.
Table 1.15.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1) n: set value of TBiMR register (i= 0 to 5)
000016 to FFFF16
(Note)
Count start condition
Count stop condition
Set TBiS bit
to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
I/O port
Count value can be read by reading TBi register
•
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S
bits are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i= 0 to 5)
Symbol
Address
After reset
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR
TB3MR to TB5MR
039B16 to 039D16
035B16 to 035D16
00XX0000
00XX0000
2
0
0
2
Bit symbol
Bit name
Function
0 0 : Timer mode
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
MR1
TB0MR, TB3MR registers
Must be set to “0” in timer mode
MR2
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
RO
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
1
8
or f2
RW
RW
0 1 : f
1 0 : f32
1 1 : fC32
Figure 1.15.4. TBiMR Register in Timer Mode
125
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 1.15.2) . Figure 1.15.5 shows TBiMR register in event counter mode.
Table 1.15.2. Specifications in Event Counter Mode
Item
Specification
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
Count source
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
• Down-count
Count operation
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
1
Count start condition
Count stop condition
Set TBiS bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
Symbol
Address
After reset
00XX00002
00XX00002
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16
TB3MR to TB5MR 035B16 to 035D16
0
1
RW
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode
RW
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's
falling edges
RW
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
MR1
MR2
RW
RW
TB0MR, TB3MR registers
Must be set to “0” in timer mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
MR3
RO
Has no effect in event counter mode.
Can be set to “0” or “1”.
TCK0
TCK1
RW
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
Event clock select
RW
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 1.15.5. TBiMR Register in Event Counter Mode
126
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3. Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 1.15.3). Figure 1.15.6 shows TBiMR register in pulse period and pulse width
measurement mode. Figure 1.15.7 shows the operation timing when measuring a pulse period. Figure
1.15.8 shows the operation timing when measuring a pulse width.
Table 1.15.3. Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
3
Count start condition
Count stop condition
Set TBiS (i=0 to 5) bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
1
Interrupt request generation timing • When an effective edge of measurement pulse is input
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
Measurement pulse input
TBiIN pin function
Read from timer
Write to timer
Notes:
Contents of the reload register (measurement result) can be read by reading TBi register2
Value written to TBi register is written to neither reload register nor counter
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned
to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
TB0MR to TB2MR
TB3MR to TB5MR
039B16 to 039D16
035B16 to 035D16
00XX0000
00XX0000
2
1
0
2
Bit symbol
TMOD0
Bit name
Function
RW
RW
RW
b1 b0
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
TMOD1
MR0
b3 b2
Measurement mode
select bit
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
RW
MR1
MR2
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
RW
RW
TB0MR and TB3MR registers
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
flag ( Note)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
MR3
RO
TCK0
Count source
select bit
RW
0 0 : f
0 1 : f
1
8
or f2
1 0 : f32
1 1 : fC32
TCK1
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register's bit 5 to bit 7.
Figure 1.15.6. TBiMR Register in Pulse Period and Pulse Width Measurement Mode
127
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
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Timers (Timer B)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
TBiIC register's
IR bit
Set to “0” upon accepting an interrupt request or by writing in
program
“1”
“0”
TBiMR register's
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “00
from falling edge to falling edge of the measurement pulse).
2” (measure the interval
Figure 1.15.7. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
TBiIC register's
IR bit
Set to “0” upon accepting an interrupt request or by
writing in program
“1”
“0”
TBiMR register's
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 1.15.8. Operation timing when measuring a pulse width
128
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
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Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 1.16.1 lists the
specifications of the three-phase motor control timer function. Figure 1.16.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figure 1.16.2 to Figure
1.16.7.
Table 1.16.1. Three-phase Motor Control Timer FunctionS Specifications
Item
Specification
___
___
___
Three-phase waveform output pin
Forced cutoff input
Six pins (U, U, V, V, W, W)
Input “L” to NMI pin
_______
1
Used Timers
Timer A4, A1, A2 (used in the one-shot timer mode)
___
Timer A4: U- and U-phase waveform control
___
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead timer timer (3 eight-bit timer and shared reload register)
Dead time control
Output waveform
Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase
level respectively
Carrier wave cycle
Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting
the INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time
Count source x p, or no dead time
p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Eable to select “H” or “L”
active disable function
Active level
Positive and negative-phase concurrent
Positive and negative-phases concurrent active disable
function
Positive and negative-phases concurrent active detect func
tion
Interrupt frequency
For Timer B2 interrupt, select a carrier wave cycle-to-cycle
basis through 15 times carrier wave cycle-to-cycle basis
Notes:
_______
1. Forced cutoff with NMI input is effective when the IVPCR1 bit of TB2SC register is set to “1” (three-phase
_______
_______
output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin when the IVPCR1 bit
is “1”, the related pins go to a high-impedance state regardless of which functions of those pins are being
used.
Related pins
P72/CLK2/TA1OUT/V
_________ _________
___
P73/CTS2/RTS2/TA1IN/V
P74/TA2OUT/W
____
P75/TA2IN/W
P80/TA4OUT/U
___
P81/TA4IN/U
129
Under
development
ICTB2 register
n = 1 to 15
INV13
INV01
INV11
Interrupt occurrence set circuit
INV00
D
Q
INV03
1
Timer B2 underflow
R
RESET
NMI
ICTB2 counter
Timer B2
interrupt request bit
n = 1 to 15
0
INV05
INV12
0
1
Signal to be
written to
timer B2
Reload register
n = 1 to 255
INV14
INV04
f1
1/2
INV07
Trigger
Trigger
INV10
U
Reverse
control
Q
D
T
Timer B2
Dead tim
e timer
n = 1 to 255
(Timer mode)
INV06
phase output
U
control circuit
Timer Ai(i = 1, 2, 4) start trigger signal
DU0
bit
DU1
bit
Transfer trigger
(Note 1)
Timer A4 reload control signal
TA41 register
U
phase output signal
D
T
Q
D
T
Q
TA4 register
Trigger
Reload
Timer A4
Three-phase output
shift register
(U phase)
counter
er mode)
INV11
Timer A4
one-shot pulse
(One-shot tim
DUB1
bit
DUB0
bit
T Q
phase output signal
U
Reverse
control
Set to 0 when TA4S bit =
0
D
T
Q
D
Q
T
U
V
D
T
Q
Q
Reverse
control
Trigger
Trigger
D
T
Dead tim
e timer
n = 1 to 255
INV06
V
phase output signal
TA1 register
Trigger
Reload
Timer A 1 counter
TA11 register
phase output
control circuit
V
phase output
V
Reverse
control
signal
V
D
T
Q
Q
(One-shot tim
er mode)
INV11
Reverse
control
Trigger
Trigger
T Q
W
D
T
Dead tim
n = 1 to 255
e timer
Set to 0 when TA1S bit =
0
INV06
W
phase output signal
phase output signal
TA2 register
Reload
TA21 register
W phase output
control circuit
Trigger
Reverse
control
W
Timer A 2 counter
W
Q
D
T
(One-shot tim
er mode)
INV11
T Q
Set to 0 when TA2S bit =
Diagram for switching to P8
0
, P81 and P7
2
- P7
5
is not shown.
0
Note : If the INV06 bit = 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase PWM control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
034816
After reset
0016
Bit symbol
INV00
Bit name
Description
RW
RW
Effective interrupt output
polarity select bit
0: ICTB2 counter incremented by 1 at
odd-numbered occurrences of a timer
B2 underflow
1: ICTB2 counter incremented by 1 at
even-numbered occurrences of a timer
B2 underflow
(Note 3)
Effective interrupt output
specification bit
0: ICTB2 counter incremented by 1 at a
timer B2 underflow
INV01
RW
RW
(Note 2)
1: Selected by INV00 bit
(Note 3)
Mode select bit
(Note 4) 0: Three-phase motor control timer
function unused
1: Three-phase motor control timer
function
(Note 5)
INV02
INV03
Output control bit (Note 6) 0: Three-phase motor control timer output
disabled
(Note 5)
RW
1: Three-phase motor control timer output
enabled
Positive and negative
phases concurrent output
disable function enable bit
0: Simultaneous active output enabled
1: Simultaneous active output disabled
INV04
RW
RW
RW
Positive and negative
phases concurrent output
detect flag
0: Not detected yet
1: Already detected
(Note 7)
INV05
INV06
INV07
0: Triangular wave modulation mode
(Note 9)
Modulation mode select
1: Sawtooth wave modulation mode
bit
(Note 8)
Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated.
The value of this bit when read is “0”.
Software trigger select bit
RW
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that this register
can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
Note 3: Effective when the INV11 bit is “1” (three-phase mode 1). If INV11 is “0” (three-phase mode 0), the ICTB2 counter
is incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
Note 4: Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
Note 5: All of the U, U, V, V, W and W pins are placed in the high-impedance state by setting the INV02 bit to 1 (three-
phase motor control timer function) and setting the INV03 bit to “0” (three-phase motor control timer output
disable).
Note 6: The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active simultaneously while INV04 bit is “1”
• When set to “0” in a program
• When input on the NMI pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when NMI input is
“L”.)
Note 7: Can only be set by writing “0” in a program, and cannot be set to “1”.
Note 8: The effects of the INV06 bit are described in the table below.
Item
INV06=0
INV06=1
Mode
Sawtooth wave modulation mode
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Transferred every transfer trigger
Timing at which dead time timer trigger is
generated when INV16 bit is “0”
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
INV13 bit
Effective when INV11 is “1” and INV06
is “0”
Has no effect
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
Note 9: If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2
reloaded by a timer B2 underflow).
Figure 1.16.2. INVC0 Register
131
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase PWM control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
034916
After reset
0016
Bit symbol
INV10
Bit name
Description
RW
RW
Timer A1, A2, A4 start
trigger signal select bit
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
Timer A1-1, A2-1, A4-1
control bit
0: Three-phase mode 0
1: Three-phase mode 1
(Note 3)
INV11
INV12
RW
RW
(Note 2)
Dead time timer count
source select bit
0 : f1 or f2
1 : f1 divided by 2 or f2 divided by 2
Carrier wave detect flag
0: Timer A output at even-numbered occ-
urrences (TAj1 register value counted)
1: Timer A output at odd-numbered occ-
urrences (TAj1 register value counted)
(Note 4)
INV13
RO
0 : Output waveform “L” active
1 : Output waveform “H” active
Output polarity control bit
Dead time invalid bit
INV14
INV15
RW
RW
0: Dead time timer enabled
1: Dead time timer disabled
Dead time timer trigger
select bit
0: Falling edge of timer A4, A1 or A2
one-shot pulse
1: Rising edge of three-phase output shift
register (U, V or W phase) output
INV16
(b7)
RW
RW
(Note 5)
This bit should be set to “0”
Reserved bit
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that this
register can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: The effects of the INV11 bit are described in the table below.
Item
INV11=0
INV11=1
Three-phase mode 1
Used
Mode
Three-phase mode 0
Not used
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
Effect
whether the INV00 to INV01 bits are set.
Effective when INV11 bit is “1” and
INV06 bit is “0”
INV13 bit
Has no effect
Note 3: If the INV06 bit is “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the
INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
Note 4: The INV13 bit is effective only when the INV06 bit is “0” (triangular wave modulation mode) and the INV11 bit
is “1” (three-phase mode 1).
Note 5: If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge
of three-phase output shift register output)
• The INV15 bit is “0” (dead time timer enabled)
• When the INV03 bit is set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U,
V, or W, j: 0 to 1) have always different values (the positive-phase and negative-phase always output
different levels during the period other than dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered
by the falling edge of one-shot pulse).
Figure 1.16.3. INVC1 Register
132
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase output buffer register i (i=0, 1) (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0
IDB1
Address
034A16
034B16
After reset
0016
0016
Bit name
Bit Symbol
Function
RW
RW
RW
DUi
DUBi
DVi
U phase output buffer i
U phase output buffer i
V phase output buffer i
Write the output level
0: Active level
1: Inactive level
When read, these bits show the
three-phase output shift register
value.
RW
DVBi
DWi
V phase output buffer i
W phase output buffer i
W phase output buffer i
RW
RW
RW
DWBi
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
(b7-b6)
Note: The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The
value written to the IDB0 register after a transfer trigger represents the output signal of each phase, and the
next value written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents
the output signal of each phase.
Dead time timer (Note 1, Note 2)
b7
b0
Symbol
DTT
Address
034C16
After reset
Indeterminate
Setting range
1 to 255
RW
WO
Function
Assuming the set value = n, upon a start trigger the
timer starts counting the count source selected by
the INV12 bit and stops after counting it n times. The
positive or negative phase whichever is going from
an inactive to an active level changes at the same
time the dead time timer stops.
Note 1: Use MOV instruction to write to this register.
Note 2: Effective when the INV15 bit is “0” (dead time timer enable). If the INV15 bit is “1”, the dead time timer is
disabled and has no effect.
Figure 1.16.4. IDB0 Register, IDB1Register, and DTT Register
133
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B2 interrupt occurrences frequency set counter
b3
b0
Symbol
ICTB2
Address
034D16
After reset
Indeterminate
RW
WO
Function
Setting range
1 to 15
If the INV01 bit is “0” (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow.
If the INV01 bit is “1” (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every n’th
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
(Note)
Nothing is assigned. When write, set to “0”. When read, its content is
indeterminate.
Note : Use MOV instruction to write to this register.
If the INV01 bit = “1”, make sure the TB2S bit also = “0” (timer B2 count stopped) when writing to this register.
If the INV01 bit = “0”, although this register can be written even when the TB2S bit = “1” (timer B2 count start),
do not write synchronously with a timer B2 underflow.
Timer Ai, Ai-1 register (i=1, 2, 4) (Note 1, Note 2, Note 3, Note 4, Note 5, Note 6)
Symbol
Address
After reset
TA1
TA2
TA4
TA11
TA21
TA41
038916-038816
038B16-038A16
038F16-038E16
034316-034216
034516-034416
034716-034616
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
Function
Setting range
RW
WO
000016 to FFFF16
Assuming the set value = n, upon a start trigger the timer
starts counting the count source and stops after counting
it n times. The positive and negative phases change at
the same time timer A, A2 or A4 stops.
Note 1: The register must be accessed in 16 bit units.
Note 2: When the timer Ai register is set to “000016”, the counter does not operate and a timer Ai interrupt does
not occur.
Note 3: Use MOV instruction to write to these registers.
Note 4: If the INV15 bit is “0” (dead time timer enable), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
Note 5: If the INV11 bit is “0” (three-phase mode 0), the TAi register value is transferred to the reload register by
a timer Ai (i = 1, 2 or 4) start trigger.
If the INV11 bit is “1” (three-phase mode 1), the TAi1 register value is transferred to the reload register
by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the
next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the
reload register alternately.
Note 6: Do not write to these registers synchronously with a timer B2 underflow.
Note 7: Write to the TAi1 register as follows:
(1) Write a value to the TAi1 register.
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
XXXXXX00
2
RW
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 reload timing
switching bit
(Note 2)
occurrences
Three phase output port 0 : Three-phase output forcible cutoff
IVPCR1
NMI control bit 1
(Note 3)
by NMI input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by NMI input (high impedance)
enabled
Nothing is assigned.
When write, set to “0”. When read, its content is “0”.
(b7-b2)
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: If the INV11 bit is “0” (three-phase mode 0) or the INV06 bit is “1” (triangular wave modulation mode), set
this bit to “0” (timer B2 underflow).
Note 3: Related pins are U(P80), U(P81), V(P72), V(P73), W(P74) and W(P75). If a low-level signal is applied to
the NMI pin when the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of which
functions of those pins are being used. After forced interrupt (cutoff), input “H” to the NMI pin and set
IVPCR1 bit to “0”: this forced cutoff will be reset.
Figure 1.16.5. ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2SC Registers
134
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B2 register (Note )
Symbol
TB2
Address
039516-039416
After reset
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
Function
Setting range
RW
RW
000016 to FFFF16
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
Note : The register must be accessed in 16 bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1
b0
Symbol
TRGSR
Address
038316
After reset
0016
Bit symbol
TA1TGL
Bit name
Function
To use the V-phase output control
RW
Timer A1 event/trigger
select bit
RW
RW
circuit, set these bits to “01
2”(TB2
underflow).
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
To use the W-phase output control
RW
RW
RW
RW
circuit, set these bits to “01
underflow).
2”(TB2
TA2TGH
TA3TGL
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note 1)
0 1 : TB2 overflow is selected (Note 2)
1 0 : TA2 overflow is selected (Note 2)
1 1 : TA4 overflow is selected (Note 2)
TA3TGH
TA4TGL
TA4TGH
To use the U-phase output control
Timer A4 event/trigger
select bit
RW
RW
circuit, set these bits to “01
underflow).
2”(TB2
Note 1: Set the corresponding port direction bit to “0” (input mode).
Note 2: Overflow or underflow.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
Figure 1.16.6. TB2 Register, TRGSR Register, and TABSR Register
135
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
Symbol
TA1MR
TA2MR
TA4MR
Address
After reset
0016
0016
b7 b6 b5 b4 b3 b2 b1 b0
039716
039816
039A16
0
1
1 0
0016
Bit symbol
Bit name
Function
RW
RW
RW
TMOD0
TMOD1
MR0
Must set to “102” (one-shot timer mode) for
the three-phase motor control timer function
Operation mode
select bit
Must set to “0” for the three-phase motor
control timer function
Pulse output function
select bit
MR1
MR2
Has no effect for the three-phase motor
control timer function
External trigger select
bit
RW
RW
Trigger select bit
Must set to “1” (selected by event/trigger
select register) for the three-phase motor
control timer function
MR3
Must set to “0” for the three-phase motor control timer function
RW
RW
b7 b6
Count source select bit
0 0 : f1 or f2
TCK0
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
RW
Timer B2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2MR
Address
039D16
After reset
00XX00002
0
0 0
Bit symbol
Bit name
RW
RW
RW
Function
TMOD0
TMOD1
MR0
Set to “002” (timer mode) for the three-
phase motor control timer function
Operation mode select bit
RW
RW
Has no effect for the three-phase motor control timer function.
When write, set to “0”. When read, its content is indeterminate.
MR1
Must set to “0” for the three-phase motor control timer function
MR2
MR3
RW
RO
When write in three-phase motor control timer function, write “0”.
When read, its content is indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
RW
RW
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Figure 1.16.7. TA1MR, TA2MR, TA4MR, and TB2MR Registers
136
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used
__
___
___
to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated
dead time timer. Figure 1.16.8 shows the example of triangular modulation waveform and Figure 1.16.9
shows the example of sawtooth modulation waveform.
Carrier wave
Signal wave
TB2S bit of the
TABSR register
Timer B2
Start trigger signal
for timer A4*
p
p
n
n
m
m
Timer A4
one-shot pulse*
Rewriting IDB0, IDB1 registers
U phase
output signal *
Transfer to three-phase
output shift register
U phase
output signal *
U phase
INV14 = 0
(“L” active)
U phase
U phase
Dead time
INV14 = 1
(“H” active)
Dead time
U phase
INV13
(INV11=1(three-phase
mode 1))
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0 = 00XX11XX
An example for changing PWM outputs is shown below.
2 (X = set as suitable for the system) and INVC1 = 010XXXX02.
(1)When INV11=1(three-phase mode 1)
(2)When INV11=0(three-phase mode 0)
· INV01=0, ICTB2=216(timer B2 interrupt is generated at every 2’th
occurrence of a timer B2 underflow), or INV01=1, INV00=1,
ICTB2=116(timer B2 interrupt is generated at even-numbered
occurrences of a timer B2 underflow).
· Initial timer value: TA41=m, TA4=m. The TA4 and TA41 registers
are modified every time a timer B2 interrupt occurs. First time,
TA41= n, TA4 = n. Second time, TA41 = p, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0,
DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1,
DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2
interrupt occurs.
· INV01=0, ICTB2=116(timer B2 interrupt is generated at every
occurrence of a timer B2 underflow)
· Initial timer value: TA4 = m. The TA4 register is modified each time
a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n.
Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0,
DUB1=1.The register values are changed to DU0 = 1, DUB0 = 0, DU1=
1 and DUB1 = 0 the sixth time a timer B2 interrupt occurs.
The value written to the TA4 register and TA41 register are inverted at odd-numbered timer A outputs.
Figure 1.16.8. Triangular Wave Modulation Operation
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Three-phase Motor Control Timer Functions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Carrier wave: sawtooth waveform
Carrier wave
Signal wave
Timer B2
Start trigger signal
for timer A4*
Timer A4
one-shot pulse*
Rewriting IDB0, IDB1 registers
Transfer to three-phase
output shift register
U phase
output signal *
U phase
output signal *
U phase
INV14 = 0
(“L” active)
Dead time
Dead time
U phase
U phase
INV14 = 1
(“H” active)
U phase
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the
system) and INVC1 = 010XXX00 . An example for changing PWM outputs is shown below.
2
• ICTB2=n (timer B2 interrupt is generated at every n’th occurrence of a timer B2 underflow)
• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are
changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.
Figure 1.16.9. Sawtooth Wave Modulation Operation
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.
UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 1.17.1 shows the block diagram of UARTi. Figures 1.17.2 shows the block diagram of the UARTi
transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
2
•
•
•
•
Special mode 1 (I C mode)
Special mode 2
Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
Special mode 4 (SIM mode) : UART2
Figures 1.17.3 to 1.17.8 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
PCLK1=0
f
f
2SIO
1SIO
1/2
1/8
f
1SIO or f2SIO
Main clock, PLL clock, or ring oscillator clock
PCLK1=1
1/4
f
8SIO
f
32SIO
(UART0)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD0
TxD0
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
1/16
1/2
Reception
control circuit
Clock synchronous
type
00
01
10
External
2
Transmit/
receive
unit
U0BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
CKDIR=1
UART transmission
2
Transmit
clock
f
1 / (n0+1)
Transmission control
circuit
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
CKPOL
CKDIR=1
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
VCC
CTS/RTS selected
CRS=1
RTS0
CTS0 / RTS0
CRS=0
CTS/RTS disabled
RCSP=0
CRD=1
CTS0
CRD=0
CTS0 from UART1
RCSP=1
(UART1)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD1
TxD1
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
Reception
control circuit
Clock synchronous
type
Transmit/
receive
unit
00
01
10
2
U1BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
CKDIR=1
2
UART transmission
Transmit
clock
f
1/16
1/2
1 / (n1+1)
Transmission
control circuit
Clock synchronous
type
External
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKPOL
CKDIR=1
CLK
polarity
reversing
circuit
CLKMD0=0
CLKMD0=1
CLK1
Clock output
pin select
CLKMD1=1
CTS/RTS selected
CRS=1
CTS/RTS disabled
CTS1 / RTS1/
CTS0/ CLKS1
RTS1
CLKMD1=0
CRS=0
VCC
CTS/RTS disabled
CRD=1
CTS1
CTS
RCSP=0
0
from UART0
CRD=0
RCSP=1
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
TxD2
UART reception
Clock source selection
CLK1 to CLK0
00
Receive
clock
1/16
(Note)
Reception
control circuit
Clock synchronous
type
2
Transmit/
receive
unit
U2BRG
register
f
1SIO or
f
2SIO
8SIO
32SIO
01
2
Internal
CKDIR=0
CKDIR=1
f
UART transmission
10
2
Transmit
clock
f
1/16
1/2
1 / (n2+1)
Transmission
control circuit
Clock synchronous
type
External
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK2
CTS/RTS disabled
VCC
CTS/RTS
selected
CRS=1
CRS=0
RTS2
CTS2
CTS2 / RTS2
CTS/RTS disabled
CRD=1
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 1.17.1. UARTi Block Diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
No reverse
IOPOL=0
RxD data
reverse circuit
RxDi
Reverse
IOPOL=1
Clock
synchronous type
UART
1SP
PAR
disabled
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UARTi receive register
UART(7 bits)
STPS= 0
STPS= 1
PRYE=0
PAR
SP
SP
2SP
PRYE=1
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UiRB register
0
0
0
0
0
0
0
D
8
D7
D
6
D
5
D
4
D3
D
2
D1
D
0
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UiTB register
D
7
D
6
D
5
D
4
D3
D
2
D1
D
0
D
8
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
PRYE=1
PRYE=0
STPS= 1
SP
SP
PAR
STPS
= 0
UART
(7 bits)
UART
(8 bits)
UARTi transmit register
Clock
synchronous
type
UART(7 bits)
1SP
PAR
disabled
“0”
Clock
synchronous type
Error signal output
disable
i=0 to 2
SP: Stop bit
PAR: Parity bit
No reverse
UiERE=0
UiERE=1
IOPOL=0
IOPOL=1
TxD data
reverse circuit
Error signal
output circuit
TxDi
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
UiERE: UiC0 register's bit
Error signal output
enable
Reverse
Figure 1.17.2. UARTi Transmit/Receive Unit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register (i=0 to 2)(Note)
Symbol
U0TB
U1TB
U2TB
Address
After reset
(b15)
b7
(b8)
03A316-03A216
03AB16-03AA16
037B16-037A16
Indeterminate
Indeterminate
Indeterminate
b0 b7
b0
Function
RW
WO
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
Address
After reset
b0
03A716-03A616
03AF16-03AE16
037F16-037E16
Indeterminate
Indeterminate
Indeterminate
Bit
symbol
Function
Bit name
RW
Receive data (D
7
to D
0
)
RO
RO
(b7-b0)
(b8)
Receive data (D
8
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
(b10-b9)
ABT
Arbitration lost detecting
flag (Note 2)
0 : Not detected
1 : Detected
RW
RO
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
OER
FER
Framing error flag (Note 1) 0 : No framing error
1 : Framing error found
RO
RO
PER
SUM
Parity error flag (Note 1)
Error sum flag (Note 1)
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
RO
Note 1: When the UiMR register’s SMD2 to SMD0 bits = “0002” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)
UARTi bit rate generator (i=0 to 2)(Notes 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
After reset
b7
b0
Indeterminate
Indeterminate
Indeterminate
Function
Setting range
0016 to FF16
RW
WO
Assuming that set value = n, UiBRG divides the count source
by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 1.17.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
0016
U0MR to U2MR 03A016, 03A816, 037816
Bit
symbol
Function
RW
Bit name
b2 b1 b0
SMD0
Serial I/O mode select bit
(Note 2)
RW
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C mode
(Note 3)
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
SMD1
SMD2
RW
RW
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
RW
RW
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Odd/even parity select bit
Effective when PRYE = 1
0 : Odd parity
RW
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
RW
RW
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
IOPOL
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0C0 to U2C0 03A416, 03AC16, 037C16 00001000
2
Bit
symbol
RW
Bit name
Function
b1 b0
CLK0
BRG count source
select bit
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
RW
RW
CLK1
CRS
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
CTS/RTS function
select bit
(Note 4)
RW
RO
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
TXEPT Transmit register empty
flag
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
CRD
CTS/RTS disable bit
RW
RW
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
Data output select bit
(Note 2)
NCH
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CKPOL CLK polarity select bit
RW
RW
UFORM Transfer format select bit
(Note 3)
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: T /SDA and SCL are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS /RTS can be used when the UCON register’s CLKMD1 bit = “0” (only CLK output) and the UCON register’s RCSP bit =
“0” (CTS /RTS not separated).
X
D2
2
2
1
1
1
0
0
Figure 1.17.4. U0MR to U2MR Register and U0C0 to U2C0 Register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0C1, U1C1
03A516,03AD16 00000010
2
Bit
symbol
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
RO
RW
RO
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
(b5-b4)
UiLCH Data logic select bit
0 : No reverse
1 : Reverse
RW
RW
UiERE
Error signal output
enable bit
0 : Output disabled
1 : Output enabled
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
After reset
000000102
Bit
Function
Bit name
symbol
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
RO
Transmit buffer
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
TI
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RO
0 : No data present in U2RB register
1 : Data present in U2RB register
RI
Receive complete flag
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1)
RW
RW
cause select bit
1 : Transmit is completed (TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
Figure 1.17.5. U0C1 to U2C1 Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After reset
X0000000
2
Bit
Function
0 : Transmit buffer empty (Tl = 1)
Bit
RW
RW
symbol
name
U0IRS UART0 transmit
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
U1IRS UART1 transmit
0 : Transmit buffer empty (Tl = 1)
RW
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
U0RRM UART0 continuous
0 : Continuous receive mode disabled
RW
RW
RW
receive mode enable bit 1 : Continuous receive mode enable
U1RRM UART1 continuous
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
receive mode enable bit
CLKMD0 UART1 CLK/CLKS
select bit 0
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
RW
RW
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RCSP
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
X0000000
0
U0SMR to U2SMR 036F16, 037316, 037716
2
Bit
symbol
Function
Bit
name
RW
0 : Other than I2C mode
1 : I2C mode
IICM
I2C mode select bit
RW
RW
ABC
BBS
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
RW
(Note1)
Bus busy flag
Set to “0”
Reserved bit
RW
RW
(b3)
Bus collision detect
0 : Rising edge of transfer clock
sampling clock select bit 1 : Underflow signal of timer Aj (Note 2)
ABSCS
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
ACSE
RW
RW
0 : Irrelevant to RxDi
1 : Synchronous with RxDi (Note 3)
Transmit start condition
select bit
SSS
(b7)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (irrelevant to RxDi).
Figure 1.17.6. UCON Register and U0SMR to U2SMR Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0SMR2 to U2SMR2 036E16, 037216, 037616
X00000002
Bit
symbol
Bit name
Function
RW
2
I C mode select bit 2
Refer to Table 1.20.4
IICM2
RW
RW
RW
RW
CSC
SWC
ALS
Clock-synchronous bit
SCL wait output bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
SDA output stop bit
UARTi initialization bit
SCL wait output bit 2
SDA output disable bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
STAC
SWC2
RW
RW
RW
0: Transfer clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
SDHI
(b7)
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0SMR3 to U2SMR3
036D16, 037116, 037516
000X0X0X
2
Bit
Bit name
symbol
Function
RW
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b0)
CKPH
Clock phase set bit
0 : Without clock delay
1 : With clock delay
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
NODC Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b4)
DL0
b7 b6 b5
SDAi digital delay
setup bit
RW
RW
RW
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
(Note 1, Note 2)
DL1
DL2
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “000 ” (no delay).
2
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 1.17.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi special mode register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
0016
U0SMR4 to U2SMR4 036C16, 037016, 037416
Bit
symbol
Bit name
Start condition
Function
RW
RW
0 : Clear
1 : Start
STAREQ
generate bit (Note)
Restart condition
generate bit (Note)
0 : Clear
1 : Start
RSTAREQ
RW
RW
RW
RW
RW
RW
RW
Stop condition
generate bit (Note)
0 : Clear
1 : Start
STPREQ
STSPSEL
SCL,SDA output
select bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
ACK data bit
0 : ACK
1 : NACK
ACKD
ACK data output
enable bit
0 : Serial I/O data output
1 : ACK data output
ACKC
SCLHI
SWC9
0 : Disabled
1 : Enabled
SCL output stop
enable bit
SCL wait bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
Note: Set to “0” when each condition is generated.
Figure 1.17.8. U0SMR4 to U2SMR4 Registers
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Serial I/O (Clock Synchronous Serial I/O)
Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.18.1
lists the specifications of the clock synchronous serial I/O mode. Table 1.18.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 1.18.1. Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• CKDIR bit = “1” (external clock) : Input from CLKi pin
0016 to FF16
_______
_______
Transmission, reception control
Transmission start condition
• Selectable from CTS function, _R__T__S__ function or C___T__S__/RTS function disable
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Reception start condition
Interrupt request
generation timing
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Select function
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______
• Separate CTS/_R__T__S__ pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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Serial I/O (Clock Synchronous Serial I/O)
Table 1. 18. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
Bit
Function
Set transmission data
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
Reception data can be read
Overrun error flag
UiBRG
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
Set to “0012”
CKDIR
IOPOL
Select the internal clock or external clock
Set to “0”
UiC0
CLK1 to CLK0
CRS
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TxDi pin output mode (Note 2)
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
NCH
CKPOL
UFORM
TE
UiC1
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
U2IRS (Note 1)
U2RRM (Note 1)
UiLCH
Select the source of UART2 transmit interrupt
Set this bit to “1” to use continuous receive mode
Set this bit to “1” to use inverted data logic
Set to “0”
UiERE
0 to 7
UiSMR
Set to “0”
UiSMR2
UiSMR3
0 to 7
Set to “0”
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
UiSMR4
UCON
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
Set to “0”
7
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
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Serial I/O (Clock Synchronous Serial I/O)
Table 1.18.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
1.18.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 1.18.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 1.18.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
Serial data output
(Outputs dummy data when performing reception only)
(P6
3, P6
7, P70)
Serial data input
RxDi
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
(P6 , P6
2
6
, P7
1
)
)
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
UiMR register’s CKDIR bit=0
1
5, P7
2
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
CTSi/RTSi
(P6 , P6 , P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
CTS input
0
4
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output
I/O port
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
UiC0 register’s CRD bit=1
Table 1.18.4. P64 Pin Functions
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
Input: 0, Output: 1
CLKMD0
CLKMD1
0
RCSP
CRS
CRD
P64
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
CTS
1
1
RTS
0
CTS
0(Note1)
CLKS
1
1(Note 2)
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS
C0 register’s CRS bit to “1” (RTS selected).
0/RTS0 enabled) and the U0
0
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
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Serial I/O (Clock Synchronous Serial I/O)
(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
UiC1 register
“0”
“1”
“0”
“H”
Write data to the UiTB register
TE bit
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
Stopped pulsing because CTSi = “H”
CTSi
CLKi
TCLK
“L”
Stopped pulsing because the TE bit = “0”
TxDi
D0
D
1
D2
D3
D4
D5
D6
D7
D0
D
1
D2
D3
D4
D5
D
6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
“1”
UiC1 register
RE bit
“0”
“1”
UiC1 register
TE bit
“0”
“1”
“0”
“H”
Write dummy data to UiTB register
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D
0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UiRB register
Read out from UiRB register
“1”
“0”
UiC1 register
RI bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register CKDIR bit = 1 (external clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
• UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register RE bit = 1 (Receive enabled)
• Write dummy data to the UiTB register
fEXT: frequency of external clock
Figure 1.18.1. Transmit and Receive Operation
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Serial I/O (Clock Synchronous Serial I/O)
(a) CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 1.18.2 shows
the polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
i
(Note 2)
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D0
D
1
D
2
D
D4
D
D
D
RXDi
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(Note 3)
CLK
i
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 1.18.2. Transfer Clock Polarity
(b) LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 1.18.3 shows the
transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 1.18.3. Transfer Format
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Serial I/O (Clock Synchronous Serial I/O)
(c) Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “1”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 4.
(d) Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register. Figure 1.18.4 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
i
TxD
(no reverse)
D0
D1
D2
D3
D4
D5
D6
D7
“L”
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
i
D0
D1
D2
D3
D4
D5
D6
D7
(reverse)
“L”
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Figure 1.18.4. Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
(See Figure 1.18.5.) This function can be used when the selected transfer clock for UART1 is an
internal clock.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Transfer enabled
when the UCON
register's
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).
Figure 1.18.5. Transfer Clock Output From Multiple Pins
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Serial I/O (Clock Synchronous Serial I/O)
_______ _______
(f) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
IN
R
X
D0
(P6
2)
OUT
CLK
0
(P6
1)
CLK
CTS
RTS
RTS
CTS
0
(P6
(P6
0)
0
4)
_______ _______
Figure 1.18.6. CTS/RTS Separat Function
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (UART)
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.19.1 lists the specifications of the UART mode.
Table 1.19.1. UART Mode Specifications
Item
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
Transfer data format
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock
• UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
0016 to FF16
fEXT: Input from CLKi pin. n :Setting value of UiBRG register
0016 to FF16
_______
_______
Transmission, reception control • Selectable from CTS function, _R__T__S__ function or _C__T__S__/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection
Reception start condition
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Interrupt request
generation timing
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
• Separate _C__T__S__/R___T__S__ pins (UART0)
_________
CTS0 and _R__T__S___0_ are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (UART)
Table 1. 19. 2. Registers to Be Used and Settings in UART Mode
Register
UiTB
Bit
0 to 8
0 to 8
Function
Set transmission data (Note 1)
Reception data can be read (Note 1)
UiRB
OER,FER,PER,SUM Error flag
UiBRG
UiMR
---
Set a transfer rate
Set these bits to ‘1002’ when transfer data is 7 bits long
SMD2 to SMD0
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
Select whether parity is included and whether odd or even
Select the TxD/RxD input/output polarity
UiC0
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
NCH
Select TxDi pin output mode (Note 2)
CKPOL
UFORM
Set to “0”
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
UiC1
TE
TI
RE
RI
U2IRS (Note 2)
U2RRM (Note 2)
UiLCH
Set this bit to “1” to use inverted data logic
Set to “0”
UiERE
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
Set to “0”
7
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2
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Serial I/O (UART)
Table 1.19.3 lists the functions of the input/output pins during UART mode. Table 1.19.4 lists the P64 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin
is in a high-impedance state.)
Table 1.19.3. I/O Pin Functions
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
Serial data output
(Outputs dummy data when performing reception only)
(P6
3, P6
7, P70)
Serial data input
RxDi
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
(P6 , P6
2
6
, P7
1
)
)
CLKi
(P6 , P6
Input/output port
UiMR register’s CKDIR bit=0
1
5, P7
2
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
Transfer clock input
CTSi/RTSi
(P6 , P6 , P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
CTS input
0
4
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
Input/output port
UiC0 register’s CRD bit=1
Table 1.19.4. P64 Pin Functions
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
CLKMD1
RCSP
CRS
CRD
P64
1
0
0
0
0
0
0
1
0
0
0
0
Input: 0, Output: 1
0
CTS1
0
1
0
RTS1
CTS0 (Note)
0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).
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Serial I/O (UART)
(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
TE bit
“1”
“0”
Write data to the UiTB register
UiC1 register
TI bit
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
“L”
CTSi
TxDi
Stopped pulsing
because the TE bit
= “0”
Start
bit
Parity Stop
bit bit
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D
7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
UiC0 register
TXEPT bit
“1”
“0”
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
)
f
• UiMR register STPS bit = 0 (1 stop bit)
n : value set to UiBRG
i: 0 to 2
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
UiC1 register
Write data to the UiTB register
TE bit
“0”
“1”
UiC1 register
TI bit
“0”
Transferred from UiTB register to UARTi
transmit register
Start
bit
Stop Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 0 (parity disabled)
)
f
• UiMR register STPS bit = 1 (2 stop bits)
n : value set to UiBRG
i: 0 to 2
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
• UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 1.19.1. Transmit Operation
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Serial I/O (UART)
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
“1”
“0”
UiC1 register
RE bit
Stop bit
Start bit
Sampled “L”
D
1
D7
RxDi
D0
Receive data taken in
Transfer clock
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
UiC1 register
RI bit
“0”
“H”
“L”
RTSi
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 1.19.2. Receive Operation
(a) LSB First/MSB First Select Function
As shown in Figure 1.19.3, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
ST
ST
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D
7
7
P
P
SP
SP
TXDi
D0
D
1
D
2
D
3
D
D
5
D6
D
RXDi
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
T
X
D
i
D
6
D
5
D
4
D
3
D
2
D
1
D0
ST
ST
P
P
SP
SP
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
RXDi
D
7
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 1.19.3. Transfer Format
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Serial I/O (UART)
(b) Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 1.19.4 shows serial data
logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
TxD
i
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse)
“L”
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
i
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
“L”
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge of the transfer clock), the
UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's
STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity
enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Figure 1.19.4. Serial Data Logic Switching
(c) TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 1.19.5 shows the TXD
pin output and RXD pin input polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
i
(no reverse) “L”
TxD
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
“H”
RxD
i
“L”
(no reverse)
(2) When the UiMR register's IOPOL bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
i
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(reverse) “L”
“H”
RxD
i
“L”
(reverse)
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the
UiMR register's PRYE bit = 1 (parity enabled).
Figure 1.19.5. TXD and RXD I/O Polarity Inverse
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Serial I/O (UART)
_______ _______
(d) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
T
X
D0
(P6
3)
IN
R
X
D0
(P6
2)
OUT
CTS
RTS
RTS
CTS
0
(P6
(P6
0)
0
4)
_______ _______
Figure 1.19.6. CTS/RTS Separate Function
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Serial I/O (Special Modes)
2
Special Mode 1 (I C mode)
2
2
I C mode is provided for use as a simplified I C interface compatible mode. Table 1.20.1 lists the speci-
2
2
fications of the I C mode. Table 1.20.2 lists the registers used in the I C mode and the register values
2
set. Figure 1.20.1 shows the block diagram for I C mode. Figure 1.20.2 shows SCLi timing.
2
As shown in Table 1.20.3, the microcomputer is placed in I C mode by setting the SMD2 to SMD0 bits to
‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
2
Table 1.20.1. I C Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
CKDIR bit = “1” (external clock) : Input from CLKi pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Interrupt request
generation timing
Error detection
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
• Arbitration lost
Select function
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change
.
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Serial I/O (Special Modes)
Start and stop condition generation block
SDAi
DMA0, DMA1 request
(UART1: DMA0 only)
STPSEL=1
STPSEL=0
SDASTSP
SCLSTSP
Delay
circuit
IICM2=1
Transmission
register
UARTi transmit,
NACK interrupt
request
ACK=1
ACK=0
IICM=1 and
IICM2=0
UARTi
SDHI
ALS
ACKD register
DMA0
(UART0, UART2)
D
T
Arbitration
Q
Noise
Filter
IICM2=1
UARTi receive,
ACK interrupt request,
DMA1 request
Reception register
UARTi
IICM=1 and
IICM2=0
Start condition
detection
S
R
Bus
busy
Q
Stop condition
detection
NACK
D
Q
T
Falling edge
detection
SCLi
D
Q
ACK
T
R
Port register
(Note)
IICM=0
I/O port
STPSEL=0
UARTi
9th bit
Q
Internal clock
Start/stop condition detection
interrupt request
SWC2
External
clock
CLK
control
IICM=1
STPSEL=1
Noise
Filter
UARTi
9th bit falling edge
SWC
R
S
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM: UiSMR register bit
IICM2: UiSMR2 register bit
i=0 to 2
Note: When the IICM bit =1, the pins can be read even if the direction bit = 1 (output).
2
Figure 1.20.1. I C Mode Block Diagram
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Serial I/O (Special Modes)
Table 1. 20. 2. Registers to Be Used and Settings in I2C Mode (1) (Continued)
Register
Bit
Function
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘0102’
Slave
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to ‘0102’
UiTB3
UiRB3
0 to 7
0 to 7
8
ABT
OER
UiBRG ---
UiMR3 SMD2 to SMD0
CKDIR
IOPOL
Set to “0”
Set to “0”
Set to “1”
Set to “0”
UiC0
CLK1, CLK0
Select the count source for the UiBRG
register
Invalid
CRS
TXEPT
CRD
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
NCH
Set to “1”2
Set to “1”2
CKPOL
UFORM
TE
Set to “0”
Set to “1”
Set to “0”
Set to “1”
UiC1
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI
RE
RI
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
U2IRS1
U2RRM1,
UiLCH, UiERE
Set to “0”
Set to “0”
UiSMR IICM
ABC
Set to “1”
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
BBS
3 to 7
Bus busy flag
Set to “0”
Bus busy flag
Set to “0”
UiSMR2 IICM2
CSC
Refer to Table 1.20.4.
Set this bit to “1” to enable clock
synchronization
Refer to Table 1.20.4.
Set to “0”
SWC
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
ALS
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
Set to “0”
Set to “0”
STAC
SWC2
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to have SCLi output
forcibly pulled low
SDHI
7
Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output
Set to “0”
Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
Set to “0”
CKPH
DL2 to DL0
Refer to Table 1.20.4
Set the amount of SDAi digital delay
Refer to Table 1.20.4
Set the amount of SDAi digital delay
i=0 to 2
Notes:
1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
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Serial I/O (Special Modes)
Table 1. 20. 3. Registers to Be Used and Settings in I2C Mode (2) (Continued)
Register
Bit
Function
Master
Set this bit to “1” to generate start
condition
Set this bit to “1” to generate restart
condition
Slave
UiSMR4 STAREQ
RSTAREQ
Set to “0”
Set to “0”
Set to “0”
STPREQ
Set this bit to “1” to generate stop
condition
STSPSEL
ACKD
Set this bit to “1” to output each condition Set to “0”
Select ACK or NACK
Select ACK or NACK
ACKC
SCLHI
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to output ACK data
Set to “0”
SWC9
Set this bit to “1” to set the SCLi to “L”
hold at the falling edge of the 9th bit of
clock
IFSR2A IFSR26, ISFR27 Set to “1”
Set to “1”
Invalid
Set to “0”
UCON U0IRS, U1IRS
2 to 7
Invalid
Set to “0”
i=0 to 2
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Serial I/O (Special Modes)
2
Table 1.20.4. I C Mode Functions
Clock synchronous serial I/O
I2C mode (SMD2 to SMD0 = 010
2, IICM = 1)
Function
mode (SMD2 to SMD0 = 001
IICM = 0)
2,
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 0
CKPH = 1
CKPH = 0
(Clock delay)
(No clock delay) (Clock delay) (No clock delay)
Factor of interrupt number
6, 7 and 10 (Note 1)(Refer
to Fig 1.20.2)
Start condition detection or stop condition detection
(Refer to Fig 1.20.4)
Factor of interrupt number
15, 17 and 19 (Note 1)(
Refer to Fig 1.20.2)
UARTi transmission
Falling edge of SCLi
next to the 9th bit
No acknowledgment
UARTi transmission
UARTi transmission
Transmission started or
completed (selected by UiIRS)
detection (NACK)
Rising edge of
Rising edge of SCLi 9th bit
SCLi 9th bit
Factor of interrupt number UARTi reception
UARTi transmission
Falling edge of SCLi 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
16, 18 and 20 (Note 1)(
Refer to Fig 1.20.2)
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for transferring data
from the UART reception
shift register to the UiRB
register
Falling and rising
edges of SCLi 9th
bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Falling edge of
SCLi 9th bit
Rising edge of SCLi 9th bit
UARTi transmission output
delay
Delayed
Not delayed
TxDi output
SDAi input/output
SCLi input/output
Functions of P6
P7 pins
Functions of P6
P7 pins
3
2
1
, P6
, P6
, P6
7
6
5
and
and
and
0
RxDi input
1
(Cannot be used in I2C mode)
CLKi input or output selected
Functions of P6
P7 pins
Noise filter width
2
200ns
15ns
Read RxDi and SCLi pin
levels
Possible when the
corresponding port direction bit
= 0
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C mode (Note 2)
CKPOL = 0 (H)
CKPOL = 1 (L)
Initial value of TxDi and
SDAi outputs
Initial and end values of
SCLi
H
L
H
L
UARTi reception
DMA1 factor (Refer to Fig
1.20.2)
Acknowledgment detection
(ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store received data
1st to 8th bits are stored in
UiRB register bit 0 to bit 7
1st to 8th bits are stored in
UiRB register bit 7 to bit 0
1st to 7th bits are stored in UiRB register
bit 6 to bit 0, with 8th bit stored in UiRB
register bit 8
1st to 8th bits are
stored in UiRB
register bit 7 to bit 0
(Note 3)
Read received data
Read UiRB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
UiRB register status is read
directly as is
i = 0 to 2
Note 1: To change the interrupt sources from one to another, follow the procedure described below.
1. Disable the interrupt of the corresponding interrupt number to be changed.
2. Change interrupt sources from one to another.
3. Set the IR bit for the corresponding interrupt number to 0 (no interrupt request).
4. Set the IPL2 to IPL0 bits for the corresponding interrupt number.
Note 2: Set the initial value of SDAi output while the UiMR register’s SMD2 to SMD0 bits = ‘000
Note 3: Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
Note 4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
2’ (serial I/O disabled).
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Serial I/O (Special Modes)
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Transmit interrupt
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9
b8 b7
D0
b0
D7 D6 D5 D4 D3 D2 D1
•••
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Transmit interrupt
Receive interrupt
(DMA1 request)
Transfer to UiRB register Transfer to UiRB register
b15
b9
b8 b7
D0
b0
b15
b9
b8 b7
b0
D7 D6 D5 D4 D3 D2 D1
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
•••
UiRB register
UiRB register
i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
Figure 1.20.2. Transfer to UiRB Register and Interrupt Timing
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Serial I/O (Special Modes)
• Detection of Start and Stop Condtion
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO
f
.
Figure 1.20.3. Detection of Start and Stop Condition
• Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
A start condition is output by setting the STAREQ bit to “1” and then the UiSMR4 register’s STSPSEL
bit to “1” (start). Similarly, a restart condition is output by setting the RSTAREQ bit to “1” and then the
STSPSEL bit to “1”, and a stop condition is output by setting the STPREQ bit to “1” and then the
STSPSEL bit to “1”.
Table 1.20.5 and Figure 1.20.4 show the functions of the STSPSEL.
If start, stop and restart conditions are to be output, make sure no interrupts will occur between the
instruction that sets the STAREQ, STPREQ or RSTAREQ bit to “1” and the instruction that sets the
STSPSEL bit to “1”.
Also, if a start condition is to be output, make sure the STAREQ bit is set to “1” before setting the
STSPSEL bit to “1”.
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Serial I/O (Special Modes)
Table 1.20.5. STSPSEL Bit Functions
Function
STSPSEL = 0
STSPSEL = 1
Output of SCLi and SDAi pins
Output of transfer clock and
data
Output of a start/stop condition
according to the STAREQ,
Output of start/stop condition is RSTAREQ and STPREQ bit
accomplished by a program
using ports (not automatically
generated in hardware)
Star/stop condition interrupt
request generation timing
Start/stop condition detection
Finish generating start/stop condi-
tion
(1) When slave
CKDIR=1 (external clock)
STPSEL bit
0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STPSEL bit
Set to “1” in
a program
Set to “0” in
a program
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Set STAREQ=
1 (start)
Set STPREQ=
1 (start)
Stop condition
detection interrupt
Start condition
detection interrupt
Figure 1.20.4. STSPSEL Bit Functions
• Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising
edge of SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT
bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC
bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring
the next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
• Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 1.20.4.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi)
and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchro-
nization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the
internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in
the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low,
counting stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi
pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st
bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a
low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s
CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
• SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
2
The initial value of SDAi transmit output can only be set when IICM = 1 (I C mode) and the UiMR
register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
• SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit
7 to bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit
6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing
the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB
register after the rising edge of the corresponding clock pulse of 9th bit.
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Serial I/O (Special Modes)
• ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the
UiSMR4 register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low
at the rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
• Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O
operates as described below.
- The transmit shift register is initialized, and the content of the UiTB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UARTi output value does not change state and remains the same
as when a start condition was detected until the first bit of data is output synchronously with the input
clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
Special Mode 2
Multiple slaves can be serially communicated from one master. Synchronous clock polarity and phase
are selectable. Table 1.20.6 lists the specifications of Special Mode 2. Table 1.20.7 lists the registers
used in Special Mode 2 and the register values set. Figure 1.20.5 shows communication control example
for Special Mode 2.
Table 1.20.6. Special Mode 2 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• Master mode
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Controlled by input/output ports
Transmit/receive control
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Interrupt request
generation timing
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Select function
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.
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Serial I/O (Special Modes)
P1
P1
3
2
P9
P72(CLK
P71(RxD
P70(TxD
3
P72(CLK
2
)
2
)
P71(RxD
2
)
2
)
P70(TxD
2
)
2
)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK
2
)
)
P71(RxD
2
P70(TxD )
2
Microcomputer
(Slave)
Figure 1.20.5. Serial Bus Communication Control Example (UART2)
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Serial I/O (Special Modes)
Table 1. 20. 7. Registers to Be Used and Settings in Special Mode 2
Register
Bit
Function
Set transmission data
Reception data can be read
Overrun error flag
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
UiBRG
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
Set to ‘0012’
CKDIR
IOPOL
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
UiC0
UiC1
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TxDi pin output format(Note 2)
Clock phases can be set in combination with the UiSMR3 register's CKPH bit
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
RI
U2IRS (Note 1)
U2RRM(Note 1),
U2LCH, UiERE
0 to 7
Select UART2 transmit interrupt cause
Set to “0”
UiSMR
Set to “0”
UiSMR2
UiSMR3
0 to 7
CKPH
Set to “0”
Clock phases can be set in combination with the UiC0 register's CKPOL bit
NODC
Set to “0”
0, 2, 4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
Set to “0”
Set to “0”
UiSMR4
UCON
Select UART0 and UART1 transmit interrupt cause
Set to “0”
Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
i = 0 to 2
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Serial I/O (Special Modes)
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be commu-
nicated.
(a) Master (Internal Clock)
Figure 1.20.6 shows the transmission and reception timing in master (internal clock).
(b) Slave (External Clock)
Figure 1.20.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 1.20.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).
"H"
Clock output
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.20.6. Transmission and Reception Timing in Master Mode (Internal Clock)
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Serial I/O (Special Modes)
"H"
Slave control input
"L"
"H"
Clock input
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock input
(CKPOL=1, CKPH=0)
"H"
"L"
Data output timing
(Note)
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Indeterminate
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 1.20.7. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H"
Clock input
"L"
(CKPOL=0, CKPH=1)
"H"
"L"
Clock input
(CKPOL=1, CKPH=1)
"H"
"L"
Data output timing
(Note)
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 1.20.8. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 1.20.8 lists the registers used in IE mode and the register values set. Figure 1.20.9 shows the
functions of bus collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect
function.
Table 1. 20. 8. Registers to Be Used and Settings in IE Mode
Register
UiTB
Bit
Function
Set transmission data
Reception data can be read
OER,FER,PER,SUM Error flag
0 to 8
UiRB(Note3) 0 to 8
UiBRG
UiMR
---
Set a transfer rate
SMD2 to SMD0
CKDIR
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
STPS
PRY
Invalid because PRYE=0
Set to “0”
PRYE
IOPOL
Select the TxD/RxD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
Select TxDi pin output mode (Note 2)
Set to “0”
CKPOL
UFORM
TE
Set to “0”
UiC1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
TI
RE
RI
U2IRS (Note 1)
UiRRM (Note 1),
UiLCH, UiERE
0 to 3, 7
ABSCS
ACSE
UiSMR
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
SSS
Select the transmit start condition
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
IFSR26, IFSR27
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
CLKMD1,RCSP,7 Set to “0”
Note 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IEmode.
i= 0 to 2
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
UiBCNIC register
IR bit (Note)
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
UiC1 register
TE bit
Note: BCNIC register when UART2.
(3) UiSMR register SSS bit (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
CLKi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
(Note 2)
TxDi
RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 1.20.9. Bus Collision Detect Function-Related Bits
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 1.20.9 lists the specifications of SIM mode. Table 1.20.10 lists the registers used in the SIM mode
and the register values set.
Table 1.20.9. SIM Mode Specifications
Item
Specification
Transfer data format
• Direct format
• Inverse format
Transfer clock
• U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
0016 to FF16
0016 to FF16
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register= 1 (reception enabled)
_ Start bit detection
• For transmission
Interrupt request
generation timing
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
• Overrun error (Note)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
Table 1. 20. 10. Registers to Be Used and Settings in SIM Mode
Register
Bit
Function
Set transmission data
Reception data can be read
U2TB(Note) 0 to 7
U2RB(Note) 0 to 7
OER,FER,PER,SUM Error flag
U2BRG
U2MR
---
Set a transfer rate
Set to ‘1012’
Select the internal clock or external clock
Set to “0”
SMD2 to SMD0
CKDIR
STPS
PRY
Set this bit to “1” for direct format or “0” for inverse format
PRYE
Set to “1”
Set to “0”
IOPOL
U2C0
CLK1, CLK0
CRS
Select the count source for the U2BRG register
Invalid because CRD=1
TXEPT
CRD
Transmit register empty flag
Set to “1”
NCH
Set to “0”
CKPOL
UFORM
TE
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
U2C1
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
U2RRM
U2LCH
U2ERE
Set to “1”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set to “1”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
U2SMR(Note) 0 to 3
U2SMR2
U2SMR3
U2SMR4
0 to 7
0 to 7
0 to 7
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
(1) Transmission
Transfer clock
Tc
“1”
U2C1 register
TE bit
Write data to U2TB register
“0”
“1”
U2C1 register
TI bit
“0”
Transferred from U2TB register to UART2 transmit register
Parity Stop
Start
bit
bit
bit
TxD
2
ST
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
7
P
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
6
D
6
SP
Parity error signal sent
back from receiver
An “L” level returns due to the
occurrence of a parity error.
RxD
2
pin level
(Note)
ST
D
D
D
D
D
D
D7
P
SP
ST
D0
D1
D2
D3
D
4
D5
D7
P
D
D6
SP
The level is detected by the
interrupt routine.
“1”
“0”
U2C0 register
TXEPT bit
The level is
detected by the
interrupt routine.
The IR bit is set to “1” at the
falling edge of transfer clock
“1”
“0”
S2TIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
The above timing diagram applies to the case where data is transferred in
the direct format.
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
)
f
Note : Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the TxD
2
output and the parity error signal
sent back from receiver.
(1) Reception
Tc
Transfer clock
“1”
“0”
U2C1 register
RE bit
Stop
bit
Parity
bit
Start
bit
Transmitter's
transmit waveform
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
SP
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
D6
TxD2
An “L” level is output from TxD
the occurrence of a parity error
2 due to
RxD2
pin level
(Note)
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
U2C0 register
RI bit
Read the U2RB register
Read the U2RB register
“1”
“0”
S2RIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is received in
direct format.
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD
2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Figure 1.20.10. Transmit and Receive Timing in SIM Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Special Modes)
Figure 1.20.11 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 1.20.11. SIM Interface Connection
(a) Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 1.20.12. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD
2
“L”
“H”
“L”
(Note)
TxD
2
“1”
“0”
U2C1 register
RI bit
This timing diagram applies to the case where the direct format is
implemented.
ST : Start bit
P : Even Parity
SP : Stop bit
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 1.20.12. Parity Error Signal Output Timing
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Serial I/O (Special Modes)
(b) Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH
bit to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 1.20.13 shows the SIM interface format.
(1) Direct format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D0
D1
D2
D3
D4
D5
D6
D7
P
“L”
P : Even parity
(2) Inverse format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D7
D6
D5
D4
D3
D2
D1
D0
P
“L”
P : Odd parity
Figure 1.20.13. SIM Interface Format
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SI/O3, SI/O4
SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 1.21.1 shows the block diagram of SI/O3 and SI/O4, and Figure 1.21.2 shows the SI/O3 and SI/O4-
related registers.
Table 1.21.1 shows the specifications of SI/O3 and SI/O4.
Clock source select
f
2SIO
PCLK1=0
SMi1 to SMi0
00
1/2
Data bus
2
Main clock,
PLL clock,
or ring oscillator clock
f
1SIO
01
2
2
f
8SIO
32SIO
PCLK1=1
1/4
1/8
10
f
Synchronous
circuit
1/(n+1)
1/2
SiBRG register
SMi3
SMi4
SMi6
CLK
SMi6
polarity
reversing
circuit
SI/Oi
interrupt request
SI/O counter i
CLK
i
SMi2
SMi3
SMi5 LSB
MSB
SOUTi
SiTRR register
S
INi
8
Note: i = 3, 4.
n = A value set in the SiBRG register.
Figure 1.21.1. SI/O3 and SI/O4 Block Diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SI/O3, SI/O4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
Address
036216
036616
After reset
010000016
010000016
Bit
symbol
Description
RW
Bit name
b1 b0
SMi0 Internal synchronous
clock select bit
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
RW
RW
RW
RW
SMi1
1 0 : Selecting f32SIO
1 1 : Must not be set.
SMi2 SOUTi output disable bit
(Note 4)
0 : SOUTi output
1 : SOUTi output disable(high impedance)
0 : Input/output port
1 : SOUTi output, CLKi function
S I/Oi port select bit
SMi3
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
CLK polarity select bit
SMi4
RW
SMi5 Transfer direction select
bit
0 : LSB first
1 : MSB first
RW
RW
(Note 2)
(Note 3)
SMi6
Synchronous clock
select bit
0 : External clock
1 : Internal clock
SMi7 SOUTi initial value
set bit
Effective when SMi3 = 0
0 : “L” output
RW
1 : “H” output
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
Symbol
S3BRG
S4BRG
Address
036316
036716
After reset
Indeterminate
Indeterminate
b7
b0
Setting range
0016 to FF16
Description
RW
WO
Assuming that set value = n, BRGi divides the count
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
Symbol
S3TRR
S4TRR
Address
036016
036416
After reset
Indeterminate
Indeterminate
b7
b0
RW
RW
Description
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 1.21.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
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SI/O3, SI/O4
Table 1.21.1. SI/O3 and SI/O4 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register (Notes 2, 3)
• When SiC register's SMi4 bit = 0
0016 to FF16.
Transmission/reception
start condition
Interrupt request
generation timing
The rising edge of the last transfer clock pulse (Note 4)
• When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
CLKi pin fucntion
SOUTi pin function
SINi pin function
Select function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not tranmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-
fore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
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SI/O3, SI/O4
(a) SI/Oi Operation Timing
Figure 1.21.3 shows the SI/Oi operation timing
1.5 cycle (max)
(Note 3)
"H"
"L"
SI/Oi internal clock
CLKi output
"H"
"L"
"H"
"L"
Signal written to the
SiTRR register
(Note 2)
S
OUTi output
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
"H"
"L"
S
INi input
"1"
"0"
SiIC register
IR bit
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 1.21.3. SI/Oi Operation Timing
(b) CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.21.4 shows
the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = “0”
(Note 2)
CLK
i
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
S
INi
D0
D
1
D
2
D
D4
D
D
D
S
OUTi
(2) When SiC register's SMi4 bit = “1”
(Note 3)
CLK
i
D0
D1
D
2
D3
D
4
D
5
D
6
D7
SINi
D0
D1
D2
D3
D
4
D
5
D6
D7
S
OUTi
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 1.21.4. Polarity of Transfer Clock
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SI/O3, SI/O4
(c) Functions for Setting an SOUTi Initial Value
If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. Figure 1.21.5 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When “H” selected for SOUTi initial value (Note 1)
Setting of the initial value of SOUT
output and starting of transmission/
reception
i
Signal written to
SiTRR register
SMi7 bit
SMi3 bit
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)
Set the SMi7 bit to “1”
(SOUTi initial value = “H”)
D0
D0
S
OUTi (internal)
Set the SMi3 bit to “1”
(SOUTi pin functions as SOUTi output)
Port output
S
OUTi pin output
“H” level is output
from the SOUTi pin
Initial value = “H” (Note 3)
(i = 3, 4)
Setting the SOUT
initial value to “H”
(Note 2)
i
Port selection switching
(I/O port OUTi)
Write to the SiTRR register
S
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)
Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC
register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or
in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
Serial transmit/reception starts
Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 1.21.5. SOUTi’s Initial Value Setting
188
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95,
___________
P96, P00 to P07, and P20 to P27. Similarly, ADTRG input shares the pin with P97. Therefore, when using
these inputs, make sure the corresponding port direction bits are set to “0” (= input mode).
When not using the A-D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7).
Table 1.22.1 shows the performance of the A-D converter. Figure 1.22.1 shows the block diagram of the
A-D converter, and Figures 1.22.2 and 1.22.3 show the A-D converter-related registers.
Table 1.22.1. Performance of A-D Converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC1)
Operating clock φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
Resolution
8-bit or 10-bit (selectable)
Integral nonlinearity error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±3LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±7LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±5LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±7LSB
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN00 to AN07)
+ 8 pins (AN20 to AN27)
A-D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
• External trigger (retriggerable)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles 10-bit resolution: 59 AD cycles
• With sample and hold function
8-bit resolution: 28 AD cycles, 10-bit resolution: 33 φAD cycles
φ
,
φ
φ
Note 1: Does not depend on use of sample and hold function.
Note 2: The fAD frequency must be 10 MHz or less.
Without sample-and-hold function, limit the fAD frequency to 250kHZ or less.
With the sample and hold function, limit the fAD frequency to 1MHZ or less.
Note 3: If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
189
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D conversion rate
selection
CKS1=1
CKS2=0
øAD
CKS0=1
CKS0=0
CKS1=0
1/2
1/2
fAD
1/3
CKS2=1
TRG=0
Software trigger
A-D trigger
ADTRG
TRG=1
V
REF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
ADCON1 register
(address 03D716)
ADCON0 register
(address 03D616)
Addresses
(03C116 to 03C016
)
AD register 0(16)
(03C316 to 03C216
)
)
AD register 1(16)
AD register 2(16)
AD register 3(16)
(03C516 to 03C416
Decoder
for A-D register
(03C716 to 03C616
(03C916 to 03C816
(03CB16 to 03CA16
(03CD16 to 03CC16
(03CF16 to 03CE16
)
)
AD register 4(16)
AD register 5(16)
AD register 6(16)
)
)
)
AD register 7(16)
Data bus high-order
ADCON2 register
Data bus low-order
(address 03D416
)
PM00
PM01
V
ref
(Note)
Decoder
for channel
selection
Comparator
VIN
CH2 to CH0
=0002
Port P10 group
ADGSEL1 to ADGSEL0=002
OPA1 to OPA0=002
AN
0
1
2
3
4
5
6
7
=0012
=0102
AN
AN
AN
AN
AN
AN
AN
Port P0 group
CH2 to CH0
=0002
=0112
=1002
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
=1012
=1102
=0012
=0102
PM01 to PM00=002
ADGSEL1 to ADGSEL0=102
OPA1 to OPA0=002
=1112
=0112
=1002
=1012
=1102
PM01 to PM00=002
ADGSEL1 to ADGSEL0=112
OPA1 to OPA0=002
=1112
CH2 to CH0
=0002
Port P2 group
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
=0012
=0102
ADGSEL1 to ADGSEL0=002
OPA1 to OPA0=112
=0112
=1002
=1012
=1102
PM01 to PM00=002
ADGSEL1 to ADGSEL0=102
OPA1 to OPA0=112
=1112
PM01 to PM00=002
ADGSEL1 to ADGSEL0=112
OPA1 to OPA0=112
OPA1 to OPA0
=012
OPA0=1
OPA1=1
ANEX
0
1
OPA1=1
ANEX
Note: Port P0 group (AN00 to AN07) can be used as analog input pins even when PM01
to PM00 bits are set to “01 ” (memory expansion mode) and PM05 to PM04 bits are
set to “11 ” (multiplex bus allocated to the entire CS space).
2
2
Figure 1.22.1. A-D Converter Block Diagram
190
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
After reset
00000XXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
RW
RW
CH0
Analog input pin select bit Function varies with each operation mode
CH1
RW
RW
RW
RW
CH2
MD0
MD1
b4 b3
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
RW
RW
RW
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0
See Note 3 for the ADCON2 register
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
Bit symbol
Bit name
Function
RW
RW
A-D sweep pin select bit
Function varies with each operation mode
SCAN0
SCAN1
RW
RW
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
MD2
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
BITS
RW
RW
RW
CKS1
Frequency select bit 1
See Note 3 for the ADCON2 register
Vref connect bit (Note 2)
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
External op-amp
connection mode bit
Function varies with each operation mode
RW
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.2. ADCON0 to ADCON1 Registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0
0016
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
b2 b1
A-D input group select bit
ADGSEL0
ADGSEL1
0 0 : Port P10 group is selected
RW
RW
RW
RW
0 1 : Must not be set
1 0 : Port P0 group is selected (Note 3)
1 1 : Port P2 group is selected
Reserved bit
Must always be set to “0”
(b3)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
Frequency select bit 2
(Note 3)
CKS2
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
(b7-b5)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
Note 3: The ØAD frequency must be 10 MHz or less. The selected ØAD frequency is determined by a combination of
the ADCON0 register's CKS0 bit, ADCON1 register's CKS1 bit, and ADCON2 register's CKS2 bit.
CKS0 CKS1 CKS2
ØAD
0
0
0
Divide-by-4 of fAD
Divide-by-2 of fAD
0
0
0
1
1
0
f
AD
0
1
1
0
1
0
Ddivide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
1
1
1
0
1
1
1
0
1
Symbol
Address
After reset
A-D register i (i=0 to 7)
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
03C116 to 03C016 Indeterminate
03C316 to 03C216 Indeterminate
03C516 to 03C416 Indeterminate
03C716 to 03C616 Indeterminate
03C916 to 03C816 Indeterminate
03CB16 to 03CA16 Indeterminate
03CD16 to 03CC16 Indeterminate
03CF16 to 03CE16 Indeterminate
(b15)
b7
(b8)
b0 b7
b0
Function
RW
When the ADCON1 register's
BITS bit is “1” (10-bit mode)
When the ADCON1 register's
BITS bit is “0” (8-bit mode)
Eight low-order bits of
A-D conversion result
A-D conversion result
RO
RO
Two high-order bits of
A-D conversion result
When read, the content is
indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 1.22.3. ADCON2 Register, and AD0 to AD7 Registers
192
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot Mode
In this mode, the input voltage on one selected pin is A-D converted once. Table 1.22.2 shows the
specifications of one-shot mode. Figure 1.22.4 shows the ADCON0 to ADCON1 registers in one-shot
mode.
Table 1.22.2. One-shot Mode Specifications
Item
Specification
Function
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted once.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision • Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A-D conversion
Analog input pin (Note)
Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: If VCC2 < VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.
193
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog input pin select
bit
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
RW
RW
(Note 2)
(Note 3)
b4 b3
MD0
MD1
RW
RW
A-D operation mode
select bit 0
0 0 : One-shot mode
(Note 3)
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
RW
RW
RW
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0
See Note 3 for the ADCON2 register
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN to AN . Use the ADCON2 register’s
0
7
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
RW
RW
Invalid in one-shot mode
SCAN0
SCAN1
select bit
RW
RW
A-D operation mode
select bit 1
MD2
BITS
CKS1
Set to “0” when one-shot mode is selected
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
RW
See Note 3 for the ADCON2 register
Frequency select bit1
RW
RW
RW
RW
Vref connect bit (Note 2) 1 : Vref connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.4. ADCON0 Register and ADCON1 Register (One-shot Mode)
194
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
I
n this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 1.22.3 shows the
specifications of repeat mode. Figure 1.22.5 shows the ADCON0 to ADCON1 registers in repeat mode.
Table 1.22.3. Repeat Mode Specifications
Item
Specification
Function
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits or the ADCON1
register's OPA1 to OPA0 bits is A-D converted repeatdly.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pin (Note)
Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, ANEX0 to ANEX1
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: If VCC2 < VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.
195
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
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Under
M16C / 62P Group
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
1
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
RW
RW
b2 b1 b0
Analog input pin
select bit
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
CH1
RW
RW
(Note 2)
(Note 3)
CH2
b4 b3
MD0
MD1
RW
RW
A-D operation mode
select bit 0
0 1 : Repeat mode
(Note 3)
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
RW
RW
RW
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
See Note 3 for the ADCON2 register
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN to AN . Use the ADCON2 register’s
0
7
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
RW
RW
SCAN0
SCAN1
Invalid in repeat mode
select bit
RW
RW
A-D operation mode
select bit 1
Set to “0” when this mode is selected
MD2
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
BITS
CKS1
Frequency select bit 1
See Note 3 for the ADCON2 register
VCUT
OPA0
Vref connect bit (Note 2) 1 : Vref connected
RW
RW
b7 b6
External op-amp
0 0 : ANEX0 and ANEX1 are not used
connection mode bit
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.5. ADCON0 Register and ADCON1 Register (Repeat Mode)
196
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single Sweep Mode
I
n this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 1.22.4 shows
the specifications of single sweep mode. Figure 1.22.6 shows the ADCON0 to ADCON1 registers in
single sweep mode.
Table 1.22.4. Single Sweep Mode Specifications
Item
Specification
Function
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D con-
verted, one pin at a time.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision • Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A-D conversion
Analog input pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.
197
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
0
1
2
Bit symbol
Bit name
Function
RW
RW
RW
RW
Analog input pin
select bit
Invalid in single sweep mode
CH0
CH1
CH2
b4 b3
RW
RW
RW
MD0
MD1
A-D operation mode
select bit 0
1 0 : Single sweep mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
RW
RW
Frequency select bit 0
See Note 3 for the ADCON2 register
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
RW
RW
Bit symbol
Bit name
Function
A-D sweep pin select bit
When single sweep mode is selected
SCAN0
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
RW
(Note 2)
A-D operation mode
select bit 1
Set to “0” when single sweep mode is selected
RW
RW
MD2
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
VCUT
OPA0
See Note 3 for the ADCON2 register
Frequency select bit 1
RW
RW
Vref connect bit (Note 3) 1 : Vref connected
b7 b6
External op-amp
connection mode
bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
RW
RW
OPA1
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN to AN . Use the ADCON2 register’s
0
7
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.6. ADCON0 Register and ADCON1 Register (Single Sweep Mode)
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A-D Converter
(4) Repeat Sweep Mode 0
In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 1.22.5 shows the
specifications of repeat sweep mode 0. Figure 1.22.7 shows the ADCON0 to ADCON1 registers in repeat
sweep mode 0.
Table 1.22.5. Repeat Sweep Mode 0 Specifications
Item
Specification
Function
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits and ADCON2 register's ADGSEL1 to ADGSEL0 bits are A-D con-
verted repeatdly.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
RW
RW
Analog input pin
select bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
RW
RW
b4 b3
MD0
MD1
A-D operation mode
select bit 0
RW
RW
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
RW
RW
RW
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
See Note 3 for the ADCON2 register
Frequency select bit 0
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
RW
RW
Bit symbol
SCAN0
Bit name
Function
A-D sweep pin select bit When repeat sweep mode 0 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
SCAN1
(6 pins)
(8 pins)
RW
(Note 2)
Set to “0” when repeat sweep mode 0 is
selected
A-D operation mode
select bit 1
RW
RW
MD2
BITS
0 : 8-bit mode
1 : 10-bit mode
8/10-bit mode select bit
CKS1
VCUT
OPA0
RW
RW
RW
Frequency select bit 1
See Note 3 for the ADCON2 register
Vref connect bit (Note 3) 1 : Vref connected
b7 b6
External op-amp
connection mode
bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
OPA1
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN to AN . Use the ADCON2 register’s
0
7
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.7. ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(5) Repeat Sweep Mode 1
In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the se-
lected pins. Table 1.22.6 shows the specifications of repeat sweep mode 1. Figure 1.22.8 shows the
ADCON0 to ADCON1 registers in repeat sweep mode 1.
Table 1.22.6. Repeat Sweep Mode 1 Specifications
Item
Specification
Function
The input voltages on all pins selected by the ADCON2 register's ADGSEL1 to
ADGSEL0 bits are A-D converted repeatdly, with priority given to pins se-
lected by the ADCON1 register's SCAN1 to SCAN0 bits and ADGSEL1 to
ADGSEL0 bits.
Example : If AN0 selected, input voltages are A-D converted in order of
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision Set the ADST bit to “0” (A-D conversion halted)
Interrupt request generation timing None generated
Analog input pins to be given
priority when A-D converted
Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3
(4 pins) (Note)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Note: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN0 to AN7. However, if VCC2 <
VCC1, do not use AN00–AN07 and AN20–AN27 as analog input pins.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
Analog input pin
select bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
RW
RW
Frequency select bit 0
See Note 3 for the ADCON2 register
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
1
RW
RW
Bit symbol
SCAN0
Bit name
Function
A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
1
SCAN1
to AN
to AN
2
3
(3 pins)
(4 pins)
RW
(Note 2)
A-D operation mode
select bit 1
Set to “1” when repeat sweep mode 1 is
selected
MD2
BITS
CKS1
RW
RW
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
See Note 3 for the ADCON2 register
RW
RW
RW
VCUT
OPA0
Vref connect bit (Note 3) 1 : Vref connected
b7 b6
External op-amp
connection mode
bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
OPA1
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07, and AN20 to AN27 can be used in the same way as AN to AN . Use the ADCON2 register’s
0
7
ADGSEL1 to ADGSEL0 bits to select the desired pin. However, if VCC2 < VCC1, do not use AN00 to AN07 and
AN20 to AN27 as analog input pins.
Note 3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 1.22.8. ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1)
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A-D Converter
(a) Resolution Select Function
The desired resolution can be selected using the ADCON1 register’s BITS bit. If the BITS bit is set to “1”
(10-bit conversion accuracy), the A-D conversion result is stored in the ADi register (i = 0 to 7)'s bit 0 to bit
9. If the BITS bit is set to “0” (8-bit conversion accuracy), the A-D conversion result is stored in the ADi
register's bit 0 to bit 7.
(b) Sample and Hold
If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is
increased to 28 ØAD cycles for 8-bit resolution or 33 ØAD cycles for 10-bit resolution. Sample-and-hold is
effective in all operation modes. Select whether or not to use the sample-and-hold function before starting
A-D conversion.
(c) Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the
ADCON1 register’s OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1.
The A-D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
(d) External Operation Amp Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the ADCON1 register’s OPA1 OPA0 bits to ‘112’ (external op-amp connection mode). The inputs from
(Note 1)
ANi (i = 0 to 7)
are output from the ANEX0 pin. Amplify this output with an external op-amp before
sending it back to the ANEX1 pin. The A-D conversion result is stored in the corresponding ADi register.
The A-D conversion speed depends on the response characteristics of the external op-amp. Note that the
ANXE0 and ANEX1 pins cannot be directly connected to each other. Figure 1.22.9 is an example of how
to connect the pins in external operation amp.
Note: AN0i and AN2i can be used the same as ANi. However, if VCC2 < VCC1, do not use AN0i and AN2i as
analog input pins.
Microcomputer
ADCON2 register's ADGSEL1 to ADGSEL0 bits=00
2
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Resistor ladder
Successive conversion
register
ADGSEL1 to ADGSEL0 bits=10
2
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
ADGSEL1 to ADGSEL0 bits=11
2
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
ANEX0
ANEX1
Comparator
External op-
amp
Figure 1.22.9. External Op-amp Connection
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(e) Current Consumption Reducing Function
When not using the A-D converter, its resistor ladder and reference voltage input pin (VREF) can be
separated using the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin
into the resistor ladder, helping to reduce the power consumption of the chip.
To use the A-D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s
ADST bit to “1” (A-D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A-D conversion.
Note that this does not affect VREF for the D-A converter (irrelevant).
(f) Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 1.22.10 shows analog input pin and external sensor equivalent circuit example.
Microcomputer
Sensor equivalent
circuit
R0
R (7.8kΩ)
VIN
Sampling time
C (3.0pF)
3
AD
Sample-and-hold function enabled:
VC
f
2
AD
Sample-and-hold function disabled:
f
Figure 1.22.10. Analog Input Pin and External Sensor Equivalent Circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(g) Caution of Using A-D Converter
(1) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit
___________
for the ADTRG pin is set to “0” (input mode).
(2) When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
(3) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i=0 to 7), AN0i, and AN2i) each and
the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 1.22.11 is an
example connection of each pin.
(4) If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
(5) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the IR
bit in the ADIC register to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(6) If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit
to “0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The con-
tents of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D con-
version is underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
Microcomputer
V
V
CC1
SS
AVCC
C4
V
REF
C2
C1
C3
AVSS
ANi
V
V
CC2
SS
C5
ANi: ANi, AN
0i, and AN
2i (i=0 to 7)
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 1.22.11. VCC, VSS, AVCC, AVSS, VREF and ANi Connection
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. These are two independent D-A converters.
D-A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set
the DACON register’s DAiE bit to “1” (output enabled). Before D-A conversion can be used, the correspond-
ing port direction bit must be cleared to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from
the corresponding port.
Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.23.1 lists the performance of the D-A converter. Figure 1.23.1 shows the block diagram of the D-A
converter. Figure 1.23.2 shows the D-A converter related registers. Figure 1.23.3 shows the D-A converter
equivalent circuit.
Table 1.23.1. D-A Converter Performance
Item
D-A conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 (DA0 and DA1)
Data bus low-order
DA0 register
R-2R resistor ladder
DA0
DA0E bit
DA1 register
R-2R resistor ladder
DA1
DA1E bit
Figure 1.23.1. D-A Converter Block Diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A control register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DC16
After reset
0016
Bit symbol
DA0E
Bit name
Function
RW
RW
0 : Output disabled
1 : Output enabled
D-A0 output enable bit
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
RW
RW
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”
(b7-b2)
Note: When not using the D-A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to ‘0016’ to prevent current from
flowing into the R-2R resistor ladder.
D-Ai register (Note) (i= 0 to 1)
Symbol
DA0
DA1
Address
03D816
03DA16
After reset
Indeterminate
Indeterminate
b7
b0
Function
RW
Output value of D-A conversion
RW
Note: When not using the D-A converter, clear the DAiE bit (i = 0 to 1) to “0” (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to ‘0016’ to prevent current from
flowing into the R-2R resistor ladder.
Figure 1.23.2. DACON Register, DA0 Register, and DA1 Register
DAiE bit
“0”
R
R
R
R
R
R
R
R
2R
DAi
“1”
2R
MSB
2R
2R
2R
2R
2R
2R
2R
LSB
DAi register
“0”
“1”
AVSS
VREF
Note: The above diagram shows an instance in which the DA0 register is assigned “2A16”.
Figure 1.23.3. D-A Converter Equivalent Circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation
CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses
16
12
5
a generator polynomial of CRC_CCITT (X + X + X + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8
bit units. After the initial value is set in the CRCD register, the CRC code is set in that register each time one
byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two
cycles.
Figure 1.24.1 shows the block diagram of the CRC circuit. Figure 1.24.2 shows the CRC-related registers.
Figure 1.24.3 shows the calculation example using the CRC operation.
Data bus high-order
Data bus low-order
Eight low-order bits
CRCD register
Eight high-order bits
CRC code generating circuit
16
12
5
x
+ x + x + 1
CRCIN register
Figure 1.24.1. CRC Circuit Block Diagram
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
After reset
b0
03BD16 to 03BC16 Indeterminate
Setting range
Function
RW
RW
When data is written to the CRCIN register after setting
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.
000016 to FFFF16
CRC input register
b7
b0
Symbo
CRCIN
Address
03BE16
After reset
Indeterminate
Setting range
0016 to FF16
Function
RW
RW
Data input
Figure 1.24.2. CRCD Register and CRCIN Register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation
Setup procedure and CRC operation when generating CRC code “80C416
”
(a) CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
16
12
5
Generator polynomial: X + X + X + 1 (1 0001 0000 0010 0001
2
)
(b) Setting procedure
(1) Reverse the bit positions of the value “80C416” bytewise in a program.
“8016 “0116”, “C416 “2316
”
”
”
→
→
b15
b0
b0
(2) Write 000016 (initial value)
(3) Write 0116
CRCD register
CRCIN register
b7
Two cycles later, the CRC code for “8016,” i.e.,
918816, has its bit positions reversed to become
“118916” which is stored in the CRCD register.
b0
b0
b15
CRCD register
118916
b7
(4) Write 2316
CRCIN register
Two cycles later, the CRC code for “80C416,” i.e.,
825016, has its bit positions reversed to become
“0A4116” which is stored in the CRCD register.
b15
b0
CRCD register
0A4116
(c) Details of CRC operation
In the case of (3) above, the value written to the CRCIN register “0116 (00000001
2)” has its bit positions reversed to
become “10000000 .” The value “1000 0000 0000 0000 0000 0000 ” derived from that by adding 16 digits and the
2
2
CRCD register’s initial value “000016” are added, the result of which is divided by the generator polynomial using
modulo-2 arithmetic.
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
Data
1 0001 0000 0010 0001
Generator polynomial
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
CRC code
The value “0001 0001 1000 1001
2
(118916)” derived from the remainder “1001 0001 1000 1000
2
(918816)” by
reversing its bit positions may be read from the CRCD register.
If operation (4) above is performed subsequently, the value written to the CRCIN register “2316 (00100011
positions reversed to become “11000100 . The value “1100 0100 0000 0000 0000 0000 ” derived from that by adding
16 digits and the remainder in (3) “1001 0001 1000 1000 ” which is left in the CRCD register are added, the result of
which is divided by the generator polynomial using modulo-2 arithmetic.
2)” has its bit
2
2
2
The value “0000 1010 0100 0001
from the CRCD register.
2 (0A4116)” derived from the remainder by reversing its bit positions may be read
Figure 1.24.3. CRC Calculation
209
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Under
Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 87 lines P0 to
P10 (except P85) for the 100-pin version, or 113 lines P0 to P14 (except P85) for the 128-pin version. Each
port can be set for input or output every line by using a direction register, and can also be chosen to be or
not be pulled high every 4 lines. P85 is an input-only port and does not have a pull-up resistor. Port P85
_______
______
shares the pin with NMI, so that the NMI input level can be read from the P8 register P8_5 bit.
Figures 1.25.1 to 1.25.4 show the I/O ports. Figure 1.25.5 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input or D-A converter output pin, set the direction bit for that pin to “0” (input
mode). Any pin used as an output pin for peripheral functions other than the D-A converter is directed for
output no matter how the corresponding direction bit is set.
When using any pin as a bus control pin, refer to “Bus Control.”
P0 to P5, P12, and P13 are capable of VCC2-level input/output; P6 to P11 and P14 are capable of VCC1-
level input/output.
(1) Port Pi Direction Register (PDi Register, i = 0 to 13)
Figure 1.25.6 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 0 to 13)
Figure 1.25.7 and 1.25.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 1.25.9 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high
in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory
extension and microprocessor modes. Although the register contents can be modified, no pull-up resis-
tors are connected.
(4) Port Control Register
Figure 1.25.10 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.
210
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up selection
Direction register
P0
0
to P0
7
, P2
0
to P2
to P4
7
7
(inside dotted-line
included)
Port latch
Data bus
P3
P5
0
0
to P3
to P5
7, P4
0
6
,
4, P5
,
(Note 1)
P11
P12
P13
P14
0
0
0
0
to P11
to P12
to P13
7
7
7
(Note 2),
(Note 2),
(Note 2),
(inside dotted-line
not included)
, P141(Note 2)
Analog input
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Port latch
Data bus
(Note 1)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction
register
P5
P8
7
0
, P6
, P8
0
1
, P6
, P9
4
, P7
3
2
to P76,
"1"
0, P9
Output
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2: Available in only the 128-pin version.
Figure 1.25.1. I/O Ports (1)
211
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up selection
Direction
register
P61, P6
5
, P7
2
"1"
Output
Port latch
Data bus
(Note 1)
Switching
between
CMOS and
Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P8
2
to P8
4
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P7
7, P9
1, P97
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2: Available in only the 128-pin version.
Figure 1.25.2. I/O Ports (2)
212
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up selection
Direction register
P62, P66
Port latch
Data bus
(Note 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
“1”
Output
Port latch
Data bus
(Note 1)
Switching between CMOS and Nch
P8
5
Data bus
(Note 1)
NMI interrupt input
Direction register
P70, P7
1
“1”
Output
Data bus
Port latch
(Note 2)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
symbolizes a parasitic diode.
Note 2:
Figure 1.25.3. I/O Ports (3)
213
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up selection
Direction register
P100 to P103
(inside dotted-line
not included)
P104 to P107
(inside dotted-line
included)
Data bus
Port latch
(Note)
Analog input
Input to respective peripheral functions
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog output
D-A output enabled
Pull-up selection
Direction register
P9
6
“1”
Output
Data bus
Port latch
(Note)
Analog input
Pull-up selection
Direction register
P9
5
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog input
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 1.25.4. I/O Ports (4)
214
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up selection
Direction register
P8
7
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Direction register
Rd
P8
6
"1"
Output
Data bus
Port latch
(Note)
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 1.25.5. I/O Ports (5)
(Note 2)
BYTE
BYTE signal input
(Note 1)
(Note 2)
(Note 1)
CNVSS
CNVSS signal input
RESET
Note 1:
RESET signal input
(Note 1)
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2: A parasitic diode on the VCC side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed Vcc.
Figure 1.25.6. I/O Pins
215
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Port Pi direction register (i=0 to 7 and 9 to 13) (Note 1, 2, 3)
Symbol
PD0 to PD3
PD4 to PD7
PD9 to PD12
PD13
Address
After reset
0016
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03EE16, 03EF16
03F316, 03F616, 03F716, 03FA16
03FB16
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
0016
Bit symbol
Bit name
Function
RW
PDi_0
PDi_1
PDi_2
PDi_3
Port Pi
0
direction bit
direction bit
direction bit
direction bit
RW
RW
RW
RW
RW
RW
RW
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
Port Pi
1
2
3
Port Pi
Port Pi
(Functions as an output port)
(i = 0 to 7 and 9 to 13)
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi
Port Pi
Port Pi
Port Pi
4
5
6
7
direction bit
direction bit
direction bit
direction bit
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register’s PRC2 bit to “1” (write enabled).
Note 2: During memory extension and microprocessor modes, the PD register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 pins are placed in the high-impedance state.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
After reset
00X00000
2
RW
RW
RW
Bit symbol
PD8_0
Bit name
Function
Port P8
0
direction bit
direction bit
direction bit
direction bit
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_1
PD8_2
PD8_3
PD8_4
Port P8
Port P8
Port P8
Port P8
1
2
3
4
RW
RW
RW
(Functions as an output port)
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b5)
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
Port P8
Port P8
6
direction bit
direction bit
RW
RW
PD8_7
7
(Functions as an output port)
Figure 1.25.7. PD0 to PD13 Registers
216
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Port Pi register (i=0 to 7 and 9 to 13) (Note 2, 3)
Symbol
P0 to P3
P4 to P7
P9 to P12
P13
Address
After reset
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03EC16, 03ED16
03F116, 03F416, 03F516, 03F816
03F916
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
bit
bit
bit
bit
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
bit
bit
bit
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7 and 9 to 13)
Note 1: Since P7
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A to A19, D to D15, CS to CS , RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
0 and P71 are N-channel open drain ports, the data is high-impedance.
0
0
0
3
Note 3: To use ports P11 to P14, set the PUR3 register’s PU37 bit to “1” (enable). If this bit is set to
“0” (disable), the P11 to P14 registers are cleared to ‘0016’ and the P11 to P14 pins are
placed in the high-impedance state.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
After reset
Indeterminate
RW
RW
RW
RW
Bit symbol
P8_0
Bit name
Function
Port P8
0
bit
bit
bit
bit
bit
bit
bit
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
P8_1
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
1
2
3
4
5
6
7
P8_2
P8_3
RW
RW
P8_4
P8_5
RO
RW
RW
this register (except for P8
0 : “L” level
5)
P8_6
1 : “H” level
P8_7
Figure 1.25.8. P0 to P13 Registers
217
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Port P14 control register (128-pin package)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PC14
Address
03DE16
After reset
XX00XXXX
2
Bit symbol
P140
Bit name
Function
RW
RW
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
Port P14
0
bit
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
P141
Port P14
1
bit
RW
0 : “L” level
1 : “H” level
Nothing is assigned. In an attempt to write to this bit, write “0”. The
value, if read, turns out to be indeterminate.
(b3-b2)
PD140
0 : Input mode
RW
RW
Port P14
0
direction bit
(Functions as an input port)
1 : Output mode
(Functions as an output port)
PD141
(b7-b6)
Port P141 direction bit
Nothing is assigned. In an attempt to write to this bit, write “0”. The
value, if read, turns out to be indeterminate.
Pull-up control register 3 (128-pin package)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR3
Address
03DF16
After reset
0016
RW
Bit symbol
PU30
Bit name
Function
P11
P11
0
4
to P11
3
7
pull-up
RW
RW
0 : Not pulled high
1 : Pulled high (Note 1)
PU31
to P11
pull-up
PU32
PU33
PU34
PU35
P12
P12
P13
P13
0
4
0
4
to P12
to P12
to P13
to P13
3
7
3
7
pull-up
pull-up
pull-up
pull-up
RW
RW
RW
RW
RW
PU36
PU37
P14
0
, P14
1
pull-up
0 : Unusable (Note 2)
1 : Usable
P11 to P14 enabling bit
RW
Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 2: If the PU37 bit is set to “0” (unusable), the P11 to P14 pins are placed in the high-impedance state and
the P11 to P14 registers are cleared to “0”.
Figure 1.25.9. PC14 Register and PUR3 Register
218
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
After reset
0016
Bit symbol
PU00
Bit name
Function
0 : Not pulled high
RW
RW
RW
RW
RW
RW
RW
RW
RW
P0
0
to P0
3
pull-up
PU01
PU02
PU03
PU04
PU05
PU06
PU07
P0
P1
P1
P2
P2
P3
P3
4
0
4
0
4
0
4
to P0
to P1
to P1
to P2
to P2
to P3
to P3
7
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
1 : Pulled high (Note 2)
Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their
corresponding register contents can be modified.
Note 2: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
After reset(Note 5)
000000002
000000102
Bit symbol
PU10
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
P4
0
to P4
3 pull-up (Note 2)
0 : Not pulled high
1 : Pulled high (Note 3)
PU11
PU12
PU13
PU14
PU15
P4
P5
P5
P6
P6
4
to P4
7
pull-up (Note 4)
pull-up (Note 2)
pull-up (Note 2)
pull-up
0
4
0
4
to P5
to P5
to P6
to P6
3
7
3
7
pull-up
PU16
PU17
P7
2
to P7
3
pull-up (Note 1)
pull-up
P7
4
to P7
7
Note 1: The P70 and P71 pins do not have pull-ups.
Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents
of these bits can be modified.
Note 3: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 4: If the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor mode) in a
program during single-chip mode, the PU11 bit becomes “1”.
Note 5: The values after hardware reset 1 and 2 are as follows:
• 00000000
• 00000010
2
when input on CNVss pin is “L“
when input on CNVss pin is “H“
2
The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows:
• 00000000
• 00000010
2
when PM 01 to PM00 bits of PM0 register are “00
when PM 01 to PM00 bits of PM0 register are “01
2
“ (single-chip mode)
“ (memory expansion mode) or
2
2
“112“ (microprocessor mode)
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
After reset
0016
Bit symbol
PU20
Bit name
Function
RW
RW
RW
RW
P8
0
4
to P8
3
pull-up
0 : Not pulled high
1 : Pulled high (Note 1)
PU21
PU22
P8
to P8
7
pull-up (Note 2)
pull-up
P9
P9
P10
P10
0
to P9
3
PU23
PU24
4
to P9
7
pull-up
RW
RW
RW
0
to P10 pull-up
3
PU25
4
to P107 pull-up
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b7-b6)
Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 2: The P8 pin does not have pull-up.
5
Figure 1.25.10. PUR0 to PUR2 Registers
219
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Programmable I/O Ports
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PCR
Address
03FF16
After reset
0016
Bit symbol
PCR0
Bit name
Function
RW
RW
Port P1 control bit
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
(b7-b1)
Figure 1.25.11. PCR Register
220
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Programmable I/O Ports
Table 1.25.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 2)
Ports P0 to P14
(excluding P85)
XOUT (Note 1)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
Connect to VSS
Note 1: With external clock input to XIN pin.
Note 2: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3
register’s PU37 bit to “0” (unusable) without causing any problem.
Table 1.25.2. Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin name
Connection
Ports P6 to P10
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
(excluding P8
5)
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
corresponding direction bit for CSi (i=1 to 3) to “0” (input mode) and the
CSR register’s CSi bit to “0” (chip select disabled).
P4 / CS1 to P47 / CS3
5
Open
BHE, ALE, HLDA,
OUT (Note 1), BCLK (Note 2)
X
Connect via resistor to VCC (pull-up)
Connect to VCC
HOLD, RDY, NMI
AVCC
AVSS, VREF
Connect to VSS
Note 1: With external clock input to XIN pin.
Note 2: If the PM0 register’s PM07 bit is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
Note 3: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3
register’s PU37 bit to “0” (unusable) without causing any problem.
221
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Specifications in this manual are tentative and subject to change.
development
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Microcomputer
Microcomputer
Port P6 to P14 (except for P85)
Port P0 to P14 (except for P85)
(Note 2)
(Note 2)
(Input mode)
(Input mode)
·
·
·
·
·
·
·
·
·
·
·
·
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
NMI
NMI
BHE
HLDA
ALE
Port P45 / CS1
to P47 / CS3
XOUT
Open
Open
VCC
VCC
XOUT
AVCC
BYTE
AVSS
VREF
BCLK (Note)
HOLD
RDY
AVCC
AVSS
VREF
VSS
VSS
In memory expansion mode or
in microprocessor mode
In single-chip mode
Note 1: If the PM0 register’s PM07 bit is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
Note 2: When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PUR3
register’s PU37 bit to “0” (unusable) without causing any problem.
Figure 1.25.12. Unassigned Pins Handling
222
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Electrical Characteristics
Table 1.26.1. Absolute Maximum Ratings
Symbol
VCC1, VCC2
VCC2
Parameter
Condition
VCC1=AVCC
Rated value
Unit
V
Supply voltage
Supply voltage
-0.3 to 6.5
-0.3 to VCC1+0.1
V
VCC2
AVCC
Analog supply voltage
VCC1=AVCC
-0.3 to 6.5
V
RESET, CNVSS, BYTE,
Input
P60 to P67, P72 to P77, P80 to P87,
P90 to P97, P100 to P107, P110 to P117,
P140, P141,
voltage
-0.3 to VCC1+0.3
V
VI
VREF, XIN
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P120 to P127, P130 to P137
-0.3 to VCC2+0.3
-0.3 to 6.5
V
V
V
P70, P71
Output
voltage
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P110 to P117, P140, P141,
XOUT
-0.3 to VCC1+0.3
VO
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P120 to P127, P130 to P137
-0.3 to VCC2+0.3
V
P70, P71
V
mW
C
-0.3 to 6.5
300
C
Topr=25
Pd
Power dissipation
Topr
Tstg
Operating ambient temperature
Storage temperature
-20 to 85 / -40 to 85
-65 to 150
C
223
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.26.2. Recommended Operating Conditions (Note 1)
Standard
Unit
Symbol
Parameter
Min.
Typ.
Max.
V
CC1, VCC2 Supply voltage(VCC1
≥
VCC2
)
2.7
5.0
5.5
V
AVcc
Vss
Analog supply voltage
Supply voltage
V
CC1
0
V
V
AVss
Analog supply voltage
0
V
V
0.8VCC2
0.8VCC2
V
V
CC2
CC2
P3
P0
P0
1
0
0
to P3
to P0
to P0
7
7
7
, P4
, P1
, P1
0
0
0
to P4
to P1
to P1
7
7
7
, P5
, P2
, P2
0
0
0
to P57, P12
0
to P12
7, P130 to P137
HIGH input
voltage
to P2
to P2
7
, P3
, P3
0
(during single-chip mode)
V
V
7
0
0.5VCC2
V
CC2
VIH
(data input function during memory expansion and microprocessor modes)
P6 to P6 , P7 to P7 , P8 to P8 , P9 to P9 , P10 to P10
P11 to P11 , P14 , P14
IN, RESET, CNVSS, BYTE
0
7
2
7
0
7
0
7
0
7,
0.8VCC1
0.8VCC1
V
CC1
V
V
0
7
0
1,
X
P7
0
, P7
1
6.5
LOW input
voltage
P3
1
to P3
to P0
to P0
7
, P4
, P1
, P1
0
to P4
to P1
to P1
7
, P5
, P2
, P2
0
to P57, P12
0
to P12
7, P130 to P137
0
0
0.2VCC2
0.2VCC2
V
V
P0
P0
0
0
7
7
0
0
7
7
0
0
to P2
to P2
7
, P3
, P3
0
(during single-chip mode)
7
0
0
V
IL
0.16VCC2
0.2VCC1
-10.0
V
(data input function during memory expansion and microprocessor modes)
P6
P11
IN, RESET, CNVSS, BYTE
0
to P6
7
, P7
0
to P77, P80 to P87, P90 to P97, P100 to P107,
V
0
to P11
7, P14
0, P14
1,
0
X
HIGH peak output
current
P0
P4
P8
0
0
0
to P0
to P4
to P84,P86,P87,P9
7, P1
0
0
to P1
to P5
7
, P2
0
0
to P2
to P6
7
,P30 to P3
,P72 to P7
7,
IOH (peak)
mA
mA
7, P5
7, P6
7
7,
0
to P97,P10
, P13
0
to P10
7
,
P11
0
to P11 , P12 to P12
7
0
7
0
to P13
7
, P14
0
, P14
1
1
1
1
HIGH average
output current
P0
P4
P8
0
0
0
to P0
to P4
to P84,P86,P87,P9
7, P1
0
0
to P1
to P5
7
, P2
0
to P2
to P6
7
,P30 to P3
,P72 to P7
7
7
,
,
,
IOH (avg)
7, P5
7, P6
0
7
-5.0
0
to P97,P10
0
to P107
P11
0
to P11 , P12 to P12
7
0
7, P13
0
to P13
7, P14
0
0
0
, P14
, P14
, P14
LOW peak output
current
P0
P4
P8
0
0
0
to P0
to P4
to P84,P86,P87,P9
7, P1
0
0
to P1
to P5
7
, P2
0
0
to P2
to P6
7
,P30 to P3
,P70 to P7
7
7
,
,
,
7, P5
7, P6
7
IOL (peak)
10.0
mA
mA
0
to P97,P10
0
to P107
P11
0
to P11 , P12 to P12
7
0
7, P13
0
to P137, P14
LOW average
output current
P0
P4
P8
0
0
0
to P0
to P4
to P84,P86,P87,P9
7, P1
0
0
to P1
to P5
7
, P2
0
0
to P2
to P6
7
,P30 to P3
,P70 to P7
7
7
,
,
,
IOL (avg)
5.0
16
7, P5
7, P6
7
0
to P97,P10
0
to P107
P11
0
to P11 , P12 to P12
7
0
7, P13
0
to P137, P14
V
V
CC=3.0 to 5.5V
CC=2.7 to 3.0V
MHz
MHz
kHz
0
0
Main clock input oscillation frequency
(Note 4)
f (XIN
)
20 X VCC-44
50
f (XCIN
)
Sub-clock oscillation frequency
Ring oscillation frequency
32.768
1
f (Ring)
f (PLL)
MHz
MHz
MHz
V
V
CC=3.0 to 5.5V
CC=2.7 to 3.0V
24
PLL clock oscillation frequency (Note 4)
10
10
46.67 X VCC
-
116
24
MHz
ms
f (BCLK)
CPU operation clock
0
V
V
CC=5.0V
CC=3.0V
T
SU(PLL)
PLL frequency synthesizer stabilization wait time
20
50
ms
Note 1: Referenced to VCC = VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P8
for ports P3, P4, P5, P6, P7, P8 to P8 , P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2
must be -40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for
6, P87, P9, P10, P11, P140 and P141 must be 80mA max. The total IOL (peak)
0
4
ports P6, P7, and P80 to P84 must be -40mA max. The total IOH (peak) for ports P86, P87, P9, P10, P11, P140, and P141
must be -40mA max.
Note 4: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
PLL clock oscillation frequency
46.67 x VCC-116MH
Main clock input oscillation frequency
20 x VCC-44MH
Z
24.0
Z
16.0
10.0
10.0
0.0
0.0
2.7
3.0
5.5
2.7
3.0
5.5
Supply voltage[V] (main clock: no division)
Supply voltage[V] (PLL clock oscillation)
224
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.26.3. A-D Conversion Characteristics (Note 1)
Standard
Unit
Symbol
–
Parameter
Measuring condition
Min. Typ. Max.
Resolution
V
REF =VCC1
10
Bits
AN0 to AN7 input
±3
LSB
V
V
5V
REF
=
=
ANEX0, ANEX1 input
External operation amp
connection mode
CC1
Integral
non-
linearity
error
±7
LSB
INL
10 bit
AN00 to AN07 input
AN20 to AN27 input
AN0 to AN7 input
±5
±7
LSB
LSB
V
V
3.3V
REF
=
=
ANEX0, ANEX1 input
External operation amp
connection mode
CC1
AN00 to AN07 input
AN20 to AN27 input
±2
±1
±3
±3
40
LSB
LSB
V
REF =VCC1=3.3V
8 bit
Differential non-linearity error
DNL
–
–
Offset error
LSB
LSB
kΩ
Gain error
Ladder resistance
10
R
LADDER
V
REF =VCC1
Conversion time(10bit), Sample & hold
function available
3.3
µs
t
CONV
V
REF =VCC1=5V, øAD=10MHz
Conversion time(8bit), Sample & hold
function available
2.8
µs
V
REF =VCC1=5V, øAD=10MHz
t
t
V
V
CONV
SAMP
Sampling time
0.3
2.0
0
µs
V
REF
IA
Reference voltage
Analog input voltage
V
CC1
V
V
REF
Note 1: Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: If VCC1 > VCC2, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
Note 3: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC1 is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 4: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 3.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 3.
Table 1.26.4. D-A Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
8
Symbol
Parameter
Measuring condition
Unit
–
–
Bits
%
Resolution
1.0
3
Absolute accuracy
t
su
µs
Setup time
R
O
4
10
20
kΩ
Output resistance
IVREF
(Note 2)
1.5
mA
Reference power supply input current
Note 1: Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The
A-D converter’s ladder resistance is not included. Also, when D-A register contents are not “0016”, the current
IVREF always flows even though Vref may have been set to be unconnected by the A-D control register.
Table 1.26.5. Flash Memory Version Electrical Characteristics (Note 1)
Standard
Parameter
Unit
Min.
Typ.
30
Max
200
4
Word program time
µs
s
Block erase time
1
Erase all unlocked blocks time
Lock bit program time
1 X n
30
4 X n
200
s
µs
Note 1: Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C unless otherwise specified.
Note 2: n denotes the number of block erases.
Table 1.26.6. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60oC)
Flash program, erase voltage
CC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V
Flash read operation voltage
CC1=2.7 to 5.5 V
V
V
225
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.26.7. Low Voltage Detection Circuit Electrical Characteristics (Note 1
)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
3.3
Max.
4.4
Power supply down detection voltage (Notes 1, 2)
Reset level detection voltage (Notes 1, 2)
Vdet4
Vdet3
3.8
2.8
V
V
2.2
3.6
V
CC1=0.8 to 5.5V
V
V
V
Low voltage reset retention voltage
0.8
2.2
1.4
Vdet3s
Vdet3r
Vdet2
2.9
2.0
4.0
2.7
Low voltage reset release voltage (Note 3)
RAM retention limit detection voltage (Notes 1, 2)
Note 1: Vdet4 > Vdet3 > Vdet2
Note 2: Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the
operation at f(BCLK) ≤ 10MHz is guaranteed.
Note 3: Vdet3r > Vdet3 is not guaranteed.
Table 1.26.8. Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
ms
Min.
Max.
2
td(P-R)
td(R-S)
td(M-L)
td(S-R)
td(E-A)
Time for internal power supply stabilization during powering-on
STOP release time
150
µs
µs
V
CC1=2.7 to 5.5V
Time for internal power supply stabilization when main clock oscillation starts
50
20
20
V
CC1=Vdet3r to 5.5V
CC1=2.7 to 5.5V
6 (Note)
Hardware reset 2 release wait time
ms
µs
Low voltage detection circuit operation start time
V
Note : When Vcc1 = 5V
Vdet3r
V
CC1
td(S-R)
Interrupt for
stop mode
release
CPU clock
td(R-S)
226
Mitsubishi microcomputers
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Table 1.26.9. Electrical Characteristics (Note 1
)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
V
Min.
Max.
P6
P10
0
to P6
7
,P72
to P77,P8
0
to P8
4
,P8
,P14
,P3
,P13
,P8 ,P8
,P14
,P3
to P12 ,P13
6
,P8
7
,P9
0
to P9
7
,
HIGH output
voltage
I
I
OH=-5mA
V
CC1-2.0
V
V
V
CC1
CC2
CC1
0
to P10
7,P11
0
to P11
7,P14
0
1
V
V
OH
OH
P0
P4
P6
P10
P0
P4
0
0
to P0
to P4
to P6
7
,P1
,P5
,P7
0
to P1
to P5
to P7
7
,P2
,P12
,P8
0
to P2
7
0
to P3
to P13
,P9 to P9
7,
OH=-5mA(Note 2)
V
V
CC2-2.0
CC1-0.3
7
0
7
0
to P12
to P8
,P14
to P2
7
0
7
0
7
2
7
0
4
6
7
0
7,
HIGH output
voltage
I
I
OH=-200µA
0
to P10
7,P11
0
to P11
7
0
1
V
0
to P0
to P4
7
,P10
to P17,P2
0
7
0
to P3
0
7,
OH=-200µA(Note 2)
V
CC2-0.3
V
CC2
0
7
,P50
to P57,P12
0
7
to P13
7
HIGHPOWER
LOWPOWER
I
I
OH=-1mA
V
V
CC1-2.0
CC1-2.0
V
V
CC1
CC1
HIGH output voltage
HIGH output voltage
X
OUT
V
V
OH=-0.5mA
VOH
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
X
COUT
P6
P10
0
to P6
7
,P7
0
to P7
7
,P8
0
to P8
4
,P8
,P14
,P3
,P13
,P8 ,P8
,P14
,P3
to P12 ,P13
6
,P8
7
,P9
0
to P9
7
,
,
LOW output
voltage
I
OL=5mA
2.0
2.0
0
to P10
7,P11
0
to P11
7
,P14
0
1
V
V
OL
OL
V
V
P0
P4
P6
0
0
0
to P0
to P4
to P6
7,P1
7,P5
7
,P7
0
0
0
to P1
to P5
to P7
7
7
7
,P2
,P12
,P8
0
to P2
7
0
to P3
to P13
,P9 to P9
7,
I
I
I
OL=5mA(Note 2)
OL=200µA
0
to P12
to P8
,P14
to P2
7
0
7
0
4
6
7
0
7
LOW output
voltage
0.45
0.45
P10
0
to P10
7,P11
0
to P11
7
0
1
P0
P4
0
0
to P0
to P4
7,P1
0
0
to P1
7
,P2
,P12
0
7
0
to P3
0
7,
OL=200µA(Note 2)
7,P5
to P5
7
0
7
to P13
7
I
I
OL=1mA
2.0
2.0
HIGHPOWER
LOWPOWER
X
OUT
V
OL
LOW output voltage
LOW output voltage
V
V
OL=0.5mA
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
XCOUT
HOLD, RDY, TA0IN to TA4IN
TB0IN to TB5IN, INT to INT
ADTRG, CTS to CTS , SCL, SDA,
CLK to CLK ,TA2OUT to TA4OUT
KI to KI , RxD to RxD , SIN3, SIN4
RESET
,
Hysteresis
0
5, NMI,
V
V
T+-
T+-
V
V
T-
T-
0.2
0.2
1.0
V
0
2
0
4
,
0
3
0
2
Hysteresis
2.2
5.0
V
P0
P4
P8
0
0
0
to P0
to P4
to P8
7,P1
7,P5
7
,P9
0
to P1
to P5
to P9
7
7
7
,P2
,P6
,P10
0
0
to P2
to P6
7
,P3
0
0
to P3
to P7
7
,
,
HIGH input
current
0
7,P7
7
µA
0
0
to P107,P11
0
to P11
7,
I
IH
V
V
I
=5V
=0V
P12
0
to P12
7,P13
0
to P13
7
,P14 ,P14
0
1,
X
IN, RESET, CNVss, BYTE
P0
P4
P8
P12
X
0
to P0
to P4
to P8
7
7
7
,P1
,P5
,P9
0
0
0
to P1
to P5
to P9
7
7
7
,P2
,P6
,P10
0
0
to P2
to P6
7
,P3
0
0
to P3
to P7
7
,
,
LOW input
current
0
0
7,P7
7
0
to P107,P11
,P14 ,P14
IN, RESET, CNVss, BYTE
0 to P117,
I
IL
I
-5.0
170
µA
kΩ
0
to P12
7,P13
0
to P13
7
0
1,
RPULLUP
P0
P4
P8
0
0
0
to P0
to P4
to P8
7,P1
7,P5
4
,P8
0
0
6
to P1
to P5
7
,P2
,P6
0
0
to P2
to P6
7
,P3
0
2
to P3
to P7
7,
7,
7
,
Pull-up
resistance
7
7,P7
VI=0V
30
50
,P8
7,P9
0
to P9
7
,P10
0
to P10
P11
0
to P11
7,P12
0
to P12
7,P13
0
to P137,P140,P141
R
fXIN
Feedback resistance
Feedback resistance
X
IN
1.5
15
MΩ
MΩ
RfXCIN
X
CIN
V
RAM
RAM retention voltage
At stop mode
2.0
V
Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.
Note 2: Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on the VCC2 port side.
227
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Table 1.26.10. Electrical Characteristics (2) (Note 1
)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
Max.
20
f(BCLK)=24MHz,
No division, PLL operation
In single-chip mode, the output
pins are open and other pins are
VSS
Mask ROM
14
mA
mA
No division, Ring oscillation
1
f(BCLK)=24MHz,
No division, PLL operation
Flash memory
18
27
mA
No division, Ring oscillation
1.8
15
mA
mA
Flash memory
Program
f(BCLK)=10MHz,
VCC=5.0V
Flash memory
Erase
f(BCLK)=10MHz,
VCC=5.0V
25
25
mA
f(XCIN)=32kHz,
Mask ROM
µA
Low power dissipation mode,
ROM(Note 3)
Power supply current
(VCC=4.0 to 5.5V)
ICC
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
Flash memory
µA
µA
25
f(BCLK)=32kHz
Low power dissipation mode,
Flash memory(Note 3)
420
Ring oscillation,
Wait mode
µA
µA
50
f(BCLK)=32kHz,
7.5
Wait mode (Note 2),
Oscillation capacity High
Mask ROM
Flash memory
f(BCLK)=32kHz,
µA
µA
2.0
0.8
Wait mode(Note 2),
Oscillation capacity Low
Stop mode,
Topr=25°C
3.0
0.7
1.2
1.1
4
8
6
µA
µA
µA
Idet4
Idet3
Idet2
Power supply down detection dissipation current (Note 4)
Reset area detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
Note 1: Referenced to VCC=VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.
Note 2: With one timer operated using fC32.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
228
Mitsubishi microcomputers
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Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Timing Requirements
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.11. External Clock Input
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
62.5
25
Max.
t
c
ns
ns
ns
ns
ns
t
w(H
)
t
w(L)
25
t
r
15
15
t
f
External clock fall time
Table 1.26.12. Memory Expansion Mode and Microprocessor Mode
Standard
Symbol
Parameter
Unit
Min.
Max.
t
ac1(RD-DB)
Data input access time (for setting with no wait)
ns
ns
ns
(Note 1)
t
ac2(RD-DB)
(Note 2)
(Note 3)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
t
ac3(RD-DB)
t
su(DB-RD)
40
30
40
0
ns
ns
ns
ns
ns
ns
ns
t
su(RDY-BCLK )
RDY input setup time
HOLD input setup time
Data input hold time
t
su(HOLD-BCLK )
h(RD-DB)
h(BCLK -RDY)
t
t
0
RDY input hold time
t
h(BCLK-HOLD )
d(BCLK-HLDA )
0
HOLD input hold time
HLDA output delay time
t
40
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 45
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 45
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
setting.
[ns]
f(BCLK)
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
f(BCLK)
– 45
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
229
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Timing Requirements
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.13. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 1.26.14. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
400
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.15. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.16. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.17. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 1.26.18. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
230
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Timing Requirements
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.19. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 1.26.20. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.21. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.22. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 1.26.23. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.26.24. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
231
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Switching Characteristics
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.25. Memory Expansion and Microprocessor Modes (for setting with no wait)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
25
t
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
4
0
t
h(RD-AD)
t
h(WR-AD)
(Note 2)
t
t
d(BCLK-CS)
25
25
25
25
40
h(BCLK-CS)
Chip select output hold time (refers to BCLK)
ALE signal output delay time
4
t
t
d(BCLK-ALE)
h(BCLK-ALE)
Figure 1.26.1
–4
ALE signal output hold time
t
t
d(BCLK-RD)
RD signal output delay time
h(BCLK-RD)
RD signal output hold time
0
0
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
t
t
d(BCLK-DB)
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
h(BCLK-DB)
4
t
t
d(DB-WR)
h(WR-DB)
(Note 1)
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 40
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC2
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2
)
= 6.7ns.
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
Figure 1.26.1. Ports P0 to P10 Measurement Circuit
232
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Switching Characteristics
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.26. Memory Expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
25
t
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
4
0
ns
ns
h(RD-AD)
(Note 2)
t
t
h(WR-AD)
ns
ns
d(BCLK-CS)
25
25
25
25
40
Chip select output hold time (refers to BCLK)
ALE signal output delay time
4
t
t
h(BCLK-CS)
d(BCLK-ALE)
ns
ns
–4
t
h(BCLK-ALE)
ALE signal output hold time
Figure 1.26.1
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
0
0
t
t
d(BCLK-WR)
WR signal output delay time
ns
ns
h(BCLK-WR)
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
t
t
d(BCLK-DB)
ns
ns
h(BCLK-DB)
4
t
t
d(DB-WR)
h(WR-DB)
ns
ns
(Note 1)
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
n is “1” for 1-wait setting, “2” for 2-wait
setting and “3” for 3-wait setting.
– 40
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC2
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2
)
= 6.7ns.
233
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Switching Characteristics
o
o
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.27. Memory Expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
ns
ns
ns
t
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
4
(Note 1)
t
h(RD-AD)
(Note 1)
t
h(WR-AD)
Address output hold time (refers to WR)
ns
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
25
25
ns
ns
ns
ns
ns
ns
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
Chip select output hold time (refers to WR)
RD signal output delay time
4
(Note 1)
th(RD-CS)
(Note 1)
t
h(WR-CS)
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output hold time
0
0
t
t
t
d(BCLK-WR)
WR signal output delay time
25
40
ns
ns
ns
Figure 1.26.1
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (refers to BCLK)
t
h(BCLK-DB)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
4
ns
ns
(Note 2)
t
d(DB-WR)
h(WR-DB)
(Note 1)
t
Data output hold time (refers to WR)
ns
ns
ns
ns
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (refers to BCLK)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
25
– 4
(Note 3)
t
d(AD-ALE)
h(ALE-AD)
t
ALE signal output hold time (refers to Adderss)
RD signal output delay from the end of Adress
30
0
ns
ns
t
d(AD-RD)
t
d(AD-WR)
WR signal output delay from the end of Adress
Address output floating start time
0
ns
ns
t
dZ(RD-AD)
8
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
–40
[ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
0.5 X 109
–25
[ns]
f(BCLK)
234
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
tc(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
t
c(TB)
tw(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
tw(ADL)
ADTRG input
Figure 1.26.2. Timing Diagram (1)
235
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
t
w(INH)
Figure 1.26.3. Timing Diagram (2)
236
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
• VCC1=VCC2=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 1.26.4. Timing Diagram (3)
237
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
t
h(BCLK-ALE)
t
h(RD-AD)
-4ns.min
25ns.max
0ns.min
ALE
RD
DB
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac1(RD-DB)
(0.5 X tcyc-45)ns.max
Hi-Z
t
SU(DB-RD)
t
h(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
25ns.max
t
h(BCLK-CS)
4ns.min
CSi
tcyc
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 X tcyc)ns.min
ALE
t
d(BCLK-WR)
25ns.max
t
h(BCLK-WR)
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 X tcyc)ns.min
(0.5 X tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.5. Timing Diagram (4)
238
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
25ns.max
ALE
RD
DB
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac2(RD-DB)
(1.5 X tcyc-45)ns.max
Hi-Z
t
h(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
25ns.max
(0.5 X tcyc)ns.min
ALE
t
d(BCLK-WR)
25ns.max
t
h(BCLK-WR)
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 X tcyc-40)ns.min
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.6. Timing Diagram (5)
239
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(
for 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(2.5 X tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DB
t
d(DB-WR)
(1.5 X tcyc-40)ns.min
t
h(WR-DB)
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.7. Timing Diagram (6)
240
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(
for 3-wait setting and external area access
)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(3.5 X tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DB
t
d(DB-WR)
(2.5 X tcyc-40)ns.min
t
h(WR-DB)
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.8. Timing Diagram (7)
241
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
4ns.min
tcyc
(0.5 X tcyc)ns.min
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5 X tcyc-25)ns.min 30ns.min
ADi
/DBi
Address
Address
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
tac3(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
(1.5 X tcyc-45)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(RD-AD)
(0.5 X tcyc)ns.min
25ns.max
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
th(WR-CS)
(0.5 X tcyc)ns.min
tcyc
td(BCLK-CS)
25ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
Address
Data output
Address
/DBi
td(DB-WR)
(1.5 X tcyc-40)ns.min
th(WR-DB)
(0.5 X tcyc)ns.min
td(AD-ALE)
(0.5 X tcyc-25)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
th(WR-AD)
(0.5 X tcyc)ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage
: VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.9. Timing Diagram (8)
242
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 5V)
VCC1 = VCC2 = 5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
t
h(RD-CS)
t
h(BCLK-CS)
4ns.min
(0.5 X tcyc)ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
d(AD-ALE)
t
h(ALE-AD)
(0.5 X tcyc-25)ns.min 30ns.min
ADi
/DB
Data input
Address
t
h(RD-DB)
0ns.min
t
dZ(RD-AD)
t
ac3(RD-DB)
t
d(BCLK-AD)
8ns.max
t
SU(DB-RD)
40ns.min
td(AD-RD)
t
h(BCLK-AD)
4ns.min
25ns.max
(2.5 X tcyc-45)ns.max
0ns.min
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
(0.5 X tcyc)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
Write timing
tcyc
BCLK
t
h(WR-CS)
t
h(BCLK-CS)
4ns.min
(0.5 X tcyc)ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-DB)
4ns.min
t
d(BCLK-DB)
40ns.max
ADi
/DB
Address
Data output
t
d(AD-ALE)
t
d(DB-WR)
t
h(WR-DB)
(0.5 X tcyc)ns.min
(0.5 X tcyc-25)ns.min
(2.5 X tcyc-40)ns.min
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
d(AD-WR)
0ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 1.26.10. Timing Diagram (9)
243
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Table 1.26.28. Electrical Characteristics (Note)
Standard
Typ.
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
HIGH output P0
0
0
0
to P0
to P4
to P8
7,P1
7,P5
4
,P8
0
0
6
to P1
7
,P2
,P6
0
0
to P2
to P6
7
,P3
,P7
0
2
to P3
to P7
7,
7,
7
,
voltage
P4
to P5
7
7
V
V
OH
OH
V
CC
V
I
OH
=
-
1mA
V
CC
-
0.5
P8
,P8
7,P9
0
to P9
7
,P10
0
to P10
P11
0
to P11
7
,P12
0
to P12
7
,P13
0
to P137,P140,P141
V
V
CC
CC
HIGHPOWER
LOWPOWER
V
V
CC-
0.5
0.5
I
I
OH=
-
-
0.1mA
V
V
X
X
OUT
HIGH output voltage
HIGH output voltage
OH=
50µA
CC-
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
COUT
LOW output
voltage
P0
P4
P8
0
0
0
to P0
7
7
4
,P1
0
0
6
to P1
7
,P2
,P6
0
0
to P2
to P6
7
,P3
,P7
0
0
to P3
to P7
7
7
7
,
to P4
,P5
to P5
7
7
,
V
V
OL
OL
0.5
I
OL=1mA
V
to P8
,P8
,P8
7,P9
0
to P9
7
,P10
0
to P10
,
P11
0
to P11
7,P12
0
to P12
7
,P13
0
to P137,P140,P141
I
I
OL=0.1mA
0.5
0.5
HIGHPOWER
LOWPOWER
X
OUT
LOW output voltage
LOW output voltage
V
V
OL=50µA
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
X
COUT
Hysteresis
HOLD, RDY, TA0IN to TA4IN
TB0IN to TB5IN, INT to INT
ADTRG, CTS to CTS , SCL, SDA,
CLK to CLK , TA2OUT to TA4OUT
KI to KI , RxD to RxD , SIN3,SIN4
,
0
5, NMI,
V
V
T+-
T+-
V
V
T-
T-
0
2
0.2
0.2
0.8
V
0
4
,
0
3
0
2
Hysteresis
(0.7)
1.8
4.0
V
RESET
P0
P4
P8
0
0
0
to P0
to P4
to P8
7,P1
7,P5
7,P9
0
to P1
to P5
to P9
7
7
7
,P2
,P6
,P10
0
0
to P2
to P6
7
,P3
,P7
0
0
to P3
to P7
7
,
,
HIGH input
current
0
7
7
I
IH
V
I
=3V
µA
0
0
to P107,P11
0
to P11
7
,
,
P12
0
to P12
7
,P13
0
to P13
7
,P14 ,P14
0
1,
X
IN, RESET, CNVss, BYTE
P0
P4
P8
0
0
0
to P0
to P4
to P8
7,P1
7,P5
7,P9
0
0
0
to P1
to P5
to P9
7
7
7
,P2
,P6
,P10
0
0
to P2
to P6
7,P3
0
to P3
7
,
,
LOW input
current
7,P7
0 to P7
7
0
to P107,P11
0 to P11
7
I
IL
V
V
I
=0V
=0V
µA
kΩ
-
4.0
P12
0
to P12
7
,P13
0
to P13
7
,P14 ,P14
0
1,
X
IN, RESET, CNVss, BYTE
R
PULLUP
P0
P4
P8
0
0
0
to P0
to P4
to P8
7,P1
7,P5
4,P8
0
0
6
to P1
7
,P2
,P6
0
0
to P2
to P6
7
,P3
,P7
0
2
to P3
to P7
7
7
7
,
,
,
Pull-up
resistance
to P5
7
7
I
66
160
500
,P8
7,P9
0
to P9
7
,P10
0
to P10
P11
0
to P11
7,P12
0
to P12
7,P13
0
to P137,P140,P141
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
X
IN
CIN
3.0
25
MΩ
MΩ
V
RfXCIN
V
RAM
At stop mode
2.0
Note : Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
244
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Table 1.26.29. Electrical Characteristics (2) (Note 1)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
Max.
11
f(BCLK)=10MHz,
No division
In single-chip mode, the output
pins are open and other pins are
Mask ROM
8
mA
mA
V
SS
No division, Ring oscillation
1
8
f(BCLK)=10MHz,
No division
Flash memory
13
mA
No division, Ring oscillation
1.8
12
mA
mA
mA
Flash memory
Program
f(BCLK)=10MHz,
Vcc
1=3.0V
Flash memory
Erase
f(BCLK)=10MHz,
Vcc1=3.0V
22
25
Mask ROM
f(XCIN)=32kHz,
Low power dissipation mode,
ROM(Note 3)
µA
Power supply current
(VCC=2.7 to 3.6V)
I
CC
f(BCLK)=32kHz,
Flash memory
25
µA
µA
Low power dissipation mode,
RAM(Note 3)
f(BCLK)=32kHz,
420
Low power dissipation mode,
Flash memory(Note 3)
Ring oscillation,
Wait mode
µA
µA
45
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
6.0
Mask ROM
Flash memory
f(BCLK)=32kHz,
µA
µA
1.8
0.7
Wait mode (Note 2),
Oscillation capacity Low
Stop mode,
3.0
T
opr=25°C
0.6
0.4
0.9
4
2
4
µA
µA
µA
Idet4
Idet3
Idet2
Power supply down detection dissipation current (Note 4)
Reset level detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
Note 1: Referenced to VCC=VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
245
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Timing Requirements
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.30. External Clock Input
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
t
w(H)
t
w(L)
40
t
r
18
18
t
f
External clock fall time
Table 1.26.31. Memory Expansion and Microprocessor Modes
Standard
Symbol
Parameter
Unit
Min.
Max.
t
ac1(RD-DB)
Data input access time (for setting with no wait)
ns
ns
ns
(Note 1)
(Note 2)
(Note 3)
t
ac2(RD-DB)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
t
ac3(RD-DB)
t
t
su(DB-RD)
50
40
50
0
ns
ns
ns
ns
ns
ns
ns
su(RDY-BCLK )
RDY input setup time
HOLD input setup time
Data input hold time
t
su(HOLD-BCLK )
h(RD-DB)
h(BCLK -RDY)
t
t
0
RDY input hold time
t
h(BCLK-HOLD )
d(BCLK-HLDA )
0
HOLD input hold time
HLDA output delay time
t
40
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 60
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 60
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
setting.
[ns]
f(BCLK)
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
f(BCLK)
– 60
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
246
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Timing Requirements
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.32. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
ns
ns
ns
t
t
t
c(TA)
TAiIN input cycle time
60
60
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 1.26.33. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
t
t
t
c(TA)
600
300
300
TAiIN input cycle time
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 1.26.34. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Min. Max.
300
Symbol
Parameter
Unit
ns
ns
ns
t
t
t
c(TA)
TAiIN input cycle time
w(TAH)
w(TAL)
150
150
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 1.26.35. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.36. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
t
t
t
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
su(UP-TIN
h(TIN-UP)
)
600
Table 1.26.37. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
t
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
500
500
247
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Timing Requirements
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 1.26.38. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
60
t
t
300
160
160
t
w(TBH)
t
w(TBL)
Table 1.26.39. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.40. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.41. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 1.26.42. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
160
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.26.43. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
248
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Switching Characteristics
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.44. Memory Expansion, Microprocessor Modes (for setting with no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
30
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
t
t
4
0
ns
ns
h(RD-AD)
(Note 2)
t
t
h(WR-AD)
ns
ns
d(BCLK-CS)
30
30
30
30
40
Chip select output hold time (refers to BCLK)
ALE signal output delay time
4
t
t
h(BCLK-CS)
d(BCLK-ALE)
ns
ns
Figure 1.26.11
–4
t
h(BCLK-ALE)
ALE signal output hold time
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
0
0
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
ns
ns
t
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
t
t
d(BCLK-DB)
h(BCLK-DB)
ns
ns
4
t
t
d(DB-WR)
h(WR-DB)
ns
ns
(Note 1)
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 40
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC2
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2
)
= 6.7ns.
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
Figure 1.26.11. Ports P0 to P10 Measurement Circuit
249
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Switching Characteristics
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.45. Memory expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
ns
Min.
Max.
30
t
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
4
0
ns
ns
h(RD-AD)
(Note 2)
t
t
h(WR-AD)
ns
ns
d(BCLK-CS)
30
30
30
30
40
Chip select output hold time (refers to BCLK)
ALE signal output delay time
4
t
t
h(BCLK-CS)
d(BCLK-ALE)
ns
ns
Figure 1.26.11
–4
t
h(BCLK-ALE)
ALE signal output hold time
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
0
0
t
t
d(BCLK-WR)
WR signal output delay time
ns
ns
h(BCLK-WR)
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
t
t
d(BCLK-DB)
ns
ns
h(BCLK-DB)
4
t
t
d(DB-WR)
h(WR-DB)
ns
ns
(Note 1)
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
– 40
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC2
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2
)
= 6.7ns.
250
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Switching Characteristics
o
o
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, CM15=“1” unless otherwise
specified)
Table 1.26.46. Memory expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
50
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
ns
ns
ns
t
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
4
(Note 1)
t
h(RD-AD)
(Note 1)
t
h(WR-AD)
Address output hold time (refers to WR)
ns
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
50
40
ns
ns
ns
ns
ns
ns
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
Chip select output hold time (refers to WR)
RD signal output delay time
4
(Note 1)
th(RD-CS)
(Note 1)
t
h(WR-CS)
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output hold time
0
0
Figure 1.26.11
t
t
t
d(BCLK-WR)
WR signal output delay time
40
50
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (refers to BCLK)
t
h(BCLK-DB)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
4
ns
ns
(Note 2)
t
d(DB-WR)
h(WR-DB)
(Note 1)
t
Data output hold time (refers to WR)
ns
ns
ns
ns
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (refers to BCLK)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
40
– 4
(Note 3)
t
d(AD-ALE)
h(ALE-AD)
t
ALE signal output hold time (refers to Adderss)
RD signal output delay from the end of Address
30
0
ns
ns
t
d(AD-RD)
t
d(AD-WR)
WR signal output delay from the end of Address
Address output floating start time
0
ns
ns
t
dZ(RD-AD)
8
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
[ns]
f(BCLK)
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
–50
[ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
0.5 X 109
–40
[ns]
f(BCLK)
251
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN–UP)
tsu(UP–TIN
)
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT
)
tsu(TAIN-TAOUT
)
tsu(TAOUT-TAIN
)
TAiOUT input
tsu(TAOUT-TAIN
)
tc(TB)
tw(TBH)
tw(ADL)
TBiIN input
tw(TBL)
tc(AD)
ADTRG input
Figure 1.26.12. Timing Diagram (1)
252
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
th(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 1.26.13. Timing Diagram (2)
253
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 = Vcc2 = 3V)
VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
t
d(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit of PM0 register and PM11 bit of PM1 register.
Measuring conditions :
• VCC1=VCC2=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 1.26.14. Timing Diagram (3)
254
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
th(BCLK-ALE)
td(BCLK-ALE)
t
h(RD-AD)
-4ns.min
30ns.max
0ns.min
ALE
RD
DB
t
d(BCLK-RD)
t
h(BCLK-RD)
30ns.max
0ns.min
t
ac1(RD-DB)
(0.5 X tcyc-60)ns.max
Hi-Z
t
SU(DB-RD)
t
h(RD-DB)
50ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
30ns.max
t
h(BCLK-CS)
4ns.min
CSi
tcyc
t
d(BCLK-AD)
30ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 X tcyc)ns.min
ALE
t
d(BCLK-WR)
30ns.max
t
h(BCLK-WR)
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
h(WR-DB)
t
d(DB-WR)
(0.5 X tcyc)ns.min
(0.5 X tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.15. Timing Diagram (4)
255
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
30ns.max
ALE
RD
DB
t
d(BCLK-RD)
t
h(BCLK-RD)
30ns.max
0ns.min
t
ac2(RD-DB)
(1.5 X tcyc-60)ns.max
Hi-Z
t
h(RD-DB)
tSU(DB-RD)
0ns.min
50ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
30ns.max
(0.5 X tcyc)ns.min
ALE
t
d(BCLK-WR)
30ns.max
t
h(BCLK-WR)
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 X tcyc-40)ns.min
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.16. Timing Diagram (5)
256
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(
for 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
t
ac2(RD-DB)
(2.5 X tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DB
t
d(DB-WR)
(1.5 X tcyc-40)ns.min
t
h(WR-DB)
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.17. Timing Diagram (6)
257
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(
for 3-wait setting and external area access
)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
t
ac2(RD-DB)
(3.5 X tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DB
t
d(DB-WR)
(2.5 X tcyc-40)ns.min
t
h(WR-DB)
(0.5 X tcyc)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.18. Timing Diagram (7)
258
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
40ns.max
t
h(RD-CS)
(0.5 X tcyc)ns.min
tcyc
CSi
t
d(AD-ALE)
(0.5 X tcyc-40)ns.min
t
h(ALE-AD)
30ns.min
ADi
/DBi
Address
Address
Data input
t
dZ(RD-AD)
t
h(RD-DB)
0ns.min
8ns.max
t
ac3(RD-DB)
tSU(DB-RD)
(1.5 X tcyc-60)ns.max
50ns.min
t
d(AD-RD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
40ns.max
ADi
BHE
t
d(BCLK-ALE)
40ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(RD-AD)
(0.5 X tcyc)ns.min
ALE
RD
t
d(BCLK-RD)
40ns.max
t
h(BCLK-RD)
0ns.min
Write timing
BCLK
t
h(BCLK-CS)
tcyc
t
h(WR-CS)
t
d(BCLK-CS)
4ns.min
(0.5 X tcyc)ns.min
40ns.max
CSi
t
h(BCLK-DB)
t
d(BCLK-DB)
4ns.min
50ns.max
ADi
Address
Data output
Address
/DBi
t
d(DB-WR)
t
h(WR-DB)
t
d(AD-ALE)
(1.5 X tcyc-50)ns.min
(0.5 X tcyc)ns.min
(0.5 X tcyc-40)ns.min
t
d(BCLK-AD)
t
h(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-WR)
t
h(WR-AD)
40ns.max
-4ns.min
0ns.min
(0.5 X tcyc)ns.min
ALE
t
d(BCLK-WR)
t
h(BCLK-WR)
0ns.min
40ns.max
WR,WRL,
WRH
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.19. Timing Diagram (8)
259
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics (Vcc1 ≥ Vcc2 = 3V)
VCC1 ≥ VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
t
h(RD-CS)
(0.5 X tcyc)ns.min
t
h(BCLK-CS)
6ns.min
t
d(BCLK-CS)
40ns.max
CSi
t
d(AD-ALE)
t
h(ALE-AD)
(0.5 X tcyc-40)ns.min 30ns.min
ADi
/DB
Data input
Address
t
h(RD-DB)
0ns.min
t
dZ(RD-AD)
t
ac3(RD-DB)
t
d(BCLK-AD)
8ns.max
t
SU(DB-RD)
50ns.min
td(AD-RD)
t
h(BCLK-AD)
4ns.min
40ns.max
(2.5 X tcyc-60)ns.max
0ns.min
ADi
BHE
(No multiplex)
t
d(BCLK-ALE)
40ns.max
t
h(RD-AD)
(0.5 X tcyc)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
40ns.max
Write timing
tcyc
BCLK
t
h(WR-CS)
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
40ns.max
(0.5 X tcyc)ns.min
CSi
t
h(BCLK-DB)
4ns.min
t
d(BCLK-DB)
50ns.max
ADi
/DB
Address
Data output
t
d(AD-ALE)
t
d(DB-WR)
t
h(WR-DB)
(tcyc/2)ns.min
(0.5 X tcyc-40)ns.min
(2.5 X tcyc-50)ns.min
t
d(BCLK-AD)
40ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
(No multiplex)
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-ALE)
40ns.max
t
h(WR-AD)
(0.5 X tcyc)ns.min
t
d(AD-WR)
0ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
40ns.max
WR, WRL
WRH
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 1.26.20. Timing Diagram (9)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory Version
Flash Memory Version
Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally con-
tains flash memory.
The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/
output modes—in which its internal flash memory can be operated on.
Table 1.27.1 shows the outline performance of flash memory version (see Table 1.1.1 for the items not
listed in Table 1.27.1.).
Table 1.27.1. Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
See Figure 1.27.1
User ROM area
Boot ROM area
Erase block
1 block (4 Kbytes) (Note 1)
In units of word, in units of byte (Note 2)
Collective erase, block erase
Program and erase controlled by software command
Protected for each block by lock bit
8 commands
Method for program
Method for erasure
Program, erase control method
Protect method
Number of commands
Number of program and erasure
100 times
10 years
Data Retention
Parallel I/O and standard serial I/O modes are supported.
ROM code protection
Note 1: The boot ROM area contains a standard serial I/O mode rewrite control program which is stored
in it when shipped from the factory. This area can only be rewritten in parallel input/output mode.
Note 2: Can be programmed in byte units in only parallel input/output mode.
Table 1.27.2. Flash Memory Rewrite Modes Overview
Flash memory
rewrite mode
Function
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
The user ROM area is rewrit-
ten by executing software
commands from the CPU.
EW0 mode:
Can be rewritten in any
area other than the flash
memory
The user ROM area is rewrit- The boot ROM and user
ten by using a dedicated se- ROM areas are rewritten by
rial programmer.
Standard serial I/O mode 1: programmer.
Clock sync serial I/O
Standard serial I/O mode 2:
UART
using a dedicated parallel
EW1 mode:
Can be rewritten in the
flash memory
Areas which User ROM area
can be rewritten
User ROM area
Boot mode
User ROM area
Boot ROM area
Parallel I/O mode
Operation
mode
Single chip mode
Memory expansion mode
(EW0 mode)
Boot mode (EW0 mode)
None
ROM
Serial programmer
Parallel programmer
programmer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory Version
1. Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 1.27.1 shows the block diagram of flash momoery. The user ROM area has a 4K-byte block A, in
addition to the area that stores a program for microcomputer operation during singe-chip or memory expan-
sion mode.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial
input/output, and parallel input/output modes. Block A is enabled for use by setting the PM1 register’s
PM10 bit to “1” (block A enabled, CS2 area at addresses 1000016 to 26FFF16).
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in
parallel input/output mode. After a hardware reset that is performed by applying a high-level signal to the
CNVSS and P50 pins and a low-level signal to the P55 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the
user ROM area is executed (but the boot ROM area cannot be read).
00F00016
Block A :4K bytes
00FFFF16
08000016
Block 12 : 64K bytes
08FFFF16
09000016
Block 11 : 64K bytes
09FFFF16
0A000016
Block 10 : 64K bytes
0AFFFF16
0B000016
Block 9 : 64K bytes
0BFFFF16
0F000016
0C000016
Block 8 : 64K bytes
Block 7 : 64K bytes
Block 6 : 64K bytes
0CFFFF16
0D000016
Block 5 : 32K bytes
0DFFFF16
0E000016
0F7FFF16
0F800016
Block 4 : 8K bytes
Block 3 : 8K bytes
Block 2 : 8K bytes
0F9FFF16
0FA00016
0EFFFF16
0F000016
0FBFFF16
0FC00016
Block 0 to Block 5 (32+8+8+8
+4+4)K bytes
0FDFFF16
0FE00016
0FEFFF16
0FF00016
0FFFFF16
Block 1 : 4K bytes
Block 0 : 4K bytes
0FF00016
0FFFFF16
4K bytes
0FFFFF16
User ROM area
Boot ROM area
Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Note 4: Block A can be made usable by setting the PM1 register’s PM10 bit to “1” (block A enabled, CS2 area allocated at addresses 1000016 to 26FFF16).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it.
Figure 1.27.1. Flash Memory Block Diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Boot Mode
After a hardware reset which is performed by applying a low-level signal to the P55 pin and a high-level
signal to the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the pro-
gram in the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0
register.
The boot ROM area contains a standard serial input/output mode based rewrite control program which was
stored in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite
control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the
system.
Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM
code protect and standard serial input/output mode has an ID code check function.
• ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
input/output mode. Figure 1.27.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area.The ROMCP1 bit consists of two bits. The ROM
code protect function is enabled by clearing one or both of two ROMCP1 bits to “0” when the ROMCR bits
are not ‘002,’ with the flash memory thereby protected against reading or rewriting. Conversely, when the
ROMCR bits are ‘002’ (ROM code protect removed), the flash memory can be read or rewritten. Once the
ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel input/output
mode. Therefore, use standard serial input/output or other modes to rewrite the flash memory.
• ID Code Check Function
Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes
sent from the programmer and the ID codes written in the flash memory are compared to see if they
match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316,
0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes
are preset at these addresses and write it in the flash memory.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROMCP
Address
0FFFFF16
Value when shipped
FF16 (Note 4)
1
1
1
1
RW
RW
Bit symbol
Bit name
Function
Set this bit to “1”
Reserved bit
RW
Set this bit to “1”
Set this bit to “1”
Reserved bit
Reserved bit
RW
RW
Set this bit to “1”
Reserved bit
b5 b4
ROM code protect reset
bit (Note 2, Note 4)
ROMCR
RW
RW
RW
RW
00: Removes protect
01:
Enables ROOMCP1 bit
10:
11:
}
b7 b6
00:
01:
10:
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
ROMCP1
Protect enabled
}
11: Protect disabled
Note 1: If the ROMCR bits are set to other than ‘002’ and the ROMCP1 bits are set to other than ‘112’ (
ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to ‘00
2’ when the ROMCR bits are other than ‘002’ and the ROMCP1
bits are other than ‘11 ,’ ROM code protect level 1 is removed. However, because the ROMCR
2
bits cannot be modified during parallel input/output mode, they need to be modified in standard
serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘012,’ ‘102,’ or ‘112.’
Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to ‘FF16.’
Figure 1.27.2. ROMCP Register
Address
Undefined instruction vector
Overflow vector
ID1
ID2
0FFFDF16 to 0FFFDC16
0FFFE316 to 0FFFE016
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
0FFFEF16 to 0FFFEC16
0FFFF316 to 0FFFF016
0FFFF716 to 0FFFF416
0FFFFB16 to 0FFFF816
0FFFFF16 to 0FFFFC16
BRK instruction vector
Address match vector
ID3
ID4
Single step vector
Watchdog timer vector
DBC vector
ID5
ID6
ID7
NMI vector
Reset vector
ROMCP
4 bytes
Figure 1.27.3. Address for ID Code Stored
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 1.27.1 can be rewritten and the boot ROM
area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on
each block in the user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase
Write 1 (EW1) mode. Table 1.27.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1
(EW1) modes.
Table 1.27.3. EW0 Mode and EW1 Mode
Item
EW0 mode
• Single chip mode
EW1 mode
Single chip mode
Operation mode
• Memory expansion mode
• Boot mode
Areas in which a
rewrite control
• User ROM area
• Boot ROM area
User ROM area
program can be located
Areas in which a
rewrite control
Must be transferred to any area other Can be executed directly in the user
than the flash memory (e.g., RAM)
ROM area
program can be executed before being executed
Areas which can be
rewritten
User ROM area
User ROM area
However, this does not include the area
in which a rewrite control program
exists
Software command
limitations
None
• Program, Block Erase command
Cannot be executed on any block in
which a rewrite control program exists
• Erase All Unlocked Block command
Cannot be executed when the lock bit
for any block in which a rewrite control
program exists is set to “1” (unlocked)
or the FMR0 register’s FMR02 bit is set
to “1” (lock bit disabled)
• Read Status Register command
Cannot be executed
Modes after Program or Read Status Register mode
Erase
Read Array mode
CPU status during Auto Operating
Write and Auto Erase
Hold state (I/O ports retain the state in
which they were before the command
(Note)
was executed)
Flash memory status
detection
• Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a
program
FMR06, and FMR07 bits in a program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
_______
Note: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
• EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit
= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
• EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Figure 1.27.4 shows the FIDR, FMR0 and FMR1 registers.
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or
Lock Bit program is running; otherwise, the bit is “1”.
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode). During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to
the description of the data protect function.) The lock bits set are enabled by setting the FMR02 bit to “0”.
The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status
flag). However, if the Erase command is executed while the FMR02 bit is set to “1”, the lock bit data
changes state from “0” (locked) to “1” (unlocked) after Erase is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. The internal flash memory is disabled against access by setting
the FMSTP bit to “1”. Therefore, the FMSTP bit must be written to by a program in other than the flash
memory.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00
bit not reset to “1” (ready))
• When entering low power mode or ring low power mode
Figure 1.27.7 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power
for the internal flash memory is automatically turned off and is turned back on again after returning from
stop or wait mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area
(for read, write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is cleared to “0”. For details, tefer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase
error occurs; otherwise, it is cleared to “0”. For details, tefer to the description of the full status check.
Figure 1.27.5 and 1.27.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
FMR11 Bit
Setting this bit to “1” places the microcomputer in EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Flash identification register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FIDR
Address
01B416
After reset
XXXXXX00
2
Bit symbol
FIDR0
Bit name
RW
RO
Function
b1 b0
Flash module type
identification value
0 0: M16C/62N, M3062GF8N type flash module
1 0: M16C/62P type flash module
1 1: M16C/62M, M16C/62A type flash module
RO
FIDR1
Nothing is assigned.
When write, set to “0”. When read, their contents are indeterminate.
(b7-b2)
Note: This register identifies on-chip flash module type of M16C/62 group. Note, however, no chip version is known
by this register. Follow the procedure described below for the identification.
(1) Write FF16 to FIDR register
(2) Read FIDR register
(3) Check two low-order bits of read value
Make sure no access to external memories or other SFRs or no interrupts or DMA transfers will occur between
the above two instructions no. 1 and no. 2.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
01B716
After reset
XX000001
2
0
Bit name
Function
RW
RO
Bit symbol
0: Busy (being written or erased)
1: Ready
FMR00
RY/BY status flag
CPU rewrite mode select bit
(Note 1)
0: Disables CPU rewrite mode
1: Inables CPU rewrite mode
FMR01
RW
RW
Lock bit disable select bit
(Note 2)
0: Inables lock bit
1: Disables lock bit
FMR02
FMSTP
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
flash memory initialized)
Flash memory stop bit
(Note 3, Note 5))
RW
RW
Reserved bit
(b4)
Must always be set to “0”
User ROM area select bit
(Note 3)
(Effective in only boot mode)
0: Boot ROM area is accessed
1: User ROM area is accessed
FMR05
RW
FMR06
FMR07
Program status flag (Note 4)
Erase status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
RO
0: Terminated normally
1: Terminated in error
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, write to this bit from
a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Note 6: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
01B516
After reset
0X00XX0X
2
0
0
0
0
Bit symbol
Bit name
Function
RW
RO
The value in this bit when read is
indeterminate.
Reserved bit
(b0)
FMR11
EW1 mode select bit (
Note)
0: EW0 mode
1: EW1 mode
RW
The value in this bit when read is
indeterminate.
Reserved bit
RO
(b3-b2)
Reserved bit
RW
Must always be set to “0”
(b5-b4)
FMR06
0: Lock
1: Unlock
Lock bit status flag
RO
Reserved bit
Must always be set to “0”
RW
(b7)
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 1.27.4. FIDR Register and FMR0 and FMR1 Registers
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Flash Memory
EW0 mode operation procedure
Rewrite control program
For only boot mode
set the FMR05 bit to “1” (user ROM area access)
Single-chip mode, memory expansion
mode, or boot mode
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)
Set CM0, CM1, and PM1 registers (Note
1)
Transfer a CPU rewrite mode based rewrite control
program to any area other than the flash memory
Execute software commands
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory)
Execute the Read Array command
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write “0” to the FMR05 bit (Boot ROM area
accessed) (Note 4)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6
bits. Also, set the PM1 register’s PM17 bit to “1” (with wait state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA
transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is
“H” level.
Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to “1”.
Figure 1.27.5. Setting and Tesetting of EW0 Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
EW1 mode operation procedure
Program in ROM
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note
2)
Set the FMR01 bit by writing “0” and then “1” (CPU
rewrite mode enabled)
Set the FMR11 bit by writing “0” and then “1” (EW1
mode) (Note 3)
Execute software commands
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set the microcomputer in memory expansion or boot mode.
Note 2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait
state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write
only when the NMI pin is “H” level.
Figure 1.27.6. Setting and Resetting of EW1 Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Low power dissipation
mode program
Transfer a low power dissipation mode program
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)
to any area other the flash memory
Set FMSTP bit to “1”
(flash memory stopped. Low power state)(Note 1)
Jump to the low power dissipation mode program
which has been transferred to any area other the
flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.)
Switch the clock source for CPU clock.
Turn main clock off. (Note 2)
Process of low power dissipation mode or
ring oscillator low power dissipation mode
wait until oscillation stabilizes
Turn main clock on
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to “0” (flash memory operation)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (15 µs)
(Note 3)
Jump to a specified address in the flash memory
Note 1: Set the FMR03 bit to 1 after setting the FMR01 bit to “1”.
Note 2: Before the clock source for CPU clock can be changed to
main clock or sub clock, the clock to which to be changed
must be stable.
Note 3: Insert a 15 µs wait time in a program. The flash memory
cannot be accessed during this wait time.
Figure 1.27.7. Processing Before and After Low Power Sissipation Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in
the PM1 register to “1” (with wait state).
(2) Instructions to Prevent from Using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruc-
tion
(3) Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
(4) How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
(5) Writing in the User ROM Space
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
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Flash Memory
(6) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
(7) Writing Command and Data
Write the command code and data at even addresses.
(8) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
(9) Stop Mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after returning from stop mode
(10) Low Power Dissipation Mode and Ring Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Software Commands
Software commands are described below. The command code and data must be read and written in 16-
bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-
order bits (D1t–D8) are ignored.
Table 1.27.4. Software Commands
First bus cycle
Address
Second bus cycle
Address
Command
Data
to D
Data
to D7)
Mode
Mode
Read
(D
0
7
)
(D
0
Write
Write
Write
Write
Write
Write
Write
Write
Read array
X
X
xxFF16
xx7016
xx5016
xx4016
xx2016
xxA716
xx7716
xx7116
X
SRD
Read status register
Clear status register
Program
X
WA
WD
WA
X
Write
Write
Write
Write
Write
Block erase
BA
X
xxD016
xxD016
xxD016
xxD016
(Note)
Erase all unlocked block
X
BA
X
Lock bit program
BA
BA
Read lock bit status
Note: It is only blocks 0 to 12 that can be erased by the Erase All Unlocked Block command.
Block A cannot be erased. Use the Block Erase command to erase block A.
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address
as the write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
x: High-order 8 bits of command code (ignored)
Read Array Command (FF16)
This command reads the flash memory.
Writing ‘xxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16-bit units.
Because the microcomputer remains in read array mode until another command is written, the con-
tents of multiple addresses can be read in succession.
Read Status Register Command (7016)
This command reads the status register.
Write ‘xx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
to “Status Register.”) When reading the status register too, specify an even address in the user ROM
area.
Do not execute this command in EW1 mode.
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Flash Memory
Clear Status Register Command (5016)
This command clears the status register to “0”.
Write ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to
SR5 in the status register will be cleared to “0”.
Program Command (4016)
This command writes data to the flash memory in 1 word (2 byte) units.
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is
“0” during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check.”)
Each block can be protected against programming by a lock bit. (Refer to “Data Protect Function.”)
Writing over already programmed addresses is inhibited.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto program-
ming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to
“0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In
this case, the microcomputer remains in read status register mode until a read command is written
next. The result of auto programming can be known by reading the status register after auto program-
ming has finished.
Start
Write the command code ‘xx4016’
to the write address
Write data to the write address
NO
FMR00=1?
YES
Full status check
Program
completed
Note: Write the command code and data at even number.
Figure 1.27.8. Program Command
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Block Erase
Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” during auto erasing and set to “1” when auto erasiing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known. (Refer to “Full Status Check.”)
Figure 1.27.9 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
Writing over already programmed addresses is inhibited.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Start
Write the command code ‘xx2016
’
Write ‘xxD016’ to the uppermost
block address
NO
FMR00=1?
YES
Full status check
Block erase completed
Note: Write the command code and data at even number.
Figure 1.27.9. Block Erase Command
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Erase All Unlocked Block
Write ‘xxA716’ in the first bus cycle and write ‘xxD016’ in the second bus cycle, and all blocks except
block A will be erased successively, one block at a time.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The result of the auto erase
operation can be known by inspecting the FMR0 register’s FMR07 bit.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the
rewrite control program is stored, or when the FMR0 register’s FMR02 bit = 1 (lock bit disabled).
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Note that only blocks 0 to 12 can be erased by the Erase All Unlocked Block command. Block A
cannot be erased. Use the Block Erase command to erase block A.
Lock Bit Program Command (7716/D016)
This command sets the lock bit for a specified block to “0” (locked).
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Figure 1.27.10 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can
be read using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
For details about the lock bit function, and on how to set the lock bit to “1”, refer to “Data Protect
Function.”
Start
Write command code ‘xx7716’ to
the uppermost block address
Write ‘xxD016’ to the uppermost
block address
NO
FMR00=1?
YES
Full status check
Lock bit program completed
Note: Write the command code and data at even number.
Figure 1.27.10. Lock Bit Program Command
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Read Lock Bit Status Command (7116)
This command reads the lock bit status of a specified block.
Write ‘xx7116’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the
FMR1 register’s FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1”
(ready).
Figure 1.27.11 shows an example of a read lock bit status flowchart.
Start
Write the command code ‘xx7116
’
Write ‘xxD016’ to the uppermost
block address
NO
FMR00=1?
YES
NO
FMR16=0?
YES
Blocks not locked
Block locked
Note: Write the command code and data at even number.
Figure 1.27.11. Read Lock Bit Status Command
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit =
0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program-
ming and erasure. This helps to prevent data from inadvertently written to or erased from the flash
memory. The following shows the relationship between the lock bit and the block status.
• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased.
The lock bit is cleared to “0” (locked) by executing the Lock Bit Program command, and is set to “1”
(unlocked) by erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command
The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function
(lock bit data retained).
If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target
block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to “1”
after completion of erasure.
For details about the commands, refer to “Software Commands.”
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program-
ming operation terminated normally or in error. The status of the status register can be known by reading
the FMR0 register’s FMR00, FMR06, and FMR07 bits.
Table 1.27.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register
command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,
Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array
command.
Sequencer Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation
finishes.
Erase Status (SR5 and FMR07 Bits)
Refer to “Full Status Check.”
Program Status (SR4 and FMR06 Bits)
Refer to “Full Status Check.”
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Flash Memory
Table 1.27.5. Status Register
Value
after
reset
Status
register
bit
FMR0
register
bit
Contents
Status name
"0"
"1"
Ready
-
SR7 (D
SR6 (D
SR5 (D
SR4 (D
SR3 (D
SR2 (D
SR1 (D
SR0 (D
7)
6)
5)
4)
3)
2)
1)
0)
Sequencer status
Reserved
FMR00
Busy
-
1
Erase status
Program status
Reserved
FMR07
FMR06
Terminated normally
Terminated normally
0
0
Terminated in error
Terminated in error
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to “0” by executing the Clear Status Register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked Block,
and Lock Bit Program commands are not accepted.
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Flash Memory
Full Status Check
When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check). Table 1.27.6 lists errors and FMR0 register status. Figure 1.27.12 shows a full status
check flowchart and the action to be taken when each error occurs.
Table 1.27.6. Errors and FMR0 Register Status
FRM00 register
(status register)
status
FMR06
Error
Error occurance condition
FMR07
(SR5)
1
(SR4)
1
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be writ-
ten in the second bus cycle of the Lock Bit Program, Block Erase,
or Erase All Unlocked Block command (i.e., other than ‘xxD016’ or
‘xxFF16’) (Note 1)
1
0
0
1
Erase error
• When the Block Erase command was executed on locked blocks
(Note 2)
• When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not auto-
matically erased correctly
Program error • When the Block Erase command was executed on locked blocks
(Note 2)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not pro-
grammed correctly
281
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
Full status check
FMR06 =1
and
FMR07=1?
YES
NO
(1) Execute the Clear Status Register command to
clear these status flags to “0”.
(2) Reexecute the command after checking that it is
entered correctly.
Command
sequence error
NO
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Block Erase or Erase All Unlocked
Block command.
FMR07=
0?
Erase error
YES
Note 1: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During programming]
NO
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
Program error
FMR06=
0?
YES
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During lock bit programming]
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Set the FMR0 register’s FMR02 bit to “1”.
(3) Execute the Block Erase command to erase the
block in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error
cannot be used.
Full status check completed
Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Erase All Unlocked
Block, Lock Bit Program, or Read Lock Bit Status command is not accepted.
Execute the Clear Status Register command before executing those commands.
Figure 1.27.12. Full Status Check and Handling Procedure for Each Error
282
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer suitable for the M16C/62P group. For more information
about serial programmers, contact the manufacturer of your serial programmer. For details on how to use,
refer to the user’s manual included with your serial programmer.
Table 1.27.7 lists pin functions (flash memory standard serial input/output mode). Figures 1.27.13 to
1.27.15 show pin connections for serial input/output mode.
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to the desctiption of the functions to inhibit rewriting flash memory version.)
283
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.27.7. Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin
Name
Description
I/O
Apply the voltage guaranteed for Program and Erase to Vcc pin and 0
V to Vss pin.
VCC,VSS
Power input
CNVSS
RESET
CNVSS
I
I
Connect to Vcc pin.
Reset input
Reset input pin. While RESET pin is "L" level, input a 20 cycle or
longer clock to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
XIN
Clock input
I
O
I
XOUT
Clock output
BYTE
BYTE
Connect this pin to Vcc or Vss.
AVCC, AVSS
Analog power supply input
Connect AVss to Vss and AVcc to Vcc, respectively.
VREF
Reference voltage input
Input port P0
I
I
I
I
I
I
Enter the reference voltage for AD from this pin.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
Input port P1
Input port P2
Input port P3
Input port P4
P51 to P54,
P56, P57
Input port P5
I
Input "H" or "L" level signal or open.
P50
CE input
I
I
Input "H" level signal.
P55
EPM input
Input port P6
BUSY output
Input "L" level signal.
P60 to P63
P64
I
Input "H" or "L" level signal or open.
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
O
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P65
SCLK input
I
P66
RxD input
I
O
I
Serial data input pin
P67
TxD output
Input port P7
Serial data output pin
(Note 1)
P70 to P77
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P80 to P84, P86,
P87
Input port P8
NMI input
I
I
P85
Connect this pin to Vcc.
(Note 2)
(Note 2)
P90 to P97
Input port P9
Input port P10
Input port P11
I
I
I
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P100 to P107
P110 to P117
(Note 2)
(Note 2)
(Note 2)
(Note 2)
P120 to P127
P130 to P137
P140 to P147
Input port P12
Input port P13
Input port P14
I
I
I
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
___________
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET
pin is pulled low. Therefore, connect this pin to VCC via a resistor. Because this pin is directed for
data output after reset, adjust the pull-up resistance value in the system so that data transfers will
not be affected.
Note 2: Available in only the 128-pin version.
284
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CE
M16C/62P Group
(Flash memory version)
EPM
BUSY
SCLK
RxD
TxD
00
1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vss
Vcc
Mode setup method
Signal
CNVss
Value
Vcc
EPM
RESET
CE
Vss
Vss to Vcc
Vcc
Connect
oscillator
circuit.
Package: 100P6S-A
Figure 1.27.13. Pin Connections for Serial I/O Mode (1)
285
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
50
49
48
47
46
45
44
43
42
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10 0
CE
41
40
39
38
37
36
35
34
33
32
31
30
29
EPM
M16C/62P Group
(Flash memory version)
BUSY
SCLK
RXD
TXD
28
27
26
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
V
SS
V
CC
Mode setup method
Value
Vcc
Signal
CNVss
EPM
Vss
RESET
Vss to Vcc
CE
Vcc
Connect
oscillator
circuit.
Package: 100P6Q-A
Figure 1.27.14. Pin Connections for Serial I/O Mode (2)
286
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
102 101
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
CE
M16C/62P Group
(Flash memory version)
EPM
BUSY
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Vss
Vcc
Mode setup method
Valu
Signal
e
CNVss
Vcc
Vss
EPM
RESET
Vss to Vcc
Vcc
Connect
oscillator
circuit.
CE
Package: 128P6Q-A
Figure 1.27.15. Pin Connections for Serial I/O Mode (3)
287
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of Circuit Application in the Standard Serial I/O Mode
Figure 1.27.16 and 1.27.17 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.
Microcomputer
SCLK
Clock input
P50(CE)
TXD
Data input
P5 (EPM)
5
BUSY
RxD
BUSY output
Data output
CNVss
M16C/62P Group
(Flash memory version)
Reset input
RESET
User reset
singnal
NMI
(1) Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
(3) If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 1.27.16. Circuit Application in Standard Serial I/O Mode 1
288
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer
SCLK
TxD
P5
0(CE)
Data output
P5 (EPM)
5
BUSY
RxD
Monitor output
Data input
CNVss
NMI
(1) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
Figure 1.27.17. Circuit Application in Standard Serial I/o Mode 2
289
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Flash Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
In parallel input/output mode, the user ROM and boot ROM areas can be rewritten by using a parallel
programmer suitable for the M16C/62P group. For more information about parallel programmers, contact
the manufacturer of your parallel programmer. For details on how to use, refer to the user’s manual in-
cluded with your parallel programmer.
User ROM and Boot ROM Areas
In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area
contains a standard serial input/output mode based rewrite control program which was written in it when
shipped from the factory. Therefore, when using a serial programmer, be careful not to rewrite the boot
ROM area.
When in parallel output mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other
than the addresses 0FF00016 to 0FFFFF16.)
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)
290
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Package Outline
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package Outline
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
M
D
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I
2
–
–
–
Detail F
y
M
M
D
E
–
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
Weight(g)
0.63
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
–
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A1
0
0.1
A
2
–
1.4
b
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
c
D
E
e
25
51
H
H
L
D
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
L
M
b2
0.225
–
14.4
14.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
291
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Package Outline
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MMP
128P6Q-A
Plastic 128pin 14✕20mm body LQFP
EIAJ Package Code
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
M
D
LQFP128-P-1420-0.50
–
–
HD
D
128
103
1
102
l2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
1.4
0.05
–
Nom
1.5
0.125
1.4
Max
1.7
0.2
–
A
A
1
2
b
0.17
0.105
13.9
19.9
–
15.8
21.8
0.35
–
0.45
–
–
–
0°
0.22
0.125
14.0
20.0
0.5
16.0
22.0
0.5
1.0
0.6
0.25
–
–
0.27
0.175
14.1
20.1
–
16.2
22.2
0.65
–
0.75
–
0.08
0.1
8°
c
D
E
e
65
38
HD
HE
39
64
L
L
1
A
L1
F
Lp
A3
x
e
y
–
L
b2
–
–
0.225
1.0
–
–
b
y
x
M
Detail F
I2
Lp
M
M
D
–
–
14.4
20.4
–
–
E
292
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Differences Between M16C/62P and M16C/62A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences Between M16C/62P and M16C/62A
Differences in Mask ROM Version and Flash Memory Version (1) (Note)
Item
M16C/62P
M16C/62A
, VCC=4.2V to 5.5V)
Shortest instruction
execution time
41.7ns (f(BCLK)=24MH , VCC1=3.0 to 5.5V) 62.5ns (f(XIN)=16MH
Z
Z
100ns (f(BCLK)=10MH , VCC1=2.7 to 5.5V) 100ns (f(XIN)=10MH
Z
Z, VCC=2.7V to 5.5V
with software one-wait)
Supply voltage
VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1
4.2V to 5.5V (f(XIN)=16MH
Z
, without
(f(BCLK)=24MH
CC1=VCC2=2.7 to 5.5V
(f(BCLK)=10MH
Z
)
software wait)
V
2.7V to 5.5V (f(XIN)=10MH
one-wait)
Z
, with software
Z
)
I/O power supply
Package
Double (VCC1, VCC2
)
Single (VCC)
100-pin, 128-pin plastic mold QFP
80-pin, 100-pin plastic mold QFP
None
Voltage detection
circuit
Built-in
Vdet2, Vdet3, Vdet4 detect
Power supply voltage down detect interrupt
Hardware reset 2
X
IN, XCIN
PLL, XIN, XCIN, ring oscillator
Main clock division rate when main clock is
stopped: Divide-by-8 frequency
Clock Generating
Circuit
Main clock division rate when main
clock is stopped: No change
X
IN drive capacity when main clock is
XIN drive capacity when main clock is
stopped: No change
stopped: HIGH
System clock
protective function
Built-in
None
(protected by protect register)
Oscillation stop,
re-oscillation detection
function
Built-in
None
Low power
consumption
18mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
when wait mode)
32.5mA (VCC=5V, f(XIN)=16MHz)
8.5mA (VCC=3V, f(XCIN)=10MHz with
software one-wait)
0.9µA (VCC=3V, f(XCIN)=32kHz,
when wait mode)
Memory area
Memory area expandable
(4 Mbytes)
1 Mbytes fixed
External device
connect area
0400016–07FFF16(PM13=0)
0800016–0FFFF16(PM10=0)
1000016–26FFF16
0400016–05FFF16(PM13=0)
0600016–CFFFF16
D000016–FFFFF16(Microprocessor mode)
2800016–7FFFF16
8000016–CFFFF16(PM13=0)
D000016–FFFFF16(Microprocessor mode)
Upper address in
memory expansion
mode and
P4
0 to P43 (A16 to A19), P34 to P37 (A12 to
P40 to P43 (A16 to A19) : Switchable between
address bus and port
A
15) : Switchable between address bus and
port
microprocessor mode
Access to SFR
Variable (1 to 2 waits)
Variable (0 to 3 waits)
1 wait fixed
Software wait to
external area
Variable (0 to 1 wait)
Protect
Can be set for PM0, PM1, PM2, CM0,
CM1, CM2, PLC0, INVC0, INVC1, PD9, S3
C, S4C, TB2SC, PCLKR, VCR2, D4INT
registers
Can be set for PM0, PM1, CM0, CM1,
PD9, S3C, S4C registers
Watchdog timer interrupt
No count source protective mode
Watchdog timer interrupt or watchdog
timer reset is selected
Watchdog timer
Count source protective mode is available
2
Address match
interrupt
4
Note: About the details and the electric characteristics, refer to data sheet.
293
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Differences Between M16C/62P and M16C/62A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences in Mask ROM version and Flash memory version (2) (Note)
Item
M16C/62P
, f
M16C/62A
Selectable: f1, f8, f32, fC32
Timers A, B count
source
Selectable: f
1, f2
8
, f32, fC32
Timer A two-phase
pulse signal
Z-phase (counter reset) input is available
No Z-phase (counter reset input
processing
No function protect by protect register
Count source is selectable:
f1, f8, f32, fC32
Dead time timer count source is fixed at f
Timer functions for
three-phase motor
control
Function protect by protect register
Count source is selectable:
f1, f2, f8, f32, fC32
1/2
Dead time timer count source is selectable:
divided by 2, f , f divided by 2
Output polarity is selectable
Carrier wave phase detectable
f
1,
f1
2
2
Three-phase output port NMI control
(UART, clock synchronous, I2C bus, IE bus)
x 3
Serial I/O
(UART0 to UART2)
(UART, clock synchronous,) x 2
(UART, clock synchronous, IIC bus, IE bus)
x 1
UART0 to UART2,
SI/O3, SI/O4 count
source
Selectable: f1SIO, f2SIO, f8SIO, f32SIO
Selectable: f1, f8, f32
Serial I/O RTS timing
Assert low when receive buffer is read
Have
Assert low when reception is completed
None
CTS/RTS separate
function
UART2 data transmit
timing
After data was written, transfer starts at the
1st BRG overflow timing
After data was written, transfer starts at the
2nd BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
(same as UART0 and UART1)
Have
None
Serial I/O sleep
function
Serial I/O I2C mode
Start condition, stop condition:
Auto-generationable
Start condition, stop condition:
Not auto-generationable
Serial I/O I2C mode
SDA delay
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(XIN
)
SI/O3, SI/O4 clock
polarity selection
Selectable
Not selectable
A-D converter
10 bits X 8 channels
10 bits X 8 channels
Expandable up to 26 channels
Expandable up to 10 channels
A-D converter
operation clock
Selectable: fAD, fAD divided by 2, 3, 4, 6, 12
Selectable: ports P0, P2, P10
Selectable: fAD, fAD/2, fAD/4
Fixed at port P10
A-D converter
input pin
Note: About the details and the electric characteristics, refer to data sheet.
294
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Differences Between M16C/62P and M16C/62A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences in Flash memory version(Note)
Item
M16C/62P
M16C/62A
User ROM blocks
14 blocks: 4 Kbytes x 3, 8 Kbytes x 3,
32 Kbytes x1, 64 Kbytes x 7
7 blocks: 8 Kbytes x 2, 16 Kbytes x1,
32 Kbytes x 1, 64 Kbytes x 3
(Flash memory: max. 512 Kbytes)
(Flash memory: max. 256 Kbytes)
Program manner
Word
Page
Program command
(software command)
Page program command: none
Program command: have
(program method: in units of word, in units
of byte)
Page program command: have
Program command: none
(program method: in units of page)
None
Have
Block status after
program function
No EW1 mode
EW1 mode is available
CPU rewrite
mode
Note: About the details and the electric characteristics, refer to data sheet.
295
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Register Index
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Register Index
INVC0 131
A
INVC1 132
AD0 to AD7 192
ADCON0 191
ADCON1 191
ADCON2 192
AIER 92
O
ONSF 111
P
AIER2 92
P0 to P13 217
PC14 218
PCLKR 56
PCR 220
C
CM0 53
CM1 54
PD0 to PD13 216
PLC0 57
CM2 55
CPSRF 111, 124
CRCD 208
CRCIN 208
CSE 40
PM0 30
PM1 31
PM2 56
PRCR 74
CSR 34
PUR0 to PUR2 219
PUR3 218
D
R
D4INT 25
DA0 207
RMAD0 to RMAD3 92
DA1 207
ROMCP 264
DACON 207
DAR0 101
DAR1 101
DBR 44
S
S3BRG 185
S3C 185
DM0CON 100
DM1CON 100
DM1SL 100
DTT 133
S3TRR 185
S4BRG 185
S4C 185
S4TRR 185
SAR0 101
SAR1 101
F
FIDR 268
FMR0 268
T
TA0 to TA4 110
TA0MR to TA4MR 109
TA1 134
I
ICTB2 134
IDB0 133
IDB1 133
IFSR 89
TA11 134
TA1MR 136
TA2 134
IFSR2A 89
TA21 134
296
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
Mitsubishi microcomputers
development
M16C / 62P Group
Register Index
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TA2MR 136
TA4 134
TA41 134
TA4MR 136
TABSR 110, 124, 135
TB0 to TB5 124
TB0MR to TB5MR 123
TB2 135
TB2MR 136
TB2SC 134
TBSR 124
TCR0 101
TCR1 101
TRGSR 111, 135
U
U0BRG to U2BRG 142
U0C0 to U2C0 143
U0C1 to U2C1 144
U0MR to U2MR 143
U0RB to U2RB 142
U0SMR to U2SMR 145
U0SMR2 to U2SMR2 146
U0SMR3 to U2SMR3 146
U0SMR4 to U2SMR4 147
U0TB to U2TB 142
UCON 145
UDF 110
V
VCR1 25
VCR2 25
W
WDC 24, 96
WDTS 96
297
REVISION HISTORY
M16C/62P GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1
2
5
1.0 Jan/31/Y03
(Continued)
Applications are partly revised.
Table 1.1.1 is partly revised.
Table 1.1.3 is partly revised.
Figure 1.1.2 is partly revised.
5
11
20
21
22
24
25
26
27
30
31
39
41
43
44
53
54
55
57
60
61
62
63
63
64
64
65
68
69
70
71
77
78
88
96
99
100
103
104
105
109
115
117
Explanation of “Memory” is partly revised.
Explanation of “Hardware Reset 1” is partly revised.
Figure 1.5.1 is partly revised.
Figure 1.5.2 is partly revised.
Figure 1.5.4 is partly revised.
VCR2 Register in Figure 1.5.6 is partly revised.
Figure 1.5.6 is partly revised.
Explanation of “Power Supply Down Detection Interrupt” is partly revised.
Figure 1.6.1 is partly revised.
Figure 1.6.2 is partly revised.
Table 1.7.5 is partly revised.
Table 1.7.7 is partly revised.
Figure 1.7.8 is partly revised.
Explanation of “4 Mbyte Mode” is partly revised.
Notes 12 and 13 in Figure 1.9.2 is partly revised.
Notes 2 and 5 in Figure 1.9.3 is partly revised.
Figure 1.9.4 is partly revised.
Note 4 in Figure 1.9.6 is partly revised.
Explanation of “PLL Clock” is partly revised.
Figure 1.9.9 is partly revised.
Explanation of “CPU Clock and BCLK” is partly revised.
Explanation of “Low-speed Mode” is partly revised.
Explanation of “Low Power Dissipation Mode” is partly revised.
Explanation of “Ring Oscillator Low Power Dissipation Mode” is partly revised.
Table 1.9.3 is partly revised.
Table 1.9.5 is partly revised.
Figure 1.9.10 is partly revised.
Figure 1.9.11 is partly revised.
Table 1.9.7 is added.
Explanation of “System Clock Protective Function” is partly revised.
Explanation of “Power Supply Down Detection Interrupt” is partly revised.
Table 1.11.1 is partly revised.
Figure 1.11.9 is partly revised.
WDTS Register in Figure 1.12.2 is partly revised.
Figure 1.13.2 is partly revised.
Figure 1.13.3 is partly revised.
Figure 1.13.5 is partly revised.
Table 1.13.3 is partly revised.
Explanation of “DMA Enable” is partly revised.
Figure 1.14.3 is partly revised.
Table 1.14.3 is partly revised.
Explanation of “Counter Initialization by Two-Phase Pulse Signal Processing” is
partly revised.
117
122
122
Figure 1.14.10 is partly revised.
Figure 1.14.14 is partly revised.
Figure 1.14.15 is partly revised.
298
REVISION HISTORY
M16C/62P GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1.0 Jan/31/Y03
(Continued)
124
128
128
130
132
134
137
146
163
Figure 1.15.3 is partly revised.
Figure 1.15.7 is partly revised.
Figure 1.15.8 is partly revised.
Figure 1.16.1 is partly revised.
Figure 1.16.3 is partly revised.
Note 7 is added to TAi, TAi1 Register in Figure 1.16.5.
Figure 1.16.8 is partly revised.
UiSMR2 Register in Figure 1.17.7 is partly revised.
Figure 1.20.1 is partly revised.
164, 165 Table 1.20.2 and Table 1.20.3 are partly revised.
169
169
170
171
179
179
184
187
203
205
205
206
207
218
223
224
225
225
225
227
228
229
229
230
230
231
232
233
234
235
242
244
245
246
246
247
247
248
249
250
Figure 1.20.4 is partly revised.
Explanation of “Arbitration” is partly revised.
Explanation of “Transfer Clock” is partly revised.
Explanation of “ACK and NACK” is partly revised.
Explanation of “Special Mode 4 (SIM Mode)” is partly revised.
Table 1.20.9 is partly revised.
Figure 1.21.1 is partly revised.
Figure 1.21.4 is partly revised.
Explanation of “External Operation Amp Connection Mode” is partly revised.
Explanation of “Caution of Using A-D Converter” is partly revised.
Figure 1.22.11 is partly revised
Table 1.23.1 is partly revised.
Figure 1.23.3 is partly revised.
Figure 1.25.9 is partly revised.
Table 1.26.1 is partly revised.
Table 1.26.2 is partly revised.
Note 1 of Table 1.26.3 is partly revised.
Note 1 of Table 1.26.4 is partly revised.
Table 1.26.6 is partly revised.
Note 1 of Table 1.26.9 is partly revised.
Note 1 of Table 1.26.10 is partly revised.
Measurement conditions of timing requirements are partly revised.
Table 1.26.11 is partly revised.
Measurement conditions of timing requirements are partly revised.
Table 1.26.18 is added.
Measurement conditions of timing requirements are partly revised.
Measurement conditions of switching characteristics are partly revised.
Measurement conditions of switching characteristics are partly revised.
Measurement conditions of switching characteristics are partly revised.
Figure 1.26.2 is partly revised.
Figure 1.26.9 is partly revised.
Note of Table 1.26.28 is partly revised.
Figure 1.26.29 is partly revised.
Measurement conditions of timing requirements are partly revised.
Table 1.26.30 is partly revised.
Measurement conditions of timing requirements are partly revised.
Table 1.26.37 is added.
Measurement conditions of timing requirements are partly revised.
Measurement conditions of switching characteristics are partly revised.
Measurement conditions of switching characteristics are partly revised.
299
REVISION HISTORY
M16C/62P GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1.0 Jan/31/Y03
(Continued)
251
252
255
256
257
258
259
260
262
263
264
268
271
272
272
274
274
278
287
293
Measurement conditions of switching characteristics are partly revised.
Figure 1.26.12 is partly revised.
Figure 1.26.15 is partly revised.
Figure 1.26.16 is partly revised.
Figure 1.26.17 is partly revised.
Figure 1.26.18 is partly revised.
Figure 1.26.19 is partly revised.
Figure 1.26.20 is partly revised.
Explanation of “Memory Map” is partly revised.
Explanation of “Boot Mode” is partly revised.
Figure 1.27.3 is partly revised.
Note of FIDR Register in Figure 1.27.4 is partly revised.
Figure 1.27.7 is partly revised.
Explanation of “Interrupts” is partly revised.
Explanation of “Writing in the User ROM Space” is partly revised.
Table 1.27.4 is partly revised.
Explanation of “Read Array Command” is partly revised.
Explanation of “Program Command” is partly revised.
Figure 1.27.15 is partly revised.
Partly revised.
300
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is
always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property
damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best
suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights,
belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in
the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents
information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a
product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes
no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi
Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and
algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the
information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting
from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as
apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from
the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on
these materials or the products contained therein.
© 2003 MITSUBISHI ELECTRIC CORP.
Printed in Japan (ROD) II
New publication, effective February 2003.
Specifications subject to change without notice.
M16C/62
(M16C/62P)
G r o u p
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is the most
current document available.
Revision date: February 14, 2003
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
•
•
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without notice due
to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).
•
•
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-
tion as a total system before making a final decision on the applicability of the information
and products. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use
in a device or system that is used under circumstances in which human life is potentially at
stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon-
ductor product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or repro-
duce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be im-
ported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
Preface
This book describes the M16C/62 (M16C/62P) group's
precautions for use, which contains paragraphs describing pre-
cautions of the user's manual and technical news relevant to
these paragraphs. Please refer to this book when developing
your systems. However, all of precautions are not contained in
this book, please perform sufficient evaluation under systems
development.
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1. Usage Precaution
1.1 Precautions for Interrupts
1.1.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt is generated.
1
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1.1.2 Setting the SP
Set any value in the SP before accepting an interrupt. The SP is cleared to ‘000016’ after reset. Therefore,
if an interrupt is accepted before setting any value in the SP, the program may go out of control.
_______
Especially when using NMI interrupt, set a value in the SP at the beginning of the program. For the first
_______
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
2
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1.1.3 The _N__M___I_ Interrupt
_______
_______
1. The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
_______
2. The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5
_______
bit can only be read when determining the pin level after an NMI interrupt is generated.
_______
3. Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
_______
NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
_______
_______
4. Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
_______
5. The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.
3
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1.1.4 _I_N__T__ Interrupt
________
1. Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT5 regardless of the CPU operation clock.
________
________
2. When the polarity of the INT0 to INT5 pins is changed or the interrupt request cause of the software
interrupt numbers 8 to 9 is changed, the IR bit is sometimes set to “1” (interrupt request). After these
changes were made, set the interrupt request bit to “0” (no interrupt request). Figure 1.1.1 shows the
______
procedure for changing the INT interrupt generate factor.
Set the I flag to “0” (=disable interrupt)
Set the ILVL2 to ILVL0 bits to '000
2' (= level 0)
(Disable INT interrupt)
Set the POL bit
Set the IR bit to “0” (=interrupt not requested)
Set the ILVL2 to ILVL0 bits to
'0012' (=level 1) to '1112' (=level 7)
(Enable the accepting of INT interrupt request)
Set the I flag to “1” (= enable interrupt)
Note: Execute the setting above individually. Do not execute two or
more settings at once (by one instruction).
______
Figure 1.1.1. Procedure for Changing the INT Interrupt Generate Factor
4
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1.1.5 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
5
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.1 Precautions for Interrupts
1.1.6 Rewrite the Interrupt Control Register
Each interrupt control register can only be modified while no interrupt requests corresponding to that
register are generated. If interrupt requests managed by any interrupt control register are likely to occur,
disable the interrupts before modifying the register. A sample program is shown below.
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Set the TA0IC register to “0016”.
POPC FLG ; Enable interrupts.
Why the FSET I instruction is preceded by two NOP instructions (four when using HOLD function) in
Example 1 and why the FSET I instruction is preceded by a dummy read in Example 2
This is to prevent the I flag from being set to “1” before writing to the interrupt control register for reasons
of the instruction queue buffer.
To modify any interrupt control register after disabling interrupts, be careful with the instructions used.
(1) Modifying Other Than the IR Bit
If an interrupt request corresponding to that register is generated while executing the instruction, the IR
bit may not be set to “1” (= interrupt requested), with the result that the interrupt request is ignored. If this
presents a problem, use the following instructions to modify the register.
Instructions to use: AND, OR, BCLR, BSET
(2) Modifying the IR Bit
Even when the IR bit is cleared to “0” (= interrupt not requested), it may not actually be cleared to “0”
depending on the instruction used. Therefore, use the MOV instruction to clear the IR bit.
6
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.2 Precautions for Protect
1.2 Precautions for Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
7
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.3 Precautions for DMAC
1.3 Precautions for DMAC
1.3.1 Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
(*1)
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously
.
(*2)
Step 2: Make sure that the DMAi is in an initial state
in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes:
*1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to
“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
*2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If
the read value is a value in the middle of transfer, the DMAi is not in an initial state.
8
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4 Precautions for Timers
1.4.1 Timers A and B
This section describes precautions for timers A and B. Precautions for each mode should be referred as
well.
1. After reset, timers stop. After setting mode, count source or counter value, the TAiS bit (i=0 to 4) or
TBjS bit (j=0 to 5) in the TABSR or TBSR register should be set to “1” (starts counting). Make sure that
the TAiS bit or TBjS bit is set to “0” (stops counting) before changing the registers and bits listed below.
• TAiMR register and TBjMR register
• TAi register and TBj register
• UDF register
• TAZIE, TA0TGL and TA0TGH bits in ONSF register
• TRGSR register
9
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4.2 Timer A
1.4.2.1 Timer A (Timer Mode)
1. After reset, the TABSR register TAiS bit (i = 0 to 4) is cleared to “0” (stops counting). Select opera-
tion mode and set a value in the TAi register before setting the TAiS bit to “1” (starts counting).
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
______
3. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
10
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4.2.2 Timer A (Event Counter Mode)
1. After reset, the TABSR register TAiS bit (i = 0 to 4) is cleared to “0” (stopped counting). Select
operation mode and set a value in the TAi register before setting the TAiS bit to “1” (start counting).
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in the
TAi register while not counting, the set value is read.
______
3. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
11
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4.2.3 Timer A (One-shot Timer Mode)
1. After reset, the TABSR register TAiS bit (i = 0 to 4) is cleared to “0” (stopped counting). Select
operation mode and set a value in the TAi register before setting the TAiS bit to “1” (start counting).
2. When setting TABSR register to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs between
a trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, gener-
ate a second trigger between occurring the previous trigger and operating longer than one cycle of
a timer count source.
______
6. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
12
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4.2.4 Timer A (Pulse Width Modulation Mode)
1. After reset, the TABSR register TAiS bit (i = 0 to 4) is cleared to “0” (stopped counting). Select
operation mode and set a value in the TAi register before setting the TAiS bit to “1” (start counting).
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
______
4. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
______
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
13
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.4 Precautions for Timers
1.4.3 Timer B
1.4.3.1 Timer B (Timer Mode and Event Counter Mode)
1. After reset, the TBiS bit (i = 0 to 5) is cleared to “0” (stopped counting). Select operation mode and
set a value in the TBi register before setting the TBiS bit to “1” (start counting).
The TB0S to TB2S bits are the bits 5 to 7 of TABSR register, the TB3S to TB5S bits are the bits 5 to
7 of TBSR register.
2. A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
14
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1.4 Precautions for Timers
1.4.3.2 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The IR bit of TBiIC register (i=0 to 5) goes to “1” (overflow), when an effective edge of a measure-
ment pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by
use of the MR3 bit of TBiMR register within the interrupt routine.
2. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
3. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
4. Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
5. When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
6. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer
Bi interrupt request may be generated between a count start and an effective edge input.
7. When changing the MR1 to MR0 bits of TBiMR after a count is started, the IR bit of TBiIC register
may be set to “1” (interrupt request). Note that the IR bit does not change if the same value as
before is written to the MR1 to MR0 bits.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
15
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.5 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.5.1 Transmission/reception
_______
________
1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
________
________
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
_______
reception data with consistent timing. With the internal clock, the RTS function has no effect.
_______
2. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______
_________
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance
state.
16
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.5.2 Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit =
“0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer
clock), the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is
in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register = “0” (data present in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = “L”
17
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.5 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.5.3 Reception
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix set-
tings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data to the
UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an overrun
error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case, because
the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on
the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit-
ted. Note that when an overrun error occurred, the SiRIC register IR bit does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
• The RE bit of UiC1 register= “1” (reception enabled)
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register= “0” (data present in the UiTB register)
18
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.6 Precautions for Serial I/O (UART Mode, Special Mode 2)
1.6 Precautions for Serial I/O (UART Mode, Special Mode 2)
_______
1. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______
_________
output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance
state.
19
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for A-D Converter
1.7 Precautions for A-D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con-
nected), start A-D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi) each and the AVSS pin. Similarly,
insert a capacitor between the VCC pin and the VSS pin. Figure 1.7.1 is an example connection of each
pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.
Microcomputer
V
V
CC1
SS
AVCC
C4
V
REF
C2
C1
C3
AVSS
ANi
V
V
CC2
SS
C5
ANi: ANi, AN
0i, and AN
2i (i=0 to 7)
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 1.7.1. Use of capacitors to reduce noise
20
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.7 Precautions for A-D Converter
8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the
ADiIC register’s IR bit to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents of
ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
10. If VCC2 < VCC1, do not use AN00 to AN07 and AN20 to AN27 as analog input pins.
21
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1.8 Precautions for Power Control
1.8 Precautions for Power Control
____________
1. When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is
stabilized.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, de-
pending on a combination of instruction and an execution timing.
3. Wait until the tsu(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
4. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connec-
tion). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after setting
the VCUT bit to “1” (VREF connection).
(c) D-A converter
When not performing D-A conversion, set the DAi bit (i=0, 1) of DACON register to “0” (input inhibited)
and DAi register to “0016”.
(d) Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode. How-
ever, because the peripheral function clock (fC32) generated from the sub-clock does not stop, this
measure is not conducive to reducing the power consumption of the chip. During low speed mode and
low power dissipation mode, do not set the CM02 bit to “1” (peripheral function clock stopped when in
wait mode) before entering wait mode.
(e) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(f) External clock
When using an external clock input for the CPU clock, set the CM0 register CM05 bit to “1” (stop).
Setting the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the amount
of current drawn in the chip. (When using an external clock input, note that the clock remains fed into
the chip regardless of how the CM05 bit is set.)
22
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1.9 Precautions for External Bus
1.9 Precautions for External Bus
1. The external ROM version can operate only in the microprocessor mode, connect the CNVSS pin to
VCC.
2. When resetting CNVss pin with "H" input, contents of internal ROM cannot be read out.
23
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.10 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
1.10 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-
ducted in the flush memory version.
24
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.11 Precautions for Flash Memory Version
1.11 Precautions for Flash Memory Version
1.11.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written
in standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.
25
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1.11 Precautions for Flash Memory Version
1.11.2 Precautions for Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
26
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1.11 Precautions for Flash Memory Version
1.11.3 Precautions for Lock Bit Program Command
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure the
address value specified in the first bus cycle is the same uppermost block address that is specified in the
second bus cycle.
27
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1.11 Precautions for Flash Memory Version
1.11.4 Precautions for Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after returning from stop mode
28
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1.11 Precautions for Flash Memory Version
1.11.5 Precautions for Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode diabled) before executing the
WAIT instruction.
29
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1.11 Precautions for Flash Memory Version
1.11.6 Precautions for CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
1.11.6.1 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM0 register’s CM06 bit and CM1 register’s CM17–6 bits. Also, set the PM1 register’s PM17 bit to 1
(with wait state).
30
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1.11 Precautions for Flash Memory Version
1.11.6.2 Instructions inhibited against use
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
31
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1.11 Precautions for Flash Memory Version
1.11.6.3 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
32
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1.11 Precautions for Flash Memory Version
1.11.6.4 How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
33
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1.11 Precautions for Flash Memory Version
1.11.6.5 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
34
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.11 Precautions for Flash Memory Version
1.11.6.6 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
35
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.11 Precautions for Flash Memory Version
1.11.6.7 Writing command and data
Write the command code and data at even addresses.
36
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.11 Precautions for Flash Memory Version
1.11.7 Precautions for Low power dissipation mode, ring oscillator low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
37
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.12 Precautions for PLL Frequency Synthesizer
1.12 Precautions for PLL Frequency Synthesizer
Make the supply voltage stable to use the PLL frequency synthesizer.
For ripple with the supply voltage 5V, keep below 10kHz as frequency, below 0.5V (peak to peak) as
voltage fluctuation band and below 1V/mS as voltage fluctuation rate.
For ripple with the supply voltage 3V, keep below 10kHz as frequency, below 0.3V (peak to peak) as
voltage fluctuation band and below 0.6V/mS as voltage fluctuation rate.
38
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.13 Precautions for Programmable I/O Ports
1.13 Precautions for Programmable I/O Ports
_______
1. If a low-level signal is applied to the NMI pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_______
output forcible cutoff by input on NMI pin enabled), the P72 to P75, P80 and P81 pins go to a high-imped-
ance state.
39
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Under
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.1 Vdet2 Detection
2. Differences Made Depending on Manufactured Time
2.1 Vdet2 Detection
The present version of the products may not detect the Vdet2 voltage in the voltage detection circuit prop-
erly. Therefore, the followings should be noted.
(1) When the VC25 bit in the VCR2 register is set to “1” (enabling the RAM retention limit detection
circuit), the present version may not be reset even if the voltage at the Vcc1 input pin drops below
Vdet2.
(2) The WD5 bit in the WDC register may not change properly.
Supplementary Explanation
Normally, during the stop mode, the Vdet3 voltage is not detected, and thus no reset is generated even
when the input voltage at the VCC1 pin drops to Vdet3 or less. Therefore, if the microcomputer is not reset
when the VCC1 voltage drops below Vdet2 due to the reason described in the above No.1, the microcom-
puter cannot get out of the stop mode with Hardware Reset 2.
40
Mitsubishi microcomputers
Preliminary Specifications Rev.1.0
Under
Specifications in this manual are tentative and subject to change.
M16C / 62P Group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2 RESET Input
2.2 RESET Input
Ensure that pin RESET must hold valid-low state during powering-up.
When using a reset IC, use a CMOS type IC. When using an open-drain type reset IC, insert a capacitor
between the reset input and Vss and a resistor between the input and Vcc respectively. The R-C time
constant of the capacitor and resistor must provide a low state at least 10 times longer than the Vcc rise
time.
41
REVISION HISTORY
M16C/62P GROUP USAGE NOTES
Rev.
Date
Description
Summary
Page
1
8
9
1.0 Jan/31/Y03
Figure 1.1.1 is partly revised.
The section “1.3 Precautions for DMAC” is added.
The section “1.4.1 Timers A and B” is added.
The section “1.4.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode” is
partly revised.
15
18
19
The section “1.5.3 Reception” is partly revised.
The section “1.6 Precautions for Serial I/O (UART Mode, Special Mode 2)” is partly
revised.
22
25
The section “1.8 Precautions for Power Control” is partly revised.
The section “1.11.1 Precautions for Functions to Inhibit Rewriting Flash Memory
Rewrite” is partly revised.
26
38
The section “1.11.2 Precautions for Program Command” is partly revised.
The section “1.12 Precautions for PLL Frequency Synthesizer” is partly revised.
42
MITSUBISHI SEMICONDUCTORS
USAGE NOTES REFERENCE BOOK
M16C/62 (M16C/62P) Group
February First Edition 2003
Editioned by
Committee of editing of Mitsubishi Semiconductor Usage Notes Reference
Book
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©2003 MITSUBISHI ELECTRIC CORPORATION
Usage Notes Reference Book
M16C/62 (M16C/62P) Group
New publication, effective February 2003.
Specifications subject to change without notice.
© 2003 MITSUBISHI ELECTRIC CORPORATION.
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