M37733 [MITSUBISHI]

16-BIT CMOS MICROCOMPUTER; 16位微机的CMOS


型号：	M37733
厂家：	Mitsubishi Group
描述：	16-BIT CMOS MICROCOMPUTER 16位微机的CMOS 计算机
文件：	总36页 (文件大小：927K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

DESCRIPTION

●Serial I/O (UART or clock synchronous)..................................... 3

●10-bit A-D converter .............................................. 8-channel inputs

●12-bit watchdog timer

The M37733S4LHP is a microcomputer using the 7700 Family core.

This microcomputer has a CPU and a bus interface unit. The CPU is

a 16-bit parallel processor that can be an 8-bit parallel processor,

and the bus interface unit enhances the memory access efficiency to

execute instructions fast. This microcomputer also includes a 32 kHz

oscillation circuit, in addition to the RAM, multiple-function timers,

serial I/O, A-D converter, and so on.

●Programmable input/output

(ports P4, P5, P6, P7, P8) ........................................................ 37

●Clock generating circuit ........................................ 2 circuits built-in

●Small package ..................... 80-pin plastic molded fine-pitch QFP

(80P6D-A;0.5 mm lead pitch)

Its strong points are the low power dissipation, the low supply voltage

and the small package.

APPLICATION

Control devices for general commercial equipment such as office

automation, office equipment, personal information equipment, and

so on.

FEATURES

●Number of basic instructions .................................................. 103

●Memory size

RAM ................................................ 2048 bytes

Control devices for general industrial equipment such as

communication equipment, and so on.

●Instruction execution time

The fastest instruction at 12 MHz frequency ...................... 333 ns

●Single power supply ...................................................... 2.7–5.5 V

●Low power dissipation (At 3 V supply voltage, 12 MHz frequency)

............................................ 10.8 mW (Typ.)

●Interrupts ............................................................ 19 types, 7 levels

●Multiple-function 16-bit timer ................................................. 5 + 3

PIN CONFIGURATION (TOP VIEW)

/CTS

XD0

/CLK

/RTS

/CLKS

P8 /CLK

/RTS /CLKS

/A¹⁸/D

/CTS

VSS

/A ¹⁹/D

/A²⁰/D

/A²¹/D

/A²²/D

/A23/D

/R/W

/BHE

/ALE

/HLDA

VCC

AV^CC

REF

AV^SS

M37733S4LHP

VSS

P7 /AN

/AN /AD^TRG/T

P7 /AN /R

P7 /CLK

P7 /CTS

7/AN

7/X^CIN

OUT

/X^COUT

P75

RESET

CNV^SS

BYTE

HOLD

RDY

/AN

/TB2^IN

/AN

P42 / 1

SUB

Outline

80P6D-

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Data Bus(Even)

Data Bus(Odd)

Data Buffer DBH(8)

Data Buffer DB

L(8)

Instruction Queue Buffer Q

0(8)

Instruction Queue Buffer Q

1(8)

Instruction Queue Buffer Q

2(8)

Address Bus

Incrementer(24)

Program Address Register PA(24)

Data Address Register DA(24)

Incrementer/Decrementer(24)

Program Counter PC(16)

Program Bank Register PG(8)

Data Bank Register DT(8)

Input Butter Register IB(16)

Processor Status Register PS(11)

Direct Page Register DPR(16)

Stack Pointer S(16)

Index Register Y(16)

Index Register X(16)

Accumulator B(16)

Accumulator A(16)

COUT

CIN

Arithmetic Logic

Unit(16)

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

FUNCTIONS OF M37733S4LHP

Parameter

Functions

Number of basic instructions

Instruction execution time

103

333 ns (the fastest instruction at external clock 12 MHz frequency)

Memory size

RAM

2048 bytes

P5 – P8

8-bit ✕ 4

5-bit ✕ 1

Input/Output ports

TA0, TA1, TA2, TA3, TA4

TB0, TB1, TB2

16-bit ✕ 5

16-bit ✕ 3

Multi-function timers

Serial I/O

A-D converter

Watchdog timer

(UART or clock synchronous serial I/O) ✕ 3

10-bit ✕ 1 (8 channels)

12-bit ✕ 1

3 external types, 16 internal types

Interrupts

Each interrupt can be set to the priority level (0 – 7.)

2 circuits built-in (externally connected to a ceramic resonator or a

quartz-crystal oscillator)

Clock generating circuit

Supply voltage

2.7 – 5.5 V

10.8 mW (at 3 V supply voltage, external clock 12 MHz frequency)

27 mW (at 5 V supply voltage, external clock 12 MHz frequency)

Power dissipation

Input/Output voltage

Output current

5 V

5 mA

Input/Output characteristic

Memory expansion

Operating temperature range

Device structure

Maximum 16 Mbytes

–40 to 85 °C

CMOS high-performance silicon gate process

80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch)

Package

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

BASIC FUNCTION BLOCKS

The 2048-byte area allocated to addresses from 8016 to 87F16 is the

built-in RAM. In addition to storing data, the RAM is used as stack

during a subroutine call or interrupts.

The M37733S4LHP has the same functions as the

M37733MHBXXXFP except for the following :

(1) The memory map is different.

Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,

and interrupt control registers are allocated to addresses from 016 to

7F16.

(2) The processor mode is different.

(3) The reset circuit is different.

(4) Pulse output port mode of timer A is available.

(5) The function of ROM area modification is not available.

A 256-byte direct page area can be allocated anywhere in bank 016

by using the direct page register (DPR). In the direct page addressing

mode, the memory in the direct page area can be accessed with two

words. Hence program steps can be reduced.

MEMORY

The memory map is shown in Figure 1. The address space has a

capacity of 16 Mbytes and is allocated to addresses from 016 to

FFFFFF16. The address space is divided by 64-Kbyte unit called bank.

The banks are numbered from 016 to FF16.

Built-in RAM and control registers for internal peripheral devices are

assigned to bank 016.

Addresses FFD616 to FFFF16 are the RESET and interrupt vector

addresses and contain the interrupt vectors. Use ROM for memory

of this address.

00000016

00007F16

00008016

00000016

Internal peripheral

devices

Bank 016

Bank 116

control registers

refer to Fig. 2 for

detail information

00FFFF16

01000016

Internal RAM

00007F16

2048 bytes

Interrupt vector table

00FFD616

A-D/UART2 trans./rece.

00087F16

UART1 transmission

UART1 receive

01FFFF16

UART0 transmission

UART0 receive

Timer B2

Timer B1

Timer B0

Timer A4

Timer A3

Timer A2

FE000016

Timer A1

Timer A0

Bank FE16

Bank FF16

INT /Key input

INT1

INT0

FEFFFF16

FF000016

Watchdog timer

DBC

BRK instruction

00FFD616

00FFFF16

Zero divide

RESET

00FFFE16

FFFFFF16

: Internal

: External

Fig. 1 Memory map

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Address (Hexadecimal notation)

Count start flag

One-shot start flag

Up-down flag

000000

000001

000002

000003

000004

000040

000041

000042

000043

000044

000045

000046

000047

000048

000049

00004A

00004B

00004C

00004D

00004E

00004F

000050

000051

000052

000053

000054

000055

000056

000057

000058

000059

00005A

00005B

00005C

00005D

00005E

00005F

000060

000061

000062

000063

000064

000065

000066

000067

000068

000069

00006A

00006B

00006C

00006D

00006E

00006F

000070

000071

000072

000073

000074

000075

000076

000077

000078

000079

00007A

00007B

00007C

00007D

00007E

Port P0 register

Port P1 register

Port P0 direction register

000005 Port P1 direction register

Port P2 register

000006

000007

000008

000009

00000A

00000B

00000C

00000D

00000E

00000F

000010

000011

000012

000013

000014

000015

000016

000017

000018

000019

00001A

00001B

00001C

00001D

00001E

00001F

000020

000021

000022

000023

000024

000025

000026

000027

000028

000029

00002A

00002B

00002C

00002D

00002E

00002F

000030

000031

000032

000033

000034

000035

000036

000037

000038

000039

00003A

00003B

00003C

00003D

00003E

00003F

Timer A0 register

Timer A1 register

Timer A2 register

Timer A3 register

Timer A4 register

Timer B0 register

Timer B1 register

Timer B2 register

Port P3 register

Port P2 direction register

Port P3 direction register

Port P4 register

Port P5 register

Port P4 direction register

Port P5 direction register

Port P6 register

Port P7 register

Port P6 direction register

Port P7 direction register

Port P8 register

Port P8 direction register

Timer A0 mode register

Timer A1 mode register

Timer A2 mode register

Timer A3 mode register

Timer A4 mode register

Timer B0 mode register

Timer B1 mode register

Pulse output data register 1

Pulse output data register 0

A-D control register 0

Timer B2 mode register

Processor mode register 0

Processor mode register 1

Watchdog timer register

Watchdog timer frequency selection flag

Waveform output mode register

Reserved area (Note)

A-D control register 1

A-D register 0

A-D register 1

A-D register 2

A-D register 3

A-D register 4

A-D register 5

A-D register 6

A-D register 7

UART2 transmit/receive mode register

UART2 baud rate register (BRG2)

UART2 transmission buffer register

UART2 transmit/receive control register 0

UART2 transmit/receive control register 1

UART2 receive buffer register

Oscillation circuit control register 0

Port function control register

Serial transmit control register

Oscillation circuit control register 1

A-D/UART2 trans./rece. interrupt control register

UART 0 transmission interrupt control register

UART 0 receive interrupt control register

UART 1 transmission interrupt control register

UART 1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

UART 0 transmit/receive mode register

UART 0 baud rate register (BRG0)

UART 0 transmission buffer register

UART 0 transmit/receive control register 0

UART 0 transmit/receive control register 1

UART 0 receive buffer register

UART 1 transmit/receive mode register

UART 1 baud rate register (BRG1)

UART 1 transmission buffer register

UART 1 transmit/receive control register 0

UART 1 transmit/receive control register 1

INT

interrupt control register

INT1

UART 1 receive buffer register

00007F INT

2/Key input interrupt control register

Note . Do not write to this address.

Fig. 2 Location of internal peripheral devices and interrupt control registers

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

shows the bit configuration of the pulse output data register. The

contents of the pulse output data register 1 (low-order four bits of

1C16 address) corresponding to RTP10, RTP11, RTP12, and RTP13

is output to the ports each time the counter of timer A2 becomes

000016. The contents of the pulse output data register 0 (low-order

four bits of 1D16 address) corresponding to RTP00, RTP01, RTP02,

and RTP03 is output to the ports each time the counter of timer A0

becomes 000016.

Pulse output port mode

The pulse motor drive waveform can be output by using plural internal

timer A.

Figure 3 shows a block diagram for pulse output port mode. In the

pulse output port mode, two pairs of four-bit pulse output ports are

used. Whether using pulse output port or not can be selected by

waveform output selection bit (bit 0, bit 1) of waveform output mode

output selection bit is set to “1”, RTP10, RTP11, RTP12, and RTP13

are used as pulse output ports, and when bit 1 of waveform output

selection bit is set to “1”, RTP00, RTP01, RTP02, and RTP03 are

used as pulse output ports. When bits 1 and 0 of waveform output

selection bit are set to “1”, RTP10, RTP11, RTP12, and RTP13, and

RTP00, RTP01, RTP02, and RTP03 are used as pulse output ports.

The ports not used as pulse output ports can be used as normal

parallel ports, timer input/output or key input interrupt input.

In the pulse output port mode, set timers A0 and A2 to timer mode as

timers A0 and A2 are used. Figure 5 shows the bit configuration of

timer A0, A2 mode registers in pulse output port mode.

Figure 7 shows example of waveforms in pulse output port mode.

When “0” is written to a specified bit of the pulse output data register,

“L” level is output to the corresponding pulse output port when the

counter of corresponding timer becomes 000016, and when “1” is

written, “H” level is output to the pulse output port.

Pulse width modulation can be applied to each pulse output port.

Since pulse width modulation involves the use of timers A1 and A3,

activate these timers in pulse width modulation mode.

Data can be set in each bit of the pulse output data register

corresponding to four ports selected as pulse output ports. Figure 6

Pulse width modulation selection bit

(Bit 4, 5 of 62¹⁶address)

Pulse width modulation output

by timer A3

Pulse width modulation output

by timer A1

Timer A2

Pulse output data

RTP1³(P57)

RTP1²(P56)

D³

RTP1¹(P55)

RTP10 (P54)

RTP0³(P53)

D11

D10

RTP02 (P52)

RTP0¹(P51)

RTP0⁰(P50)

Pulse output data

Polarity selection bit

(Bit 3 of 62¹⁶address)

Timer A0

Fig. 3 Block diagram for pulse output port mode

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

RTP10, RTP11, RTP12, and RTP13 are applied pulse width modulation

by timer A3 by setting the pulse width modulation selection bit by

timer A3 (bit 5) of the waveform output mode register to “1”.

Address

RTP00, RTP01, RTP02, and RTP03 are applied pulse width modulation

by timer A1 by setting the pulse width modulation selection bit by

timer A1 (bit 4) of the waveform output mode register to “1”.

Timer A0 mode register 5616

Timer A2 mode register 5816

Always “100” in pulse output

port mode

The contents of the pulse output data register 0 can be reversed and

output to pulse output ports RTP00, RTP01, RTP02, and RTP03 by

the polarity selection bit (bit 3) of the waveform output mode register.

When the polarity selection bit is “0”, the contents of the pulse output

data register 0 is output unchangeably, and when “1”, the contents of

the pulse output data register 0 is reversed and output. When pulse

width modulation is applied, likewise the polarity reverse to pulse

width modulation can be selected by the polarity selection bit.

Not used in pulse output port mode

Always “00” in pulse output port mode

Clock source selection bit

0 0 : Select f

0 1 : Select f16

1 0 : Select f64

1 1 : Select f512

Fig. 5 Timer A0, A2 mode register bit configuration in pulse output

port mode

6 5 4 3 2 1 0

Address

Weveform output mode register 6216

Weveform output selection bit

0 0 : Parallel port

0 1 : RTP1 selected

1 0 : RTP0 selected

6 5 4 3 2 1 0

Address

1 1 : RTP1 and RTP0 selected

Pulse output data register 0 1D16

Polarity selection bit

0 : Positive polarity

1 : Negative polarity

RTP0

output data

Pulse width modulation selection bit

by timer A1

0 : Not modulated

1 : Modulated

Pulse width modulation selection bit

by timer A3

0 : Not modulated

1 : Modulated

6 5 4 3 2 1 0

Address

Pulse output data register 1 1C16

Always “0”

RTP1

output data

Fig. 4 Waveform output mode register bit configuration

Fig. 6 Pulse output data register bit configuration

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Example of pulse output port (RTP10 – RTP13)

Output signal at each time

when timer A2 becomes 000016

RTP13 (P57)

RTP12 (P56)

RTP11 (P55)

RTP10 (P54)

Example of pulse output port (RTP10 – RTP13) when pulse width modulation is applied by timer A3.

Output signal at each time

when timer A2 becomes 000016

RTP13 (P57)

RTP12 (P56)

RTP11 (P55)

RTP10 (P54)

Example of pulse output port (RTP00 – RTP03) when pulse width modulation is applied

by timer A1 with polarity selection bit = “1”.

Output signal at each time

when timer A0 becomes 000016

RTP03 (P53)

RTP02 (P52)

RTP01 (P51)

RTP00 (P50)

Fig. 7 Example of waveforms in pulse output port mode

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

PROCESSOR MODE

• BYTE pin

The bits 0 of processor mode register 0 as shown in Figure 8 is used

to select which mode of microprocessor mode, and evaluation chip

mode.

When accessing the external memory, the level of the BYTE pin is

used to determine whether to use the data bus as 8-bit width or 16-

bit width.

Figure 9 shows functions of P00/A0 to P47 pins in each mode.

The external memory area also changes when the mode changes.

Figure 10 shows the memory map for each mode.

The accessing of the external memory is affected by the BYTE pin,

the bit 2 (wait bit) of processor mode register 0, and bit 0 (wait selection

bit) of processor mode register 1.

The data bus width is 8 bits when the level of the BYTE pin is “H”,

and P20/A16/D0 to P27/A23/D7 pins become the data I/O pins.

The data bus width is 16 bits when the level of the BYTE pin is “L”,

and both P20/A16/D0 to P27/A23/D7 pins and P10/A8/D8 to P17/A15/

D15 pins become the data I/O pins.

When accessing the internal memory, the data bus width is always

16 bits regardless of the BYTE pin level.

7 6 5 4 3 2 1 0

Address

5E16

Address

5F16

Processor mode register 0

Processor mode register 1

Wait selection bit

0 : Wait 0

1 : Wait 1

Processor mode bit

0 : Microprocessor mode

1 : Evaluation chip mode

This bit must be “1”

(becomes “1” after reset release)

Wait bit

0 : Wait

1 : No Wait

Software reset bit

Reset occurs when this bit is set to “1”

Interrupt priority detection time selection bit

0 0 : Internal clock ✕ 7

0 1 : Internal clock ✕ 4

1 0 : Internal clock ✕ 2

This bit must be “0”

Not used

Fig. 8 Processor mode register bit configuration

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Mode

Microprocessor mode

Evaluation Chip mode

Same as left

P00/A0 - P07/A7

Address A0-A7

P07

to A15

Address

P10/A8/D8

BYTE = “L”

BYTE = “H”

Data(odd)

7/A15/D15

0/A8/D8

to A15

Address

P10/A

0/A8/D8

P17

/A15/D15

Data(odd)

Address A8-A15

P17/A15/D15

Ports P4, P5 and their direction registers

are treated as 16-bit wide bus.

/A16/D

16 to A23

Address

BYTE = “L”

BYTE = “H”

Same as left

Data(even)

P27

/A23/D

P20

/A16/D

/A16/D0

16 to A23

Address

16 to A23

Address

P27

/A23/D

P20

/A16/D

Data(even, odd)

P27

/A23/D

P27/A23/D7

Ports P4, P5 and their direction registers

are treated as 16-bit wide bus.

/R/W

/BHE

/ALE

R/W

BHE

ALE

P30

P31

P32

P33

/R/W,

BHE,

Same as left

/ALE,

HLDA

P33/HLDA

HOLD,

RDY,

HOLD

RDY

HOLD

RDY

HOLD

RDY

P42

Port P4

to P47

P42

I/O Port

QCL

VDA

VPA

DBC

Fig. 9 Relationship between pins P00 /A0 to P47 and processor modes

Note. The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the

1 output

in the microprocessor mode. In the microprocessor mode, signal E can also be fixed to “H” when the internal

memory area is accessed.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

• Wait bit

Internal clock

Ai/Dj

As shown in Figure 11, when the external memory area is accessed

with the processor mode register 0 (address 5E16) bit 2 (wait bit)

cleared to “0”, the access time can be extended compared with no

wait (the wait bit is “1”).

Address

Data

Wait bit “1”

(No wait)

The access time is extended in two ways and this is selected with bit

0 (wait selection bit) of processor mode register 1 (address 5F16).

When this bit is “1”, the access time is 1.5 times compared to that for

no wait. When this bit is “0”, the access time is twice compared to

that for no wait.

ALE

Access time

Address

Data

Ai/Dj

Wait bit “0”

(Wait 1)

At reset, the wait bit and the wait selection bit are “0”.

The accessing of internal memory area is performed in no wait mode

regardless of the wait bit.

ALE

The processor modes are described below.

Access time

Address

Data

Ai/Dj

Wait bit “0”

(Wait 0)

Microprocessor

mode

Evaluation chip

mode

ALE

216

A16

0016

Access time

SFR

C16

Fig. 11 Relationship between wait bit, wait selection bit, and access time

SFR

8016

(1) Microprocessor mode [10]

Microprocessor mode is entered by connecting the CNVss pin to Vcc

and starting from reset.

RAM

87F16

Signal E is output from pin E and is “L” during the data/instruction

code read or data write term. When the internal memory area is read

or written, E can be fixed to “H” by setting the signal output disable

selection bit (bit 6 of oscillation circuit control register 0) to “1”.

P00/A0 to P07/A7 pins become address output pins.

P10/A8/D8 to P17/A15/D15 pins have two functions depending on the

level of the BYTE pin.

When the BYTE pin level is “L”, P10/A8/D8 to P17/A15/D15 pins function

as an address output pin while E is “H” and as an odd address data

I/O pin while E is “L”. However, if an internal memory is read, external

data is ignored while E is “L”.

When the BYTE pin level is “H”, P10/A8/D8 to P17/A15/D15 pins function

as an address output pin.

When the BYTE pin level is “L”, P20/A16/D0 to P27/A23/D7 pins function

as an address output pin while E is “H” and as an even address data

FFFFFF16

I/O pin while E is “L”. However, if an internal memory is read, external

data is ignored while E is “L”.

The shaded area is the external memory area.

R/W is a read /write signal which indicates a read when it is “H” and a

write when it is “L”.

___

Fig. 10 External memory area for each processor mode

BHE is a byte high enable signal which indicates that an odd address

is accessed when it is “L”.

Therefore, two bytes at even and odd addresses are accessed

___

simultaneously if address A0 is “L” and BHE is “L”.

ALE is an address latch enable signal used to latch the address signal

from a multiplexed signal of address and data. The latch is transparent

while ALE is “H” to let the address signal pass through and held

while ALE is “L”.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

____

HLDA is a hold acknowledge signal and is used to notify externally

____

addresses are accessed, the data bus width is treated as 16 bits

regardless of the BYTE pin level, and the access cycle is treated as

internal memory regardless of the wait bit.

when the microcomputer receives HOLD input and enters hold state.

____

HOLD is a hold request signal. It is an input signal used to put the

____

___

microcomputer in hold state. HOLD input is accepted when the internal

The functions of HOLD and RDY are the same as those in

microprocessor mode. Clock 1 from P42/ 1 pin is always output

clock

falls from “H” level to “L” level while the bus is not used.

P00/A0 to P07/A7 pins, P10/A8/D8 to P17/A15/D15 pins, P20/A16/D0 to

regardless of signal output disable selection bit.

___

P27/A23/D7 pins, P30/R/W pin, and P31/BHE pin are floating while the

Ports P43 to P46 become MX, QCL, VDA, and VPA output pins

___

microcomputer stays in hold state. These pins are floating after one

____

respectively. Port P47 becomes the DBC input pin.

cycle of the internal clock

later than HLDA signal changes to “L”

The MX signal normally contents of flag m, but the contents of flag x

is output if the CPU is using flag x.

level. At the removing of hold state, these ports are removed from

____

later than HLDA signal

floating state after one cycle of internal clock

QCL is the queue buffer clear signal. It becomes “H” when the

instruction queue buffer is cleared, for example, when a jump

instruction is executed.

changes to “H” level.

___

RDY is a ready signal. If this signal goes “L”, the internal clock

___

stops at “L”. RDY is used when slow external memory is attached.

VDA is the valid data address signal. It becomes “H” while the CPU

is reading data from data buffer or writing data to data buffer. It also

becomes “H” when the first byte of the instruction (operation code) is

read from the instruction queue buffer.

P42/

1 pin is an output pin for clock

1. The

1 output is

___

independent of RDY and does not stop even when internal clock

___

stops because of “L” input to the RDY pin. As shown in Table 2,

output can also be stopped with the signal output disable selection

bit “1”. In this case, write “1” to the port P42 direction register.

VPA is the valid program address signal. It becomes “H” while the

CPU is reading an instruction code from the instruction queue buffer.

___

DBC is the debug control signal and is used for debugging. Table 1

shows the relationship between the CNVSS pin input levels and

processor modes.

(2) Evaluation chip mode [11]

Evaluation chip mode is entered by applying voltage twice the VCC

voltage to the CNVSS pin. This mode is normally used for evaluation

tools.

____

___

The functions of E, P00/A0 to P07/A7 pins, R/W, BHE, ALE, and HLDA

are the same as those in microprocessor mode.

Table 1. Relationship between CNVss pin input levels and processor

modes

P10/A8/D8 to P17/A15/D15 pins function as address output pins while

E is “H” and as data I/O pin of odd addresses while E is “L” regardless

CNVss

Mode

Description

of the BYTE pin level. However, if an internal memory is read, external

• Microprocessor

(• Evaluation chip) starting after reset.

Microprocessor mode upon

Vss

data is ignored while E is “L”. P20/A16/D0 to P27/A23/D7 pins function

• Evaluation chip Evaluation chip mode only.

2 • Vcc

as address output pins while E is “H” and as data I/O pin of even

addresses while E is “L” when the BYTE pin level is “L”. However, if

an internal memory is read, external data is ignored while E is “L”.

When the BYTE pin level is “H” or 2•VCC, port P2 functions as an

address output pin while E is “H” and as data I/O pin of even and odd

addresses while E is “L”. However, if an internal memory is read,

external data is ignored while E is “L”.

Port P4 and its data direction which are located at address 0A16 and

0C16 are treated differently in evaluation chip mode. When these

Table 2. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0)

Function

Processor mode

CM6 = “0”

CM6 = “1”

E is output when the internal/external memory E is output only when the external memory

area is accessed.

After WIT/STP instruction is executed,

“H” is output.

“L” is output after WIT/STP instruction is

executed.

Microprocessor mode

Standby state selection bit (bit 0 of port

function control register) must be set to “1”.

Clock

1 is output.

“H”or “L” is output. (Output the content of

P42 latch.)

Port P42 direction register must be set to

“1”.

Note. Functions shown in Table 2 cannot be emulated in a debugger.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

RESET CIRCUIT

is input from the external to the main-clock oscillation circuit, the reset

input voltage must be 0.55 V or less when the power source voltage

reaches 2.7 V. If a resonator/oscillator is connected to the main-clock

oscillation circuit, change the reset input voltage from “L” to “H” after

the main-clock oscillation is fully stabilized.

_____

The microcomputer is released from the reset state when the RESET

pin is returned to “H” level after holding it at “L” level with the power

source voltage at 2.7 – 5.5 V. Program execution starts at the address

formed by setting address A23 – A16 to 0016, A15 – A8 to the contents

of address FFFF16, and A7 – A0 to the contents of address FFFE16.

Figure 12 shows the status of the internal registers during reset.

Figure 13 shows an example of a reset circuit. If the stabilized clock

Address

Port P0 direction register

Port P1 direction register

0016

Watchdog timer frequency selection flag

Waveform output mode register

(6116

)

•••

(0416

(0516

(0816

(0916

)

•••

(6216

(6416

(6816

(6916

)

•••

0 0

UART2 transmit/receive mode register

UART2 transmit/receive control register 0

)

0 0 0 0 0 0 0

1 0 0 0

Port P2 direction register

Port P3 direction register

Port P4 direction register

Port P5 direction register

Port P6 direction register

Port P7 direction register

0 0 0 0

•••

(0C16

)

•••

0016

UART2 transmit/receive control register 1

Oscillation circuit control register 0

0 0 0 0 0 1 0

(0D16

)

•••

(6C16

)

•••

0 0 0 0 0

0016

(1016

(1116

(1416

)

•••

(6D16

)

•••

0016

Port function control register

Serial transmit control register

)

0 0

(6E16

)

•••

0016

(6F16

)

0 0 0 0 0

0 0 0 0

Oscillation circuit control register 1

Port P8 direction register

A-D control register 0

0 0 0 0 0 ? ? ?

)•••

A-D/UART2 trans./rece. interrupt control register

(7016

(7116

(7216

)

(1E16

(1F16

)

•••

0 0 0

0016

1 1

UART 0 transmission interrupt control register

UART 0 receive interruupt control register

0 0 0 0

)

A-D control register 1

UART 0 transmit/receive mode register

(3016

(3816

(3416

)

•••

0 0 0 0

)

•••

UART 1 transmit/receive mode register

0016

0 0 0 0

_{UART 1 transmission interrupt control register}(7316

•••

0 0 0 0 1 0 0

UART 0 transmit/receive

control register 0

UART 1 transmit/receive

control register 0

UART 0 transmit/receive

control register 1

UART 1 transmit/receive

control register 1

Count start flag

One- shot start flag

Up-down flag

0 0 0 0

(7416

(7516

(7616

(7716

(7816

(7916

UART 1 receive interruupt control register

Timer A0 interrupt control register

(3C16

)

•••

0 0 0 0

0 0 0 0 0 0 1 0

0016

(3516

(3D16

)

•••

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

0 0 0 0

)

•••

0 0 0 0

(4016

(4216

(4416

(5616

(5716

(5816

(5916

)

•••

0 0 0 0

)

•••

0 0 0 0

Timer A4 interrupt control register

Timer B0 interrupt control register

0016

•••

0 0 0 0

(7A16

)

•••

0016

•••

0 0 0 0

Timer A0 mode register

Timer A1 mode register

Timer A2 mode register

Timer A3 mode register

Timer A4 mode register

Timer B0 mode register

(7B16

)

•••

Timer B1 interrupt control register

Timer B2 interrupt control register

0016

0 0 0 0

(7C16

)

•••

INT

interrupt control register

0 0 0 0 0 0

(7D16

)

•••

0016

INT

(7E16

)

•••

(5A16

(5B16

)

•••

0016

(7F16

)

•••

INT2/Key input interrupt control register

)

•••

0 0 1 0 0 0 0

0 0 0 ? ? 0 0 0 1 ? ?

Processor status register (PS)

Program bank register (PG)

(5C16

)

^•••0 0 1

0 0 0

0016

Content of FFFF16

Content of FFFE16

000016

Timer B1 mode register

Timer B2 mode register

Processor mode register 0

Processor mode register 1

(5D16

)

^•••0 0 1

Program counter (PC

(5E16

)

•••

0016

Program counter (PC

(5F16

)

•••

Direct page register (DPR)

Data bank register (DT)

FFF16

(6016)•••

0016

Watchdog timer register

Contents of other registers and RAM are undefined during reset. Initialize them by software.

Fig. 12 Microcomputer internal status during reset

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Power on

2.7V

VCC

RESET

VCC

RESET

0.55V

Note. In this case, stabilized clock is input from the

external to the main-clock oscillation circuit.

Perform careful evalvation at the system design

level before using.

Fig. 13 Example of a reset circuit

ADDRESSING MODES

The M37733S4LHP has 28 powerful addressing modes. Refer to the

MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP

16-BIT MICROCOMPUTERS for the details of each addressing mode.

MACHINE INSTRUCTION LIST

The M37733S4LHP has 103 machine instructions. Refer to the

MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP

16-BIT MICROCOMPUTERS for details.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS

Symbol

Vcc

AVcc

Parameter

Power source voltage

Conditions

Ratings

Unit

–0.3 to +7

–0.3 to +12

Analog power source voltage

____

Input voltage RESET, CNVss, BYTE

Input voltage P10/A8/D8 – P17/A15/D15,

P20/A16/D0 – P27/A23/D7, P43 – P47,

–0.3 to Vcc + 0.3

P50 – P57, P60 – P67, P70 – P77,

_{P80 – P87, VREF, XIN,}__HO__L__D,__R__DY_

Output voltage P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

^{P20/A16/D0 – P27/A23/D7}_^{, P}_³_^0/R/W,

P31/BHE, P32/ALE, P33/HLDA , P42/

–0.3 to Vcc + 0.3

P43 – P47, P50 – P57, P60 – P67,

P70 – P77, P80 – P87, XOUT, E

Topr

Tstg

Power dissipation

Operating temperature

Storage temperature

Ta = 25 °C

200

–40 to +85

–65 to +150

°C

RECOMMENDED OPERATING CONDITIONS (Vcc = 2.7 – 5.5 V, Ta = –40 to +85 °C, unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Unit

Min.

2.7

Max.

5.5

f(XIN) : Operating

f(XIN) : Stopped, f(XCIN) = 32.768 kHz

Vcc

Power source voltage

AVcc

Vss

AVss

Analog power source voltage

Power source voltage

Vcc

Analog power source voltage

___ ___

High-level input voltage HOLD, RDY, P43 – P47, P50 – P57, P60 – P67, P70 – P77,

_{P80 – P87, XIN,}__RE__S__E__{T, CNVss, BYTE, XCIN (Note 3)}

Vcc

0.8 Vcc

0.5 Vcc

VIH

High-level input voltage P10/A8/D8 – P17/A15/D15, P20/A16/D0 – P27/A23/D7

___ ___

Low-level input voltage HOLD, RDY, P43 – P47, P50 – P57, P60 – P67, P70 – P77,

_{P80 – P87, XIN,}__RE__S__E__{T, CNVss, BYTE, XCIN (Note 3)}

VIL

0.2Vcc

Low-level input voltage P10/A8/D8 – P17/A15/D15, P20/A16/D0 – P27/A23/D7

High-level peak output current P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

0.16Vcc

___

P20/A16/D0 – P27/A23/D7, P30/R/W, P31/BHE,

P32/ALE, P33/HLDA, P42/ 1, P43 – P47,

P50 – P57, P60 – P67, P70 – P77, P80 – P87

___

IOH(peak)

–10

–5

High-level average output current P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

___

P20/A16/D0 – P27/A23/D7, P30/R/W, P31/BHE,

____

IOH(avg)

P32/ALE, P33/HLDA, P42/ 1, P43 – P47,

P50 – P57, P60 – P67, P70 – P77, P80 – P87

Low-level peak output current P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

___

P20/A16/D0 – P27/A23/D7, P30/R/W, P31/BHE,

____

IOL(peak)

IOL(avg)

P32/ALE, P33/HLDA, P42/ 1, P43, P54 – P57,

P60 – P67, P70 – P77, P80 – P87

Low-level peak output current P44 – P47, P50 – P53

Low-level average output current P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

___

P20/A16/D0 – P27/A23/D7, P30/R/W, P31/BHE,

____

P32/ALE, P33/HLDA, P42/ 1, P43, P54 – P57,

P60 – P67, P70 – P77, P80 – P87

IOL(avg)

f(XIN)

Low-level average output current P44 – P47, P50 – P53

Main-clock oscillation frequency (Note 4)

MHz

kHz

f(XCIN)

Sub-clock oscillation frequency

32.768

Notes 1. Average output current is the average value of a 100 ms interval.

___

2. The sum of IOL(peak) for ports P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15, P20/A16/D0 – P27/A23/D7, P30/R/W, P31/BHE, P32/ALE, P33/

____

HLDA and P8 must be 80 mA or less, the sum of IOH(peak) for ports P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15, P20/A16/D0 – P27/A23/

___

____

D7, P30/R/W, P31/BHE, P32/ALE, P33/HLDA and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be

100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.

3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”.

4. The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

Max.

High-level output voltage P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

_{P20/A16/D0 – P27/A23/D7, P33/}__HL__D__{A, P42/}

VCC = 5 V, IOH = –10 mA

V^CC= 3 V, IOH = –1 mA

V^CC= 5 V, IOH = –400

VOH

P43 – P47, P50 – P57, P60 – P67, P70 – P77,

P80 – P87

2.5

4.7

High-level output voltage P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

_{P20/A16/D0 – P27/A23/D7, P33/}__HL__D__{A, P42/}

VOH

3.1

4.8

2.6

3.4

4.8

2.6

VCC = 5 V, IOH = –10 mA

VCC = 5 V, IOH = –400

___

High-level output voltage P30/R/W, P31/BHE, P32/ALE

VCC = 3 V, IOH = –1 mA

VCC = 5 V, IOH = –10 mA

High-level output voltage E

VOH

VOL

VCC = 5 V, IOH = –400

VCC = 3 V, IOH = –1 mA

Low-level output voltage P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

_{P20/A16/D0 – P27/A23/D7, P33/}__HL__D__{A, P42/}

VCC = 5 V, IOL = 10 mA

P43, P54 – P57, P60 – P67, P70 – P77,

P80 – P87

VCC = 3 V, IOL = 1 mA

0.5

1.8

1.5

VCC = 5 V, IOL = 16 mA

VCC = 3 V, IOL = 10 mA

VOL

Low-level output voltage P44 – P47, P50 – P53

Low-level output voltage P00/A0 – P07/A7, P10/A8/D8 – P17/A15/D15,

_{P20/A16/D0 – P27/A23/D7, P33/}__HL__D__{A, P42/}

VCC = 5 V, IOL = 2 mA

0.45

VCC = 5 V, IOL = 10 mA

VCC = 5 V, IOL = 2 mA

VCC = 3 V, IOL = 1 mA

VCC = 5 V, IOL = 10 mA

VCC = 5 V, IOL = 2 mA

VCC = 3 V, IOL = 1 mA

1.9

0.43

0.4

1.6

0.4

___

VOL

Low-level output voltage P30/R/W, P31/BHE, P32/ALE

Low-level output voltage E

0.4

____ ___

Hysteresis HOLD, RDY, TA0IN – TA4IN, TB0IN – TB2IN,

___ ___ ____ ____________

^{INT0 – INT2, A}_^D_^{TRG, CTS0, CTS1, CTS2, CLK0,}

VCC = 5 V

VCC = 3 V

0.4

0.1

VT+ – VT–

0.7

CLK1, CLK2, KI0 – KI3

_____

0.2

0.1

0.06

0.1

0.06

VCC = 5 V

VCC = 3 V

VCC = 5 V

VCC = 3 V

VCC = 5 V

VCC = 3 V

0.5

0.4

0.26

0.4

0.26

VT+ – VT–

Hysteresis RESET

Hysteresis XIN

Hysteresis XCIN (When external clock is input)

High-level input current P10/A8/D8 – P17/A15/D15,

P20/A16/D0 – P27/A23/D7, P43 – P47,

VCC = 5 V, VI = 5 V

VCC = 3 V, VI = 3 V

VCC = 5 V, VI = 0 V

VCC = 3 V, VI = 0 V

IIH

IIL

P50 – P57, P60 – P67, P70 – P77, P80 – P87,

____

XIN, RESET, CNVss, BYTE

Low-level input current P10/A8/D8 – P17/A15/D15,

P20/A16/D0 – P27/A23/D7, P43 – P47,

–5

P50 – P53, P60, P61, P65 – P67, P70 – P77,

_{P80 – P87, XIN,}__RE__S__E__{T, CNVss, BYTE}

–4

–5

VI = 0 V,

VCC = 5 V

without a pull-up

transistor

Low-level input current P54 – P57, P62 – P64

V^CC= 3 V

V^CC= 5 V

–4

VI = 0 V,

–0.25

–0.08

–0.5

–0.18

–1.0

with a pull-up

VCC = 3 V

transistor

–0.35

When clock is stopped

RAM hold voltage

VRAM

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Max.

10.8

Min.

VCC = 5 V,

f(XIN) = 12 MHz (square waveform),

(f(f2) = 6 MHz),

f(XCIN) = 32.768 kHz,

in operating (Note 1)

5.4

3.6

0.5

VCC = 3 V,

f(XIN) = 12 MHz (square waveform),

(f(f2) = 6 MHz),

f(XCIN) = 32.768 kHz,

in operating (Note 1)

7.2

1.0

VCC = 3 V,

f(XIN) = 12 MHz (square waveform),

(f(f2) = 0.75 MHz),

f(XCIN) = Stopped,

in operating

When external bus

is in use, output

pins are open, and

other pins are VSS.

Power source

current

ICC

VCC = 3 V,

f(XIN) = 12 MHz (square waveform),

f(XCIN) = 32.768 kHz,

when a WIT instruction is executed (Note 2)

VCC = 3 V,

f(XIN) = Stopped,

f(XCIN) = 32.768 kHz,

in operating (Note 3)

VCC = 3 V,

f(XIN) = Stopped,

f(XCIN) = 32.768 kHz,

when a WIT instruction is executed (Note 4)

Ta = 25 °C,

when clock is stopped

Ta = 85 °C,

when clock is stopped

Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop

bit = “1”.

2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.

3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.

4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.

A–D CONVERTER CHARACTERISTICS

(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note))

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

Min.

Max.

± 3

—

RLADDER

tCONV

VREF

VIA

Resolution

VREF = VCC

Bits

LSB

kΩ

Absolute accuracy

Ladder resistance

Conversion time

Reference voltage

Analog input voltage

19.6

2.7

VCC

VREF

Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V , VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1))

Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ.

2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.

External clock input

Limits

Symbol

Parameter

Unit

Min.

Max.

External clock input cycle time (Note 1)

tw(H)

tw(L)

External clock input high-level pulse width (Note 2)

External clock input low-level pulse width (Note 2)

External clock rise time

External clock fall time

Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns.

2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.

Microprocessor mode

Limits

Symbol

Parameter

Unit

Min.

200

Max.

tsu(P4D–E)

tsu(P5D–E)

tsu(P6D–E)

tsu(P7D–E)

tsu(P8D–E)

th(E–P4D)

th(E–P5D)

th(E–P6D)

th(E–P7D)

th(E–P8D)

tsu(D–E)

Port P4 input setup time

Port P5 input setup time

Port P6 input setup time

Port P7 input setup time

Port P8 input setup time

Port P4 input hold time

Port P5 input hold time

Port P6 input hold time

Port P7 input hold time

Port P8 input hold time

Data input setup time

___

tsu(RDY– 1) RDY input setup time

tsu(HOLD– 1) HOLD input setup time

th(E–D)

th( 1–RDY)

th( 1–HOLD) HOLD input hold time

____

Data input hold time

___

RDY input hold time

____

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Timer A input (Count input in event counter mode)

Symbol parameter

Limits

Unit

Min.

250

125

Max.

tc(TA)

TAiIN input cycle time

tw(TAH)

tw(TAL)

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Timer A input (Gating input in timer mode)

Limits

Symbol

parameter

Unit

Min.

666

333

tc(TA)

TAiIN input cycle time (Note)

tw(TAH)

tw(TAL)

TAiIN input high-level pulse width (Note)

TAiIN input low-level pulse width (Note)

Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”

Timer A input (External trigger input in one-shot pulse mode)

Limits

Symbol

parameter

Unit

Min.

666

166

Max.

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time (Note)

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”

Timer A input (External trigger input in pulse width modulation mode)

Limits

Symbol

parameter

Unit

Min.

166

Max.

tw(TAH)

tw(TAL)

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Timer A input (Up-down input in event counter mode)

Symbol parameter

Unit

Min.

3333

1666

666

tc(UP)

tw(UPH)

tw(UPL)

TAiOUT input cycle time

TAiOUT input high-level pulse width

TAiOUT input low-level pulse width

TAiOUT input setup time

tsu(UP–TIN)

th(TIN–UP)

TAiOUT input hold time

666

Timer A input (Two-phase pulse input in event counter mode)

Symbol parameter

Limits

Unit

Min.

2000

500

Max.

tc(TA)

TAjIN input cycle time

tsu(TAjIN–TAjOUT) TAjIN input setup time

tsu(TAjOUT–TAjIN) TAjOUT input setup time

500

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Timer B input (Count input in event counter mode)

Symbol Parameter

Limits

Unit

Min.

250

125

500

250

Max.

tc(TB)

TBiIN input cycle time (one edge count)

tw(TBH)

tw(TBL)

tc(TB)

TBiIN input high-level pulse width (one edge count)

TBiIN input low-level pulse width (one edge count)

TBiIN input cycle time (both edges count)

tw(TBH)

tw(TBL)

TBiIN input high-level pulse width (both edges count)

TBiIN input low-level pulse width (both edges count)

Timer B input (Pulse period measurement mode)

Limits

Symbol

Parameter

Unit

Min.

666

333

Max.

tc(TB)

tw(TBH)

tw(TBL)

TBiIN input cycle time (Note)

TBiIN input high-level pulse width (Note)

TBiIN input low-level pulse width (Note)

Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”

Timer B input (Pulse width measurement mode)

Limits

Symbol

Parameter

Unit

Min.

666

333

Max.

tc(TB)

TBiIN input cycle time (Note)

tw(TBH)

tw(TBL)

TBiIN input high-level pulse width (Note)

TBiIN input low-level pulse width (Note)

Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS.”

A-D trigger input

Limits

Symbol

Parameter

Unit

Min.

1333

166

Max.

____

ADTRG input cycle time (minimum allowable trigger)

tc(AD)

tw(ADL)

____

ADTRG input low-level pulse width

Serial I/O

Symbol

Parameter

Unit

Min.

333

166

Max.

100

tc(CK)

CLKi input cycle time

tw(CKH)

tw(CKL)

td(C–Q)

th(C–Q)

tsu(D–C)

th(C–D)

CLKi input high-level pulse width

CLKi input low-level pulse width

TXDi output delay time

TXDi hold time

RXDi input setup time

RXDi input hold time

____

___

External interrupt INTi input, key input interrupt KIi input

Limits

Symbol

Parameter

Unit

Min.

250

Max.

___

INTi input high-level pulse width

tw(INH)

tw(INL)

tw(KIL)

___

INTi input low-level pulse width

KIi input low-level pulse width

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

DATA FORMULAS

Timer A input ^{(Gating input in timer mode)}

Limits

Unit

Symbol

Parameter

Min.

Max.

8 ✕ 10⁹

2 • f(f2)

4 ✕ 10⁹

2 • f(f2)

4 ✕ 10⁹

2 • f(f2)

tc(TA)

TAiIN input cycle time

tw(TAH)

tw(TAL)

TAiIN input high-level pulse width

TAiIN input low-level pulse width

Timer A input (External trigger input in one-shot pulse mode)

Symbol Parameter

Limits

Unit

Min.

Max.

8 ✕ 10⁹

2 • f(f2)

tc(TA)

TAiIN input cycle time

Timer B input (In pulse period measurement mode or pulse width measurement mode)

Symbol Parameter

Limits

Unit

Min.

Max.

8 ✕ 10⁹

2 • f(f2)

4 ✕ 10⁹

2 • f(f2)

4 ✕ 10⁹

2 • f(f2)

tc(TB)

TBiIN input cycle time

tw(TBH)

tw(TBL)

TBiIN input high-level pulse width

TBiIN input low-level pulse width

Note. f(f2) expresses the clock f2 frequency.

For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

SWITCHING CHARACTERISTICS

(VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note))

Microprocessor mode

Limits

Unit

Symbol

Parameter

Test conditions

Fig. 14

Min.

Max.

300

td(E–P4Q)

td(E–P5Q)

td(E–P6Q)

td(E–P7Q)

td(E–P8Q)

Port P4 data output delay time

Port P5 data output delay time

Port P6 data output delay time

Port P7 data output delay time

Port P8 data output delay time

Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.

– A

– A 23/D

A 8/D 8

BHE

ALE

HLDA

P 4

P 5

P 6

P 7

P 8

50 pF

Fig. 14 Measuring circuit for each pin

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Microprocessor mode

(VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1))

Limits

Test

conditions

(Note2)

Symbol

Parameter

Unit

Wait mode

No wait

Wait 1

Min.

Max.

td(An–E)

Address output delay time

182

Wait 0

No wait

Wait 1

Wait 0

162

td(A–E)

Address output delay time

Address hold time

th(E–An)

tw(ALE)

No wait

Wait 1

Wait 0

No wait

Wait 1

Wait 0

No wait

Wait 1

Wait 0

No wait

Wait 1

Wait 0

ALE pulse width

123

tsu(A–ALE)

th(ALE–A)

td(ALE–E)

Address output setup time

Address hold time

Fig. 14

ALE output delay time

td(E–DQ)

th(E–DQ)

Data output delay time

Data hold time

131

No wait

Wait 1

Wait 0

E pulse width

tw(EL)

298

tpxz(E–DZ)

tpzx(E–DZ)

Floating start delay time

Floating release delay time

No wait

Wait 1

Wait 0

No wait

Wait 1

Wait 0

___

BHE output delay time

td(BHE–E)

td(R/W–E)

182

R/W output delay time

___

BHE hold time

th(E–BHE)

th(E–R/W)

R/W hold time

td(E–

td(

1 output delay time

____

HLDA output delay time

1–HLDA)

120

Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz.

2. No wait : Wait bit = “1”.

Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.

Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Bus timing data formulas

(VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz (Max.), unless otherwise noted (Note 1))

Limits

Symbol

Parameter

Unit

Wait mode

No wait

Wait 1

Min.

1 ✕ 10⁹

Max.

– 63

– 68

– 63

– 88

– 43

– 73

2 • f(f2)

3 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

3 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

2 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

2 ✕ 10⁹

2 • f(f2)

td(An–E)

Address output delay time

Wait 0

No wait

Wait 1

td(A–E)

Address output delay time

Address hold time

Wait 0

th(E–An)

tw(ALE)

No wait

Wait 1

ALE pulse width

Wait 0

No wait

Wait 1

tsu(A–ALE)

th(ALE–A)

td(ALE–E)

Address output setup time

Address hold time

Wait 0

No wait

Wait 1

1 ✕ 10⁹

2 • f(f2)

– 43

Wait 0

No wait

Wait 1

ALE output delay time

1 ✕ 10⁹

2 • f(f2)

Wait 0

td(E–DQ)

th(E–DQ)

Data output delay time

Data hold time

1 ✕ 10⁹

2 • f(f2)

2 ✕ 10⁹

2 • f(f2)

4 ✕ 10⁹

2 • f(f2)

– 43

– 35

No wait

E pulse width

tw(EL)

Wait 1

Wait 0

tpxz(E–DZ)

tpzx(E–DZ)

Floating start delay time

1 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

3 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

3 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

1 ✕ 10⁹

2 • f(f2)

– 30

– 63

– 68

– 63

– 68

– 50

Floating release delay time

No wait

Wait 1

___

BHE output delay time

td(BHE–E)

td(R/W–E)

Wait 0

No wait

Wait 1

R/W output delay time

Wait 0

___

BHE hold time

th(E–BHE)

th(E–R/W)

R/W hold time

td(E–

1 output delay time

Notes 1. This applies when the main-clock division selection bit = “0”.

2. f(f2) expresses the clock f2 frequency.

For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

c(TA)

tw(TAH)

TAiIN input

w(TAL)

tc(UP)

w(UPH)

TAi^OUTinput

w(UPL)

In event count mode

TAiOUT input

(Up-down input)

TAi^INinput

(when count by falling)

TAi^INinput

(when count by rising)

h(TIN–UP)

su(UP–TIN)

In event counter mode

(When two-phase pulse input is selected)

c(TA)

TAjIN input

su(TAjIN–TAjOUT)

su(TAjOUT–TAjIN)

TAj^OUTinput

su(TAjOUT–TAjIN)

c(TB)

tw(TBH)

TBiIN input

tw(TBL)

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

c(AD)

w(ADL)

ADTRG input

c(CK)

w(CKH)

CLK

w(CKL)

th(C–Q)

TxD

d(C–Q)

tsu(D–C)

th(C–D)

RxD

w(INL)

INTi input

Kli input

tw(INH)

tw(KNL)

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Microprocessor mode

(When wait bit = “1”)

RDY input

su(RDY–

)

1–RDY)

(When wait bit = “0”)

RDY input

su(RDY–

1–RDY)

(When wait bit = “1” or “0” in common)

tsu(HOLD–

)

th(

1–HOLD)

HOLD input

–HLDA)

1–HLDA)

HLDA output

Test conditions

• VCC = 2.7 – 5.5 V

• Input timing voltage : VIL = 0.2VCC, VIH = 0.8VCC

• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Microprocessor mode

(No wait : When wait bit = “1”)

w(L)

w(H)

d(E–

td(E–

w(EL)

h(E–An)

d(An–E)

ALE

Address

w(ALE)

td(ALE–E)

th(ALE–A)

h(E–DQ)

tpxz(E–DZ)

tpzx(E–DZ)

su(A–ALE)

Am/Dm

Address

Data

Address

td(E–DQ)

d(A–E)

h(E–D)

su(D–E)

DmIN

BHE

Data

h(E–BHE)

d(BHE–E)

h(E–R/W)

d(R/W–E)

R/W

Test conditions

• Vcc = 2.7 – 5.5 V

• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V

• Data input DmIN : VIL = 0.16VCC, VIH = 0.5VCC

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Microprocessor mode

(Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.)

w(L)

w(H)

XIN

d(E–

td(E–

w(EL)

d(An–E)

th(E–An)

Address

d(ALE–E)

w(ALE)

ALE

h(ALE–A)

su(A–ALE)

tpzx(E–DZ)

pxz(E–DZ)

h(E–DQ)

Am/Dm

Address

Data

Address

d(E–DQ)

td(A–E)

tsu(D–E)

h(E–D)

Data

Dm^IN

BHE

th(E–BHE)

d(BHE–E)

th(E–R/W)

d(R/W–E)

R/W

Test conditions

• Vcc = 2.7 – 5.5 V

• Output timing voltage : V^OL= 0.8 V, VOH = 2.0 V

• Data input Dm^IN: VIL = 0.16VCC, VIH = 0.5VCC

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

PACKAGE OUTLINE

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

MEMO

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

MEMO

MITSUBISHI MICROCOMPUTERS

M37733S4LHP

16-BIT CMOS MICROCOMPUTER

Keep safety first in your circuit designs!

•

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of

substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

•

These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any

intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples

contained in these materials.

All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi

Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor

product distributor for the latest product information before purchasing a product listed herein.

•

Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact

Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for

transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

•

The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the

approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

•

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

H-LF434-A KI-9607 Printed in Japan (ROD)

New publication, effective Jul. 1996.

Specifications subject to change without notice.

M37733 [MITSUBISHI]

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