M38003S2-XXXFP [MITSUBISHI]
8-BIT SINGLE-CHIP MICROCOMPUTER; 8位单片机
| 型号： | M38003S2-XXXFP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总173页 (文件大小：4178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED AND EVER ADVANCINGMITSUBISHI ELECTRIC
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
3800
Group
User’s Manual
MITSUBISHI
ELECTRIC
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable, but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi
Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party’s rights, originating in the use of any
product data, diagrams, charts or circuit application examples contained in
these materials.
All information contained in these materials, including product data,
diagrams and charts, represent information on products at the time of
publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for any specific purposes, such as apparatus or systems for transportation,
vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export
control restrictions, they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8-
bit microcomputers 3800 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3800 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “SERIES MELPS
740 <SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICRO-
COMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems development.
Be sure to refer to this chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16
]
At reset
B
0
1
2
Name
Function
R W
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
0
Processor mode bits
Not available
0
0
0
0
1
✻
0 : 0 page
Stack page selection bit
1 : 1 page
✕
✕
3
4
5
6
7
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
0 : Operating
Main clock (XIN-XOUT) stop bit
1 : Stopped
0 : X -XOUT selected
1 : XCININ-XCOUT selected
✻
Internal system clock selection bit
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
••••••Contents determined by option at reset release
✻
Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES...................................................................................................................................... 1-2
APPLICATIONS.............................................................................................................................. 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK................................................................................................................... 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ................... 1-9
FUNCTIONAL DESCRIPTION .................................................................................................... 1-10
Central Processing Unit (CPU) ............................................................................................ 1-10
Memory .................................................................................................................................... 1-14
I/O Ports .................................................................................................................................. 1-16
Interrupts ................................................................................................................................. 1-18
Timers ...................................................................................................................................... 1-20
Serial I/O ................................................................................................................................. 1-22
Reset Circuit ........................................................................................................................... 1-26
Clock Generating Circuit ....................................................................................................... 1-28
Processor Modes.................................................................................................................... 1-29
NOTES ON PROGRAMMING..................................................................................................... 1-31
Processor Status Register .................................................................................................... 1-31
Interrupts ................................................................................................................................. 1-31
Decimal Calculations.............................................................................................................. 1-31
Timers ...................................................................................................................................... 1-31
Multiplication and Division Instructions ............................................................................... 1-31
Ports......................................................................................................................................... 1-31
Serial I/O ................................................................................................................................. 1-31
Instruction Execution Time.................................................................................................... 1-31
Memory Expansion Mode and Microprocessor Mode ....................................................... 1-31
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-32
ROM PROGRAMMING METHOD .............................................................................................. 1-32
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-33
Interrupt ................................................................................................................................... 1-33
Timing After Interrupt............................................................................................................. 1-34
3800 GROUP USER'S MANUAL
i
Table of contents
3.3.5 Notes on memory expansion mode and microprocessor mode ............................ 3-21
3.3.6 Notes on built-in PROM .............................................................................................. 3-22
3.4 Countermeasures against noise ...................................................................................... 3-24
3.4.1 Shortest wiring length .................................................................................................. 3-24
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line............ 3-25
3.4.3 Consideration for oscillator ......................................................................................... 3-26
3.4.4 Setup for I/O ports....................................................................................................... 3-26
3.4.5 Providing of watchdog timer function by software .................................................. 3-27
3.5 List of registers ................................................................................................................... 3-28
3.6 Mask ROM ordering method ............................................................................................. 3-37
3.7 Mark specification form ..................................................................................................... 3-51
3.8 Package outline.................................................................................................................... 3-53
3.9 Machine Instructions .......................................................................................................... 3-56
3.10 List of instruction codes ................................................................................................. 3-66
3.11 SFR memory map.............................................................................................................. 3-67
3.12 Pin configuration ............................................................................................................... 3-68
3800 GROUP USER'S MANUAL
iii
List of figures
Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9
Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10
Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12
Fig. 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13
Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14
Fig. 2.2.13 Example of a peripheral circuit .............................................................................. 2-15
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] .......... 2-15
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]................................... 2-16
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16
Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17
Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18
Fig. 2.2.19 Control procedure [Measurement of frequency]................................................... 2-19
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-20
Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21
Fig. 2.2.22 Control procedure [Measurement of pulse width]................................................ 2-22
Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24
Fig. 2.3.3 Structure of Serial I/O status register .................................................................... 2-24
Fig. 2.3.4 Structure of Serial I/O control register ................................................................... 2-25
Fig. 2.3.5 Structure of UART control register ......................................................................... 2-25
Fig. 2.3.6 Structure of Baud rate generator ............................................................................ 2-26
Fig. 2.3.7 Structure of Interrupt edge selection register ....................................................... 2-26
Fig. 2.3.8 Structure of Interrupt request register 1 ................................................................ 2-27
Fig. 2.3.9 Structure of Interrupt control register 1 ................................................................. 2-27
Fig. 2.3.10 Serial I/O connection examples (1) ...................................................................... 2-28
Fig. 2.3.11 Serial I/O connection examples (2) ...................................................................... 2-29
Fig. 2.3.12 Setting of Serial I/O transfer data format ............................................................ 2-30
Fig. 2.3.13 Connection diagram [Communication using a clock synchronous serial I/O] 2-31
Fig. 2.3.14 Timing chart [Communication using a clock synchronous serial I/O] ............. 2-31
Fig. 2.3.15 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-32
Fig. 2.3.16 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] .................................. 2-33
Fig. 2.3.17 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-34
Fig. 2.3.18 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] . 2-35
Fig. 2.3.19 Connection diagram [Output of serial data] ......................................................... 2-36
Fig. 2.3.20 Timing chart [Output of serial data] ...................................................................... 2-36
Fig. 2.3.21 Setting of serial I/O related registers [Output of serial data] ............................ 2-37
Fig. 2.3.22 Setting of serial I/O transmission data [Output of serial data].......................... 2-37
Fig. 2.3.23 Control procedure of serial I/O [Output of serial data] ...................................... 2-38
Fig. 2.3.24 Connection diagram
[Cyclic transmission or reception of block data between microcomputers] 2-39
Fig. 2.3.25 Timing chart [Cyclic transmission or reception of block data between microcomputers] ........ 2-40
Fig. 2.3.26 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers] . 2-40
Fig. 2.3.27 Control in the master unit ....................................................................................... 2-41
Fig. 2.3.28 Control in the slave unit ......................................................................................... 2-42
Fig. 2.3.29 Connection diagram [Communication using UART] ............................................ 2-43
Fig. 2.3.30 Timing chart [Communication using UART] ......................................................... 2-43
3800 GROUP USER’S MANUAL
ii
List of figures
Fig. 2.3.31 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-45
Fig. 2.3.32 Setting of related registers at a receiving side [Communication using UART] ............................ 2-46
Fig. 2.3.33 Control procedure at a transmitting side [Communication using UART] ......... 2-47
Fig. 2.3.34 Control procedure at a receiving side [Communication using UART] .............. 2-48
Fig. 2.4.1 Memory map of processor mode related register ................................................ 2-49
Fig. 2.4.2 Structure of CPU mode register.............................................................................. 2-49
Fig. 2.4.3 Expansion example of ROM and RAM .................................................................. 2-50
Fig. 2.4.4 Read-cycle (OE access, SRAM).............................................................................. 2-51
Fig. 2.4.5 Read-cycle (OE access, EPROM)........................................................................... 2-51
Fig. 2.4.6 Write-cycle (W control, SRAM) ................................................................................ 2-52
Fig. 2.4.7 Application example of the ONW function ............................................................. 2-53
Fig. 2.5.1 Example of Poweron reset circuit ........................................................................... 2-54
Fig. 2.5.2 RAM back-up system ................................................................................................ 2-54
3800 GROUP USER’S MANUAL
iii
List of figures
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics......................................... 3-11
Fig. 3.1.2 Timing diagram (in single-chip mode) .................................................................... 3-12
Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1) 3-13
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2) 3-14
Fig. 3.2.1 Power source current characteristic example ....................................................... 3-15
Fig. 3.2.2 Power source current characteristic example (in wait mode)............................. 3-15
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1). 3-16
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2). 3-16
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) 3-17
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) 3-17
Fig. 3.3.1 Structure of interrupt control register 2.................................................................. 3-18
Fig. 3.4.1 Wiring for the RESET pin ........................................................................................ 3-24
Fig. 3.4.2 Wiring for clock I/O pins........................................................................................... 3-25
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version....... 3-25
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line..................................... 3-25
Fig. 3.4.5 Wiring for a large current signal line ..................................................................... 3-26
Fig. 3.4.6 Wiring to a signal line where potential levels change frequently ...................... 3-26
Fig. 3.4.7 Stepup for I/O ports .................................................................................................. 3-26
Fig. 3.4.8 Watchdog timer by software .................................................................................... 3-27
Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7) ........................................................ 3-28
Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ......................... 3-28
Fig. 3.5.3 Structure of Transmit/Receive buffer register ....................................................... 3-29
Fig. 3.5.4 Structure of Serial I/O status register .................................................................... 3-29
Fig. 3.5.5 Structure of Serial I/O control register ................................................................... 3-30
Fig. 3.5.6 Structure of UART control register ......................................................................... 3-30
Fig. 3.5.7 Structure of Baud rate generator ............................................................................ 3-31
Fig. 3.5.8 Structure of Prescaler 12, Prescaler X, Prescaler Y ........................................... 3-31
Fig. 3.5.9 Structure of Timer 1 .................................................................................................. 3-32
Fig. 3.5.10 Structure of Timer 2, Timer X, Timer Y .............................................................. 3-32
Fig. 3.5.11 Structure of Timer XY mode register ................................................................... 3-33
Fig. 3.5.12 Structure of Interrupt edge selection register ..................................................... 3-34
Fig. 3.5.13 Structure of CPU mode register............................................................................ 3-34
Fig. 3.5.14 Structure of Interrupt request register 1 .............................................................. 3-35
Fig. 3.5.15 Structure of Interrupt request register 2 .............................................................. 3-35
Fig. 3.5.16 Structure of Interrupt control register 1 ............................................................... 3-36
Fig. 3.5.17 Structure of Interrupt control register 2 ............................................................... 3-36
3800 GROUP USER’S MANUAL
iv
List of tables
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description ................................................................................................................. 1-5
Table 2 List of supported products ............................................................................................. 1-8
Table 3 List of supported products (Extended operating temperature version) .................. 1-9
Table 4 Push and pop instructions of accumulator or processor status register.............. 1-11
Table 5 Set and clear instructions of each bit of processor status register...................... 1-12
Table 6 List of I/O port functions.............................................................................................. 1-16
Table 7 Interrupt vector addresses and priority...................................................................... 1-18
Table 8 Functions of ports in memory expansion mode and microprocessor mode ........ 1-29
Table 9 Programming adapter ................................................................................................... 1-32
Table 10 Interrupt sources, vector addresses and interrupt priority.................................... 1-33
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) ................................................... 2-4
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ....... 2-4
Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit .......................................................... 2-8
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values .................... 2-44
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ...................................................................................... 3-2
Table 3.1.2 Recommended operating conditions ...................................................................... 3-2
Table 3.1.3 Electrical characteristics .......................................................................................... 3-3
Table 3.1.4 Timing requirements (1) .......................................................................................... 3-4
Table 3.1.5 Timing requirements (2) .......................................................................................... 3-4
Table 3.1.6 Switching characteristics (1) ................................................................................... 3-5
Table 3.1.7 Switching characteristics (2) ................................................................................... 3-5
Table 3.1.8 Timing requirements in memory expansion mode and microprocessor mode (1) ...................... 3-6
Table 3.1.9 Switching characteristics in memory expansion mode and microprocessor mode (1) ............... 3-6
Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (2) .................... 3-7
Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (2) ............ 3-7
Table 3.1.12 Absolute maximum ratings (Extended operating temperature version).......... 3-8
Table 3.1.13 Recommended operating conditions (Extended operating temperature version) ...... 3-8
Table 3.1.14 Electrical characteristics (Extended operating temperature version).............. 3-9
Table 3.1.15 Timing requirements (Extended operating temperature version) .................. 3-10
Table 3.1.16 Switching characteristics (Extended operating temperature version) ............ 3-10
Table 3.1.17 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-11
Table 3.1.18 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-11
3800 GROUP USER’S MANUAL
i
List of tables
Table 3.3.1 Programming adapter ............................................................................................. 3-22
Table 3.3.2 Setting of programming adapter switch ............................................................... 3-22
Table 3.3.3 Setting of PROM programmer address................................................................ 3-23
Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit........................................................ 3-33
3800 GROUP USER’S MANUAL
ii
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATIONS
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR
MASK ORDERS
ROM PROGRAMMING
METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
Power source voltage..................................................3.0 to 5.5 V
•
The 3800 group is the 8-bit microcomputer based on the 740 fam-
(Extended operating temperature version : 4.0 to 5.5 V)
Power dissipation ............................................................... 32 mW
Memory expansion possible
ily core technology.
•
•
•
The 3800 group is designed for office automation equipment,
household appliances and include four timers, serial I/O function.
The various microcomputers in the 3800 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Operating temperature range .................................... –20 to 85°C
(Extended operating temperature version : –40 to 85°C)
APPLICATIONS
Office automation, factory automation, household appliances, and
For details on availability of microcomputers in the 3800 group, re-
fer to the section on group expansion.
other consumer applications, etc.
FEATURES
Basic machine-language instructions....................................... 71
•
•
The minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
Memory size
•
ROM .................................................................. 8 K to 32 K bytes
RAM ................................................................. 384 to 1024 bytes
Programmable input/output ports ............................................. 58
•
Interrupts .................................................. 15 sources, 15 vectors
•
Timers ............................................................................. 8 bit ✕ 4
•
Serial I/O .......................8-bit ✕ 1 (UART or Clock-synchronized)
•
Clock generating circuit ....................... Internal feedback resistor
•
(connect to external ceramic resonator or quartz-crystal oscillator)
PIN CONFIGURATION (TOP VIEW)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P3
P3
P3 /SYNC
P3 /φ
/RESETOUT
P3 /ONW
7
/RD
P2
P2
0
/DB
/DB
0
1
1
6/WR
P2
2/DB
2
5
P2
P2
P2
3
4
5
/DB
/DB
/DB
3
4
5
4
P3
3
2
P2
6
/DB
6
P3
P3
1
P2
7
/DB
7
0
M38002M4-XXXFP
M38003M6-XXXHP
V
X
X
SS
VCC
OUT
IN
P7
P7
P6
P6
P6
P6
P6
1
0
7
6
5
4
3
P4
P4
0
1
RESET
CNVSS
P42/INT0
Package type : 64P6N-A/64P6D-A
64-pin plastic-molded QFP
Fig. 1 Pin configuration of M38002M4-XXXFP/M38003M6-XXXHP
3800 GROUP USER’S MANUAL
1-2
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram
3800 GROUP USER’S MANUAL
1-4
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description
Pin
Name
Function
Function except a port function
VCC
VSS
Power source
• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
CNVSS
CNVSS
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
RESET
XIN
Reset input
Clock input
• Reset input pin for active “L”
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40, P41
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P42/INT0,
P43/INT1
• CMOS 3-state output structure
• External interrupt input pins
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
• Serial I/O I/O pins
P50/INT2 –
P53/INT5
I/O port P5
• External interrupt input pins
• Timer X and Timer Y I/O pins
• 8-bit CMOS I/O port with the same function as
port P0
• CMOS compatible input level
• CMOS 3-state output structure
P54/CNTR0,
P55/CNTR1
P56, P57
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
P60 – P67
I/O port P6
I/O port P7
• 2-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P70, P71
• CMOS 3-state output structure
3800 GROUP USER’S MANUAL
1-5
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
Mitsubishi plans to expand the 3800 group as follows:
(1) Support for mask ROM, One Time PROM, EPROM,
and external ROM versions
64P4B ............................................ Shrink plastic molded DIP
64P6N-A............................. 0.8 mm pitch plastic molded QFP
64P6D-A............................. 0.5 mm pitch plastic molded QFP
64S1B ......................... Shrink ceramic DIP (EPROM version)
64D0................ 0.8 mm pitch ceramic LCC (EPROM version)
ROM/PROM capacity................................... 8 K to 32 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
Mass product
M38002S
External ROM
Being planned
Mass product
M38004M8/E8
32K
28K
M38007M8/E8
Mass product
24K
20K
16K
12K
8K
M38003M6
Mass product
M38002M4/E4
Mass product
M38002M2/E2
192 256
384
512
640
768
896
1024
RAM size (bytes)
Note : Products under development or planning: the development schedule and specifications may be revised without notice.
Fig. 5 Memory expansion plan
3800 GROUP USER’S MANUAL
1-7
HARDWARE
GROUP EXPANSION
Currently supported products are listed below.
Table 2. List of supported products
As of September 1995
Remarks
(P) ROM size (bytes)
Product
RAM size (bytes)
Package
64P4B
ROM size for User in (
)
Mask ROM version
One Time PROM version
M38002M2-XXXSP
M38002E2-XXXSP
M38002E2SP
One Time PROM version (blank)
Mask ROM version
8192
384
(8062)
M38002M2-XXXFP
M38002E2-XXXFP
M38002E2FP
64P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
M38002M4-XXXSP
M38002E4-XXXSP
M38002E4SP
64P4B
One Time PROM version
One Time PROM version (blank)
64S1B-E EPROM version
Mask ROM version
M38002E4SS
16384
(16254)
384
512
M38002M4-XXXFP
M38002E4-XXXFP
M38002E4FP
64P6N-A One Time PROM version
One Time PROM version (blank)
64D0
EPROM version
M38002E4FS
64P4B
Mask ROM version
M38003M6-XXXSP
M38003M6-XXXFP
M38003M6-XXXHP
M38004M8-XXXSP
M38004E8-XXXSP
M38004E8SP
24576
(24446)
64P6N-A Mask ROM version
64P6D-A Mask ROM version
Mask ROM version
64P4B
One Time PROM version
One Time PROM version (blank)
64S1B-E EPROM version
Mask ROM version
M38004E8SS
32768
(32638)
640
384
M38004M8-XXXFP
M38004E8-XXXFP
M38004E8FP
64P6N-A
One Time PROM version
One Time PROM version (blank)
EPROM version
M38004E8FS
64D0
64P4B
External ROM type
M38002SSP
0
External ROM type
M38002SFP
64P6N-A
3800 GROUP USER’S MANUAL
1-8
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3800 group (extended operating
temperature version) as follows:
64P4B ............................................Shrink Plastic molded DIP
64P6N-A............................. 0.8 mm pitch plastic molded QFP
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity................................... 8 K to 32 K bytes
RAM capacity ................................................ 384 to 640 bytes
Memory Expansion Plan (Extended operating temperature version)
Mass product
M38004M8D
ROM size (bytes)
32K
28K
24K
20K
16K
12K
8K
Mass product
M38002M4D/E4D
Mass product
M38002M2D
4K
192 256
384
512
RAM size (bytes)
640
768
896
1024
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently supported products are listed below.
Table 3. List of supported products (Extended operating temperature version)
As of September 1995
Remarks
(P) ROM size (bytes)
Product name
RAM size (bytes)
384
Package
64P4B
ROM size for User in (
)
M38002M2DXXXSP
M38002M2DXXXFP
M38002M4DXXXSP
M38002E4DXXXSP
M38002E4DSP
Mask ROM version
8192
(8062)
64P6N-A Mask ROM version
Mask ROM version
64P4B
One Time PROM version
One Time PROM version (blank)
Mask ROM version
16384
(16254)
384
M38002M4DXXXFP
M38002E4DXXXFP
M38002E4DFP
64P6N-A
One Time PROM version
One Time PROM version (blank)
Mask ROM version
64P4B
M38004M8DXXXSP
M38004M8DXXXFP
32768
(32638)
1024
64P6N-A
Mask ROM version
3800 GROUP USER’S MANUAL
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Stack pointer (S)
Central Processing Unit (CPU)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The 3800 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine in-
structions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real ad-
dress.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Fig. 8.
Program counter (PC)
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b7
b0
Accumulator
A
b7
b7
b7
b7
b7
b0
Index Register X
X
Y
b0
Index Register Y
b0
S
Stack Pointer
b15
b0
PCH
PCL
B D
Program Counter
b0
Processor Status Register (PS)
N V
T
I Z C
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 7 740 Family CPU register structure
3800 GROUP USER’S MANUAL
1-10
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt Request
(Note 1)
M(S) ← (PCH)
Execute JSR
(S) ← (S – 1)
Store Return Address
on Stack (Note 2)
M(S) ← (PCH)
M(S) ← (PCL)
(S) ← (S – 1)
M(S) ← (PCL)
(S) ← (S – 1)
Subroutine
(S) ← (S – 1)
Store Return Address
on Stack (Note 2)
M(S) ← (PS)
Store Contents of
Processor Status
Register on Stack
(S) ← (S – 1)
Interrupt
Service Routine
I Flag “0” to “1”
Fetch the Jump
Execute RTS
Vector
Execute RTI
(S) ← (S + 1)
(S) ← (S + 1)
Restore Return
Address
Restore Contents of
Processor Status
(PCL) ← M(S)
(S) ← (S + 1)
(PCH) ← M(S)
Register
(PS) ← M(S)
(S) ← (S + 1)
(PCL) ← M(S)
Restore Return
Address
(S) ← (S + 1)
(PCH) ← M(S)
Notes 1 : The condition to enable the interrupt → Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 4. Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
3800 GROUP USER’S MANUAL
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic op-
eration. Branch operations can be performed by testing the Carry
(C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should be
initialized in the beginning of a program.
generated by the BRK instruction. The BRK flag in the pro-
cessor status register is always “0”. When the BRK instruc-
tion is used to generate an interrupt, the processor status
register is pushed onto the stack with the break flag set to “1”.
The saved processor status is the only place where the break
flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an op-
eration between two memory locations is stored in the accu-
mulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory loca-
tions, i.e. between memory and memory, memory and I/O,
and I/O and I/O. In this case, the result of an arithmetic op-
eration performed on data in memory location 1 and memory
location 2 is stored in memory location 1. The address of
memory location 1 is specified by index register X, and the
address of memory location 2 is specified by normal address-
ing modes.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic opera-
tion. It can also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic op-
eration or a data transfer is “0”, and cleared if the result is
anything other than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
(7) Overflow flag (V)
When an interrupt occurs, this flag is automatically set to “1”
to prevent other interrupts from interfering until the current in-
terrupt is serviced.
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds + 127 to
–128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”. Decimal correction is automatic in decimal mode. Only
the ADC and SBC instructions can be used for decimal arith-
metic.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit
7 of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 5. Set and clear instructions of each bit of processor status register
C flag
SEC
CLC
Z flag
—
I flag
SEI
D flag
SED
CLD
B flag
—
T flag
SET
CLT
V flag
—
N flag
—
Set instruction
Clear instruction
—
CLI
—
CLV
—
3800 GROUP USER’S MANUAL
1-12
HARDWARE
FUNCTIONAL DESCRIPTION
CPU mode register
The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
: Memory expansion mode
: Microprocessor mode
: Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Not used (return “0” when read)
Fig. 9 Structure of CPU mode register
3800 GROUP USER’S MANUAL
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Zero page
Special function register (SFR) area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
Address
XXXX16
000016
SFR area
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
Zero page
004016
010016
RAM
XXXX16
Reserved area
Not used
044016
ROM area
ROM capacity
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
12288
16384
20480
24576
28672
32768
ZZZZ16
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 10 Memory map diagram
3800 GROUP USER’S MANUAL
1-14
HARDWARE
FUNCTIONAL DESCRIPTION
Port P0 (P0)
Prescaler 12 (PRE12)
Timer 1 (T1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Fig. 11 Memory map of special function register (SFR)
3800 GROUP USER’S MANUAL
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Direction registers
The 3800 group has 58 programmable I/O pins arranged in eight
I/O ports (ports P0 to P7). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
Table 6. List of I/O port functions
Pin
Name
Input/Output
I/O Format
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Related SFRs
Ref.No.
Input/output,
individual bits
Address low-order byte
output
P00 – P07
Port P0
CPU mode register
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Address high-order
byte output
P10 – P17
P20 – P27
P30 – P37
Port P1
Port P2
Port P3
CPU mode register
CPU mode register
CPU mode register
(1)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Data bus I/O
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Control signal I/O
P40,P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2,
P51/INT3,
P52/INT4,
P53/INT5
P54/CNTR0,
P55/CNTR1
P56,P57
Interrupt edge selection
register
External interrupt input
Serial I/O function I/O
(2)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P4
(3)
(4)
(5)
(6)
Serial I/O control
register
UART control register
Interrupt edge selection
register
External interrupt input
(2)
(7)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P5
Timer X and Timer Y
function I/O
Timer XY mode register
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
P60 – P67
P70, P71
Port P6
Port P7
(1)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
3800 GROUP USER’S MANUAL
1-16
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0, P1, P2, P3, P4
0
, P41
, P56
, P57
, P6, P7
(2) Ports P4
2
, P43
, P50
– P5
3
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Interrupt input
(3) Port P4
4
(4) Port P45
Serial I/O enable bit
Receive enable bit
P45/TXD P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O input
Serial I/O output
(5) Port P4
6
(6) Port P47
Serial I/O
synchronous clock selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Serial I/O
external
Serial I/O clock output
Serial I/O ready output
clock input
(7) Ports P54, P55
Direction register
Port latch
Data bus
Pulse output mode
Timer output
Counter input
Interrupt input
Fig. 12 Port block diagram (single-chip mode)
3800 GROUP USER’S MANUAL
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupt operation
Interrupts occur by fifteen sources: eight external, six internal, and
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Notes on use
When the active edge of an external interrupt (INT0 to INT5,
CNTR0, or CNTR1) is changed, the corresponding interrupt re-
quest bit may also be set. Therefore, please take following se-
quence;
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 7. Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Reset (Note 2)
INT0
Priority
High
Low
Generating Conditions
1
2
FFFD16
FFFC16
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O
data reception
External interrupt
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
(active edge selectable)
External interrupt
INT1
3
4
(active edge selectable)
Serial I/O
reception
Valid when serial I/O is selected
At completion of serial I/O
transfer shift or when
Serial I/O
5
FFF516
FFF416
Valid when serial I/O is selected
transmission
transmission buffer is empty
At timer X underflow
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer Y underflow
At timer 1 underflow
STP release timer underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At detection of either rising or
falling edge of INT5 input
External interrupt
CNTR0
CNTR1
INT2
10
11
12
13
14
15
16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDD16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDC16
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
INT3
(active edge selectable)
External interrupt
INT4
(active edge selectable)
External interrupt
INT5
(active edge selectable)
BRK instruction
At BRK instruction execution
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3800 GROUP USER’S MANUAL
1-18
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT
INT
INT
INT
INT
1
2
3
4
5
active edge selection bit
active edge selection bit
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16)
Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt request bit
CNTR0 interrupt request bit
INT
1
interrupt request bit
CNTR1 interrupt request bit
Serial I/O receive interrupt request bit
INT
INT
INT
INT
2
3
4
5
interrupt request bit
interrupt request bit
interrupt request bit
interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Not used (return “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
CNTR
0
1
interrupt enable bit
interrupt enable bit
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
INT
INT
INT
INT
2
3
4
5
interrupt enable bit
interrupt enable bit
interrupt enable bit
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Not used (return “0” when read)
(Do not write “1” to this bit)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
3800 GROUP USER’S MANUAL
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
Oscillator
f(XIN)
Divider
1/16
Prescaler X latch (8)
Timer X latch (8)
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Prescaler X (8)
Timer X (8)
To timer X interrupt
request bit
CNTR0 active
edge switch bit
P54/CNTR0 pin
Event
counter
mode
Timer X count stop bit
“0”
“1”
To CNTR0 interrupt
request bit
CNTR0 active
edge switch
bit
Q
Q
“1”
“0”
Toggle flip- flop
R
T
Port P54
latch
Port P54
direction register
Timer X latch write pulse
Pulse output mode
Pulse output
mode
Data bus
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Prescaler Y (8)
To timer Y interrupt
request bit
CNTR1 active
edge switch bit
P55/CNTR1 pin
Event
counter
mode
Timer Y count stop bit
“0”
“1”
To CNTR1 interrupt
request bit
CNTR1 active
edge switch
bit
Q
Q
“1”
“0”
Toggle flip- flop
R
T
Port P55
latch
Port P55
direction register
Timer Y latch write pulse
Pulse output mode
Pulse output
mode
Data bus
Prescaler
12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
To timer 2 interrupt
request bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 1 interrupt
request bit
Fig. 16 Block diagram of timer X, timerY, timer 1, and timer 2
3800 GROUP USER’S MANUAL
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Asynchronous serial I/O (UART) mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re-
ceive buffer.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next charac-
ter is being received.
Data bus
Address 001816
Serial I/O control register Address 001A16
Receive buffer
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
P44/RXD
STdetector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE SP detector
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
f(XIN)
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer
Address 001816
Address 001916
Serial I/O status register
Data bus
Fig. 19 Block diagram of UART serial I/O
3800 GROUP USER’S MANUAL
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1✽
SP
TBE=1
Serial output TXD
ST
D0
D1
D0
D1
ST
SP
✽Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
X
D
D0
D1
D1
ST
D0
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 20 Operation of UART serial I/O function
Serial I/O control register (SIOCON) 001A16
spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the Serial I/O Control Register) also clears all the status flags, in-
cluding the error flags.
The serial I/O control register consists of eight control bits for the
serial I/O function.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
Transmit buffer/Receive buffer register (TB/
RB) 001816
Serial I/O status register (SIOSTS) 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial trans-
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. A write to the serial I/O status reg-
ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
3800 GROUP USER’S MANUAL
1-24
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
Address
Register contents
0016
To reset the microcomputer, the RESET pin should be held at an
“L” level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 3.0 V and 5.5
V, and between 4.0 V and 5.5 V for extended operating tempera-
ture version), reset is released. Internal operation does not begin
until after 8 to 13 XIN clock cycles are completed. After the reset is
completed, the program starts from the address contained in ad-
dress FFFD16 (high-order byte) and address FFFC16 (low-order
byte).
(000116) • • •
(1)
Port P0 direction register
(000316) • • •
(000516) • • •
(000716) • • •
(000916) • • •
(000B16) • • •
(000D16) • • •
(000F16) • • •
(001916) • • •
(001A16) • • •
(001B16) • • •
0016
0016
0016
0016
0016
0016
0016
(2) Port P1 direction register
(3)
(4)
(5)
(6)
(7)
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Make sure that the reset input voltage is less than 0.6 V for VCC of
3.0 V (Extended operating temperature version: the reset input
voltage is less than 0.8 V for VCC of 4.0 V).
(8) Port P7 direction register
(9) Serial I/O status register
(10) Serial I/O control register
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0016
(11)
(12)
UART control register
Prescaler 12
0
0
3.0V (Note 1)
(002016) • • •
(002116) • • •
(002216) • • •
(002316) • • •
(002416) • • •
(002516) • • •
(002616) • • •
(002716) • • •
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
Power source
(13) Timer 1
(14) Timer 2
0V
voltage
(15)
(16)
(17)
(18)
Timer XY mode register
Prescaler X
0.6V (Note 2)
Reset input
voltage
0V
Timer X
Note 1 : Extended operating temperature version : 4.0V
Note 2 : Extended operating temperature version : 0.8V
Prescaler Y
(19) Timer Y
VCC
1
(20)
Interrupt edge selection register (003A16) • • •
0016
(21) CPU mode register
(003B16) • • •
(003C16) • • •
(003D16) • • •
(003E16) • • •
(003F16) • • •
(PS)
0
0
0
0
0
0
✽ 0
5
4
RESET
Interrupt request register 1
Interrupt request register 2
(22)
(23)
M51953AL
3
0016
0016
0016
0016
0.1 µ F
(24) Interrupt control register 1
VSS
(25)
Interrupt control register 2
3800 group
(26)
Processor status register
✕
✕
✕
✕
✕
✕ ✕
1
(27) Program counter
(PC
H
) Contents of address FFFD16
) Contents of address FFFC16
Fig. 22 Example of reset circuit
(PC
L
Note.
✕ : Undefined
✽ : The initial values of CM1 are determined by the level at the
CNVSS pin.
The contents of all other registers and RAM are undefined
after a reset, so they must be initialized by software.
Fig. 23 Internal status of microcomputer after reset
3800 GROUP USER’S MANUAL
1-26
HARDWARE
FUNCTIONAL DESCRIPTION
X
IN
φ
RESET
RESETOUT
(internal reset)
SYNC
Address
?
?
ADH, ADL
?
?
?
FFFC
FFFD
Reset address from the vector table
ADH
Data
?
?
?
?
ADL
?
Notes 1: f(XIN) and f(φ) are in the relationship: f(XIN)=2
• f(φ).
X
IN: 8 to 13 clock cycles
2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 24 Timing of reset
3800 GROUP USER’S MANUAL
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. To supply a clock signal externally, input it to
the XIN pin and make the XOUT pin open.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock φ stops at “H”.
Timer 1 is set to “0116” and prescaler 12 is set to “FF16”.
Oscillator restarts when an external interrupt is received, but the
internal clock φ remains at “H” until timer 1 underflows.
This allows time for the clock circuit oscillation to stabilize.
If oscillator is restarted by a reset, no wait time is generated, so
keep the RESET pin at “L” level until oscillation has stabilized.
XIN
XOUT
Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
CIN
COUT
Fig. 25 Ceramic resonator circuit
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
XIN
XOUT
Open
Vcc
Vss
External oscillation
circuit
Fig. 26 External clock input circuit
Interrupt request
Interrupt disable
Reset
S
R
Q
S
R
Q
Q
S
R
flag (I)
Reset
WIT
instruction
STP instruction
STP instruction
φ output
Internal clock φ
ONW pin
Single-chip mode
ONW
control
1/2
Rd
1/8
Prescaler 12
Timer 1
FF16
0116
Reset or STP instruction
Rf
X
IN
XOUT
Fig. 27 Block diagram of clock generating circuit
3800 GROUP USER’S MANUAL
1-28
HARDWARE
FUNCTIONAL DESCRIPTION
Bus control with memory expansion
The 3800 group has a built-in ONW function to facilitate access to
external memory and I/O devices in memory expansion mode or
microprocessor mode.
If an “L” level signal is input to the ONW pin when the CPU is in a
read or write state, the corresponding read or write cycle is ex-
tended by one cycle of φ. During this extended period, the RD or
WR signal remains at “L”. This extension period is valid only for
writing to and reading from addresses 000016 to 000716 and
044016 to FFFF16 in microprocessor mode, 004016 to YYYY16 in
memory expansion mode, and only read and write cycles are ex-
tended.
Dummy cycle
Read cycle Dummy cycle
Read cycle
Write cycle
Write cycle
φ
AD15 to AD
0
RD
WR
ONW
✽
✽
✽
✽:
Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations.
The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal
is received.
Fig. 30 ONW function timing
3800 GROUP USER’S MANUAL
1-30
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before executing a
BBC or BBS instruction.
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Decimal Calculations
The frequency of the internal clock φ is half of the XIN frequency.
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth the
XIN frequency.
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
Memory Expansion Mode and Microproces-
sor Mode
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Execute the LDM or STA instruction for writing to port P3 (address
000616) in memory expansion mode and microprocessor mode.
Set areas which can be read out and write to port P3 (address
000616) in a memory, using the read-modify-write instruction
(SEB, CLB).
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
3800 GROUP USER’S MANUAL
1-31
HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical
copies)
Table 9. Programming adapter
Package
64P4B, 64S1B
64P6N-A
Name of Programming Adapter
PCA4738S-64A
PCA4738F-64A
64D0
PCA4738L-64A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 31 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 31 Programming and testing of One Time PROM version
3800 GROUP USER’S MANUAL
1-32
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
by hardware, but variety of priority processing can be performed
by software, using an interrupt enable bit and an interrupt disable
3800 group permits interrupts on the basis of 15 sources. It is vec-
tor interrupts with a fixed priority system. Accordingly, when two or
more interrupt requests occur during the same sampling, the
higher-priority interrupt is accepted first. This priority is determined
flag.
For interrupt sources, vector addresses and interrupt priority, refer
to “Table 10.”
Table 10. Interrupt sources, vector addresses and interrupt priority
Vector addresses
Priority
Remarks
Interrupt sources
High-order
Low-order
FFFC16
FFFA16
1
2
Reset (Note)
FFFD16
FFFB16
Non-maskable
INT0 interrupt
External interrupt
(active edge selectable)
External interrupt
3
FFF916
FFF816
INT1 interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
4
5
Serial I/O receive interrupt
Serial I/O transmit interrupt
Timer X interrupt
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
6
7
Timer Y interrupt
STP release timer underflow
8
Timer 1 interrupt
9
Timer 2 interrupt
10
CNTR0 interrupt
External interrupt
(active edge selectable)
External interrupt
11
12
13
14
15
16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDC16
CNTR1 interrupt
INT2 interrupt
FFE916
FFE716
FFE516
FFE316
FFE116
FFDD16
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
INT3 interrupt
(active edge selectable)
External interrupt
INT4 interrupt
(active edge selectable)
External interrupt
INT5 interrupt
(active edge selectable)
Non-maskable software interrupt
BRK instruction interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
3800 GROUP USER’S MANUAL
1-33
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
Figure 32 shows a timing chart after an interrupt occurs, and Fig-
ure 33 shows the time up to execution of the interrupt processing
routine.
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in execu-
tion.
φ
SYNC
RD
WR
Address bus
Data bus
PC
S
,
SPS S-1, SPS S-2
,
SPS
B
L
B
H
A
L, AH
Not used
PC
H
PC
L
PS
AL
A
H
SYNC : CPU operation code fetch cycle
B
A
L
, B
, A
H
: Vector address of each interrupt
: Jump destination address of each interrupt
L
H
SPS : “0016” or “0116
”
Fig. 32 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
Interrupt processing routine
Main routine
0 to 16 ✻ cycles
2 cycles
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µs to 5.75 µs)
✻: at execution of DIV instruction (16 cycles)
Fig. 33 Time up to execution of the interrupt processing routine
3800 GROUP USER’S MANUAL
1-34
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Timer
2.3 Serial I/O
2.4 Processor mode
2.5 Reset
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Fig. 2.1.1 Memory map of I/O port related registers
3800 GROUP USER’S MANUAL
2-2
APPLICATION
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16
]
At reset
B
Name
Function
R W
Port Pi
0
1
0
1
2
3
4
5
6
7
?
●
●
In output mode
Write
Read
Port latch
Port Pi
?
?
?
?
?
?
?
In input mode
Write : Port latch
Read : Value of pins
Port Pi
2
Port Pi
3
4
(Note)
Port Pi
Port Pi
Port Pi
Port Pi
5
6
7
Port P7 register [Address : 0E16
]
Note :
Port P7 is a 2-bit port (P7
0
, P7 ). Accordingly, when bits 2 to 7 are read
1
out, the contents are “0.”
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i =0, 1, 2, 3, 4, 5, 6, 7)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16]
Name
Function
At reset
B
0
R W
0 : Port Pi0 input mode
1 : Port Pi0 output mode
Port Pi direction register
0
✕
0 : Port Pi1 input mode
1 : Port Pi1 output mode
1
2
3
4
5
6
7
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
(Note)
(Note)
0 : Port Pi4 input mode
1 : Port Pi4 output mode
(Note)
(Note)
(Note)
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
(Note)
Note :
Port P7 direction register [Address : 0F16]
Port P7 is a 2-bit port (P70, P71). Accordingly, these bits do not have a
direction register function.
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7)
3800 GROUP USER’S MANUAL
2-3
APPLICATION
2.2 Timer
2.2.2 Related registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
[Address : 2016, 2416, 2616]
At reset
Function
R W
B
0
●
●
The count value of each prescaler is set.
The value set in this register is written to both the prescaler and
the prescaler latch at the same time.
When the prescaler is read out, the value (count value) of the
prescaler is read out.
1
1
2
3
4
5
6
7
1
1
1
1
1
1
1
●
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
At reset
Function
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
B
0
R W
●
●
1
1
2
3
4
5
6
7
0
0
0
0
0
0
0
●
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
Fig. 2.2.3 Structure of Timer 1
3800 GROUP USER’S MANUAL
2-6
APPLICATION
2.2 Timer
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
At reset
Function
R W
●
●
The count value of each timer is set.
The value set in this register is written to both the Timer and the
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
●
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y
3800 GROUP USER’S MANUAL
2-7
APPLICATION
2.2 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 2316]
At reset
Name
B
0
R
Function
W
b1 b0
Timer X operating mode bit
0 0 : Timer mode
0
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer X (refer to Table 2.2.1).
0 : Count start
1 : Count stop
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1
2
3
4
5
6
7
0
0
0
0
0
0
0
CNTR0 active edge switch bit
Timer X count stop bit
Timer Y operating mode bit
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR1 active edge switch bit It depends on the operating mode
of the Timer Y (refer to Table 2.2.1).
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 2.2.5 Structure of Timer XY mode register
Table. 2.2.1 Function of CNTR0/CNTR1 edge switch bit
Operating mode of
Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)
Timer X/Timer Y
Timer mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
(No effect on timer count)
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
(No effect on timer count)
• Start of pulse output : From “H” level
Pulse output mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
Event counter mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
Pulse width measurement mode
3800 GROUP USER’S MANUAL
2-8
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Name
Function
0 : No interrupt request
1 : Interrupt request
At reset R W
B
0
INT0 interrupt request bit
0
0
0
✻
✻
✻
0 : No interrupt request
1 : Interrupt request
INT1 interrupt request bit
1
0 : No interrupt request
1 : Interrupt request
2 Serial I/O receive interrupt
request bit
Serial I/O transmit interrupt
3
0 : No interrupt request
1 : Interrupt request
✻
✻
✻
0
request bit
0 : No interrupt request
1 : Interrupt request
Timer X interrupt request
4
0
0
0
0
bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request
5
bit
✻
✻
Timer 1 interrupt request bit
6
7
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
✻
“0” is set by software, but not “1.”
Fig. 2.2.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
At reset
B
Name
Function
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
CNTR0 interrupt request bit
CNTR1 interrupt request bit
INT2 interrupt request bit
0
1
2
3
4
5
0
✻
✻
✻
0
0
0
0
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT3 interrupt request bit
INT4 interrupt request bit
INT5 interrupt request bit
✻
✻
6
7
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
0
0
✻ “0” is set by software, but not “1.”
Fig. 2.2.7 Structure of Interrupt request register 2
3800 GROUP USER’S MANUAL
2-9
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
INT0 interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
INT1 interrupt enable bit
1
2
3
4
5
6
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive interrupt
enable bit
Serial I/O transmit interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
7
Fig. 2.2.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
At reset
Name
Function
B
0
R W
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
CNTR1 interrupt enable bit
INT2 interrupt enable bit
1
2
3
4
5
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT3 interrupt enable bit
INT4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
INT5 interrupt enable bit
Fix these bits to “0.”
0 : Interrupt disabled
1 : Interrupt enabled
0
0
6
7
Fig. 2.2.9 Structure of Interrupt control register 2
3800 GROUP USER’S MANUAL
2-10
APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 250 ms)
Outline : The input clock is divided by a timer so that the clock counts up every 250 ms.
Specifications : • The clock f(XIN) = 4.19 MHz (222 Hz) is divided by a timer.
• The clock is counted at intervals of 250 ms by the Timer X interrupt.
Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figures 2.2.11 show a
setting of related registers, and Figure 2.2.12 shows a control procedure.
Fixed
1/16
Prescaler X
1/256
Timer X
1/256
Timer X interrupt request bit
The clock is divided by 4 by software.
f(XIN) =
4.19 MHz
0 or 1
1/4
250 ms
1 second
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function]
3800 GROUP USER’S MANUAL
2-12
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7
b0
1
TM
0 0
Timer X operating mode bits : Timer mode
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Prescaler X (Address : 2416)
b7
b0
PREX
TX
255
Timer X (Address:2516)
Set “division ratio – 1”
b7
b0
255
Interrupt control register 1 (Address : 3E16)
b7
b0
1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7
b0
IREQ1
0
Timer X interrupt request bit
(becomes “1” every 250 ms)
Fig. 2.2.11 Setting of related registers [Clock function]
3800 GROUP USER’S MANUAL
2-13
APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output
Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer
output.
Specifications : • The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about
2 kHz (2048 Hz) is output from the P54/CNTR0 pin.
• The level of the P54/CNTR0 pin fixes to “H” while a piezoelectric buzzer output is
stopped.
Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the
timer and setting of the division ratio.
The “H” level is output while a piezoelectric buzzer output is stopped.
CNTR0 output
3800 group
P54/CNTR0
PiPiPi....
244 µs
244 µs
Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.13 Example of a peripheral circuit
Timer X
1/64
Fixed
Prescaler X
1
Fixed
1/2
f(XIN) = 4.19 MHz
1/16
CNTR0
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
3800 GROUP USER’S MANUAL
2-15
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316)
b7
b0
TM
1 1 1 0
Timer Y operating mode bit : Event counter mode
CNTR1 active edge switch bits : Count at falling edge
Timer Y count stop bit : Count stop
Set to “0” at starting to count.
Prescaler 12 (Address : 2016)
b7
b0
PRE12
T1
63
Timer 1 (Address : 2116)
b7
b0
7
Set “division ratio – 1”
Prescaler Y (Address : 2616)
b7
b0
0
PREY
TY
Timer Y (Address : 2716)
b7
b0
Set “255” to this register immediately before
counting pulse.
(After a certain time, this value is decreased by
the number of input pulses)
255
Interrupt control register 1 (Address : 3E16)
b7
b0
ICON1
IREQ1
1 0
Timer Y interrupt enable bit : Interrupt disabled
Timer 1 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16)
b7
b0
0
Judgment of Timer Y interrupt request bit
(When this bit is set to “1” at reading out
the count value of the Timer Y (address : 2716),
256 pulses or more are input (at setting 255 to
the Timer Y).)
Fig. 2.2.18 Setting of related registers [Measurement of frequency]
3800 GROUP USER’S MANUAL
2-18
APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor
Outline : The “H” level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An
underflow is detected by Timer X interrupt and an end of the input pulse “H” level is detected
by CNTR0 interrupt.
Specifications : • The “H” level width of a FG pulse input to the P54/CNTR0 pin is counted by Timer
X.
(Example : When the clock frequency is 4.19 MHz, the count source would be
3.8 µs that is obtained by dividing the clock frequency by 16.
Measurement can be made up to 250 ms in the range of FFFF16 to
000016.)
Figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and Figure 2.2.21
shows a setting of related registers.
Timer X
1/256
Timer X interrupt request bit
0 or 1
Fixed
1/16
Prescaler X
1/256
f(XIN) =4.19 MHz
250 ms
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width]
3800 GROUP USER’S MANUAL
2-20
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316
)
b7
b0
TM
1 0 1 1
Timer X operating mode bits : Pulse width measurement mode
CNTR active edge switch bit : Count “H” level width
0
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Prescaler X (Address : 2416
)
b7
b0
PREX
TX
255
Set “division ratio – 1”
Timer X (Address : 2516
)
b0
b7
255
Interrupt control register 1 (Address : 3E16
)
b7
b0
1
ICON1
IREQ1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register (Address : 3C16
)
b7
b0
0
Timer X interrupt request bit
(This bit is set to “1” at underflow of Timer X.)
Interrupt control register 2 (Address : 3F16
)
b7
b0
1
ICON2
IREQ2
CNTR
0
interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D16
)
b7
b0
0
CNTR
0
interrupt request bit
(This bit is set to “1” at completion of inputting
“H” level signal.)
Fig. 2.2.21 Setting of related registers [Measurement of pulse width]
3800 GROUP USER’S MANUAL
2-21
APPLICATION
2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
At reset
Name
Function
0 : No interrupt request
1 : Interrupt request
R W
B
0
✻
INT0 interrupt request bit
0
0 : No interrupt request
1 : Interrupt request
✻
1
2
INT1 interrupt request bit
0
0 : No interrupt request
1 : Interrupt request
✻
Serial I/O receive interrupt
request bit
0
Serial I/O transmit interrupt
request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
3
4
5
6
7
0
✻
Timer X interrupt request bit
0
0 : No interrupt request
1 : Interrupt request
✻
Timer Y interrupt request bit
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
Timer 1 interrupt request bit
Timer 2 interrupt request bit
0
✻
0
“0” is set by software, but not “1.”
✻
Fig. 2.3.8 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
INT0 interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
INT1 interrupt enable bit
1
2
3
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive interrupt
enable bit
Serial I/O transmit interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.9 Structure of Interrupt control register 1
3800 GROUP USER’S MANUAL
2-27
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
There are connection examples using a clock synchronous serial I/O mode.
Figure 2.3.10 shows connection examples of a peripheral IC equipped with the CS pin.
(2) Transmission and reception
(1) Only transmission
(using the RXD pin as an I/O port)
Port
SCLK
CS
CS
Port
SCLK
TXD
CLK
IN
CLK
DATA
TXD
OUT
RXD
3800 group
Peripheral IC
(OSD controller etc.)
3800 group
Peripheral IC
(E2 PROM etc.)
(3) Transmission and reception
(Pins RXD and TXD are connected)
(Pins IN and OUT in peripheral IC
are connected)
(4) Connecting ICs
Port
Port
SCLK
CS
CS
CLK
IN
CLK
IN
SCLK
TXD
RXD
TXD
OUT
OUT
RXD
3800 group ✻1
Peripheral IC 1
Peripheral IC ✻2
Port
(E2 PROM etc.)
3800 group
CS
✻1: Select an N-channel open-drain output control of TXD pin.
2: Use such OUT pin of peripheral IC as an N-channel open-
drain output in high impedance during receiving data.
CLK
IN
OUT
Note:
“Port” is an output port controlled by software.
Peripheral IC 2
Fig. 2.3.10 Serial I/O connection examples (1)
3800 GROUP USER’S MANUAL
2-28
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.11 shows connection examples of the other microcomputers.
(2) Selecting an external clock
(1) Selecting an internal clock
SCLK
CLK
SCLK
TXD
RXD
CLK
IN
TXD
RXD
IN
OUT
OUT
3800 group
Microcomputer
3800 group Microcomputer
(3) Using the SRDY siganl output function
(Selecting an external clock)
(4) Using UART
SRDY
SCLK
TXD
RDY
CLK
TXD
RXD
RXD
TXD
IN
RXD
OUT
3800 group
Microcomputer
3800 group Microcomputer
Fig. 2.3.11 Serial I/O connection examples (2)
3800 GROUP USER’S MANUAL
2-29
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using a clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The SRDY
signal is used for communication control.
Figure 2.3.13 shows a connection diagram, and Figure 2.3.14 shows a timing chart.
Transmitting side
Receiving side
SRDY
SCLK
RXD
P42/INT0
SCLK1
TXD
3800 group
3800 group
Fig. 2.3.13 Connection diagram [Communication using a clock synchronous serial I/O]
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected)
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• The SRDY (receivable signal) is used.
• The receiving side outputs the SRDY signal at intervals of 2 ms (generated by
timer), and 2-byte data is transferred from the transmitting side to the receiving
side.
• • • •
SRDY
• • • •
SCLK
TXD
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
• • • •
2 ms
Fig. 2.3.14 Timing chart [Communication using a clock synchronous serial I/O]
3800 GROUP USER’S MANUAL
2-31
APPLICATION
2.3 Serial I/O
Figure 2.3.21 shows a setting of serial I/O related registers, and Figure 2.3.22 shows a setting of serial
I/O transmission data.
Serial I/O control register (Address : 1A16
b7 b0
1 1 0 1 1 0 0 0
)
SIOCON
BRG count source selection bit : f(XIN
)
Serial I/O synchronous clock selection bit : BRG/4
RDY output enable bit : Not use the RDY signal output function
S
S
Transmit interrupt source selection bit : Transmit shift operating completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 1B16
)
b7 b0
0
UARTCON
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C16
)
b7 b0
7
BRG
Set “division ratio – 1”
Interrupt control register 1 (Address : 3E16
)
b7 b0
ICON1
0
Serial I/O transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C16
)
b7 b0
IREQ1
0
Serial I/O transmit interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit shift completion
Fig. 2.3.21 Setting of serial I/O related registers [Output of serial data]
Transmit/Receive buffer register (Address : 1816)
b7
b0
Set a transmission data.
TB/RB
Check that transmission of the previous data is
completed before writing data (bit 3 of the
Interrupt request register 1 is set to “1”).
Fig. 2.3.22 Setting of serial I/O transmission data [Output of serial data]
3800 GROUP USER’S MANUAL
2-37
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes)
between microcomputers
[without using an automatic transfer]
Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock
and the data between the transmitting and receiving sides may be lost because of noise
included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This
“heading adjustment” is carried out by using the interval between blocks in this example.
SCLK
TXD
RXD
SCLK
RXD
TXD
Slave unit
Master unit
Fig. 2.3.24 Connection diagram [Cyclic transmission or reception of block data between
microcomputers]
Specifications : • The serial I/O is used (clock synchronous serial I/O is selected).
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 byte/block
• Block transfer cycle : 16 ms
• Block transfer period : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustive time : 8 ms
Limitations of the specifications
1. Reading of the reception data and setting of the next transmission data must be completed
within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example,
the time taken from generating of the Serial I/O receive interrupt request to generating of the
next synchronizing clock is 431 µs).
2. “Heading adjustive time < interval between blocks” must be satisfied.
3800 GROUP USER’S MANUAL
2-39
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.26 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle
Block transfer period
Block transfer cycle
Interval between blocks
Heading adjustive time
Processing for heading adjustment
Fig. 2.3.25 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Slave unit
Serial I/O control register (Address : 1A )
6
Serial I/O control register (Address : 1A16
)
b7
b0
b7
b0
1 1 1 1 1 0 0 0
1 1
0 1
SIOCON 1 1
SIOCON
BRG count source : f(XIN
Synchronous clock : BRG/4
Not use the
)
Not be effected by external clock
Synchronous clock : External clock
S
RDY output
Not use the SRDY output
Not use the serial I/O transmit interrupt
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Transmit enabled
Receive enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O enabled
Clock synchronous serial I/O
Serial I/O enabled
Both of units
UART control register (Address : 1B16
)
b7 b0
UARTCON
0
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16
)
b7 b0
Set “division ratio – 1”
BRG
7
Fig. 2.3.26 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
3800 GROUP USER’S MANUAL
2-40
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values,
Figure 2.3.31 shows a setting of related registers at a transmitting side, and Figure 2.3.32 shows a
setting of related registers at a receiving side.
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit BRG count
rate (bps) source
at f(XIN) = 4.9152 MHZ
at f(XIN) = 7.3728 MHZ
at f(XIN) = 8 MHZ
BRG setting value
BRG setting value Actual time (bps) BRG setting value Actual time (bps)
Actual time (bps)
600.96
(Note 1)
(Note 2)
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
600
127(7F16)
63(3F16)
31(1F16)
15(0F16)
7(0716)
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
191(BF16)
95(5F16)
47(2F16)
23(1716)
11(0B16)
5(0516)
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
207(CF16)
103(6716)
51(3316)
25(1916)
12(0C16)
5(0516)
1200
1201.92
2400
4800
2403.85
4807.69
9600
9615.38
19200
38400
76800
31250
62500
3(0316)
20833.33
41666.67
83333.33
31250.00
62500.00
1(0116)
2(0216)
2(0216)
3(0316)
5(0516)
5(0516)
f(XIN)
15(0F16)
7(0716)
f(XIN)
Notes 1: Equation of transfer bit rate
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m
Transfer bit rate (bps) =
m: when bit 0 of the Serial I/O control register (Address : 1A16) is set to “0,” a value of m is 1.
when bit 0 of the Serial I/O control register (Address : 1A16) is set to “1,” a value of m is 4.
2: A BRG count source is selected by bit 0 of the Serial I/O control register (Address : 1A16).
3800 GROUP USER’S MANUAL
2-44
APPLICATION
2.5 Reset
2.5 Reset
2.5.1 Connection example of reset IC
91
35
40
V
CC
1
Power source
Output
5
RESET
M62022L
Delay capacity
4
GND
0.1 µF
V
SS
3
3800 group
Fig. 2.5.1 Example of Poweron reset circuit
Figure 2.5.2 shows the system example which switch to the RAM backup mode by detecting a drop of the
system power source voltage with the INT interrupt.
System power
source voltage
+5
91
VCC
+
7
VCC1
5
35
40
RESET
RESET
2
1
3
6
INT
Cd
INT
VCC2
V1
VSS
GND
3800 group
4
M62009L, M62009P, M62009FP
Fig. 2.5.2 RAM back-up system
3800 GROUP USER’S MANUAL
2-54
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Mask ROM ordering method
3.7 Mark specification form
3.8 Package outline
3.9 List of instruction codes
3.10 Machine instructions
3.11 SFR memory map
3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Max.
“H” output voltage P0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
7
7
1
, P2
, P5
(Note)
0
0
–P2
7
,
,
V
CC–2.0
P3
P6
0
0
–P5
7
VCC = 4.0 to 5.5 V
VOH
0
0
IOH = –1.0 mA
VCC = 3.0 to 5.5 V
V
CC–1.0
“L” output voltage P0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
7
7
1
, P2
,P5
0
–P2
7
,
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
P3
P6
0
0
0
–P5
7
,
VOL
V
0
0
IOL = 1.0 mA
VCC = 3.0 to 5.5 V
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
D, SCLK
RESET
0
, CNTR
1
, INT
0
–INT
5
0.4
0.5
0.5
V
V
V
Hysteresis
RX
Hysteresis
“H” input current
P0
P3
P6
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
7
7
1
, P2
, P5
0
0
–P2
7
,
,
IIH
0
0
–P5
7
VI = VCC
5.0
5.0
µA
0
0
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
XIN
4
P0
P3
P6
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
7
7
1
, P2
, P5
0
0
–P2
7
,
,
IIL
0
0
–P5
7
VI = VSS
–5.0
µA
0
0
RESET, CNVSS
–4
µA
IIL
“L” input current
XIN
VI = VSS
2.0
VRAM
RAM hold voltage
When clock stopped
f(XIN) = 8 MHz, VCC = 5 V
f(XIN) = 5 MHz, VCC = 5 V
f(XIN) = 2 MHz, VCC = 3 V
5.5
13
8
V
6.4
4
0.8
2.0
When WIT instruction is executed
with f(XIN) = 8 MHz, VCC = 5 V
1.5
1
mA
When WIT instruction is executed
with f(XIN) = 5 MHz, VCC = 5 V
Power source current
ICC
When WIT instruction is executed
with f(XIN) = 2 MHz, VCC = 3 V
0.2
0.1
When STP instruction
is executed with clock
stopped, output
Ta = 25 °C
1
µA
Ta = 85 °C
10
transistors isolated.
Note : P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3800 GROUP USER’S MANUAL
3-3
APPENDIX
3.1 Electrical characteristics
3.1.4 Timing requirements and Switching characteristics
Table 3.1.4 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tW(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
125
50
tWH(XIN)
tWL(XIN)
50
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tc(SCLK)
200
80
80
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
220
100
tWH(SCLK)
tWL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Table 3.1.5 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
Reset input “L” pulse width
µs
tW(RESET)
tc(XIN)
500/
(3 VCC–8)
External clock input cycle time
ns
200/
(3 VCC–8)
External clock input “H” pulse width
External clock input “L” pulse width
ns
ns
tWH(XIN)
tWL(XIN)
200/
(3 VCC–8)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
500
230
230
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
t
t
su(R
X
D–SCLK
)
Serial I/O input hold time
h(SCLK–R
X
D)
Note:When bit 6 of address 001A16 is “1” (clock synchronous mode). Divide this value by four when bit 6 of address 001A16 is “0” (UART
mode).
3800 GROUP USER’S MANUAL
3-4
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
140
tWH(SCLK)
tWL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
t
t
c(SCLK
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK
)
t
t
d(SCLK–T
v(SCLK–T
X
D)
XD)
–30
Fig. 3.1.1
tr(SCLK)
tf(SCLK)
30
30
30
30
tr(CMOS)
tf(CMOS)
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
Table 3.1.7 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
350
tWH(SCLK)
tWL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
t
t
c(SCLK
)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK
)/2–50
t
t
d(SCLK–T
v(SCLK–T
X
D)
XD)
–30
Fig. 3.1.1
tr(SCLK)
tf(SCLK)
50
50
50
50
tr(CMOS)
tf(CMOS)
20
20
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
3800 GROUP USER’S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
3.1.7 Electrical characteristics (Extended operating temperature version)
Table 3.1.14 Electrical characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V,
VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage P0
0
–P0
–P3
–P6
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
–P1
–P4
, P7
7
7
1
, P2
, P5
0
0
–P2
7
,
,
VOH
P3
P6
0
0
–P5
7
IOH = –10 mA
IOL = 10 mA
VCC–2.0
0
0
(Note)
, P2 –P2
,P5 –P5
“L” output voltage P0
0
7
7
7
, P1
, P4
, P7
0
7
7
1
0
7
,
VOL
P3
P6
0
0
0
7
,
2.0
V
0
0
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
D, SCLK
RESET
0
, CNTR
1
, INT
0
–INT
5
0.4
0.5
0.5
V
V
V
Hysteresis
RX
Hysteresis
“H” input current
P0
P3
P6
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
–P1
–P4
, P7
7
7
1
, P2
, P5
0
0
–P2
7
,
,
IIH
0
0
–P5
7
VI = VCC
5.0
5.0
µA
0
0
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
P0 –P0
P4 –P4
RESET, CNVSS
IN
4
0
7
, P1
, P50
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
, P71
7,
,
IIL
0
7
–P5
7
, P6
0–P6
7, P7
0
VI = VSS
–5.0
µA
IIL
“L” input current
X
VI = VSS
–4
µA
VRAM
RAM hold voltage
When clock stopped
f(XIN) = 8 MHz
f(XIN) = 5 MHz
5.5
13
8
V
2.0
6.4
4
mA
When WIT instruction is executed
with f(XIN) = 8 MHz
1.5
1
When WIT instruction is executed
with f(XIN) = 5 MHz
ICC
Power source current
When STP instruction
is executed with clock
0.1
1
Ta = 25 °C
µA
stopped, output
transistors isolated.
10
Ta = 85 °C
Note : P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3800 GROUP USER’S MANUAL
3-9
APPENDIX
3.1 Electrical characteristics
3.1.8 Timing requirements and Switching characteristics (Extended operating temperature version)
Table 3.1.15 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tW(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
125
50
tWH(XIN)
tWL(XIN)
50
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tc(SCLK)
200
80
80
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
220
100
tWH(SCLK)
tWL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note: Bit 6 of address 001A16 is “1”. Divide this value by four bit 6 of address 001A16 is “0”.
Table 3.1.16 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
tWH(SCLK)
tWL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rise time
Serial I/O clock output fall time
t
t
c(SCLK
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK
)
t
t
d(SCLK–T
v(SCLK–T
X
D)
XD)
–30
Fig. 3.1.1
tr(SCLK)
tf(SCLK)
30
30
30
30
tr(CMOS)
tf(CMOS)
CMOS output rise time (Note 2)
CMOS output fall time (Note 2)
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
3800 GROUP USER’S MANUAL
3-10
APPENDIX
3.1 Electrical characteristics
Table 3.1.17 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
60
Typ.
Max.
tsu(ONW–φ)
th(φ–ONW)
tsu(DB–φ)
th(φ–DB)
Before φ ONW input set up time
After φ ONW input hold time
Before φ data bus set up time
After φ data bus hold time
ns
ns
ns
ns
0
tsu
tsu
(
(
ONW–RD) Before RD ONW input set up time
ONW–WR) Before WR ONW input set up time
–20
–20
ns
ns
th(RD–ONW)
After RD ONW input hold time
th(WR–ONW) After WR ONW input hold time
tsu(DB–RD
)
Before RD data bus set up time
After RD data bus hold time
65
0
ns
ns
th(RD–DB)
Table 3.1.18 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
20
10
25
10
20
10
10
5
40
45
6
6
SYNC valid time
RD and WR delay time
RD and WR valid time
20
10
70
3
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
20
15
Fig. 3.1.1
tc(XIN)–10
twL(RD)
twL(WR)
RD pulse width, WR pulse width
(When one-wait is valid)
3tc(XIN)–10
ns
ns
ns
ns
ns
td(AH–RD)
td(AH–WR)
After AD15–AD8 RD delay time
After AD15–AD8 WR delay time
tc(XIN)–35
t
t
c(XIN
)
–15
–20
td(AL–RD)
td(AL–WR)
After AD7–AD0 RD delay time
After AD7–AD0 WR delay time
tc(XIN)–40
c(XIN)
tv(RD–AH)
tv(WR–AH)
After RD AD15–AD8 valid time
After WR AD15–AD8 valid time
0
0
5
tv(RD–AL)
tv(WR–AL)
After RD AD7–AD0 valid time
After WR AD7–AD0 valid time
5
td(WR–DB)
tv(WR–DB)
After WR data bus delay time
After WR data bus valid time
RESETOUT output delay time
RESETOUT output valid time (Note)
15
65
ns
ns
ns
ns
10
0
t
d
(RESET–RESETOUT
)
200
200
tv(φ–RESET)
Note : The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
Measurement output pin
100pF
CMOS output
Fig. 3.1.1 Circuit for measuring output switching
characteristics
3800 GROUP USER’S MANUAL
3-11
APPENDIX
3.1 Electrical characteristics
3.1.9 Timing diagram
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8 VCC
CNTR0, CNTR1
INT0–INT5
0.2 VCC
tWL(INT)
tWH(INT)
0.8 VCC
0.2 VCC
tW(RESET)
RESET
0.8 VCC
0.2 VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8 VCC
XIN
0.2 VCC
tC(SCLK)
tWL(SCLK)
tWH(SCLK)
tr
tf
SCLK
0.8 VCC
0.2 VCC
tsu(SCLK-RXD)
th(SCLK-RXD)
0.8 VCC
0.2 VCC
RXD
TXD
tv(SCLK-TXD)
td(SCLK-TXD)
Fig. 3.1.2 Timing diagram (in single-chip mode)
3800 GROUP USER’S MANUAL
3-12
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)
tWL(RD)
tWL(WR)
RD,WR
0.5 VCC
td(AH-RD)
td(AH-WR)
tv(RD-AH)
tv(WR-AH)
0.5 VCC
AD15–AD8
td(AL-RD)
td(AL-WR)
tv(RD-AL)
tv(WR-AL)
0.5 VCC
AD7–AD0
th(RD-ONW)
th(WR-ONW)
tsu(ONW-RD)
tsu(ONW-WR)
0.8 VCC
0.2 VCC
ONW
(At CPU reading)
RD
tWL(RD)
0.5 VCC
tSU(DB-RD)
0.8 VCC
th(RD-DB)
DB0–DB7
0.2 VCC
(At CPU writing)
WR
tWL(WR)
0.5 VCC
tv(WR-DB)
td(WR-DB)
0.5 VCC
DB0–DB7
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2)
3800 GROUP USER’S MANUAL
3-14
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Sequence for switching an external interrupt
detection edge
Clear an interrupt enable bit to “0” (interrupt disabled)
Switch the detection edge
When the external interrupt detection edge must be
switched, make sure the following sequence.
Reason
Clear an interrupt request bit to “0” (no interrupt requ-
est issued)
The interrupt circuit recognizes the switching of the
detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
Set the interrupt enable bit to “1” ( interrupt enabled )
(2) Bits 7 and 6 of the interrupt control register 2
Fix the bits 7 and 6 of the interrupt control register 2
(Address:003F16) to “0”.
b7
b0
Interrupt control register 2
Address 003F16
0 0
Figure 3.3.1 shows the structure of the interrupt
control register 2.
Interrupt enable bits
Not used
Fix these bits to “0”.
Fig. 3.3.1 Structure of interrupt control register 2
3.3.2 Notes on the serial I/O
(1) Stop of data transmission
As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O disabled)in the
following cases :
● when stopping data transmission during transmitting data in the clock synchronous serial I/O mode
● when stopping data transmission during transmitting data in the UART mode
● when stopping only data transmission during transmitting and receiving data in the UART mode
Reason
Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK,
and SRDY function as I/O ports, the transmission data is not output). When data is written to the transmit buffer
register in this state, the data is transferred to the transmit shift register and start tp be sjifted. When the serial
I/O enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause
an operation failure to a microcomputer.
(2) Stop of data reception
As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the
following case :
● when stopping data reception during receiving data in the clock synchronous serial I/O mode
Clear the receive enable bit to “0” (receive disabled) in the following cases :
● when stopping data reception during receiving data in the UART mode
● when stopping only data reception during transmitting and receiving data in the UART mode
3800 GROUP USER’S MANUAL
3-18
APPENDIX
3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode
As for the serial I/O that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the
following case:
● when stopping data transmission and reception during transmitting and receiving data in the clock synchronous
mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of
transmission and reception is disabled, a bit error occurs because transmission and reception cannot be
synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the
transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the
transmission circuit is not initialized by clearing the serial I/O enable bit to “0” (serial I/O disabled) (refer to (1)).
(4) The SRDY pin on a receiving side
When signals are output from the SRDY pin on the reception side by using an external clock in the clock
synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable
bit to “1” (transmit enabled).
(5) Stop of data reception in a clock synchronous
Clear both the transmit
serial I/O mode
Set the serial I/O control register again after the
transmission and the reception circuits are reset by
enable bit (TE) and the
receive enable bit (RE) to “0”
clearing both the transmit enable bit and the receive
enable bit to “0.”
Set the bits 0 to 3 and bit 6 of
the serial I/O control register
Can be set with the
LDM instruction at
the same time
Set both the transmit enable
bit (TE) and the receive
enable bit (RE) to “1”
(6) Control of data transmission using the transmit shift completion flag
The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking
the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data
transmission, note this delay.
(7) Control of data transmission using an external clock
When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”
at “H” level of the SCLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input
signal.
3.3.3 Notes on the RESET pin
When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and
the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make
sure the following :
●Make the length of the wiring which is connected to a capacitor the shortest possible.
●Make sure to check the operation of application products on the user side.
Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may
malfunction.
3800 GROUP USER’S MANUAL
3-19
APPENDIX
3.3 Notes on use
3.3.4 Notes on input and output pins
(1) Fix of a port input level in stand-by state
Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state*, especially
for the I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
When determining a resistance value, make sure the following:
●External circuit
●Variation of output levels during the ordinary operation
* stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason
Even when setting as an output port with its direction register, in the following state :
●N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the
level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input and an I/O port are “undefined.” This may cause power source current.
(2) Modify of the content of I/O port latch
When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the
unspecified bit may be changed.
Reason
The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit.
Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed
to all bits of the port latch.
●As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit
managing.
●As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit
managing.
Make sure the following :
●Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
●Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,
its value may be changed in case where content of the pin differs from a content of the port latch.
* bit managing instructions : SEB and CLB instruction
3800 GROUP USER’S MANUAL
3-20
APPENDIX
3.3 Notes on use
3.3.6 Notes on built-in PROM
(1) Programming adapter
To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose
PROM programmer as shown in Table 3.3.1.
Table 3.3.1 Programming adapter
Microcomputer
M38002E4SS
M38004E8SS
M38002E2SP
M38002E4SP
M38004E8SP
(one-time blank)
M38002E4DSP
(one-time blank)
M38002E4FS
M38004E8FS
M38002E2FP
M38002E4FP
M38004E8FP
(one-time blank)
M38002E4DFP
(one-time blank)
Programming adapter
PCA4738S-64A
PCA4738L-64A
PCA4738F-64A
(2) Write and read
In PROM mode, operation is the same as that of the M5M27C256AK, but programming conditions of PROM
programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as
the CNVSS pin), or the product may be permanently damaged.
● Programming voltage : 12.5 V
● Setting of programming adapter switch : refer to table 3.3.2
● Setting of PROM programmer address : refer to table 3.3.3
Table 3.3.2 Setting of programming adapter switch
SW 1
SW 2
SW 3
OFF
Programming adapter
PCA4738S-64A
PCA4738L-64A
CMOS
CMOS
PCA4738F-64A
3800 GROUP USER’S MANUAL
3-22
APPENDIX
3.3 Notes on use
Table 3.3.3 Setting of PROM programmer address
Microcomputer
M38002E2SP
M38002E2FP
M38002E4SS
M38002E4SP
M38002E4FS
M38002E4FP
M38002E4DSP
M38002E4DFP
M38004E8SS
M38004E8SP
M38004E8FS
M38004E8FP
PROM programmer start address
PROM programmer completion address
Address : 608016 (Note 1)
Address : 7FFD16 (Note 1)
Address : 408016 (Note 2)
Address : 7FFD16 (Note 2)
Address : 008016 (Note 3)
Address : 7FFD16 (Note 3)
Note1 : Addresses E08016 to FFFD16 in the internal PROM correspond to addresses 608016 to 7FFD16 in the
ROM programmer.
2 : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the
ROM programmer.
3 : Addresses 808016 to FFFD16 in the internal PROM correspond to addresses 008016 to 7FFD16 in the
ROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537-
Angstrom . At least 15 W-sec/cm2 are required to erase EPROM contents.
3800 GROUP USER’S MANUAL
3-23
APPENDIX
3.4 Countermeasures against noise
An example of VSS patterns on the
underside of a printed circuit board
Noise
Oscillator wiring
pattern example
XIN
XOUT
VSS
XIN
XOUT
VSS
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
N.G.
O.K.
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring for the VPP pin of the One Time PROM
version and the EPROM version
(In this microcomputer the VPP pin is also used
as the CNVSS pin)
Approximately
Connect an approximately 5 kΩ resistor to theVPP
pin the shortest possible in series and also to the VSS
pin. When not connecting the resistor, make the
length of wiring between the VPP pin and the VSS pin
the shortest possible.
5kΩ
CNVSS/VPP
VSS
Note:Even when a circuit which inclued an
approximately 5 kΩ resistor is used in the Mask ROM
version, the maicrocomputer operates correctly.
3800 group
Make it the shortest possible
Reason
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM
and the EPROM version
The VPP pin of the One Time PROM and the EPROM
version is the power source input pin for the built-in
PROM. When programming in the built-in PROM,
the impedance of the VPP pin is low to allow the
electric current for wiring flow into the PROM. Be-
cause of this, noise can enter easily. If noise enters
the VPP pin, abnormal in struction codes or data are
read from the built-in PROM, which may cause a
program runaway.
3.4.2 Connection of a bypass capacitor across the
Vss line and the Vcc line
Connect an approximately 0.1 µF bypass capacitor
across the VSS line and the VCC line as follows:
●Connect a bypass capacitor across the VSS pin
and the VCC pin at equal length .
VCC
Chip
●Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
●Use lines with a larger diameter than other signal
lines for VSS line and VCC line.
VCC
VSS
VSS
Fig. 3.4.4 Bypass capacitor across the VSS line and
the VCC line
3800 GROUP USER’S MANUAL
3-25
APPENDIX
3.4 Countermeasures against noise
3.4.3. Consideration for oscillator
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
Microcomputer
Mutual inductance
M
(1) Keeping an oscillator away from large current
signal lines
XIN
XOUT
Large
current
Install a microcomputer (and especially an oscillator)
as far as possible from signal lines where a current
larger than the tolerance of current value flows.
VSS
GND
Fig.3.4.5 Wiring for a large current signal line
Reason
In the system using a microcomputer, there are
signal lines for controlling motors, LEDs, and thermal
heads or others. When a large current flows through
those signal lines, strong noise occurs because of
mutual inductance.
(2) Keeping an oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern of an
osillator away from signal lines where potential levels
change frequently. Also, do not cross such signal
lines over the clock lines or the signal lines which are
sensitive to noise.
CNTR
Do not cross
XIN
XOUT
VSS
Reason
Signal lines where potential levels change frequently
(such as the CNTR pin line) may affect other lines at
signal rising or falling edge. If such lines cross over
a clock line, clock waveforms may be deformed,
which causes a microcomputer failure or a program
runaway.
Fig.3.4.6 Wiring to a signal line where potential levels
change frequently
3.4.4 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
Noise
O.K.
<Hardware>
Data bus
●Connect a resistor of 100 Ω or more to an I/O port
Noise
inseries.
Direction register
N.G.
<Software>
Port latch
●As for an input port, read data several times by a
program for checking whether input levels are
equal or not.
I/O port
pins
●As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
Fig. 3.4.7 Setup for I/O ports
●Rewirte data to direction registers and pull-up
control registers (only the product having it) at fixed
periods.
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be
output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
3800 GROUP USER’S MANUAL
3-26
APPENDIX
3.4 Countermeasures against noise
3.4.5 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
CLI
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
>0
Main processing
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
=N
Interrupt processing routine
errors
Main routine
errors
<The main routine>
●Assigns a single byte of RAM to a software watchdog
timer (SWDT) and writes the initial value N in the
SWDT once at each execution of the main routine.
The initial value N should satisfy the following
condition:
Fig. 3.4.8 Watchdog timer by software
N+1 ≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N
should have a margin.
●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of
interrupt processing count after the initial value N has been set.
●Detects that the interrupt processing routine has failed and determines to branch to the program initialization
routine for recovery processing in the following cases:
If the SWDT contents do not change after interrupt processing
<The interrupt processing routine>
●Decrements the SWDT contents by 1 at each interrupt processing.
●Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at
almost fixed cycles (at the fixed interrupt processing count).
●Detects that the main routine has failed and determines to branch to the program initialization routine for recovery
processing in the following case:
When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value
N .
3800 GROUP USER’S MANUAL
3-27
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16
]
At reset
B
0
Name
Function
R W
Port Pi
0
1
?
●
●
In output mode
Write
Read
Port latch
Port Pi
1
2
3
4
5
6
7
?
?
?
?
?
?
?
In input mode
Write : Port latch
Read : Value of pins
Port Pi
2
Port Pi
3
4
(Note)
Port Pi
Port Pi
Port Pi
Port Pi
5
6
7
Port P7 register [Address : 0E16
]
Note :
Port P7 is a 2-bit port (P7
0
, P7 ). Accordingly, when bits 2 to 7 are read
1
out, the contents are “0.”
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i =0, 1, 2, 3, 4, 5, 6, 7)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16]
Name
Function
At reset
B
0
R W
0 : Port Pi0 input mode
1 : Port Pi0 output mode
Port Pi direction register
0
✕
0 : Port Pi1 input mode
1 : Port Pi1 output mode
1
2
3
4
5
6
7
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
(Note)
(Note)
0 : Port Pi4 input mode
1 : Port Pi4 output mode
(Note)
(Note)
(Note)
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
(Note)
Note :
Port P7 direction register [Address : 0F16]
Port P7 is a 2-bit port (P70, P71). Accordingly, these bits do not have a
direction register function.
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7)
3800 GROUP USER’S MANUAL
3-28
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
At reset
Function
B
R W
●
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
0
1
2
3
4
5
6
7
1
●
0
0
0
0
0
0
0
●
Fig. 3.5.9 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
At reset
Function
R W
●
●
The count value of each timer is set.
The value set in this register is written to both the Timer and the
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
0
1
1
2
3
4
5
6
7
1
1
1
1
1
1
1
●
Fig. 3.5.10 Structure of Timer 2, Timer X, Timer Y
3800 GROUP USER’S MANUAL
3-32
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 2316]
At reset
Name
Function
B
0
R
W
b1 b0
Timer X operating mode bit
0 0 : Timer mode
0
0
0
0
0
0
0
0
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer X (refer to Table 3.5.1).
0 : Count start
1
2
3
4
5
6
7
CNTR0 active edge switch bit
Timer X count stop bit
1 : Count stop
b5 b4
Timer Y operating mode bit
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR1 active edge switch bit It depends on the operating mode
of the Timer Y (refer to Table 3.5.1).
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 3.5.11 Structure of Timer XY mode register
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit
Operating mode of
Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)
Timer X/Timer Y
Timer mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
(No effect on timer count)
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
(No effect on timer count)
• Start of pulse output : From “H” level
Pulse output mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
Event counter mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
Pulse width measurement mode
3800 GROUP USER’S MANUAL
3-33
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
Name
Function
0 : No interrupt request
1 : Interrupt request
At reset R W
B
0
INT0 interrupt request bit
0
0
0
✻
0 : No interrupt request
1 : Interrupt request
INT1 interrupt request bit
1
✻
✻
0 : No interrupt request
1 : Interrupt request
2 Serial I/O receive interrupt
request bit
Serial I/O transmit interrupt
3
0 : No interrupt request
1 : Interrupt request
0
✻
✻
✻
request bit
0 : No interrupt request
1 : Interrupt request
Timer X interrupt request
4
0
0
0
0
bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request
5
bit
Timer 1 interrupt request bit
6
✻
✻
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
7
✻
“0” is set by software, but not “1.”
Fig. 3.5.14 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16]
At reset
B
Name
Function
R W
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
CNTR0 interrupt request bit
CNTR1 interrupt request bit
INT2 interrupt request bit
0
1
2
3
4
5
0
✻
✻
✻
0
0
0
0
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT3 interrupt request bit
INT4 interrupt request bit
INT5 interrupt request bit
✻
✻
6
7
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
0
0
✻ “0” is set by software, but not “1.”
Fig. 3.5.15 Structure of Interrupt request register 2
3800 GROUP USER’S MANUAL
3-35
APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
GZZ-SH04-34B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
M38002M2-XXXSP
M38002M2-XXXFP
Microcomputer name :
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address E08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38002M2–’
ASCII code :
‘M38002M2–’
000F16
001016
000F16
001016
607F16
608016
E07F16
E08016
data
data
ROM 8062 bytes
ROM 8062 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘2’ = 3216
‘M’ = 4D16
‘2’ = 3216
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38002M2–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3800 GROUP USER’S MANUAL
3-37
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-34B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38002M2-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
*=a$8000
*=a$0000
The pseudo-command
.BYTEa ‘M38002M2–’
.BYTEa ‘M38002M2–’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38002M2-XXXSP, 64P6N for M38002M2-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-38
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-79B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38002M2DXXXSP
M38002M2DXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address E08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38002M2D’
ASCII code :
‘M38002M2D’
000F16
001016
000F16
001016
607F16
608016
E07F16
E08016
data
data
ROM 8062 bytes
ROM 8062 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘2’ = 3216
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38002M2D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘2’ = 3216
(1/2)
3800 GROUP USER’S MANUAL
3-39
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-79B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38002M2DXXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
*=a$8000
*=a$0000
The pseudo-command
.BYTEa ‘M38002M2D’
.BYTEa ‘M38002M2D’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38002M2DXXXSP, 64P6N for M38002M2DXXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-40
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-22B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38002M4-XXXSP
M38002M4-XXXFP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38002M4–’
ASCII code :
‘M38002M4–’
000F16
001016
000F16
001016
407F16
408016
C07F16
C08016
data
data
ROM 16254 bytes
ROM 16254 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘2’ = 3216
‘M’ = 4D16
‘4’ = 3416
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38002M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3800 GROUP USER’S MANUAL
3-41
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-22B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38002M4-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
*=a$8000
*=a$0000
The pseudo-command
.BYTEa ‘M38002M4–’
.BYTEa ‘M38002M4–’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38002M4-XXXSP, 64P6N for M38002M4-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-42
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH05-12B<21A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38002M4DXXXSP
M38002M4DXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38002M4D’
ASCII code :
‘M38002M4D’
000F16
001016
000F16
001016
407F16
408016
C07F16
C08016
data
data
ROM 16254 bytes
ROM 16254 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘2’ = 3216
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38002M4D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘4’ = 3416
(1/2)
3800 GROUP USER’S MANUAL
3-43
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH05-12B<21A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38002M4DXXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
*=a$8000
*=a$0000
The pseudo-command
.BYTEa ‘M38002M4D’
.BYTEa ‘M38002M4D’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38002M4DXXXSP, 64P6N for M38002M4DXXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-44
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-62B<14B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38003M6-XXXSP
M38003M6-XXXFP
M38003M6-XXXHP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38003M6–’
ASCII code :
‘M38003M6–’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM 24446 bytes
ROM 24446 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘3’ = 3316
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38003M6–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘6’ = 3616
(1/2)
3800 GROUP USER’S MANUAL
3-45
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-62B<14B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38003M6-XXXSP/FP/HP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program.
EPROM type
27256
27512
*=a$8000
*=a$0000
The pseudo-command
.BYTEa ‘M38003M6–’
.BYTEa ‘M38003M6–’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38003M6-XXXSP, 64P6N for M38003M6-XXXFP) and attach it to the mask ROM
confirmation form.
M38003M6-XXXHP is specified to the standard mark.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-46
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-30B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38004M8-XXXSP
M38004M8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38004M8–’
000F16
001016
807F16
808016
data
ROM 32638 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘4’ = 3416
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38004M8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
(1/2)
3800 GROUP USER’S MANUAL
3-47
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-30B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38004M8-XXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembiler source program.
EPROM type
27512
*=a$0000
The pseudo-command
.BYTEa ‘M38004M8–’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38004M8-XXXSP, 64P6N for M38004M8-XXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-48
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-23B<33A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38004M8DXXXSP
M38004M8DXXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38004M8D’
000F16
001016
807F16
808016
data
ROM 32638 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘0’ = 3016
‘4’ = 3416
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38004M8D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
‘M’ = 4D16
‘8’ = 3816
(1/2)
3800 GROUP USER’S MANUAL
3-49
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-23B<33A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38004M8DXXXSP/FP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembiler source program.
EPROM type
27512
*=a$0000
The pseudo-command
.BYTEa ‘M38004M8D’
Note :If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (64P4B for M38004M8DXXXSP, 64P6N for M38004M8DXXXFP) and attach it to the mask ROM
confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) In which operation mode will you use your microcomputer?
Single-chip mode
Memory expansion mode
Microprocessor mode
❈ 4. Comments
(2/2)
3800 GROUP USER’S MANUAL
3-50
APPENDIX
3.7 Mark specification form
3.7 Mark specification form
3800 GROUP USER’S MANUAL
3-51
APPENDIX
3.7 Mark specification form
3800 GROUP USER’S MANUAL
3-52
APPENDIX
3.8 Package outline
3.8 Package outline
2.5/1
2.5/1
3800 GROUP USER’S MANUAL
3-53
APPENDIX
3.8 Package outline
2.5/1
1.5/1
3800 GROUP USER’S MANUAL
3-54
APPENDIX
3.8 Package outline
1.5/1
3800 GROUP USER’S MANUAL
3-55
APPENDIX
3.9 Machine instructions
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
#
OP
69
# OP
2
#
n
# OP
65
#
2
OP
n
#
ADC
(Note 1)
(Note 5)
When T = 0
Adds the carry, accumulator and memory con-
tents. The results are entered into the
accumulator.
2
3
←
A
A + M + C
When T = 1
Adds the contents of the memory in the ad-
dress indicated by index register X, the
contents of the memory specified by the ad-
dressing mode and the carry. The results are
entered into the memory at the address indi-
cated by index register X.
←
M(X)
M(X) + M + C
AND
(Note 1)
When T = 0
“AND’s” the accumulator and memory con-
tents.
29
2
2
25
3
2
V
←
A
A
M
The results are entered into the accumulator.
“AND’s” the contents of the memory of the ad-
dress indicated by index register X and the
contents of the memory specified by the ad-
dressing mode. The results are entered into
the memory at the address indicated by index
register X.
When T = 1
V
←
M(X)
M(X)
M
7
0
ASL
Shifts the contents of accumulator or contents
of memory one bit to the left. The low order bit
of the accumulator or memory is cleared and
the high order bit is shifted into the carry flag.
0A
2
1
06
5
2
←
C
←
0
BBC
(Note 4)
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
Branches when the contents of the bit speci-
fied in the accumulator or memory is “0”.
13
+
4
2
2
17
+
5
5
3
3
2i
2i
BBS
(Note 4)
Branches when the contents of the bit speci-
fied in the accumulator or memory is “1”.
03
+
4
07
+
2i
2i
BCC
(Note 4)
Branches when the contents of carry flag is
“0”.
BCS
(Note 4)
C = 1?
Branches when the contents of carry flag is
“1”.
BEQ
(Note 4)
Z = 1?
V
Branches when the contents of zero flag is “1”.
BIT
A
M
“AND’s” the contents of accumulator and
memory. The results are not entered any-
where.
24
3
2
BMI
(Note 4)
N = 1?
Z = 0?
N = 0?
Branches when the contents of negative flag is
“1”.
BNE
(Note 4)
Branches when the contents of zero flag is “0”.
BPL
(Note 4)
Branches when the contents of negative flag is
“0”.
←
BRA
BRK
PC
PC ± offset
Jumps to address specified by adding offset to
the program counter.
←
B
1
Executes a software interrupt.
00
7
1
←
PCH
S – 1
M(S)
←
S
←
PCL
S – 1
M(S)
←
S
←
PS
S – 1
M(S)
←
S
←
←
PCL
PCH
ADL
ADH
3800 GROUP USER’S MANUAL
3-56
APPENDIX
3.9 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
OP
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
n
4
#
2
n
# OP
6D
n
4
#
3
n
#
OP
79
n
#
3
OP
#
n
#
OP
61
n
6
#
2
OP
71
n
6
#
2
OP
#
OP
#
N
N
V
V
75
35
16
7D
3D
1E
5
3
3
3
5
•
4
2
2D
4
3
5
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
6
2
0E
6
3
7
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
2
2
2
2
2
2
•
•
•
2C
4
3
M7 M6
Z
30
D0
10
80
2
2
2
4
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
3800 GROUP USER’S MANUAL
3-57
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
OP
# OP
#
n
# OP
#
BVC
(Note 4)
V = 0?
Branches when the contents of overflow flag is
“0”.
BVS
(Note 4)
V = 1?
Branches when the contents of overflow flag is
“1”.
←
CLB
CLC
CLD
CLI
Ab or Mb
0
Clears the contents of the bit specified in the
accumulator or memory to “0”.
1B
+
2
1
1F
+
5
2
2i
2i
←
←
C
D
0
0
Clears the contents of the carry flag to “0”.
18
2
2
2
2
2
1
1
1
1
1
Clears the contents of decimal mode flag to D8
“0”.
←
I
0
Clears the contents of interrupt disable flag to 58
“0”.
←
←
CLT
CLV
T
V
0
0
Clears the contents of index X mode flag to 12
“0”.
Clears the contents of overflow flag to “0”.
B8
CMP
(Note 3)
When T = 0
A – M
Compares the contents of accumulator and
memory.
C9
2
2
C5
3
2
When T = 1
M(X) – M
Compares the contents of the memory speci-
fied by the addressing mode with the contents
of the address indicated by index register X.
←
COM
CPX
CPY
DEC
DEX
DEY
DIV
M
M
Forms a one’s complement of the contents of
memory, and stores it into memory.
44
E4
C4
C6
5
3
3
5
2
2
2
2
X – M
Y – M
Compares the contents of index register X and
memory.
E0
C0
2
2
2
Compares the contents of index register Y and
memory.
2
←
←
A
M
A – 1 or
M – 1
Decrements the contents of the accumulator
or memory by 1.
1A
2
1
←
←
←
X
Y
A
X – 1
Decrements the contents of index register X CA
by 1.
2
2
1
1
Y – 1
Decrements the contents of index register Y 88
by 1.
(M(zz + X + 1),
Divides the 16-bit data that is the contents of
M (zz + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
M(zz + X)) / A
M(S)
of Remainder
←
←
1’s complememt
S
S – 1
EOR
(Note 1)
When T = 0
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the ac-
cumulator.
49
2
2
45
3
2
–
←
A
A V M
When T = 1
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indi-
cated by index register X. The results are
stored into the memory at the address indi-
cated by index register X.
–
M(X) V M
←
M(X)
←
←
INC
INX
INY
A
M
A + 1 or
M + 1
Increments the contents of accumulator or
memory by 1.
3A
2
1
E6
5
2
←
←
X
Y
X + 1
Y + 1
Increments the contents of index register X by E8
1.
2
2
1
1
Increments the contents of index register Y by C8
1.
3800 GROUP USER’S MANUAL
3-58
APPENDIX
3.9 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
OP
ABS, Y
OP #
IND
n
ZP, IND
OP
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
N
•
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
# OP
#
n
#
n
OP
#
n
#
OP
50
#
2
OP
#
2
•
70
2
2
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
•
D5
4
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
N
2
Z
C
N
N
N
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
Z
•
•
C
C
•
EC
CC
CE
4
4
6
3
3
3
D6
6
DE
7
3
2
•
•
E2 16
2
2
•
55
4
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
N
•
•
•
•
•
Z
•
F6
6
EE
6
3
FE
7
3
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
•
•
•
2
3800 GROUP USER’S MANUAL
3-59
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
JMP
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
OP
# OP
#
n
# OP
#
n
If addressing mode is ABS
Jumps to the specified address.
←
←
PCL
PCH
ADL
ADH
If addressing mode is IND
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
PCH
S – 1
JSR
M(S)
After storing contents of program counter in
stack, and jumps to the specified address.
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
if addressing mode is ABS,
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
LDA
When T = 0
Load accumulator with contents of memory.
A9
2
2
A5
3
2
←
(Note 2)
A
M
When T = 1
Load memory indicated by index register X
with contents of memory specified by the ad-
dressing mode.
←
M(X)
M
←
←
←
7
LDM
LDX
LDY
LSR
M
X
Y
nn
Load memory with immediate value.
3C
A6
A4
46
4
3
3
5
3
2
2
2
M
Load index register
memory.
X
Y
with contents of
with contents of
A2
A0
2
2
2
M
Load index register
memory.
2
0
→
Shift the contents of accumulator or memory
to the right by one bit.
4A
2
1
→
0
C
The low order bit of accumulator or memory is
stored in carry, 7th bit is cleared.
←
S – 1
MUL
NOP
M(S) · A
A ✕ M(zz + X)
Multiplies the accumulator with the contents of
memory specified by the zero page X address-
ing mode and stores the high byte of the result
on the stack and the low byte in the accumula-
tor.
←
S
←
PC
PC + 1
No operation.
EA
2
1
ORA
(Note 1)
When T = 0
“Logical OR’s” the contents of memory and ac-
cumulator. The result is stored in the
accumulator.
09
2
2
05
3
2
←
A
A V M
When T = 1
“Logical OR’s” the contents of memory indi-
cated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
←
M(X)
M(X) V M
3800 GROUP USER’S MANUAL
3-60
APPENDIX
3.9 Machine instructions
Addressing mode
Processor status register
ZP, X
OP n
ZP, Y
OP n
ABS
ABS, X
OP
ABS, Y
IND
n
ZP, IND
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
N
•
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
#
# OP
4C
n
3
#
3
n
#
OP
n
#
OP
6C
#
3
OP
B2
n
4
#
2
OP
#
OP
#
5
•
20
6
3
•
•
•
•
•
•
•
•
02
7
2
22
5
2
B5
4
2
AD
4
3
A1
N
•
•
•
•
•
Z
•
BD 5
3
B9
5
3
6
2
B1
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
B6
4
2
AE
AC
4E
4
4
6
3
3
3
BE
5
3
N
N
0
Z
Z
Z
B4
56
4
6
2
2
•
BC 5
3
3
5E
7
C
62 15
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
15
4
2
0D
4
01
N
Z
3
1D
5
3
19
5
3
6
2
11
6
2
3800 GROUP USER’S MANUAL
3-61
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
PHA
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
1
OP
# OP
#
n
# OP
#
←
M(S)
A
Saves the contents of the accumulator in 48
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
3
←
S
S – 1
←
S – 1
PHP
PLA
PLP
ROL
ROR
M(S)
PS
Saves the contents of the processor status 08
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
3
4
4
1
1
1
←
S
←
←
S
A
S + 1
M(S)
Increments the contents of the stack pointer 68
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
←
S
S + 1
Increments the contents of stack pointer by 1 28
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
←
PS
M(S)
7
←
0
Shifts the contents of the memory or accumu-
lator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
←
←
C
Shifts the contents of the memory or accumu-
lator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag is
shifted into the high order bit.
7
0
→
→
C
RRF
RTI
7
→
0
→
Rotates the contents of memory to the right by
4 bits.
←
S
S + 1
M(S)
S + 1
Returns from an interrupt routine to the main 40
routine.
6
6
1
1
←
PS
←
S
←
PCL
M(S)
S + 1
M(S)
←
S
←
PCH
←
RTS
S
S + 1
←
M(S)
S + 1
Returns from a subroutine to the main routine. 60
PCL
←
S
←
PCH
M(S)
SBC
(Note 1)
(Note 5)
When T = 0
Subtracts the contents of memory and
complement of carry flag from the contents of
accumulator. The results are stored into the
accumulator.
E9
2
2
E5
3
2
←
A
A – M – C
When T = 1
←
M(X)
M(X) – M – C
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the ad-
dress indicated by index register X. The
results are stored into the memory of the ad-
dress indicated by index register X.
←
SEB
SEC
SED
SEI
Ab or Mb
1
Sets the specified bit in the accumulator or
memory to “1”.
0B
+
2
1
0F
+
5
2
2i
2i
←
←
C
D
1
1
Sets the contents of the carry flag to “1”.
38
2
2
2
2
1
1
1
1
Sets the contents of the decimal mode flag to F8
“1”.
←
I
1
Sets the contents of the interrupt disable flag 78
to “1”.
←
SET
T
1
Sets the contents of the index X mode flag to 32
“1”.
3800 GROUP USER’S MANUAL
3-62
APPENDIX
3.9 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
OP
ABS, Y
OP #
IND
n
ZP, IND
OP
IND, X
OP n #
IND, Y
OP n #
REL
n
SP
n
7
N
•
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
# OP
#
n
#
n
OP
#
n
#
OP
#
OP
#
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
(Value saved in stack)
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
3
3
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
7
(Value saved in stack)
•
•
•
•
•
•
•
•
•
•
•
•
F5
4
2
ED
4
3
FD
5
3
F9
5
3
E1
6
2
F1
6
2
N
V
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
1
•
•
•
1
•
•
1
•
•
3800 GROUP USER’S MANUAL
3-63
APPENDIX
3.9 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
42
#
1
OP
# OP
#
n
# OP
85
#
2
n
←
STA
STP
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
A
Stores the contents of accumulator in memory.
Stops the oscillator.
4
2
←
←
←
←
M
M
X
X
Y
Stores the contents of index register X in
memory.
86
84
4
4
2
2
Stores the contents of index register Y in
memory.
A
Transfers the contents of the accumulator to AA
index register X.
2
2
1
1
Y
A
Transfers the contents of the accumulator to A8
index register Y.
M = 0?
Tests whether the contents of memory are “0”
or not.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
Transfers the contents of the stack pointer to BA
index register X.
2
2
2
2
2
1
1
1
1
1
Transfers the contents of index register X to 8A
the accumulator.
Transfers the contents of index register X to 9A
the stack pointer.
Transfers the contents of index register Y to 98
the accumulator.
Stops the internal clock.
C2
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
3800 GROUP USER’S MANUAL
3-64
APPENDIX
3.9 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
ABS, X
OP
9D
ABS, Y
IND
n
ZP, IND
OP
IND, X
OP
81
IND, Y
OP
91
REL
n
SP
n
7
N
•
6
V
•
5
T
•
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
95
n
5
#
2
# OP
8D
n
5
#
3
n
#
OP
99
n
#
3
OP
#
n
#
n
#
2
n
#
2
OP
#
OP
#
6
3
6
7
7
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
96
5
2
8E
8C
5
5
3
3
•
•
94
5
2
•
•
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
N
•
Z
•
Symbol
Contents
Symbol
Contents
IMP
Implied addressing mode
+
Addition
IMM
A
Immediate addressing mode
Accumulator or Accumulator addressing mode
–
Subtraction
Logical OR
Logical AND
V
V
–
V
–
BIT, A
Accumulator bit relative addressing mode
Logical exclusive OR
Negation
ZP
BIT, ZP
Zero page addressing mode
Zero page bit relative addressing mode
←
X
Shows direction of data flow
Index register X
Y
Index register Y
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
PC
PS
PCH
PCL
ADH
ADL
FF
nn
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
M
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
M(X)
M(S)
Memory of address indicated by contents of stack
Z
Zero flag
pointer
I
D
B
Interrupt disable flag
Decimal mode flag
Break flag
M(ADH, ADL)
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
T
V
N
X-modified arithmetic mode flag
Overflow flag
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Ab
Mb
OP
n
#
Number of bytes
3800 GROUP USER’S MANUAL
3-65
APPENDIX
3.10 List of instruction codes
3.10 List of instruction codes
D3 – D0
0001
0010
0011
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
0000
0
Hexadecimal
notation
1
2
3
D7 – D4
0000
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
ZP
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
CLB
2, A
EOR
LSR
CLB
—
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
SEI
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
ADC
ABS, Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
DEY
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
STX
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X ZP, Y 4, ZP
LDA
LDX
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDY
LDA
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, X ZP, X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
BBC
6, A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SBC
DIV
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X ZP, X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
3-byte instruction
2-byte instruction
1-byte instruction
3800 GROUP USER’S MANUAL
3-66
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016 Port P0 (P0)
002016 Prescaler 12 (PRE12)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
002116 Timer 1 (T1)
002216 Timer 2 (T2)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
002316 Timer XY mode register (TM)
002416 Prescaler X (PREX)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
002516 Timer X (TX)
002616 Prescaler Y (PREY)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
002716 Timer Y (TY)
002816
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
002916
002A16
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
002B16
002C16
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
002D16
002E16
000F16 Port P7 direction register (P7D)
001016
002F16
003016
001116
003116
001216
003216
001316
003316
001416
003416
001516
003516
001616
003616
001716
003716
001816 Transmit/Receive buffer register (TB/RB)
001916 Serial I/O status register (SIOSTS)
001A16 Serial I/O control register (SIOCON)
001B16 UART control register (UARTCON)
001C16 Baud rate generator (BRG)
001D16
003816
003916
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001E16
001F16
3800 GROUP USER’S MANUAL
3-67
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P3
P3
P3 /SYNC
P3 /φ
/RESETOUT
P3 /ONW
7
/RD
P2
P2
0
/DB
/DB
0
1
1
6/WR
P2
2/DB
2
5
P2
P2
P2
3
4
5
/DB
/DB
/DB
3
4
5
4
P3
3
2
P2
6
/DB
6
P3
P3
1
P2
7
/DB
7
0
M38002M4-XXXFP
M38003M6-XXXHP
V
X
X
SS
VCC
OUT
IN
P7
P7
P6
P6
P6
P6
P6
1
0
7
6
5
4
3
P4
P4
0
1
RESET
CNVSS
P4
2
/INT
0
Package type : 64P6N-A/64P6D-A
64-pin plastic-molded QFP
3800 GROUP USER’S MANUAL
3-68
APPENDIX
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P71
P30
2
P31
3
P70
P32/ONW
4
P67
P33/RESETOUT
P34/φ
5
P66
6
P65
P35/SYNC
P36/WR
P37/RD
7
P64
8
P63
9
P62
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/AD8
P11/AD9
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P61
P60
P57
P56
P55/CNTR1
P54/CNTR0
P53/INT5
P52/INT4
P51/INT3
P50/INT2
P47/SRDY
P46/SCLK
P45/TXD
P44/RXD
P43/INT1
P42/INT0
CNVSS
RESET
P41
P40
XIN
XOUT
VSS
Package type : 64P4B
64-pin shrink plastic-molded DIP
3800 GROUP USER’S MANUAL
3-69
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3800Group
Mar. First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
3800 Group
MITSUBISHI ELECTRIC CORPORATION
HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO
H-EE418-A KI-9603 Printed in Japan (ROD)
© 1996 MITSUBISHI ELECTRIC CORPORATION
New publication, effective Mar. 1996.
Specifications subject to change without notice.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明