M38749M8F-XXXGP [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38749M8F-XXXGP |
| 厂家： | 
Mitsubishi Group |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总92页 (文件大小：1282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●Serial I/O3 ...................................................................... 8-bit ✕ 1
(Clock-synchronized automatic data transfer/arbitrary bit trans-
fer function available)
DESCRIPTION
The 3874 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3874 group includes data link layer communication control cir-
cuit, A-D converters, D-A converter, automatic data transfer serial
I/O, UART, and watchdog timer etc.
●A-D converter ................................................. 8-bit ✕ 8 channels
●D-A converter ................................................... 8-bit ✕ 1 channel
●Data link layer communication control circuit ............................ 1
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Watchdog timer ............................................................ 20-bit ✕ 1
●Power source voltage ................................................ 3.0 to 5.5 V
●Power dissipation
The various microcomputers in the 3874 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3874 group, re-
fer to the section on group expansion.
FEATURES
In double-speed mode ......................................................90 mW
In high-speed mode ..........................................................60 mW
(at 32 kHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .......................................................... 180 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range.................................... –40 to 85°C
(Extended operating temperature version and automotive ver-
sion)
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time................................. 0.32 µs
(at 6.4 MHz oscillation frequency, in double-speed mode)
●Memory size
ROM ............................................................... 16 K to 60 K bytes
RAM ............................................................... 1024 to 2048 bytes
●Programmable input/output ports ............................................ 72
●Input port .................................................................................... 1
●Interrupts ................................................. 27 sources, 16 vectors
(Interrupt source discrimination register exists, included key in-
put interrupt)
APPLICATION
Automotive comfort control for audio system, air conditioning etc.,
automotive body electronics control, household appliances, and
other consumer applications, etc.
●Timer 1, timer 2, timer 3 ................................................. 8-bit ✕ 3
●Timer X, timer Y............................................................ 16-bit ✕ 2
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
40
61
P1
P1
6
7
P3
1
62
63
64
65
66
67
68
69
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P30
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/KW
/KW
/KW
/KW
/KW
/KW
/KW
/KW
0
1
2
3
4
5
6
7
P8
P8
P8
P8
P8
7
/SSTB3
/SBUSY3
/SRDY3
/SCLK3
/SIN3
/SOUT3
6
5
4
3
P82
P81
P8
0
/DA
70
71
72
73
74
75
76
77
78
79
80
M38747MCT-XXXGP
VCC
V
X
X
SS
V
REF
OUT
IN
AVSS
P6
7
6
5
4
3
/AN
/AN
/AN
/AN
/AN
7
6
5
4
3
P4
0
/XCOUT
/XCIN
P6
P6
P6
P6
P4
RESET
P9 /INT
P4 /INT
P4 /INT
P4 /R
1
7
0
2
1
P62
/AN
/AN
2
1
3
2
P61
4
XD
Package type : 80P6S-A
Fig. 1 M38747MCT-XXXGP pin configuration
2
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
P87/SSTB3
P20/KW0
P21/KW1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P86/SBUSY3
P85/SRDY3
P84/SCLK3
P83/SIN3
P82/SOUT3
P81
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
P27/KW7
P80/DA
VCC
VREF
VSS
XOUT
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
XIN
P40/XCOUT
P41/XCIN
RESET
P97/INT0
P63/AN3
P42/INT1
Package type : 80D0
Fig. 2 M38749EFFS pin configuration
3
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram
4
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Functions
Pin
Name
Function except a port function
VCC, VSS
VREF
Power source input
•Apply voltage of 3.0 V – 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
Reference voltage input
Analog power source
input
AVSS
RESET
XIN
•Reset input pin for active “L.”
Reset input
•Input and output pins for the clock generating circuit.
Clock input
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
•Feedback resistor is built in between XIN pin and XOUT pin.
•8-bit CMOS I/O port.
P00–P07
P10–P17
P20–P27
P30–P37
I/O port P0
I/O port P1
I/O port P2
I/O port P3
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•Sub-clock generating circuit I/O
pins connect a resonator.
(This circuit cannot be operated by
an external clock.)
P40/XCOUT,
P41/XCIN
•CMOS 3-state output structure.
•Interrupt input pins
P42/INT1,
P43/INT2
I/O port P4
P44/RXD,
P45/TXD,
•Serial I/O1 function pins
P46/SCLK1,
P47/SRDY1
P50/TOUT
•Timer 2 output pin
•Interrupt input pins
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
P51/INT3–
P53/INT5
•CMOS 3-state output structure.
I/O port P5
•Timer X, timer Y function pins
•Real time port function pins
P5
P5
4
5
/CNTR
/CNTR
0,
1
P56/RTP0,
P57/RTP1
5
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Functions
Pin
Name
Function except a port function
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•A-D converter input pins
P60/AN0–
P67/AN7
I/O port P6
•CMOS 3-state output structure.
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•Serial I/O2 function pins
P70/SIN2,
P71/SOUT2,
P72/SCLK2
•CMOS 3-state output structure.
P73, P74
I/O port P7
P7
5
/BUSOUT
,
•Data link layer communication con-
trol pins
P76/BUSIN
P77/ADT
P80/DA
P81
•A-D trigger input pin
•8-bit I/O port with the same function as port P0.
•D-A converter output pin
P82/SOUT3,
P83/SIN3,
P84/SCLK3,
P85/SRDY3
•Serial I/O3 function pins
•Interrupt input pin
I/O port P8
P86/SBUSY3,
P87/SSTB3
•1-bit input port.
Input port P9
P97/INT0
•CMOS compatible input level.
6
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
M3874
7
M
C T- XXX GP
Product
Package type
GP : 80P6S-A
FS : 80D0
ROM number
Omitted in some types.
D– : Extended operating temperature version
F– : Extended operating speed version of “D–”
T– : Automotive version
ROM/PROM size
4: 16384 bytes
5: 20480 bytes
6: 24576 bytes
7: 28672 bytes
8: 32768 bytes
9: 36864 bytes
: 40960 bytes
A
: 45056 bytes
B
: 49152 bytes
C
: 53248 bytes
D
: 57344 bytes
E
: 61440 bytes
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
E
: Mask ROM version
: EPROM or One Time PROM version
RAM size
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Fig. 4 Part numbering
7
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3874 group main clock input oscillation frequency in double-speed mode
• Mask ROM version
• EPROM or One time PROM version
6.4 MHz
5 MHz
6.4 MHz
4.0 V 4.5 V
5.5 V
4.0 V
5.5 V
Power source voltage VCC (V)
Power source voltage VCC (V)
In low-speed mode, middle-speed mode, and high-speed mode, characteristic of main clock input oscillation frequency
guarantee limit is not different.
Fig. 5 Main clock input oscillation frequency in double-speed mode
8
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (Extended operating
temperature version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
The 3874 group (extended operating temperature version) is de-
signed for automotive comfort and amusement control such as
audio, air-conditioner etc., household appliances, and other con-
sumer applications.
Memory Size
ROM/PROM size ............................................... 48 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
Mitsubishi plans to expand the 3874 group (extended operating
temperature version) as follows:
Packages
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan of 3874 group (Extended operating temperature version)
Mass product
ROM size (bytes)
M38749MFF/EFD
60K
56K
52K
48K
44K
40K
36K
32K
28K
24K
Mass product
M38747MCF
20K
16K
1024
1536
2048
RAM size (byte)
Products under development or planning : the development schedule and specification may be revised without notice.
Planning products may be stopped during the development.
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently planning products are listed below.
As of March 1998
Table 3 Support products
(P) ROM size (bytes)
Product name
RAM size (bytes)
2048
Package
Remarks
ROM size for User in (
)
80P6S-A
80D0
One Time PROM version (blank)
M38749EFDGP
M38749EFFS
M38749MFF
M38747MCF
EPROM version (for software development, operat-
ing temperature = –20 to 85°C)
61440
(61310)
80P6S-A
Mask ROM version
49152
(49022)
1024
9
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (Automotive version)
The 3874 group (automotive version) is designed for automotive
body electronics control.
ROM/PROM size ............................................... 16 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
Mitsubishi plans to expand the 3874 group (automotive version)
as follows:
Packages
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM and One Time PROM versions
Memory Size
Memory Expansion Plan of 3874 group (Automotive version)
ROM size (byte)
60K
Mass product
M38749EFT
*Supported only PROM version
56K
shipped after writing
52K
Mass product
48K
44K
40K
36K
32K
28K
24K
M38747MCT
Mass product
M38747M6T
20K
16K
Mass product
M38747M4T
1024
1536
2048
RAM size (byte)
Products under development or planning : the development schedule and specification may be revised without notice.
Planning products may be stopped during the development.
Fig. 7 Memory expansion plan (Automotive correspondence version)
Currently planning products are listed below.
Table 4 Support products
As of March 1998
(P) ROM size (bytes)
Product name
RAM size (bytes)
2048
Package
80P6S-A
Remarks
One Time PROM version
ROM size for User in (
)
M38749EFT
M38747MCT
M38747M6T
M38747M4T
61440 (61310)
49152 (49022)
24576 (24446)
16384 (16254)
Mask ROM version
1048
10
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3874 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
:
:
:
Not available
Stack page selection bit
0
1
: Page 0
: Page 1
XCOUT drivability selection bit
0
1
: Low drive
: High drive
Port XC switch bit
0 : I/O port function
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
: φ = f(XIN)/2 (high-speed mode)
: φ = f(XIN)/8 (middle-speed mode)
: φ = f(XCIN)/2 (low-speed mode)
: φ = f(XIN) (double-speed mode)
Note: When setting b7 to b3, refer to notes of Figure 71.
Fig. 8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
000016
SFR area
043F16
063F16
083F16
1024
1536
2048
Zero page
004016
010016
RAM
Serial I/O3
automatic transfer
RAM area
020016
030016
XXXX16
Not used
YYYY16
ZZZZ16
ROM area
Reserved ROM area
(128 bytes)
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 9 Memory map diagram
12
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
Timer X (low-order) (TXL)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
002016
002116
002216
002316
002416
002516
002616
002716
Port P0 direction register (P0D)
Port P1 (P1)
Timer X (high-order) (TXH)
Timer Y (low-order) (TYL)
Timer Y (high-order) (TYH)
Timer 1 (T1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 2 (T2)
Timer 3 (T3)
Port P3 direction register (P3D)
Port P4 (P4)
Timer X mode register (TXM)
002816 Timer Y mode register (TYM)
Port P4 direction register (P4D)
Port P5 (P5)
002916 Timer 123 mode register (T123M)
002A16 Communication mode register (BUSM)
002B16 Transmit control register (TXDCON)
002C16 Transmit status register (TXDSTS)
002D16 Receive control register (RXDCON)
002E16 Receive status register (RXDSTS)
002F16 Bus interrupt source discrimination control register (BICOND)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Control field selection register (CFSEL)
003016
001116 Port P8 direction register (P8D)
001216 Port P9 (P9)
003116 Control field register (CF)
003216 Transmit/Receive FIFO (TRFIFO)
003316 PULL UP register (PULLU)
001316
Serial I/O3 register/Transfer counter (SIO3)
A-D control register (ADCON)
001416 Serial I/O3 control register 1 (SIO3CON1)
001516 Serial I/O3 control register 2 (SIO3CON2)
001616 Serial I/O3 control register 3 (SIO3CON3)
001716 Serial I/O3 automatic transfer data pointer (SIO3DP)
003416
003516
003616
003716
003816
A-D/D-A conversion register (AD)
Interrupt source discrimination register 2 (IREQD2)
Interrupt source discrimination control register 2 (ICOND2)
Interrupt source discrimination register 1 (IREQD1)
Transmit/Receive buffer register (TB/RB)
001816
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
001916
001A16
001B16
001C16
001D16
003916 Interrupt source discrimination control register 1 (ICOND1)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
003A16
003B16
003C16
003D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Serial I/O2 control register (SIO2CON)
001E16 Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
001F16
Fig. 10 Memory map of special function register (SFR)
13
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
The I/O ports P0–P8 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
Table 5 I/O port function (1)
Pin
Name
Port P0
Input/Output
Related SFRs
Ref.No.
(1)
I/O Structure
Non-Port Function
Input/output,
individual bits
P00–P07
•CMOS compatible
input level
•CMOS 3-state output
P10–P17
P20–P27
P30–P37
Port P1
Port P2
Input/output,
individual bits
•CMOS compatible
input level
•CMOS 3-state output
Input/output,
individual bits
•CMOS compatible
input level
•CMOS 3-state output
•Key input (key-on
wake-up) interrupt in-
put
•PULL UP register
•CPU mode register
(2)
(1)
Input/output,
individual bits
•CMOS compatible
input level
•CMOS 3-state output
Port P3
Port P4
P40/XCOUT
P41/XCIN
(3)
(4)
Input/output,
individual bits
•CMOS compatible
input level
•Sub-clock generating •CPU mode register
circuit I/O
•CMOS 3-state output
P42/INT1,
P43/INT2
•External interrupt input •Interrupt edge selection
register
(5)
•Serial I/O1 control reg-
ister
•Serial I/O1 status regis-
ter
(6)
(7)
(8)
P44/RXD
P45/TXD
P46/SCLK1
•Serial I/O1 function I/O
•UART control register
•PULL UP register
P47/SRDY1
P50/TOUT
(9)
•Timer 2 output
•Timer 123 mode regis-
ter
Port P5
Input/output,
individual bits
•CMOS compatible
input level
(10)
•CMOS 3-state output
•External interrupt input •Interrupt edge selection
register
P51/INT3,
P52/INT4,
P53/INT5
(5)
•Timer X function I/O
•Timer Y function I/O
•Timer X mode register
(11)
(12)
P54/CNTR0
P55/CNTR1
P56/RTP0
•Timer Y mode register
•Timer X mode register
•Real time port function
output
(13)
•Timer Y mode register
•A-D control register
•Real time port function
output
•A-D converter input
P57/RTP1
P60/AN0–
P67/AN7
Input/output,
individual bits
•CMOS compatible
input level
Port P6
(14)
•CMOS 3-state output
14
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 I/O port function (2)
Name
Port P7
Related SFRs
•CMOS compatible •Serial I/O2 function I/O •Serial I/O2 control reg-
Pin
Input/Output
I/O Function
Non-Port Function
Ref.No.
P70/SIN2
Input/output,
individual bits
(15)
(16)
(17)
input level
ister
P71/SOUT2
P72/SCLK2
•CMOS 3-state output
•PULL UP register
P73,P74
(1)
P75/BUSOUT
P76/BUSIN
•Data link layer commu- •Communication mode
(18)
(19)
nication control I/O
register
•Transmit control regis-
ter
•Transmit status register
•Receive control regiser
•Receive status register
•Bus interrupt source
discrimination control
register
•Control field selection
register
•Control field register
•Transmit/Receive FIFO
•A-D trigger input
(20)
P77/ADT
P80/DA
•A-D control register
•A-D control register
Port P8
Input/output,
individual bits
•CMOS compatible in- •D-A function output
put level
(21)
(1)
P81
•CMOS 3-state output
•Serial I/O3 function I/O
(22)
(23)
(24)
P82/SOUT3
P83/SIN3
P84/SCLK3
P85/SRDY3
P86/SBUSY3
•Serial I/O3 register/
Transfer counter
•Serial I/O3 control reg-
ister 1
(25)
(26)
•Serial I/O3 control reg-
ister 2
•Serial I/O3 control reg-
ister 3
P87/SSTB3
(27)
•Serial I/O3 automatic
transfer data pointer
Input
P97/INT0
Port P9
•CMOS compatible •External interrupt input •Interrupt edge selection
input level register
(28)
Note: Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
15
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pull-up Control
P20–P26, TXD, SCLK1, SOUT2, and SCLK2 can perform pull-up con-
trol by setting “1” to the pull-up register (address 003316).
P20–P27’s pull-up is valid in the input mode, and TXD, SCLK1,
SOUT2, and SCLK2s’ pull-up is valid in the output mode.
b7
b0
Pull-up register
(PULLU : address 0033 16)
P26, P27 pull-up
P25 pull-up
P22–P24 pull-up
P20, P21 pull-up
0: No pull-up
1: Pull-up
TXD, SCLK1 pull-up
SOUT2, SCLK2 pull-up
Not used (returns “0” when read)
(Do not write “1” to these bits.)
Fig.11 Structure of Pull-up Register
16
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0,P1,P3,P73,P74,P81
(2) Port P2
P2 pull-up
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Key input interrupt input
(3) Port P4
0
(4) Port P41
Port X
C
switch bit
Port XC switch bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator
Port P4
Port X
1
Sub-clock generating circuit input
C
switch bit
(6) Port P4
4
(5) Ports P42,P43,P51,P52,P53
Serial I/O1 enable bit
Receive enable bit
Direction register
Port latch
Direction register
Data bus
Data bus
Port latch
Serial I/O1 input
INT1–INT5 interrupt input
Fig. 12 Port block diagram (1)
17
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Port P4
5
(8) Port P46
S
CLK1 pull-up
Serial I/O1 synchronous
clock selection bit
TXD pull-up
Serial I/O1 enable bit
P4
5
/T
XD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction register
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction register
Data bus
Port latch
Port latch
Data bus
Serial I/O1 output
Serial I/O1 clock output
Serial I/O1 clock input
(9) Port P4
7
(10) Port P5
0
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 ready output
TOUT output control bit
Timer output
(11) Port P5
4
(12) Port P5
5
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
Pulse output mode
Timer output
CNTR1 interrupt input
Event count input
Reload input
CNTR
Event count input
Pulse width measurement gate input
0 interrupt input
Fig. 13 Port block diagram (2)
18
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(14) Port P6
(13) Ports P56, P5
7
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
Real time port control bit
Data for real time port
A-D converter input
Analog input pin selection bit
(15) Port P7
0
Direction register
Port latch
Data bus
Serial I/O2 input
(16) Port P7
1
S
OUT2 output signal in operating
S
OUT2 pull-up
S
CLK2 pin selection bit
OUT2 output control bit
P-channel output
disable bit
S
S
OUT2 pin selection bit
Direction register
Data bus
Port latch
Serial I/O2 output
Fig. 14 Port block diagram (3)
19
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P72
SCLK2 pull-up
P71/SOUT2 • P72/SCLK2
P-channel output disable bit
SCLK2 pin selection bit
Direction register
Data bus
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
(18) Port P75
(19) Port P76
Data link layer communication
control circuit valid signal
(output from sub-CPU)
Data link layer communication
control circuit valid signal
(output from sub-CPU)
Direction register
Port latch
Direction register
Data bus
Data bus
Port latch
Data link layer communication control
circuit transmit output
Data link layer communication control circuit
receive input
(21) Port P80
(20) Port P77
Direction register
Port latch
Direction register
Data bus
Data bus
Port latch
D-A converter output
ADT interrupt input
D-A ON
When the direction register is “0,” the schmidt
input pin is connected to port.
Fig. 15 Port block diagram (4)
20
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(22) Port P82
(23) Port P83
P82/SOUT3 • P84/SCLK3
P-channel output disable bit
Transfer mode selection bit
Serial transfer selection bit
Serial I/O disabled
SOUT3 output control bit
Serial transfer selection bit
Serial I/O disabled
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O3 input
Serial I/O3 output
(25) Port P85
(24) Port P84
P85/SRDY3 • P86/SBUSY3 pin control bit
SRDY3 output
P82/SOUT3 • P84/SCLK3
P-channel output disable bit
Serial I/O3 synchronous
clock selection bit
Internal synchronous clock
P85/SRDY3 • P86/SBUSY3 pin control bit
SRDY3 input
Serial transfer selection bit
Serial I/O disabled
Serial transfer selection bit
Serial I/O disabled
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O3 clock output
Serial I/O3 ready output
Serial I/O3 clock input
Serial I/O3 ready input
(26) Port P86
(27) Port P87
P85/SRDY3 • P86/SBUSY3 pin control bit
SBUSY3 output
P85/SRDY3 • P86/SBUSY3 pin control bit
SBUSY3 input
Serial transfer selection bit
Serial I/O disabled
Serial I/O3 synchronous clock selection bit
SSTB3,SSTB3 output
Serial I/O disabled
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O3 busy output
Serial I/O3 busy input
Fig. 16 Port block diagram (5)
21
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(28) Port P97
Data bus
INT0 interrupt input
Fig. 17 Port block diagram (6)
22
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt Factor Determination
INTERRUPTS
The interrupt request bit for each vector of “multiple factors/one
vector interrupt” is set to “1” when the interrupt disable flag (I) is “0”
and one of the factor interrupt enable bits is “1” and the corre-
sponding factor interrupt request bit changes from “0” to “1”. At
this time, if the vector interrupt enable bit is “1”, the interrupt oc-
curs. (Note that the interrupt request bit for each vector and the
factor interrupt request bit are both edge sense.)
Interrupts occur by 27 sources: 10 external, 16 internal, and 1 soft-
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
When 2 or more interrupt requests of interrupt factors assigned to
one interrupt vector are generated at the same time, confirm the
interrupt request bits for each interrupt factor assigned to the vec-
tor, and process according to the priority.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
If the interrupt request bit for the interrupt factor is “1” and the in-
terrupt enable bits for interrupt factor and each vector are both “1”;
for example, when an interrupt of another interrupt factor assigned
to the same vector occurs while an interrupt processing routine is
executed, the interrupt occurs again after returning. Clear the in-
terrupt request bits which are not necessary or which have been
already processed before executing the interrupt flag clear (CLI)
or interrupt processing routine return (RTI) instruction.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
The interrupt control circuit consists of two types of interrupts: “one
factor/one vector interrupt” and “multiple factors/one vector inter-
rupt”. The configuration is shown in Figure 18.
The interrupt request bits for each interrupt factor are not cleared
by hardware after an interrupt vector address branching. Clear
these bits by software in the interrupt processing routine. Use the
LDM, STA, etc. instructions to do it. Do not use the read- modify-
write instruction; for example, the CLB.
Interrupt Operation
When an interrupt occurs, the following operations are automati-
cally performed:
1. The contents of the program counter and the processor status
register are pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit for each vector is cleared. (The corresponding inter-
rupt request bit for each interrupt factor is not cleared.)
3. The interrupt jump destination address of interrupt which has
the highest priority is loaded to the program counter.
■ Notes
When the active edge of an external interrupt (INT0–INT5, CNTR0,
CNTR1) is set, the corresponding interrupt request bit may also be
set. Therefore, take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register (in
case of CNTR0: Timer X mode register; in case of CNTR1:
TimerY mode register).
(3) Clear the set interrupt request bit to “0”.
(4) Enable the external interrupt which is selected.
23
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Interrupt Sources
Priority
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or External interrupt
falling edge of INT0 input
(active edge selectable)
INT1
3
4
FFF916
FFF716
FFF816
FFF616
At detection of either rising or External interrupt
falling edge of INT1 input
(active edge selectable)
Receive bus
interrupt source 1
The condition which the receive
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
When receive bus interrupt
source 1 request bit becomes
“1” from “0”
When receive bus interrupt
source 2 request bit becomes
“1” from “0”
Receive bus
interrupt source 2
Receive bus
interrupt source 3
When receive bus interrupt
source 3 request bit becomes
“1” from “0”
5
FFF516
FFF416
The condition which the transmit
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
When transmit bus interrupt
source 1 request bit becomes
“1” from “0”
Transmit bus
interrupt source 1
When transmit bus interrupt
source 2 request bit becomes
“1” from “0”
Transmit bus
interrupt source 2
When transmit bus interrupt
source 3 request bit becomes
“1” from “0”
Transmit bus
interrupt source 3
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
Timer X
6
FFF316
FFF216
Timer Y
Timer 2
Timer 3
7
8
9
FFF116
FFEF16
FFED16
FFF016
FFEE16
FFEC16
INT2
10
FFEB16
FFEA16
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
Serial I/O3
interrupt
11
FFE916
FFE816
Valid only when serial I/O3 is
selected
At completion of serial I/O3 data
transmission/reception
CNTR0
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR0 input
CNTR1
12
FFE716
FFE616
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
Timer 1
INT3
13
14
FFE516
FFE316
FFE416
FFE216
At timer 1 underflow
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
INT5
ADT
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT5 input
Valid only when ADT interrupt is
selected
At falling of ADT pin input
15
FFE116
FFE016
External interrupt
(falling valid)
A-D converter
Valid only when A-D converter
interrupt is selected
At completion of A-D converter
Serial I/O2
interrupt
Valid only when serial I/O2 is
selected
At completion of serial I/O2 data
transmission/reception
Key input (key-
on wake-up)
16
17
FFDF16
FFDD16
FFDE16
FFDC16
At falling of port P20 to P25 (at External interrupt
input) input logical level AND
(falling valid)
Serial I/O1
receive
Valid only when serial I/O1 is
selected
At completion of serial I/O1 data
reception
Serial I/O1
transmit
Valid only when serial I/O1 is
selected
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
BRK instruction
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used.
24
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Multiple factors/one vector interrupt
Interrupt request bit for
interrupt factor
D
Q
Interrupt request of interrupt
factor: IDREQINYZ
Interrupt request bit for
each vector: IREQY
Interrupt request from
T
R
multiple factors: IDREQY
Clear instruction
by user program
D
Q
D
Q
Interrupt enable bit
for interrupt factor
D
T
Q
T
T
R
R
SYNC
R
Internal system
clock φ
Interrupt request get control
signal: IREQGET
STP Instruction
Clear instruction
by user program
Hardware clear signal by
occurrence of interrupt
Interrupt disable flag (I)
Clear instruction by
user program
Interrupt enable bit
for each vector
One factor/one vector interrupt
Interrupt request bit for
each vector: IREQX
D
Q
D
Q
Interrupt Request
IREQINX
T
R
T
R
Interrupt request get
control signal: IREQGET
Hardware clear signal by
occurrence of interrupt
Clear instruction by
user program
Interrupt enable bit
for each vector
Interrupt disable flag (I)
BRK Instruction
Interrupt occurrence
Reset
Fig.18 Interrupt control diagram
25
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing to Interrupt Request Acceptance
The cycle number of internal system clock required from occur-
rence to acceptance of an interrupt request depends on the type
of interrupt: “multiple factors/one vector” or “one factor/one vec-
tor”.
For “one factor/one vector interrupt”, the CPU starts processing
the management after interrupt acceptance at the next instruction
execution timing (rising edge of SYNC signal) immediately after
the interrupt request is generated. For “multiple factors/one vector
interrupt”, the CPU starts processing the management after inter-
rupt acceptance at the second instruction execution timing (rising
edge of SYNC signal) after the interrupt request for interrupt factor
determination is generated. In other words, “multiple factors/one
vector interrupt” required one instruction execution cycle number
(2 to 16 cycles of internal system clock) more than that of “one
factor/one vector interrupt” to begin the interrupt sequence.
Figure 18 shows the interrupt control diagram and Figure 19
shows the timing from occurrence to acceptance of
interrupt request.
For “one factor/one vector interrupt”, the interrupt request is gen-
erated at Timing (A) and the processing after acceptance begins
at Timing (B). For “multiple factors/one vector interrupt”, the inter-
rupt factor determination request is generated at Timing (C), the
interrupt request is generated at Timing (D), and the processing
after acceptance begins at Timing (E).
26
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal system clock φ
SYNC
Address bus
Data bus
S-1,SPS S-2,SPS
S,SPS
PC
PCL
Not used
PS
PC
H
Interrupt request signal input
IREQINx
Interrupt request signal
IREQx
IRGET
Management after
interrupt acceptance
(B)
(a) One factor/one vector interrupt
(A)
Internal system clock φ
SYNC
Address bus
Data bus
PC
Not used
Interrupt source determination
request signal input
IDREQIN
Y
Interrupt request signal from
interrupt source
IDREQ
Interrupt request signal
IREQ
Y
Y
IRGET
Management after
interrupt acceptance
(D)
(C)
2 to 16 cycles of φ
(b) Multiple factors/one vector interrupt
(E)
Fig.19 Timing from occurrence to acceptance of interrupt
27
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
INT
INT
0
active edge selection bit
1
2
3
4
5
active edge selection bit
active edge selection bit
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
b7
b0
b7 b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
INT
INT
0
interrupt request bit
interrupt request bit
INT2 interrupt request bit
1
CNTR
0
, serial I/O3 interrupt request bit
interrupt request bit
Receive bus interrupt request bit
Transmit bus interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
CNTR
1
Timer 1 interrupt request bit
INT , INT , INT interrupt request bit
3
4
5
ADT/A-D converter, serial I/O2 interrupt
request bit
Key input, serial I/O1 receive, serial
I/O1 transmit interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b7
b7
b0
b7
b7
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON1 : address 003E16
(ICON2 : address 003F16
)
)
INT interrupt enable bit
2
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
0
1
, serial I/O3 interrupt enable bit
interrupt enable bit
CNTR
Receive bus interrupt enable bit
Transmit bus interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 1 interrupt enable bit
INT , INT , INT interrupt enable bit
3
4
5
ADT/A-D converter, serial I/O2 interrupt
enable bit
Key input, serial I/O1 receive, serial
I/O1 transmit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
b0
b0
Interrupt source discrimination register 1
Interrupt source discrimination control register 1
(ICOND1 : address 003916)
(IREQD1 : address 003816
)
INT
INT
INT
3
4
5
interrupt request bit
interrupt request bit
interrupt request bit
INT
INT
INT
3
4
5
interrupt enable bit
interrupt enable bit
interrupt enable bit
Serial I/O1 receive interrupt
request bit
Serial I/O1 transmit interrupt
request bit
Key input interrupt request bit
Serial I/O2 interrupt request bit
ATD/A-D converter interrupt
request bit
Serial I/O1 receive interrupt enable
bit
Serial I/O1 transmit interrupt enable
bit
Key input interrupt enable bit
Serial I/O2 interrupt enable bit
ADT/A-D converter interrupt enable
bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupt disabled
1 : Interrupt enabled
b0
b0
Interrupt source discrimination control register 2
(ICOND2 : address 003716
Interrupt source discrimination register 2
)
(IREQD2 : address 003616
)
CNTR0 interrupt enable bit
Serial I/O3 interrupt enable bit
Not used (return “0” when read)
CNTR interrupt request bit
Serial I/O3 interrupt request bit
Not used (returns “0” when read)
0
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 20 Structure of interrupt-related registers
28
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
An example of using a key input interrupt is shown in Figure 21,
where an interrupt request is generated by pressing one of the
keys consisted as an active-low key matrix which inputs to ports
P20–P24.
Key Input Interrupt
A Key input interrupt request is generated by applying “L” level to
any pin of port P2 that have been set to input mode. In other
words, it is generated when AND of input level goes from “1” to “0”.
Port PXx
“L” level output
PULL UP register
Bit 0 = “0”
Port P2
direction register = “1”
7
Key input interrupt request
✽
✽
✽
✽
✽✽
Port P2
latch
7
6
5
4
P27
P26
P25
output
output
output
Port P2
direction register = “1”
6
✽✽
Port P2
latch
PULL UP register
Bit 1 = “0”
Port P2
direction register = “1”
5
✽✽
Port P2
latch
PULL UP register
Bit 2 = “1”
Port P2
direction register = “0”
4
✽✽
Port P2
latch
P24
P23
P22
P21
P20
input
input
input
input
input
Port P2
direction register = “0”
3
Port P2
Input reading circuit
✽
✽✽
✽✽
Port P2
latch
3
Port P2
direction register = “0”
2
✽
Port P2
latch
2
PULL UP register
Bit 3 = “1”
Port P2
direction register = “0”
1
✽
✽✽
Port P2
1
latch
Port P2
direction register = “0”
0
✽
✽✽
Port P2
latch
0
✽
P-channel transistor for pull-up
✽✽ CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P2 block diagram
29
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
responding to that timer is set to “1”.
The 3874 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first.The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
All timers are down count timers. When the timer reaches “0016” or
“000016”, an underflow occurs at the next count pulse and the cor-
responding timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Real time port
control bit “1”
Data bus
Q D
P56 data for real time port
P56/RTP0
Latch
P56 direction register “0”
P56 latch
Real time port
control bit “1”
Q D
P57 data for real time port
Real time port
P57/RTP1
Latch
P57 direction register “0”
control bit “0”
Timer X mode register
write signal
P57 latch
“1”
XIN/16
(XCIN/16 in φ = XCIN/2)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bit
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer X (high) (8)
“0”
Timer X
interrupt
P54/CNTR0
Timer X (low) (8)
“10”
“1”
Pulse width
measurement
mode
CNTR0 active
Pulse output mode
edge switch bit
“0”
“1”
S
Q
Q
T
P54 direction register
Pulse width HL continuously measurement mode
Rising edge detection
P54 latch
Pulse output mode
XIN/16
Period
measurement mode
Falling edge detection
(XCIN/16 in φ = XCIN/2)
Timer Y stop
control bit
Timer Y (low) latch (8)
CNTR1 active
edge switch bit
“0”
Timer Y (high) latch (8)
Timer Y (high) (8)
“00”,“01”,“11”
Timer Y
interrupt
P55/CNTR1
Timer Y (low) (8)
“10” Timer Y operating
mode bit
“1”
XIN/16
(XCIN/16 in φ = XCIN/2)
Timer 1
interrupt
Timer 1 count source
selection bit
“0”
Timer 2 write
control bit
Timer 2 count source
selection bit
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
“0”
Timer 2
interrupt
XCIN
Timer 2 (8)
“1”
“1”
XIN/16
(XCIN/16 in φ = XCIN/2)
TOUT output
TOUT output
active edge
switch bit “0”
control bit
S
Q
P50/TOUT
P50 direction register
T
“1”
Q
P50 latch
Timer 3 latch (8)
Timer 3 (8)
“0”
TOUT output control bit
XIN/16(XCIN/16 in φ = XCIN/2)
Timer 3
interrupt
“1”
Timer 3 count
source selection bit
Fig. 22 Timer block diagram
30
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
b7
b0
Timer X mode register
(TXM : address 002716)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P56 data for real time port
P57 data for real time port
Timer X operating mode bits
b5 b4
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in system clock φ = XCIN/
2).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode, set
the direction register of corresponding port to output mode.
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
(3) Event Counter Mode
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in system clock φ =
XCIN/2. If CNTR0 active edge switch bit is “0”, the timer counts
while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer
counts while the input signal of CNTR0 pin is at “L”.
Rising edge active for CNTR0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
■ Notes
● Timer X write control
Fig. 23 Structure of timer X mode register
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
When the value is to be written in latch only, if the value is written
to the latch at timer X underflows, the value is consequently
loaded in the timer X and the latch at the same time. Unexpected
value may be set in the high-order counter when the writing in
high-order latch and the underflow of timer X are performed at the
same timing.
● CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
● Real time port control
Data for the real time port are output from ports P56 and P57 each
time the timer X underflows. (However, if the real time port control
bit is changed from “0” to “1”, data are output independent of the
timer X operation.) When the data for the real time port is changed
while the real time port function is valid, the changed data are out-
put at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
31
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
Timer Y mode register
(TYM : address 002816)
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in system clock φ = XCIN/
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
2).
0
0
1
1
0 : Timer mode
(2) Period Measurement Mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except
for the above-mentioned, the operation in period measurement
mode is the same as in timer mode.
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
Rising edge active for CNTR1 interrupt
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt.
Timer Y stop control bit
0 : Count start
1 : Count stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
Fig. 24 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measure-
ment Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
■ Note
● CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
32
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1,Timer 2,Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
b7
b0
each timer can be selected by timer 123 mode register.
Timer 123 mode register
(T123M :address 002916)
● Timer 2 write control
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
When the timer 2 write control bit is “1”, and the value is written in
the address of timer 2, the value is loaded only in the latch. The
value in the latch is loaded in timer 2 after timer 2 underflows.
When the timer 2 write control bit is “0”, and the value is written in
the address of timer 2, the value is loaded in the timer 2 and the
latch at the same time.
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
● Timer 2 output control
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
An inversion signal from TOUT pin is output each time timer 2
underflows.
1 : f(XIN)/16
In this case, set the port P50 direction register to the output mode.
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
■ Note
● Timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer. If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Not used (return “0” when read)
Note : Internal clock φ is f(XCIN)/2 in the low-speed mode.
Therefore, set the value of timer in the order of timer 1, timer 2 and
timer 3 after the count source selection of timer 1 to 3.
Fig. 25 Structure of timer 123 mode register
33
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
(1) Clock Synchronous Serial I/O1 Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit (b6) of the serial I/O1 control
register to “1”.
Serial I/O1
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register (ad-
dress 001816).
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register (RB)
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator
Address 001C16
1/4
Clock control circuit
Falling-edge detector
F/F
P47/SRDY1
Transmit shift register shift completion flag (TSC)
Shift clock
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit interrupt request (TI)
Transmit buffer register (TB)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 26 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
D
D
0
0
D
D
1
1
D
2
D
D
3
3
D
D
4
4
D
D
5
5
D
D
6
6
D
D
7
7
Serial I/O1 output T
Serial I/O1 input R
X
X
D
D
D
2
Receive enable signal SRDY1
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)
or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O1 function
34
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Serial I/O control register
Address 001A16
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
UART control register
SP detector
PE FE
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
XIN
Frequency division ratio 1/(n+1)
Baud rate generator
BRG count source selection bit
1/4
Address 001C16
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Data bus
Fig. 28 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1✽
SP
TBE=1
ST
Serial I/O output TXD
ST
D
0
D
1
D
0
D1
SP
✽Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial I/O input RXD
D
0
D
1
ST
D
0
D1
Notes
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O function
35
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit (bit 7)
of the Serial I/O1 control register also clears all the status flags, in-
cluding the error flags.
All bits of the serial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift register shift comple-
tion flag (bit 2) and the transmit buffer empty flag (bit 0) become
“1”.
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register contains eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of a data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin and
P46/SCLK1 pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
36
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
)
(SIO1CON : address 001A16
BRG count source selection bit (CSS)
0: f(XIN
)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clockk synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O1 enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
4
7
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 30 Structure of serial I/O1 control register
37
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
b7
b0
The Serial I/O2 function can be used only for clock synchronous
Serial I/O2 control register
(SIO2CON : address 001D16
)
serial I/O.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock.When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
Serial I/O2 internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 : f(XIN)/32 or f(XCIN)/32
0 1 1 : f(XIN)/64 or f(XCIN)/64
1 0 0 :
Do not set
1 0 1 :
1 1 0 : f(XIN)/128 or f(XCIN)/128
1 1 1 : f(XIN)/256 or f(XCIN)/256
[Serial I/O2 Control Register (SIO2CON)]
001D16
The serial I/O2 control register contains 8 bits which control vari-
S
OUT2 pin selection bit
0 : I/O port
1 : SOUT2 output pin
ous serial I/O functions.
P7
1/SOUT2 • P72/SCLK2 P-channel output disable bit
In output mode
0 : CMOS 3 state
1 : N-channel open-drain output
Serial I/O2 transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK2 pin selection bit
0 : External clock (SCLK2 function as an I/O port.)
1 : Internal clock (SCLK2 function as an output port.)
S
OUT2 output control bit
(when serial data is not transferred)
0 : Output active
1 : High-impedance
Fig. 31 Structure of serial I/O2 control register
Data bus
XCIN
1/8
Main clock divide ratio
selection bit CM
7
1/16
“10”
1/32
1/64
XIN
“00,01,11”
1/128
1/256
S
CLK2 pin
selection bit
“1”
S
CLK2
Serial I/O2 internal
synchronous clock
selection bits
“0”
External clock
“0”
“1”
P72 latch
P72/SCLK2
Serial I/O2
interrupt request
Serial I/O2 counter (3)
S
CLK2 pin selection bit
“0”
“1”
P71 latch
P71/SOUT2
S
OUT2 pin selection bit
P70/SIN2
Serial I/O2 register (8)
Fig. 32 Block diagram of serial I/O2
38
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When selecting an external clock as the transfer clock source, the
interrupt request bit is set when counting the transfer clock 8
times. However, the transfer clock does not stop, so that control
the clock externally. The SOUT2 pin does not become the high-im-
pedance state after completion of data transmit.
●Serial I/O2 Operation
When writing to the serial I/O2 register (001F16), the serial I/O2
counter is set to “7”.
After the write is completed, data is output from the SOUT2 pin
each time the transfer clock goes from “H” to “L”. In addition, each
time the transfer clock goes from “L” to “H”, the contents of the se-
rial I/O2 register are shifted by 1 bit data is simultaneously
received from the SIN2 pin.
In order to set the SOUT2 pin to the high-impedance state when
selecting an external clock, set “1” to bit 7 of the serial
I/O2 control register after completion of data transmit. Also, make
sure that SCLK2 is at “H” for this process. When the next data is
transmitted (falling of transfer clock), bit 7 of the serial I/O2 control
register goes to “0” and the SOUT2 pin goes to an active state.
When selecting an internal clock as the transfer clock source, the
serial I/O2 counter goes to “0” by counting the transfer clock 8
times, and the transfer clock stops at “H”, and the interrupt request
bit is set to “1”. In addition, the SOUT2 pin becomes the high-im-
pedance state after the completion of data transfer. (Bit 7 of the
serial I/O2 control register does not go to “1” and only the SOUT2
pin becomes the high-impedance state.)
Synchronous clock
Transfer clock
Serial I/O2 register
write signal
(Note)
Serial I/O2 output
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
S
OUT2
Serial I/O2 input
S
IN2
Interrupt request
bit set
Note: When selecting an internal clock after completion of data transmit, the S OUT2 pin
becomes the high-impedance state.
Fig. 33 Serial I/O2 timing (LSB first)
39
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The P85/SRDY3, P86/SBUSY3, and P87/SSTB3 pins all have the
handshake input/output signal function and can perform active
logic high/low selection.
Serial I/O3
Serial I/O3 has the following modes: 8-bit serial I/O, arbitrary bits
from 1 to 256 serial I/O, up to 256-byte auto-transfer serial I/O.
The 8-bit serial I/O transfers through serial I/O3 register (address
001316). The arbitrary bits and auto-transfer serial I/O modes
transfer through the 256-byte serial I/O3 auto-transfer RAM (ad-
dresses 020016 to 02FF16).
Main
Local
Local
data bus data bus
Main
Serial I/O3 automatic
transfer RAM
address bus address bus
(020016 to 02FF16
)
Serial I/O3
automatic transfer
data pointer
Address decoder
Transfer counter
Serial I/O3
automatic transfer
controller
X
CIN
Serial I/O3 automatic
transfer interval register
Main clock division ratio
selection bits
“10”
1/4
1/8
X
IN
1/16
1/32
1/64
1/128
P87 latch
“00,01,11”
“00,01”
(P87/SSTB3 pin control bits)
P87/SSTB3
“10,11”
1/256
1/512
P8
6 latch
P8
P8
control bits
5
6
/SRDY3
/SBUSY3 pin
•
“0”
Serial I/O3 internal
synchronous clock
selection bits
Serial I/O3
synchronous clock
selection bits
P8
6/SBUSY3
“1”
latch
“00,10,11”
P8
P8
control bits
5
6
/SRDY3
/SBUSY3 pin
•
P8
5
Synchronous
circuit
“0”
“1”
“01”
P85/SRDY3
External clock
Serial transfer
status flag
Serial I/O3
interrupt request
P8
4
latch
“0”
P8
4
/SCLK3
Serial I/O3 counter
“1”
Serial transfer
selection bits
“0”
“1”
P83 latch
P8
2
/SOUT3
Serial transfer
selection bits
Serial I/O3 register (8)
P83/SIN3
Fig. 34 Block diagram of serial I/O3
40
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O3 control register 1
(SIO3CON1 (SC31) : address 001416
)
Serial transfer selection bits
00 : Serial I/O disabled (P8
01 : 8-bit serial I/O
2 to P87 pins are I/O ports.)
10 : Arbitrary bit serial I/O
11 : Automatic transfer serial I/O (8-bit)
Serial I/O3 synchronous clock selection bits (P87/SSTB3 pin control bits)
00 : Internal synchronous clock (P8
01 : External synchronous clock (P8
7 pin is I/O port.)
pin is I/O port.)
7
10 : Internal synchronous clock (P8
11 : Internal synchronous clock (P8
7
pin is SSTB3 output.)
pin is SSTB3 output.)
7
Serial I/O initialization bit
0 : Serial I/O initialization
1 : Serial I/O enabled
Transfer mode selection bit
0 : Full duplex (transmit/receive) mode (P8
1 : Transmit-only mode (P8 pin is I/O port.)
3 pin is SIN3 I/O.)
3
Serial I/O3 transfer direction selection bit
0 : LSB First
1 : MSB First
Automatic transfer RAM transmit/receive address selection bit
0 : Transmit/Receive address match 20016 to 2FF16
(Set automatic transfer data pointer to 0016 to FF16.)
1 : Transmit address 20016 to 27F16
Receive address 28016 to 2FF16
(Set automatic transfer data pointer to 0016 to 7F16.)
b7
b0
Serial I/O3 control register 2
(SIO3CON2 (SC32) : address 001516
)
P8
0000: P8
5
/SRDY3 • P8
6
/SBUSY3 pin control bits
pins are I/O ports.
5
, P86
0001: Unused
0010: P8
0011: P8
0100: P8
0101: P8
0110: P8
0111: P8
1000: P8
1001: P8
1010: P8
1011: P8
1100: P8
1101: P8
1110: P8
1111: P8
5
5
5
5
5
5
5
5
5
5
5
5
5
5
pin is SRDY3 output, P8
pin is SRDY3 output, P8
pin is I/O port, P8
pin is I/O port, P8
pin is I/O port, P8
pin is I/O port, P8
pin is SRDY3 input, P8
pin is SRDY3 input, P8
pin is SRDY3 input, P8
pin is SRDY3 input, P8
pin is SRDY3 output, P8
pin is SRDY3 output, P8
pin is SRDY3 output, P8
pin is SRDY3 output, P8
6
6
pin is I/O port.
pin is I/O port.
6
6
6
6
pin is SBUSY3 input.
pin is SBUSY3 input.
pin is SBUSY3 output.
pin is SBUSY3 output.
6
6
6
6
pin is SBUSY3 output.
pin is SBUSY3 output.
pin is SBUSY3 output.
pin is SBUSY3 output.
6
6
6
6
pin is SBUSY3 input.
pin is SBUSY3 input.
pin is SBUSY3 input.
pin is SBUSY3 input.
S
BUSY3 output • SSTB3 output function selection bit
(valid in automatic transfer mode)
0: Functions as signal for each 1-byte
1: Functions as signal for each transfer data set
Serial transfer status flag
0: Serial transfer complete
1: Serial transfer in-progress
S
OUT3 output control bit (when serial data is not transferred)
0: Output active
1: Output high impedance
P82/SOUT3 • P84/SCLK3 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Fig. 35 Structure of serial I/O3 control registers 1 and 2
41
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Regardless of selecting an internal or external synchronous clock,
the serial transfer has both a full duplex mode as well as a trans-
mit-only mode. These modes are set by the transfer mode
selection bit of serial I/O3 control register 1.
●Serial I/O3 Operation
An internal or external synchronous clock can be selected as the
serial transfer synchronous clock by the serial I/O3 synchronous
clock selection bits of the serial I/O3 control register 1.
LSB first or MSB first can be selected for the input/output order of
the serial transfer bit string by the serial I/O3 transfer direction se-
lection bit of serial I/O3 control register 1.
Since the internal synchronous clock has its own built-in divider, 8
types of clocks can be selected by the serial I/O3 internal synchro-
nous clock selection bits of the serial I/O3 control register 3.
Either I/O port or handshake I/O signal function can be selected
for the P85/SRDY3, P86/SBUSY3, and P87/SSTB3 pins by the serial
I/O3 synchronous clock selection bits (P87/SSTB3 pin control bits)
of the serial I/O3 control register 1 or the P85/SRDY3•P86/SBUSY3
pin control bits of the serial I/O3 control register 2.
In order to use serial I/O3, the following process must be followed
after all of the above set have been completed: First, select any
one of 8-bit serial I/O, arbitrary bit serial I/O, or auto-transfer serial
I/O by setting the serial transfer selection bits of the serial I/O3
control register 1. Then, enable the serial I/O by setting the serial
I/O initialization bit of the serial I/O3 control register 1 to “1”.
Whether using an internal or external synchronous clock, set the
serial I/O initialization bit to “0” when terminating a serial transfer
during the transmission.
CMOS output or N-channel open-drain output can be selected for
the SCLK3 and SOUT3 output pins by the P82/SOUT3 • P84/SCLK3 P-
channel output disable bit of the serial I/O3 control register 2.
The SOUT3 output control bit of the serial I/O3 control register 2
can be used to select the status of the SOUT3 pin when serial data
is not transferred; either output active or high-impedance. How-
ever, when selecting an external synchronous clock, the SOUT3
pin can go to the high-impedance status by setting the SOUT3 out-
put control bit to “1” when SCLK3 input is at “H” after transfer
completion. When the next serial transfer begins and SCLK3 goes
to “L”, the SOUT3 output control bit is automatically reset to “0” and
goes to an output active status.
b7
b0
Serial I/O3 control register 3
(SIO3CON3 (SC33) : address 001616
)
Auto-transfer interval set bit
00000: 2 cycles of transfer clock
00001: 3 cycles of transfer clock
:
11110: 32 cycles of transfer clock
11111: 33 cycles of transfer clock
Written to latch
Read from decrement counter
Serial I/O3 internal synchronous clock selection bits
000: f(XIN)/4 or f(XCIN)/4
001: f(XIN)/8 or f(XCIN)/8
010: f(XIN)/16 or f(XCIN)/16
011: f(XIN)/32 or f(XCIN)/32
100: f(XIN)/64 or f(XCIN)/64
101: f(XIN)/128 or f(XCIN)/128
110: f(XIN)/256 or f(XCIN)/256
111: f(XIN)/512 or f(XCIN)/512
Fig. 36 Structure of serial I/O3 control register 3
42
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
nal for each transfer data set by the SBUSY3 output•SSTB3 output
function selection bit, there is the transfer interval before the first
data is transmitted/received, as well as after the last data is trans-
mitted/received. When using SSTB3 output, regardless of the
contents of the SBUSY3 output • SSTB3 output function selection
bit, this transfer interval become 2 cycles longer than the value set
for each 1-byte data. In addition, when using the combined output
of SBUSY3 and SSTB3 as the signal for each transfer data set, the
transfer interval after completion of transmission/receipt of the last
data become 2 cycles longer than the set value.
(1) 8-bit serial I/O mode
Address 001316 is the serial I/O3 register. When selecting an inter-
nal synchronous clock, serial transfer of the 8-bit serial I/O starts
by the write signal to the serial I/O3 register (address 001316).
The serial transfer status flag of the serial I/O3 control register 2
indicates the serial I/O3 register status. The flag is set to “1” by a
serial I/O3 register write, which triggers a transfer start. After the
8-bit transfer is completed, the flag is reset to “0” and a serial I/O3
interrupt request occurs simultaneously.
When an external synchronous clock is selected, the contents of
the serial I/O3 register are continually shifted while the transfer
clock inputs to SCLK3. In this case, control the clock externally.
When selecting an external synchronous clock, the automatic
transfer interval cannot be set.
After all of the above bit settings have been completed, and an in-
ternal synchronous clock has been selected, serial automatic
transfer starts when the value of the number of transfer bytes,
decremented by 1, is written to the transfer counter (address
001316). When an external synchronous clock is selected, write
the value of the transfer bytes, decremented by 1, to the transfer
counter, and input the transfer clock to SCLK3 after 5 or more
cycles of internal clock φ.
(2) Auto-transfer serial I/O mode
Since read and write to the serial I/O3 register are controlled by
the serial I/O3 automatic transfer controller, address 001316 func-
tions as the transfer counter (in byte units).
In order to make a serial transfer through the serial I/O3 automatic
transfer RAM (addresses 020016 to 02FF16), it is necessary to set
the serial I/O3 automatic transfer data pointer before transferring
data. The automatic transfer data pointer set bits indicate the low-
order 8 bits of the start data stored address. The automatic
transfer RAM transmit/receive address select bit can divide the
256-byte serial I/O3 automatic transfer RAM into two areas: 128-
byte transmit data area and 128-byte receive data area.
When an internal synchronous clock is selected and any of the fol-
lowing conditions apply, the transfer interval between each 1-byte
data can be set by the automatic transfer interval set bits of the
serial I/O3 control register 3:
Set the transfer interval of each 1-byte data transmission to 5 or
more cycles of the internal clock φ after the rising edge of the last
bit of a 1-byte data.
Regardless of internal or external synchronous clock, the auto-
matic transfer data pointer and transfer counter are both
decremented after receipt of each 1-byte data is completed and it
is written to the automatic transfer RAM. The serial transfer status
flag is set to “1” by writing to the transfer counter which triggers
the start of transmission. After the last data is written to the auto-
matic transfer RAM, the serial transfer status flag is set to “0” and
a serial I/O3 interrupt request occurs simultaneously.
1. The handshake signal is not used.
2. The handshake signal’s SRDY3 output, SBUSY3 output, and
SSTB3 output are used independently.
The write values of the automatic transfer data pointer set bits and
the automatic transfer interval set bits are kept in the latch. As a
transfer counter write occurs, each value is transferred to its corre-
sponding decrement counter.
3. The handshake signal’s output is used in groups: SRDY3/SSTB3
output or SBUSY3/SSTB3.
There are 32 values among 2 and 33 cycles of the transfer clock.
When the automatic transfer interval setting is valid and SBUSY3
output is used, and the SBUSY3 and SSTB3 output function as sig-
b7
b0
Serial I/O3 automatic transfer data pointer
(SIO3DP : address 001716
)
Automatic transfer data pointer set bits
Indicates the low-order 8 bits of the address stored the start data on the
serial I/O3 automatic transfer RAM.
Write: kept in latch
Read: from decrement counter
Fig. 37 Structure of serial I/O3 automatic transfer data pointer
43
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When selecting an external synchronous clock, the automatic
transfer interval cannot be specified.
(3) Arbitrary bit serial I/O mode
Since read and write of the serial I/O3 register are controlled by
the serial I/O3 automatic transfer controller, address 001316 func-
tions as the transfer counter (in byte units).
Regardless of internal or external synchronous clock, the auto-
matic transfer data pointer is decremented after each 8-bit data is
received and then written to the auto-transfer RAM. The transfer
counter is decremented with the transfer clock. The serial transfer
status flag is set to “1” by writing to the transfer counter which trig-
gers the start of transmission. After the last data is written to the
automatic transfer RAM, the serial transfer status flag is set to “0”
and a serial I/O3 interrupt request occurs simultaneously.
The write values of the automatic transfer data pointer set bits and
the automatic transfer interval set bits are kept in the latch. As a
transfer counter write occurs, each value is transferred to its corre-
sponding decrement counter.
After the serial I/O3 automatic transfer data pointer and automatic
transfer interval set bits have been set, and an internal synchro-
nous clock selected, serial automatic transfer starts when the
value of the number of transfer bits decremented by 1 is written to
the transfer counter (address 001316), just as in the automatic
transfer serial I/O. When selecting an external synchronous clock,
write the value of the transfer bits decremented by 1 to the trans-
fer counter, then input the transfer clock to SCLK3 after 5 or more
cycles of internal clock φ. The transfer interval after each 8-bit data
transfer must be 5 or more cycles of internal clock φ after the ris-
ing edge of the last bit of the 8-bit data.
If the last data does not fill 8 bits, the receive data stored in the se-
rial I/O3 automatic transfer RAM become the closest MSB odd bit
if the transfer direction select bit is set to LSB first, or the closest
LSB odd bit if the transfer direction select bit is set to MSB first.
When selecting an internal synchronous clock, the automatic
transfer interval can be specified regardless of the contents of the
selected handshake signal.
In this case, when the automatic transfer interval setting is valid
and SBUSY3 output is used there are the transfer interval before
the first data is transmitted/received, as well as after the last data
is transmitted/received just as in the automatic transfer serial I/O
mode. When using SSTB3 output, this transfer interval become 2
cycles longer than the value set for each 8-bit data. In addition,
when using the combined output of SBUSY3 and SSTB3, the trans-
fer interval after completion of transmission/receipt of the last data
become 2 cycles longer than the set value.
Automatic transfer RAM
2FF16
Automatic transfer
data pointer
25216
25116
25016
24F16
24E16
5216
Transfer counter
0416
20016
S
IN3
S
OUT3
Serial I/O3 register
Fig. 38 Automatic transfer serial I/O operation
44
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Automatic transfer RAM
(before transfer)
Automatic transfer data pointer
1516
Transmit bit string
Start bit
MSB
LSB
0
–
0
–
1
1
1
0
0
1
1
0
0
1
1
1
21516
21416
SOUT3
1
0 1 0 1 1 0 0 1 1 0 1 0 1
Transfer counter
0D16
Odd bit
LSB first
Automatic transfer RAM
(after transfer)
Receive bit string
Start bit
MSB
LSB
0
1
1
0
0
0
1
1
0
0
0
1
1
1
21516
21416
1 0
1
0 0 1 1 0 0 1 0 1 1 0
SIN3
–
–
LSB first
Odd bit
*according to automatic
transfer interval setting
SCLK3
(Internal synchronous
clock selected)
SOUT3
SIN3
Serial transfer status flag
Transfer counter
D16
C16 B16 A16
9
8
7
6
5
4
3
2
1
0
Transfer counter write
Automatic transfer
data pointer
1516
1416
Automatic transfer RAM
Serial I/O3 register
Serial I/O3 register
Automatic transfer RAM
* When using the SSTB3 output signal, this become 2 transfer clock cycles longer than the set
interval.
Fig. 39 Arbitrary bit serial I/O operation
45
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Handshake Signal
● SSTB3 output signal
The SSTB3 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB3 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, that is, in the status in which the serial I/O ini-
tialization bit (b4) is reset to “0”, the SSTB3 output goes to “L”, and
the SSTB3 output goes to “H”.
SBUSY3
SCLK3
SOUT3
At the end of transmit/receive operation, when the data of the se-
rial I/O3 register is all output from SOUT3, pulses which are the
SSTB3 output of “H” and the SSTB3 output of “L” are output in the
period of 1 cycle of the transfer clock. After that, each pulse is re-
turned to the initial status in which SSTB3 output goes to “L” and
the SSTB3 output goes to “H”.
Fig. 41 SBUSY3 input operation (internal synchronous clock)
When the external synchronous clock is selected, input an “H”
level signal into the SBUSY3 input and an “L” level signal into the
SBUSY3 input in the initial status in which transfer is stopped. At
this time, the transfer clocks to be input in SCLK3 become invalid.
During serial transfer, the transfer clocks to be input in SCLK3 be-
come valid, enabling a transmit/receive operation, while an “L”
level signal is input into the SBUSY3 input and an “H” level signal is
input into the SBUSY3 input.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0”.
In the automatic transfer serial I/O mode, whether making the
SSTB3 output active at an end of each 1-byte data or after comple-
tion of transfer of all data can be selected by the SBUSY3 output •
SSTB3 output function selection bit (b4 of address 001516) of serial
I/O3 control register 2.
When changing the input values in to the SBUSY3 input and the
SBUSY3 input in these operations, change them while the SCLK3 in-
put is in a high state.
When the high impedance of the SOUT3 output is selected by the
SOUT3 output control bit (b6), the SOUT3 output becomes active,
enabling serial transfer by inputting a transfer clock to SCLK3, while
an “L” level signal is input into the SBUSY3 input and an “H” level
signal is input into the SBUSY3 input.
S
S
STB3
CLK3
S
OUT3
SBUSY3
Fig. 40 SSTB3 output operation
SCLK3
● SBUSY3 input signal
The SBUSY3 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the SBUSY3 input and an “L” level signal into the SBUSY3
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
into the SBUSY3 input and an “H” level signal into the SBUSY3 input
in the period of 1.5 cycles or more of the transfer clock. Then,
transfer clocks are output from the SCLK3 output.
Invalid
SOUT3
(Output high-impedance)
Fig. 42 SBUSY3 input operation (external synchronous clock)
● SBUSY3 output signal
The SBUSY3 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether making the SBUSY3 output active at
transfer of each 1-byte data or during transfer of all data can be
selected by the SBUSY3 output • SSTB3 output function selection bit
(b4).
When an “H” level signal is input into the SBUSY3 input and an “L”
level signal into the SBUSY3 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the SCLK3 output are not
stopped until the specified number of bits is transmitted and re-
ceived.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
arbitrary bit serial I/O is the bit number adding “1” to the set value
to the transfer counter, and that of the automatic transfer serial I/O
is 8 bits.
In the initial status, that is, the status in which the serial I/O initial-
ization bit (b4) is reset to “0”, the SBUSY3 output goes to “H” and
the SBUSY3 output goes to “L”.
46
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY3 out-
put function outputs in 1-byte units), the SBUSY3 output goes to “L”
and the SBUSY3 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK3 output
goes to “L” at a start of transmit/receive operation.
put goes to “L” and the SBUSY3 output goes to “H” when transmit
data is written into the serial I/O3 register to start a transmit
operation, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY3 output
returns to “H” and the SBUSY3 output returns to “L”, the initial
status, when the serial transfer status flag is set to “0”, regardless
of selecting the internal or external synchronous clock.
In the automatic transfer serial I/O mode (the SBUSY3 output func-
tion outputs all transfer data), the SBUSY3 output goes to “L” and
the SBUSY3 output goes to “H” when the first transmit data is writ-
ten into the serial I/O3 register (address 001316).
Furthermore, in the automatic transfer serial I/O mode (SBUSY3
output function outputs in 1-byte units), the SBUSY3 output goes to
“H” and the SBUSY3 output goes to “L” each time 1-byte of receive
data is written into the automatic transfer RAM.
When the external synchronous clock is selected, the SBUSY3 out-
SBUSY3
SBUSY3
Serial transfer
status flag
Serial transfer
status flag
SCLK3
SOUT3
SCLK3
Write to Serial
I/O3 register
Fig. 43 SBUSY3 output operation
Fig. 44 SBUSY3 output operation
(internal synchronous clock, 8-bits serial I/O)
(external synchronous clock, 8-bits serial I/O)
Automatic transfer
interval
SCLK3
Serial I/O3 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O3 register
SBUSY3
Serial transfer
status flag
S
OUT3
Fig. 45 SBUSY3 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY3 output function outputs each 1-byte)
47
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● SRDY3 output signal
When an “H” level signal is input into the SRDY3 input and an “L”
level signal is input into the SRDY3 input for a period of 1.5 cycles
or more of transfer clock, transfer clocks are output from the SCLK3
output and a transmit/receive operation is started.
The SRDY3 output is a transmit/receive enable signal which in-
forms the serial transfer destination that transmit/receive is ready.
In the initial status, that is, when the serial I/O initialization bit (b4)
is reset to “0”, the SRDY3 output goes to “L” and the SRDY3 output
goes to “H”. After transmitted data is stored in the serial I/O3 reg-
ister (address 001316) and a transmit/receive operation becomes
ready, the SRDY3 output goes to “H” and the SRDY3 output goes to
“L”. When a transmit/receive operation is started and the transfer
clock goes to “L”, the SRDY3 output goes to “L” and the SRDY3 out-
put goes to “H”.
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY3 input and an “H” level signal into the
SRDY3 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received,
the transfer clocks from the SCLK3 output is stopped. The hand-
shake unit of the 8-bit serial I/O and that of the automatic transfer
serial I/O are of 8 bits. That of the arbitrary bit serial I/O is the bit
number adding “1” to the set value to the transfer counter.
When the external synchronous clock is selected, the SRDY3 input
becomes one of the triggers to output the SBUSY3 signal.
To start a transmit/receive operation (SBUSY3 output to “L”, SBUSY3
output to “H”), input an “H” level signal into the SRDY3 input and an
“L” level signal into the SRDY3 input, and also write transmit data
into the serial I/O3 register.
● SRDY3 input signal
The SRDY3 input signal becomes valid only when the SRDY3 input
and the SBUSY3 output are used.The SRDY3 input is a signal for re-
ceiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY3 input and a high level signal into the SRDY3
input in the initial status in which the transfer is stopped.
Automatic transfer
interval
Transfer
interval
Transfer
interval
S
CLK3
Serial I/O3 register
→ Automatic transfer RAM
Automatic transfer RAM
→ Serial I/O3 register
SBUSY3
Serial transfer
status flag
SOUT3
Fig. 46 SBUSY3 output operation in arbitrary bit serial I/O mode (internal synchronous clock)
SRDY3
SCLK3
SOUT3
SRDY3
SCLK3
Write to serial
I/O3 register
Fig. 47 SRDY3 Output Operation
Fig. 48 SRDY3 Input Operation (internal synchronous clock)
48
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Write to serial
I/O3 register
A:
SCLK3
SRDY3
SCLK3
SRDY3
SRDY3
SBUSY3
SBUSY3
SBUSY3
SCLK3
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O3 register
B:
Fig. 49 Handshake operation at serial I/O3 mutual connecting (1)
Write to serial
I/O3 register
A:
SCLK3
SRDY3
SCLK3
SRDY3
SRDY3
SBUSY3
SBUSY3
SBUSY3
SCLK3
A:
B:
Internal synchronous
clock selection
External synchronous
clock selection
Write to serial
I/O3 register
B:
Fig. 50 Handshake operation at serial I/O3 mutual connecting (2)
49
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA LINK LAYER COMMUNICATION
CONTROL CIRCUIT
The 3874 Group has a built-in data link layer communication con-
trol circuit.
This data link layer communication control circuit is applicable for
multi-master serial bus communication control used only with data
lines through an external driver/receiver.
The data link layer communication control circuit consists of fol-
lowing.
•Communication mode register (address 002A16)
•Transmit control register (address 002B16)
•Transmit status register (address 002C16)
•Receive control register (address 002D16)
•Receive status register (address 002E16)
•Bus interrupt factor determination control register (address
002F16)
•Control field select register (address 003016)
•Control field data register (address 003116)
•Transmit/Receive FIFO (address 003216)
This function is realized by hardware and firmware so that com-
munication protocol can be partially modified according to the
user’s specification.
The following are the standard communication rate and functions
which the data link layer communication control circuit can per-
form.
•Communication rate: Approx. 40 kbps
The communication rate depends on
frame or bit protocol.
•Synchronous method: Half-duplex asynchronous
•Modification method: PWM method, NRZ, etc.
•Communication functions:
➀Bus arbitration
(CSMA/CD method, etc.)
➁Error detection
(parity, acknowledge, CRC, etc.)
➂Frame, data retry
The transmission signal is output from the BUSOUT pin and input
to the BUSIN pin.
Detailed specifications for communication protocol, bit assign-
ment, function, etc. of each register are defined according to each
communication protocol specification confirmation.
50
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Bus
Bus interrupt source
control signal
Bus interrupt source determination control register (address 002F 16)
Control field selection register (address 0030 16)
Local address
To interrupt request
register
Local
data bus
Control field register (address 0031 16)
* Register crowd
14 bytes
Local address
(addresses 0016 to 0D16)
Communication mode register (address 002A 16)
Transmit control register (address 002B 16)
Transmit status register (address 002C 16)
Receive control register (address 002D 16)
Bus interrupt request signal
Receive status register (address 002E 16)
Transmit/Receive FIFO (address 0032 16)
Transmit FIFO (8 bytes)
Receive FIFO (16 bytes)
BUSIN/BUSOUT input/output control circuit
* Each register name is defined according to the
communication protocol specifications.
BUSOUT
BUSIN
Fig. 51 Data link layer communication control circuit block example
51
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Communication Mode Register (BUSM)]
002A16
The communication mode register (address 002A16) has 6 bits
and consists of all the control bits for the communication mode.
b7
b0
Communication mode register
(BUSM : address 002A16
)
Arbitrary bits: defined according to each communication
protocol specification confirmation.
Not used (Always write “00” to these bits.)
Fig. 52 Structure of communication mode register
52
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Control Register (TXDCON)]
002B16
[Transmit Status Register (TXDSTS)] 002C16
The transmit status register (address 002C16) has 8 bits and con-
sists of the transmit error flag and transmit interrupt request flag.
The transmit control register (address 002B16) has 7 bits and con-
sists of the transmit control and transmit status flags.
b7
b0
Transmit control register
(TXDCON : address 002B16
)
Arbitrary bits: defined according to each communication
protocol specification confirmation.
Not used (return “0” when read)
Arbitrary bits: defined according to each communication
protocol specification confirmation.
Fig. 53 Structure of transmit control register
b7
b0
Transmit status register
(TXDSTS : address 002C16
)
Arbitrary bits: defined according to each communication protocol
specification confirmation.
Transmit bus Interrupt source 1 request bit
Transmit bus Interrupt source 2 request bit
Arbitrary bits: defined according to each communication protocol
specification confirmation.
Transmit bus Interrupt source 3 request bit
Note: Bits 0 to 3, bit 5, and bit 7 can be cleared only by software.
When a transmit bus interrupt source request bit is “1,” an interrupt request occurs.
The name and function of each transmit bus interrupt source is defined according to
the communication protocol specification confirmation.
Fig. 54 Structure of transmit status register
53
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Receive control register (RXDCON)] 002D16
The receive control register has 7 bits and consists of the receive
control and receive status flags.
[Receive status register (RXDSTS)] 002E16
The receive status register has 8 bits and consists of the receive
error flag and receive interrupt request flags.
b7
b0
Receive control register
(RXDCON : address 002D16
)
Arbitrary bits: defined according to each
communication protocol specification confirmation.
Not used (return “0” when read)
Arbitrary bits: defined according to each
communication protocol specification confirmation.
Fig. 55 Structure of receive control register
b7
b0
Receive status register
(RXDSTS : address 002E16
)
Arbitrary bits: defined according to each communication protocol
specification confirmation.
Receive bus interrupt source 1 request bit
Receive bus interrupt source 2 request bit
Arbitrary bits: defined according to each communication protocol
specification confirmation.
Receive bus interrupt source 3 request bit
When a receive bus interrupt source request bit is “1”, an interrupt request occurs.
The name and function of each receive bus interrupt source is defined according to
the communication protocol specification confirmation.
Fig. 56 Structure of receive status register
54
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
and changed by a read/write of the control field register (address
003016).
[Control field selection register (CFSEL)]
003016
[Control field register (CF)] 003116
The control field data select the control field selection register (ad-
dress 003016) value as the pointer. The data can be confirmed
For example, when reading/writing the local address “0016,” the
control field selection register is set to “0016” and the control field
register is read/written.
b7
b0
Control field selection register
(CFSEL : address 003016)
Control field selection bits
b3 b2 b1 b0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Arbitrary bits: defined according to each communication
protocol specification confirmation.
: Disabled
: Disabled
Not used (write “0” to these bits.)
Fig. 57 Structure of control field selection register
55
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
the section concerning interrupts for details about priority and vec-
tor addresses.
[Bus interrupt source determination control
register (BICOND)] 002F16
The bus interrupt source determination control register (address
002F16) has 6 bits and controls bus-related interrupts. Refer to
b7
b0
Bus interrupt source determination control register
(BICOND : address 002F16
)
Transmit bus interrupt source 1 enable bit
Transmit bus interrupt source 2 enable bit
Not used (return “0” when read)
Transmit bus interrupt source 3 enable bit
Receive bus interrupt source 1 enable bit
Receive bus interrupt source 2 enable bit
Receive bus interrupt source 3 enable bit
Not used (return “0” when read)
0: Interrupt disabled
1: Interrupt enabled
The name and function of each transmit/receive bus interrupt source is defined according
to the communication protocol specification confirmation.
Fig. 58 Structure of bus interrupt source determination control register
56
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion. Use a CPU
system clock dividing the main clock XIN.
[A-D/D-A Conversion Register (AD)] 003516
The A-D/D-A conversion register is a register (at reading) that con-
tains the result of an A-D conversion. When reading this register
during an A-D conversion, the previous conversion result is read.
b7
b0
[A-D Control Register (ADCON)] 003416
A-D control register
(ADCON : address 003416)
The A-D control register controls the A-D/D-A conversion process.
Bits 0 to 2 of this register select specific analog input pins. Bit 3
signals the completion of an A-D conversion. The value of this bit
remains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed. Writing “0” to this bit starts the
A-D conversion. When bit 5, which is the AD external trigger valid
bit, is set to “1”, this bit enables A-D conversion even by a falling
edge of an ADT input. Set “0” (input port) to the direction register
corresponding the ADT pin. Bit 6 is the interrupt source selection
bit. Writing “0” to this bit, A-D converter interrupt request occurs at
completion of A-D conversion. Writing “1” to this bit the interrupt
request occurs at falling edge of an ADT input.
Analog input pin selection bits
000: P60/AN0
001: P61/AN1
010: P62/AN2
011: P63/AN3
100: P64/AN4
101: P65/AN5
110: P66/AN6
111: P67/AN7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
VREF input switch bit
0: OFF
1: ON
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AD external trigger valid bit
0: AD external trigger invalid
1: AD external trigger valid
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
Interrupt source selection bit
0: Interrupt request at A-D
conversion completed
1: Interrupt request at ADT
input falling
The channel selector selects one of the input ports P67/AN7 to
P60/AN0 and inputs it to the comparator.
Comparator and Control Circuit
DA output enable bit
0: DA output disabled
1: DA output enabled
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D/
D-A conversion register. When an A-D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
Fig. 59 Structure of A-D control register
Data bus
b0
b7
A-D control register
P77/ADT
3
ADT/A-D interrupt
request
A-D control circuit
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
A-D conversion register
8
Resistor ladder
AVSS
VREF
Fig. 60 Block diagram of A-D converter
57
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 3874 group has an on-chip D-A converter with 8-bit resolution
and 1 channel. The D-A conversion is performed by setting the
value in the A-D/D-A conversion register. The result of D-A con-
verter is output from DA pin by setting the DA output enable bits to
“1”. When using the D-A converter, the corresponding port direc-
tion register bit (P80/DA) should be set to “0” (input status).
The output analog voltage V is determined by the value n (base
10) in the A-D/D-A conversion register as follows:
Data bus
D-A conversion register (8)
DA output enable bit
R-2R resistor ladder
P80/DA
V=VREF ✕ n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, the
DA output enable bits are cleared to “0”, and P80/DA pin becomes
high impedance. The DA output is not buffered, so connect an ex-
ternal buffer when driving a low-impedance load. When using D-A
converter, set 4.0 V or more to VCC.
Fig. 61 Block diagram of D-A converter
■ Note
When reading the A-D/D-A conversion register, the A-D conver-
sion result is read, and the set value for D-A conversion is not
read.
DA output enable bit
“0”
R
R
2R
R
R
R
R
R
P80/DA
“1”
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
“0”
D-A conversion
register
“1”
AVSS
VREF
Fig. 62 Equivalent connection circuit of D-A converter
58
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When bit 6 of the watchdog timer control register is kept at “0”, the
STP instruction is enabled. When that is executed, both the clock
and the watchdog timer stop. Count re-starts at the same time as
the release of stop mode (Note). The watchdog timer does not
stop while a WIT instruction is executed. In addition, the STP in-
struction is disabled by writing “1” to this bit again. When the STP
instruction is executed at this time, it is processed as an undefined
instruction, and an internal reset occurs. Once a “1” is written to
this bit, it cannot be programmed to “0” again.
WATCHDOGTIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and a 12-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to “FF16” and watchdog timer H is set to
“FFF16” by writing to the watchdog timer control register or at a re-
set. Any write instruction that causes a write signal can be used,
such as the STA, LDM, CLB, etc. Data can only be written to bits
6 and 7 of the watchdog control register. Regardless of the value
written to bits 0 to 5, the above-mentioned value will be set to
each timer.
The following shows the period between the write execution to the
watchdog timer control register and the underflow of watchdog
timer H.
Bit 7 of the watchdog timer control register is “0”:
when XCIN = 32 kHz; 524 s
when XIN = 6.4 MHz; 2.6 s
Watchdog Timer Operations
The watchdog timer stops at reset and a countdown is started by
the writing to the watchdog timer control register. An internal reset
occurs when watchdog timer H underflows. The reset is released
after its release time. After the release, the program is restarted
from the reset vector address. Usually, write to the watchdog timer
control register by software before an underflow of the watchdog
timer H. The watchdog timer does not function if the watchdog
timer control register is not written to at least once.
Bit 7 of the watchdog timer control register is “1”:
when XCIN = 32 kHz; 2 s
when XIN = 6.4 MHz; 10 ms
Note: The watchdog timer continues to count even while waiting for a stop
release. Therefore, make sure that watchdog timer H does not un-
derflow during this period.
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“FF16” is set when
watchdog timer
control register is
XCIN
“0”
“10”
written to.
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (12)
“1”
1/16
“00”
“01”
“11”
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
Internal reset
circuit
RESET
Reset release time wait
Note: Either double-speed, high-speed, middle-speed, or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 63 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 001E16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 64 Structure of Watchdog timer control register
59
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 3.0 V and 5.5
V, and the oscillation should be stable), reset is released. After the
reset is completed, the program starts from the address contained
in address FFFD16 (high-order byte) and address FFFC16 (low-
order byte). Make sure that the reset input voltage is 0.6 V or less
for VCC of 3.0 V.
Poweron
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 65 Reset circuit example
X
IN
φ
RESET
Internal
reset
Reset address from
the vector table
Address
Data
AD
H,ADL
?
?
?
?
FFFC
FFFD
AD
L
AD
H
SYNC
XIN : 40 to 56 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 66 Reset sequence
60
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address
002216
Register contents
FF16
(31) Timer Y (low-order)
(32) Timer Y (high-order)
(33) Timer 1
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001416
001516
001616
001716
001916
001A16
001B16
001D16
001E16
002016
002116
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(1) Port P0
002316
002416
002516
002616
FF16
(2) Port P0 direction register
(3) Port P1
FF16
0116
(34) Timer 2
(4) Port P1 direction register
(5) Port P2
(35) Timer 3
FF16
0016
0016
0016
(36) Timer X mode register
(37) Timer Y mode register
(38) Timer 123 mode register
(39) Communication mode register
(40) Transmit control register
(41) Transmit status register
(42) Receive control register
(43) Receive status register
(6) Port P2 direction register
(7) Port P3
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003316
003416
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(8) Port P3 direction register
(9) Port P4
0 0 0 0
0
✕ ✕✕
2016
(10) Port P4 direction register
(11) Port P5
0016
1016
0116
0016
0016
0016
0816
0016
0016
0016
0016
0016
4816
0016
0016
0016
0016
(12) Port P5 direction register
(13) Port P6
(44) Bus interrupt source discrimination control
register
(45) Control field selection register
(14) Port P6 direction register
(15) Port P7
(46) PULL UP register
(16) Port P7 direction register
(17) Port P8
(47) A-D control register
(48) Interrupt source discrimination register 2
(18) Port P8 direction register
(19) Port P9
(49) Interrupt source discrimination control
register 2
(50) Interrupt source discrimination register 1
0 0 0 0 0 0 0
0016
✕
(20) Serial I/O3 control register 1
(21) Serial I/O3 control register 2
(22) Serial I/O3 control register 3
(23) Serial I/O3 automatic transfer data pointer
(24) Serial I/O1 status register
(25) Serial I/O1 control register
(26) UART control register
(27) Serial I/O2 control register
(28) Watchdog timer control register
(29) Timer X (low-order)
(30) Timer X (high-order)
0016
0016
0016
8016
0016
E016
0016
3F16
FF16
FF16
(51) Interrupt source discrimination control
register 1
(52) Interrupt edge selection register
(53) CPU mode register
(54) Interrupt request register 1
(55) Interrupt request register 2
(56) Interrupt control register 1
(57) Interrupt control register 2
(58) Processor status register
(59) Program counter
1
✕
(PS) ✕ ✕ ✕ ✕ ✕
✕
FFFD16 contents
FFFC16 contents
(PCH)
(PCL)
Notes: ✕ : Not fixed
Notes: Since the initial values for other than above-mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 67 Internal status at reset
61
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
can be realized by reducing the drivability between XCIN and
XCOUT. At reset or during STP instruction execution this bit is set
to “1” and a reduced drivability that has an easy oscillation start is
set. The sub-clock XCIN-XCOUT oscillating circuit can no directly in-
put clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
CLOCK GENERATING CIRCUIT
The 3874 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Oscillation Control
(1) Stop mode
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
When using the XCIN oscillation circuit, XCIN and XCOUT pins’ pull-
up resistors need to be invarid.
When the STP instruction is executed, the internal clock φ stops at
an “H” level, and XIN and XCIN oscillators stop. The value set to the
timer 1 latch and the timer 2 latch is set to timer 1 and timer 2. Ei-
ther XIN or XCIN divided by 16 is input to timer 1 as count source,
and the output of timer 1 is connected to timer 2. The bits of the
timer 123 mode register except the timer 3 count source selection
bit (b4) are cleared to “0”. Set the interrupt enable bits of timer 1
and timer 2 to the disabled state (“0”) before executing the STP in-
struction.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set, this mode is selected.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize. Timer 1 latch and timer 2 latch should be set to proper
values for stabilizing oscillation before executing the STP instruc-
tion.
(2) Double-speed mode
The internal clock φ is the frequency of XIN.
(3) High-speed mode
The internal clock φ is half the frequency of XIN.
(4) Low-speed mode
The internal clock φ is half the frequency of XCIN.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore executing the WIT instruction. The internal clock φ restarts at
reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
■ Note
When switching the mode between double/middle/high-speed and
low-speed, stabilize both XIN and XCIN oscillations. Sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between double/middle/high-speed and low-speed, set the
frequency on condition that f(XIN) > 3f(XCIN).
It takes the cycle number mentioned below to switch between
each mode (machine cycle = cycle of internal clock φ).
XCIN XCOUT
XIN
XOUT
Double-speed mode→Except double-speed mode
1 to 8 machine cycles
Rf
Rd
High-speed mode→Except high-speed mode
1 to 4 machine cycles
COUT
CCIN
CCOUT
CIN
Middle-speed mode→Except middle-speed mode
1 machine cycle
Low-speed mode→Except low-speed mode
1 to 4 machine cycles
Fig. 68 Ceramic resonator circuit
The 3874 group operates in the previous mode while the mode is
switched.
XCIN
XCOUT
XIN
XOUT
(5) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Open
External oscillation
Rf
Rd
CCOUT
CCIN
circuit
VCC
VSS
By clearing furthermore the XCOUT drivability selection bit (b3) of
the CPU mode register to “0”, low power consumption operation
Fig. 69 External clock input circuit
62
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
COUT
XCIN
“0”
Port X
switch bit
“1”
C
1/16
Timer 1
count source
selection bit
Timer 2
count source
selection bit
XOUT
XIN
Main clock division ratio
selection bits (Note)
“1”
“10”
“0”
“1”
Timer 1
Timer 2
1/4
1/2
1/2
“0”
“00,01,11”
Main clock division ratio
selection bits (Note)
Main clock
stop bit
“01”
Timing φ
(internal clock)
“00,10”
“11”
Q
S
R
S
R
S
R
Q
Q
STP instruction
WIT
instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note: When low-speed mode is selected, set port X
C
switch bit (b4) to “1.”
Fig. 70 System clock generating circuit block diagram
63
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM7
“0”←→“1”
CM6
“0”←→“1”
High-speed mode
(φ=3.15 MHz)
Double-speed mode
(φ=6.3 MHz)
Middle-speed mode
(φ=788 kHz)
CM7=0 High-speed mode
CM6=0 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=0 (32 kHz stopped)
CM3=1 (XCOUT drivability
High)
CM7=1 Double-speed mode
CM6=1 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=0 (32 kHz stopped)
CM3=1 (XCOUT drivability
High)
CM7=0 Middle-speed mode
CM6=1 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=0 (32 kHz stopped)
CM3=1 (XCOUT drivability
High)
CM7
“0”←→“1”
CM6
“0”←→“1”
Middle-speed mode
(φ=788 kHz)
Double-speed mode
(φ=6.3 MHz)
High-speed mode
(φ=3.15 MHz)
CM7=0 Middle-speed mode
CM6=1 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=1 (32 kHz oscillating)
CM3=1 (XCOUT drivability
High)
CM7=1 Double-speed mode
CM6=1 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=1 (32 kHz oscillating)
CM3=1 (XCOUT drivability
High)
CM7=0 High-speed mode
CM6=0 6.3 MHz selected
CM5=0 (XIN oscillating)
CM4=1 (32 kHz oscillating)
CM3=1 (XCOUT drivability
High)
CM6
“0”←→“1”
CM7
“0”←→“1”
CM7
“0”←→“1”
CM6
“0”←→“1”
Low-speed mode (φ=16 kHz)
CM7=1 Low-speed mode
CM6=0 32 kHz selected
CM5=0 (XIN oscillating)
CM4=1 (32 kHz oscillating)
CM3=0 (XCOUT drivability
Low)
Low-speed mode (φ=16 kHz)
CM7=1 Low-speed mode
CM6=0 32 kHz selected
CM5=0 (XIN oscillating)
CM4=1 (32 kHz oscillating)
CM3=1 (XCOUT drivability
High)
CM3
“0”←→“1”
b7
b0
CPU mode register
(CPUM: address 003B16)
CM3 : XCOUT drivability selection bit
0 : Low
1 : High
CM4 : Port Xc switch bit
0 : I/O port function
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Oscillating
Low-speed mode (φ=16 kHz)
CM7=1 Low consumption
mode
CM6=0 32 kHz selected
CM5=1 (XIN stopped)
CM4=1 (32 kHz oscillating)
CM3=0 (XCOUT drivability
Low)
1 : Stopped
CM7,CM6 : Main clock division ratio selection bits
CM7 CM6
0
0
1
1
0
1
0
1
: φ=f(XIN)/2 (high-speed mode)
: φ=f(XIN)/8 (middle-speed mode)
: φ=f(XCIN)/2 (low-speed mode)
: φ=f(XIN)
(double-speed mode)
Notes 1: Switch the mode by the arrows shown between the mode blocks. (Do not switch between the modes directly without an arrow.)
2: All modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, wait time is generated automatically by connecting timer 1 and timer 2.
5: The example assumes that 6.3 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock.
6: We recommend that X COUT drivability selection bit is set to “1” (high) because reliance of oscillation stability is improved.
Fig. 71 State transitions of system clock
64
MITSUBISHI MICROCOMPUTERS
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NOTES ON PROGRAMMING
Ports
Processor Status Register
The contents of the port direction registers cannot be read. The
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O1
Interrupt Source Determination
• In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY1 signal, set the trans-
mit enable bit, the receive enable bit, and the SRDY output
enable bit to “1”.
• Use LDM, STA, etc., instructions to clear interrupt request bits
assigned to the interrupt source determination register 1, the in-
terrupt source determination register 2, the transmit status
register, or the receive status register. (Do not use read-modify-
write instructions such as CLB, SEB, etc. Use the LDM or STA
instruction to clear these bits.)
Serial I/O1 continues to output the final bit from the TXD pin af-
ter transmission is completed.
• In order to stop a transmit, set the transmit enable bit to “0”
(transmit disable).
• Request bits of interrupt source determination registers are not
automatically cleared when an interrupt occurs. After an inter-
rupt source has been determined, and before execution of the
RTI or CLI instruction, the user must clear the bit by program.
(Use the LDM or STA instruction to clear.)
Do not set only the serial I/O1 enable bit to “0”.
• A receive operation can be stopped by either setting the receive
enable bit to “0” or the serial I/O1 enable bit to “0”.
• To stop a transmit when transferring in clock synchronous serial
I/O mode, set both the transmit enable bit and the receive en-
able bit to “0” at the same time.
• The interrupt assigned to the interrupt source determination reg-
isters occur 1 instruction execution later than a normal interrupt.
The maximum timing is 16 machine cycles in the MUL, DIV in-
structions.
• To set the serial I/O1 control register again, first set the transmit
enable/receive enable bits to “0”. Next, reset the transmit/re-
ceive circuits, and, finally, reset the serial I/O1 control register.
• Note when confirming the transmit shift register completion flag
and controlling the data transmit after writing a transmit data to
the transmit buffer. There is a delay of 0.5 to 1.5 shift clock
cycles while the transmit shift register completion flag goes from
“1” to “0”.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
65
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• If switching the mode between low-speed and double-speed,
switch the mode to middle/high-speed first, and then switch the
mode to double-speed by program. Do not switch the mode
from low-speed to double-speed directly. 1 to 4 machine cycles
are required for switching from low-speed mode to other mode.
Insert “clock switch timing wait” for switching the mode to
middle/high-speed, and then switch the mode to double-speed.
Table 8 lists the recommended transition process for system
clock switch.
Serial I/O3
• When writing “1” to the serial I/O initialization bit of the serial
I/O3 control register 1, serial I/O3 is enabled, but each register
is not initialized. Set the value of each register by program.
• A serial I/O3 interrupt request occurs when “0” is written to the
serial I/O initialization bit during an operation in automatic trans-
fer serial I/O mode. Disable the interrupt enable bit as necessary
by program.
Figure 72 shows the program example.
A-D Converter/D-A Converter
• The A-D/D-A conversion register functions as an A-D conversion
register during a read and a D-A conversion during a write. Ac-
cordingly, the D-A conversion register set value cannot be read
out.
Table 8 Clock switch combination
Recommended transition process
Low-speed→High-speed
Low-speed→Middle-speed
Double-speed→High-speed
Middle-speed→High-speed
Middle-speed→Middle-speed
Middle-speed→Low-speed
• The comparator for A-D converter uses capacitive coupling am-
plifier whose charge will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Double-speed→Middle-speed High-speed→Double-speed
Do not execute the STP or WIT instruction during an A-D con-
version.
Double-speed→Low-speed
High-speed→MIddle-speed
High-speed→Low-speed
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction. The number of cycles required to execute
an instruction is shown in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
Low-speed mode → Middle/High-speed mode → Double-speed mode switch
LDM xx, CPUM •••Low-speed mode → Middle/High-speed mode switch
NOP
NOP
Clock switch timing wait
(1 to 4 machine cycles are required for switching mode.)
LDM yy, CPUM •••Switch mode to double-speed
Note: CPUM = CPU mode register (address 003B16)
Data Link Layer Communication Control
• The data link layer communication control circuit stops after a
reset. To restart or change modes, write “00XXXXX12” to the
communication mode register. Note that bits 4 and 5 are read-
only bits.
Fig. 72 Program example
• The P75/BUSOUT pin operates as a general-purpose pin after
release from reset. As a general-purpose port, its input/output
can be switched by the direction register.
Clock Changes
• Use the LDM, STA, etc. instructions to modify the division ratio
of internal system clock φ. (Do not use read-modify-write instruc-
tions such as CLB, SEB, etc.)
• Do not modify the division ratio of the internal system clock until
the mode has been changed. For details concerning the number
of cycles necessary to change modes, refer to the clock section
in the explanation of about function blocks.
• Use the LDM, STA, etc., instructions to clear interrupt request
bits assigned to the interrupt source determination register 1,
the interrupt source determination register 2, the transmit status
register, or the receive status register. (Do not use read-modify-
write instructions such as CLB, SEB, etc.)
• Before executing the CLI or RTI instruction during an interrupt
processing routine, use the LDM or STA instruction to clear the
interrupt request bits of interrupt source determination registers
which have completed the interrupt processing.
66
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DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM produc-
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 73 is recommended to verify programming.
tion:
1.Mask ROM Order Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
DATA REQUIRED FOR ROM WRITING
ORDERS
Programming with PROM
programmer
The following are necessary when ordering a ROM writing:
1.ROM Writing Confirmation Form
2.Mark Specification Form
Screening (Caution)
(150 °C for 40 hours)
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 73 Programming and testing of One Time PROM version
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ELECTRICAL CHARACTERISTICS
Table 9 Absolute maximum ratings (extended operating temperature version and automotive version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, VREF
VI
–0.3 to Vcc +0.3
V
All voltages are based
on Vss. Output transis-
tors are cut off.
Input voltage RESET, XIN
Input voltage P97
VI
VI
–0.3 to Vcc +0.3
–0.3 to Vcc +0.3
V
V
Output voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, XOUT
VO
V
–0.3 to Vcc +0.3
500
Power dissipation
Pd
Ta = 25°C
mW
°C
Operating temperature
Storage temperature
Topr
Tstg
–40 to 85
–60 to 150
°C
Table 10 Recommended operating conditions
(extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted)
Power source voltage
Symbol
Parameter
Unit
Min.
4.0
4.0
4.0
3.0
3.0
Typ.
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
At operating data link layer communication control circuit
Double-speed mode
V
V
V
V
V
V
V
V
V
V
Power source
voltage
High-speed mode
Middle-speed mode
Low-speed mode
VCC
Power source voltage
Analog reference voltage (when A-D converter is used)
VSS
2.0
3.0
VCC
VCC
VREF
Analog reference voltage (when D-A converter is used)
Analog power source voltage
AVSS
VIA
0
Analog input voltage AN0 to AN7
VCC
AVSS
0.8VCC
0.8VCC
0
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P97
VIH
VIH
VIL
VCC
VCC
V
V
V
“H” input voltage RESET, XIN
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P97
0.2VCC
VIL
VIL
“L” input voltage RESET
“L” input voltage XIN
0
0
0.2VCC
V
V
0.16VCC
68
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Table 11 Recommended operating conditions (1)
(extended operating temperature version and automotive version, Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
“H” total peak output current (Note 1)
Unit
mA
Min.
Max.
Typ.
ΣIOH(peak)
–
80
80
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87
“H” total peak output current
P40–P47, P50–P57, P60–P67, P70–P77
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
–
mA
mA
mA
mA
mA
mA
mA
“L” total peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87
80
80
“L” total peak output current
P40–P47, P50–P57, P60–P67, P70–P77
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87
–40
“H” total average output current
P40–P47, P50–P57, P60–P67, P70–P77
–40
“L” total average output current
P00–P07, P10–P17, P20–P27, P30–P37, P80–P87
40
40
“L” total average output current
P40–P47, P50–P57, P60–P67, P70–P77
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–
10
mA
mA
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
10
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
–
5.0
5.0
2.5
mA
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87
mA
f(CNTR0)
f(CNTR1)
Timer X, timer Y input oscillation frequency
(at duty cycle of 50%)
MHz
f(XIN)
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Notes 4, 5)
6.4
50
MHz
kHz
32.768
f(XCIN)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
4: Choose an external oscillator which ensures no warps in the oscillation waveform as well as sufficient amplitude for the main clock oscillation cir-
cuit. Use according to the manufacturer’s recommended conditions.
Table 12 Recommended operating conditions (2) (when ROM/PROM size is 60 Kbytes)
(Vcc = 3.0 to 5.5 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
6.4
High-speed mode/Middle-speed mode
Double-speed mode (4.0 ≤ VCC < 4.5V)
Double-speed mode (4.5 ≤ VCC ≤ 5.5V)
MHz
Main clock input
oscillation frequency
f(XIN)
2.8VCC–6.2 MHz
6.4 MHz
Note 5: When using the microcomputer in the low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
69
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Table 13 Electrical characteristics
(extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
= –10 mA
Unit
V
Min.
2.0
Typ.
Max.
IOH
VCC
“H” output voltage
VCC
–
=
4.0–5.5 V
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P80–P87
(Note)
VOH
IOH
=
–1 mA
VCC–1.0
V
VCC
=
3.0–5.5 V
IOL
VCC
= 10 mA
“L” output voltage
2.0
1.0
V
V
=
4.0–5.5 V
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
VOL
+
IOL
VCC
= 1.0 mA
= 3.0–5.5 V
Hysteresis
INT0–INT5, ADT, CNTR0, CNTR1
–
VT
–
VT
0.5
V
Valid hysteresis only
when these pins is used
as the function
Hysteresis
RXD, SCLK1, SIN2, SCLK2, P20–P27
+
–
0.5
0.5
V
V
VT
–
VT
+
–
VT
IIH
–
VT
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
VI
=
VCC
5.0
µA
IIH
IIH
IIH
VI
VI
VI
=
=
=
VCC
VCC
VCC
5.0
5.0
µA
µA
µA
“H” input current P97
“H” input current RESET
“H” input current XIN
4.0
“L” input current
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87
IIL
VI
=
VSS
–5.0
µA
–
5.0
5.0
µA
µA
µA
VI
VI
VI
=
=
=
VSS
VSS
VSS
IIL
IIL
IIL
“L” input current P97
“L” input current RESET
“L” input current XIN
–
–4.0
5.5
2.0
V
VRAM
RAM hold voltage
When clock stopped
Note: When P45/TxD, P71/SOUT2, and P72/SCLK2 are CMOS output states (when not P-channel output disable states)
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Table 14 Electrical characteristics
(extended operating temperature version and automotive version, Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
mA
Min.
Typ.
Max.
24.0
Double-speed mode, at operating data link layer
communication control circuit
f(XIN) = 6.29 MHz
18.0
f(XCIN) = 32 kHz
Output transistors “off”
During A-D conversion
Double-speed mode, at stopping data link layer
communication control circuit
f(XIN) = 6.29 MHz
f(XCIN) = 32 kHz
Output transistors “off”
12.0
2.0
18.0
3.5
mA
mA
mA
mA
mA
During A-D conversion
Double-speed mode, at stopping data link layer
communication control circuit
f(XIN) = 6.29 MHz (in WIT state)
f(XCIN) = 32 kHz
Output transistors “off”
During A-D conversion
High-speed mode, at operating data link layer
communication control circuit
f(XIN) = 6.29 MHz
f(XCIN) = 32 kHz
Output transistors “off”
12.0
8.0
19.0
12.0
3.5
During A-D conversion
ICC
Power source current
High-speed mode, at stopping data link layer
communication control circuit
f(XIN) = 6.29 MHz
f(XCIN) = 32 kHz
Output transistors “off”
During A-D conversion
High-speed mode, at stopping data link layer
communication control circuit
f(XIN) = 6.29 MHz (in WIT state)
f(XCIN) = 32 kHz
Output transistors “off”
During A-D conversion
2.0
60
Low-speed mode (VCC = 3.0 V)
f(XIN) = stopped
f(XCIN) = 32 kHz
Low power dissipation mode (CM 5 = 0)
Output transistors “off”
200
40
µA
µA
Low-speed mode (VCC = 3.0 V)
f(XIN) = stopped
f(XCIN) = 32 kHz (in WIT state)
Low power dissipation mode (CM5 = 0)
Output transistors “off”
20
Ta = 25°C
(Note)
Ta = 85°C
(Note)
All oscillation stopped
(in STP state)
Output transistors “off”
µA
µA
0.1
1.0
10
Note: The A-D conversion is inactive. (The A–D conversion complete.) VREF current is not included.
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Table 15 A-D converter characteristics
(extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to
85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Resolution
Bits
LSB
tc(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
12
50
35
150
0.5
100
200
5.0
VREF = 5.0 V
Reference power source input current
Analog port input current
µA
II(AD)
µA
Table 16 D-A converter characteristics
(extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to
85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Resolution
Bits
%
Absolute accuracy
Setting time
1.0
3.0
4.0
3.2
tsu
µs
RO
Output resistor
1
2.5
kΩ
mA
IVREF
Reference power source input current
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TIMING REQUIREMENTS
Table 17 Timing requirements
(extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
External clock input cycle time
159
63
tWH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT5 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O3 clock input cycle time
tWL(XIN)
63
tC(CNTR)
200
80
tWH(CNTR)
tWH(INT)
80
tWL(CNTR)
tWL(INT)
80
80
tC(SCLK1)
800
1000
1000
370
400
400
370
400
400
220
200
200
100
200
200
tC(SCLK2)
tC(SCLK3)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O3 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O3 clock input “L” pulse width
Serial I/O1 input setup time
tWH(SCLK1)
tWH(SCLK2)
tWH(SCLK3)
tWL(SCLK1)
tWL(SCLK2)
tWL(SCLK3)
tsu(RxD-SCLK1)
tsu(SIN2-SCLK2)
tsu(RIN3-SCLK3)
th(SCLK1-RxD)
th(SCLK2-SIN2)
th(SCLK3-SIN3)
Serial I/O2 input setup time
Serial I/O3 input setup time
Serial I/O1 input hold time
Serial I/O2 input hold time
Serial I/O3 input hold time
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
73
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Switching characteristics
(extended operating temperature version and automotive version, VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width (Note 1)
Serial I/O3 clock output “H” pulse width (Note 5)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2–30
tC(SCLK2)/2–30
tC(SCLK3)/2–30
tC(SCLK1)/2–30
tC(SCLK2)/2–30
tC(SCLK3)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH (SCLK2)
tWH (SCLK3)
tWL (SCLK1)
tWL (SCLK2)
Serial I/O2 clock output “L” pulse width (Note 1)
Serial I/O3 clock output “L” pulse width (Note 5)
Serial I/O1 output delay time (Note 3)
tWL (SCLK3)
td (SCLK1-TXD)
td (SCLK2-SOUT2)
td (SCLK3-SOUT3)
tV (SCLK1-TXD)
140
140
140
Serial I/O2 output delay time (Notes 1, 2)
Serial I/O3 output delay time (Notes 5, 6)
Serial I/O1 output valid time (Note 3)
–30
0
tV (SCLK2-SOUT2)
tV (SCLK3-SOUT3)
Serial I/O2 output valid time (Notes 1, 2)
Serial I/O3 output valid time (Notes 5, 6)
Serial I/O1 clock output rising time
0
ns
ns
30
30
30
30
30
30
30
30
tr (SCLK1)
tf (SCLK1)
tr (SCLK2)
tf (SCLK2)
tr (SCLK3)
tf (SCLK3)
tr (CMOS)
tf (CMOS)
10
10
10
10
10
10
10
10
Serial I/O1 clock output falling time
ns
ns
ns
ns
ns
ns
ns
Serial I/O2 clock output rising time (Note 1)
Serial I/O2 clock output falling time (Note 1)
Serial I/O3 clock output rising time (Note 5)
Serial I/O3 clock output falling time (Note 5)
CMOS output rising time (Note 4)
CMOS output falling time (Note 4)
Notes 1: When P72/SCLK2 is CMOS output.
2: When P71/SOUT2 is CMOS output.
3: When P45/TXD is CMOS output.
4: The XOUT pin is excluded.
5: When P84/SCLK3 is CMOS output.
6: When P82/SOUT3 is CMOS output.
74
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin
100 pF
CMOS output
Fig. 74 Circuit for measuring output switching characteristics
75
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.16VCC
tC(SCLK1), tC(SCLK2), tC(SCLK3)
tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3)
tWL(SCLK1), tWL(SCLK2), tWL(SCLK3)
tf
SCLK1
SCLK2
SCLK3
0.8VCC
0.2VCC
th(SCLK1-RXD),
th(SCLK2-SIN2),
th(SCLK3-SIN3)
tsu(RXD-SCLK1),
tsu(SIN2-SCLK2),
tsu(SIN3-SCLK3)
RXD
SIN2
SIN3
0.8VCC
0.2VCC
tv(SCLK1-TXD),
tv(SCLK2-SOUT2),
tv(SCLK3-SOUT3)
td(SCLK1-TXD),td(SCLK2-SOUT2),td(SCLK3-SOUT3)
TXD
SOUT2
SOUT3
Fig. 75 Timing diagram (in single-chip mode)
76
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-76B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
Sub ROM number of data link layer
communication control circuit
EPROM type (indicate the type used)
27512
27101
EPROM address
000016
EPROM address
000016
Product name
ASCII code :
Product name
ASCII code :
‘M38747M4T–’
‘M38747M4T–’
000F16
001016
000F16
001016
Sub ROM number
ASCII code
Sub ROM number
ASCII code
001F16
002016
C07F16
C08016
001F16
002016
C07F16
C08016
Data
Data
ROM 16K-130 bytes
ROM 16K-130 bytes
FFFD16
FFFE16
1FFFF16
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38747M4T–” must be entered in addresses 000016 to 000916. And set the data
“FF16” in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page.
(3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication
control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has
been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes
of the next page at writing.
(1/3)
77
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-76B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP
MITSUBISHI ELECTRIC
ASCII codes
‘ 0 ’ =3016 ‘ 8 ’ =3816
‘ 1 ’ =3116
‘ 2 ’ =3216 ‘ A ’ =4116
‘ 3 ’ =3316 ‘ B ’ =4216
‘ 4 ’ =3416 ‘ C ’ =4316
‘ 5 ’ =3516 ‘ D ’ =4416
‘ 6 ’ =3616
‘ 7 ’ =3716 ‘ F ’ =4616
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ G ’ =3816
‘ H ’ =3916
‘ K ’ =4B16
‘ Z ’ =5A16
‘ R ’ =5216
‘ S ’ =5316
‘ T ’ =5416
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘M’ = 4D16
‘4’ = 3416
‘ T ’ =5416
‘ - ’ =2D16
FF16
‘ 9 ’ =3916
‘ L ’ =4C16 ‘ U ’ =5516
FF16
FF16
FF16
FF16
‘ M’ =4D16
‘ N ’ =4E16
‘ P ’ =5016
‘ Q ’ =5116
‘ V ’ =5616
‘ W ’=5716
‘ X ’ =5816
‘ Y ’ =5916
‘ E ’ =4516
FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are
written to addresses 001016 to 001716 by using the pseudo-command in the same way.
EPROM type
27512
27101
*=∆$0000
.BYTE∆‘M38747M4T–’
*=∆$0000
.BYTE∆‘M38747M4T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6S) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
Not use (Use for P40,P41)
At what frequency?
f(XcIN) =
MHz
(3) Which clock division ratio will you use? (possible to select plural)
φ = XIN /2 (High-speed mode)
φ = XcIN /2 (Low-speed mode)
φ = XIN (Double-speed mode)
φ = XIN /8 (Middle-speed mode)
(2/3)
78
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-76B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747M4T-XXXGP
MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit?
Yes
No
❈ 4. Comments
(3/3)
79
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-77B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
Sub ROM number of data link layer
communication control circuit
EPROM type (indicate the type used)
27512
27101
EPROM address
000016
EPROM address
000016
Product name
ASCII code :
Product name
ASCII code :
‘M38747M6T–’
‘M38747M6T–’
000F16
001016
000F16
001016
Sub ROM number
ASCII code
Sub ROM number
ASCII code
001F16
002016
A07F16
A08016
001F16
002016
A07F16
A08016
Data
Data
ROM 24K-130 bytes
ROM 24K-130 bytes
FFFD16
FFFE16
1FFFF16
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38747M6T–” must be entered in addresses 000016 to 000916. And set the data
“FF16” in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page.
(3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication
control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has
been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of
the next page at writing.
(1/3)
80
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-77B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP
MITSUBISHI ELECTRIC
ASCII codes
‘ 0 ’ =3016 ‘ 8 ’ =3816
‘ 1 ’ =3116
‘ 2 ’ =3216 ‘ A ’ =4116
‘ 3 ’ =3316 ‘ B ’ =4216
‘ 4 ’ =3416 ‘ C ’ =4316
‘ 5 ’ =3516 ‘ D ’ =4416
‘ 6 ’ =3616
‘ 7 ’ =3716 ‘ F ’ =4616
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ G ’ =3816
‘ H ’ =3916
‘ K ’ =4B16
‘ Z ’ =5A16
‘ R ’ =5216
‘ S ’ =5316
‘ T ’ =5416
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘M’ = 4D16
‘6’ = 3616
‘ T ’ =5416
‘ - ’ =2D16
FF16
‘ 9 ’ =3916
‘ L ’ =4C16 ‘ U ’ =5516
FF16
FF16
FF16
FF16
‘ M’ =4D16
‘ N ’ =4E16
‘ P ’ =5016
‘ Q ’ =5116
‘ V ’ =5616
‘ W ’=5716
‘ X ’ =5816
‘ Y ’ =5916
‘ E ’ =4516
FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are
written to addresses 001016 to 001716 by using the pseudo-command in the same way.
EPROM type
27512
27101
*=∆$0000
.BYTE∆‘M38747M6T–’
*=∆$0000
.BYTE∆‘M38747M6T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6S) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
Not use (Use for P40,P41)
At what frequency?
f(XcIN) =
MHz
(3) Which clock division ratio will you use? (possible to select plural)
φ = XIN /2 (High-speed mode)
φ = XcIN /2 (Low-speed mode)
φ = XIN (Double-speed mode)
φ = XIN /8 (Middle-speed mode)
(2/3)
81
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-77B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747M6T-XXXGP
MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit?
Yes
No
❈ 4. Comments
(3/3)
82
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-75B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
Sub ROM number of data link layer
communication control circuit
EPROM type (indicate the type used)
27512
27101
EPROM address
000016
EPROM address
000016
Product name
ASCII code :
Product name
ASCII code :
‘M38747MCT–’
‘M38747MCT–’
000F16
001016
000F16
001016
Sub ROM number
ASCII code
Sub ROM number
ASCII code
001F16
002016
407F16
408016
001F16
002016
407F16
408016
Data
Data
ROM 48K-130 bytes
ROM 48K-130 bytes
FFFD16
FFFE16
1FFFF16
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38747MCT–” must be entered in addresses 000016 to 000916. And set the data
“FF16” in addresses 000A16 to 000F16. ASCII codes and addresses are listed to the next page.
(3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication
control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has
been used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of
the next page at writing.
(1/3)
83
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-75B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP
MITSUBISHI ELECTRIC
ASCII codes
‘ 0 ’ =3016 ‘ 8 ’ =3816
‘ 1 ’ =3116
‘ 2 ’ =3216 ‘ A ’ =4116
‘ 3 ’ =3316 ‘ B ’ =4216
‘ 4 ’ =3416 ‘ C ’ =4316
‘ 5 ’ =3516 ‘ D ’ =4416
‘ 6 ’ =3616
‘ 7 ’ =3716 ‘ F ’ =4616
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ G ’ =3816
‘ H ’ =3916
‘ K ’ =4B16
‘ Z ’ =5A16
‘ R ’ =5216
‘ S ’ =5316
‘ T ’ =5416
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘7’ = 3716
‘4’ = 3416
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
‘ T ’ =5416
‘ - ’ =2D16
FF16
‘ 9 ’ =3916
‘ L ’ =4C16 ‘ U ’ =5516
FF16
FF16
FF16
FF16
‘ M’ =4D16
‘ N ’ =4E16
‘ P ’ =5016
‘ Q ’ =5116
‘ V ’ =5616
‘ W ’=5716
‘ X ’ =5816
‘ Y ’ =5916
‘ E ’ =4516
FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are
written to addresses 001016 to 001716 by using the pseudo-command in the same way.
EPROM type
27512
27101
*=∆$0000
.BYTE∆‘M38747MCT–’
*=∆$0000
.BYTE∆‘M38747MCT–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6S) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
Not use (Use for P40,P41)
At what frequency?
f(XcIN) =
MHz
(3) Which clock division ratio will you use? (possible to select plural)
φ = XIN /2 (High-speed mode)
φ = XcIN /2 (Low-speed mode)
φ = XIN (Double-speed mode)
φ = XIN /8 (Middle-speed mode)
(2/3)
84
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-75B<84A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38747MCT-XXXGP
MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit?
Yes
No
❈ 4. Comments
(3/3)
85
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-78B<84A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM programming data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
Sub ROM number of data link layer
communication control circuit
EPROM type (indicate the type used)
27512
27101
EPROM address
000016
EPROM address
000016
Product name
ASCII code :
‘M38749EFT–’
Product name
ASCII code :
‘M38749EFT–’
000F16
001016
000F16
001016
Sub ROM number
ASCII code
Sub ROM number
ASCII code
001F16
002016
107F16
108016
001F16
002016
107F16
108016
Data
Data
ROM 60K-130 bytes
ROM 60K-130 bytes
FFFD16
FFFE16
1FFFF16
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 108016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38749EFT–” must be entered in addresses 000016 to 000916. And set the data
“FF16” in addresses 000A16 to 000F16. The ASCII codes and addresses are listed to the next page.
(3) Addresses 001016 to 001F16 are ASCII codes reserved area of Sub ROM number for the data link layer communication
control circuit. Write ASCII codes of Sub ROM number for the data link layer communication control circuit, which has been
used at developing the submitted ROM, to addresses 001016 to 001F16 of EPROM certainly. Refer to ASCII codes of the
next page at writing.
(1/3)
86
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-78B<84A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP
MITSUBISHI ELECTRIC
ASCII codes
‘ 0 ’ =3016 ‘ 8 ’ =3816
‘ 1 ’ =3116
‘ 2 ’ =3216 ‘ A ’ =4116
‘ 3 ’ =3316 ‘ B ’ =4216
‘ 4 ’ =3416 ‘ C ’ =4316
‘ 5 ’ =3516 ‘ D ’ =4416
‘ 6 ’ =3616
‘ 7 ’ =3716 ‘ F ’ =4616
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ G ’ =3816
‘ H ’ =3916
‘ K ’ =4B16
‘ Z ’ =5A16
‘ R ’ =5216
‘ S ’ =5316
‘ T ’ =5416
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘7’ = 3716
‘4’ = 3416
‘9’ = 3916
‘E’ = 4516
‘F’ = 4616
‘ T ’ =5416
‘ - ’ =2D16
FF16
‘ 9 ’ =3916
‘ L ’ =4C16 ‘ U ’ =5516
FF16
FF16
FF16
FF16
‘ M’ =4D16
‘ N ’ =4E16
‘ P ’ =5016
‘ Q ’ =5116
‘ V ’ =5616
‘ W ’=5716
‘ X ’ =5816
‘ Y ’ =5916
‘ E ’ =4516
FF16
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM. ASCII codes of sub ROM number are
written to addresses 001016 to 001716 by using the pseudo-command in the same way.
EPROM type
27512
27101
*=∆$0000
.BYTE∆‘M38749EFT–’
*=∆$0000
.BYTE∆‘M38749EFT–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6S) and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
Other (
External clock input
)
Not use (Use for P40,P41)
At what frequency?
f(XcIN) =
MHz
(3) Which clock division ratio will you use? (possible to select plural)
φ = XIN /2 (High-speed mode)
φ = XcIN /2 (Low-speed mode)
φ = XIN (Double-speed mode)
φ = XIN /8 (Middle-speed mode)
(2/3)
87
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-78B<84A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38749EFT-XXXGP
MITSUBISHI ELECTRIC
(4) Will you use the data link layer communication control circuit?
Yes
No
❈ 4. Comments
(3/3)
88
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S (80-PIN QFP) MARK SPECIFICATION FORM
80P6D, 80P6Q (80-PIN Fine-pitch QFP)
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
60
41
40
61
Mitsubishi IC catalog name
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
80
21
1
20
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
60
41
40
61
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard
Mitsubishi type.
3 : Customer’s parts number can be up to 10 alphanu-
meric characters for capital letters, hyphens, commas,
periods and so on.
80
21
1
20
4 : If the Mitsubishi logo
below.
is not required, check the box
Mitsubishi logo is not required
5 : The allocation of Mitsubishi IC catalog name and
Mitsubishi product number is different on the package
owing to the number of Mitsubishi IC catalog name’s
C. Special Mark Required
characters, and the requiring Mitsubishi logo
or not.
60
41
Notes1 : If Special mark is to be printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated technically as close as possible. Mitsubishi
product number (6-digit, or 7-digit) and Mask ROM
number (3-digit) are always marked for sorting the
products.
40
61
2 : If special character fonts (e.g., customer’s trade mark
logo) must be used in Special Mark, check the box be-
low.
For the new special character fonts, a clean font origi-
nal (ideally logo drawing) must be submitted.
80
21
1
20
Special character fonts required
89
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S-A
Plastic 80pin 14✕14mm body QFP
EIAJ Package Code
JEDEC Code
Weight(g)
1.11
Lead Material
Alloy 42
MD
QFP80-P-1414-0.65
HD
D
80
61
1
60
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
3.05
0.2
–
A1
0
0.1
A
2
–
2.8
b
0.25
0.13
13.8
13.8
–
16.5
16.5
0.4
–
–
0°
–
1.3
–
0.3
0.4
0.2
14.2
14.2
–
17.1
17.1
0.8
–
0.1
10°
–
–
–
20
41
0.15
14.0
14.0
0.65
16.8
16.8
0.6
1.4
–
–
0.35
–
c
D
E
e
A
21
40
L1
HD
HE
L
L1
F
y
e
b
b2
L
I2
Detail F
y
M
M
D
E
14.6
14.6
–
–
80D0
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
Weight(g)
21.0±0.2
18.4±0.15
3.32MAX
1.78TYP
0.8TYP
0.6TYP
41
64
65
40
25
80
1
24 1.2TYP
INDEX
90
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
3874 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980602
(1/1)
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