M5M29FB160AVP-8I_技术文档

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DESCRIPTION

PIN CONFIGURATION (TOP VIEW)

The MITSUBISHI M5M29FB/T160AVP,RV are 3.3V-only high

speed 16,777,216-bit CMOS Flash Memories suitable for mobile

and personal computing, and communication products.

The M5M29FB/T160AVP,RV are fabricated by CMOS technology

for the peripheral circuits and DINOR(Divided bit line NOR)

architecture for the memory cells, and are available in 48pin

TSOP(I).

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

BYTE#

3

GND

4

DQ15/A-1

5

DQ7

6

DQ14

7

DQ6

8

DQ13

9

DQ5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

WE#

RP#

NC

WP#

RY/BY#

A18

A17

A7

FEATURES

Organization

.................................

1,048,576 word x 16bit

2,097,152 word x 8 bit

VCC = 2.7V~3.6V

M5M29FB/T160AVP

.................................

..............................

DQ2

Supply voltage ................................

DQ9

DQ1

DQ8

DQ0

OE#

GND

A6

A5

A4

A3

A2

A1

...............

.............

Access time

80/100ns (VCC =3.0V~3.6V,Max)

100/120ns (VCC =2.7V~3.6V,Max)

CE#

.......................

A0

Wide temperature range

-80, -10 : 0~70°C

.......................

-8I

: -40~85°C

Outline

Power Dissipation

48P3E-B(12 x 20mm 48pin TSOP type-I :VP/Normal bend)

.................................

Read

90 mW (Max.)

Program

108 mW (Max.)

144 mW (Max.)

18 µW (Max.)

0.33µW (typ.)

48

A16

1

2

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

WE#

RP#

NC

Erase

BYTE#

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

Standby

3

GND

DQ15/A-1

DQ7

4

..................

Deep power down mode

5

DQ14

6

DQ6

7

Auto program

8

DQ13

DQ5

9

.................................

Program Time

Program Unit

4ms (typ.)

DQ12

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

128word(256byte)

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

M5M29FB/T160ARV

Auto Erase

Erase time

Erase Unit

Boot block

WP#

RY/BY#

A18

.................................

40 ms (typ.)

DQ9

DQ1

DQ8

DQ0

OE#

A17

A7

.................................

..............................

.................................

8Kword / 16Kbyte x 1

4Kword / 8Kbyte x 2

16Kword / 32Kbyte x 1

32Kword / 64Kbyte x 31

A6

A5

Parameter block

A4

A3

A2

A1

Main block

GND

CE#

A0

.................................

Erase block

..............................

M5M29FB160A

M5M29FT160A

Bottom boot block type

Top boot block type

Outline

48P3E-C(12x20mm 48pin TSOP type-I :RV/Reverse bend)

.........................

Program/Erase cycles

100K cycles

NC : NO CONNECTION

Other Functions

Software Command Control

Selective Block Lock

Erase Suspend/Resume

Program Suspend/Resume

Status Register Read

Package

48-Lead 12mmx 20mm TSOP (type-I) :0.5mm pin pitch

APPLICATION

Wireless Communications, Handheld PC, PDA

1

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK DIAGRAM

128 WORD PAGE BUFFER

A19

A18

A17

A16

VCC (3.3V)

GND (0V)

A15

A14

A13

A12

A11

2097152WORD X 8 BIT /

1048576WORD X 16 BIT

X-DECODER

CELL MATRIX

A10

A9

A8

A7

A6

A5

A4

A3

A2

ADDRESS

INPUTS

Y-GATE / SENSE AMP.

MULTIPLEXER

Y-DECODER

A1

A0

STATUS / ID REGISTER

CHIP ENABLE INPUT

OUTPUT ENABLE INPUT

WRITE ENABLE INPUT

CE#

OE#

WE#

CUI

WSM

WRITE PROTECT INPUT

RESET/POWER DOWN INPUT

BYTE ENABLE INPUT

WP#

RP#

BYTE#

INPUT/OUTPUT

BUFFERS

READY/BUSY OUTPUT

RY/BY#

DQ2 DQ1

DQ15/A-1 DQ14 DQ13

DQ0

DATA INPUTS/OUTPUTS

FUNCTION

Output Disable

The M5M29FB/T160AVP,RV includes on-chip program/erase

control circuitry. The Write State Machine (WSM) controls block

erase and page program operations. Operational modes are

selected by the commands written to the Command User Interface

(CUI). The Status Register indicates the status of the WSM and

when the WSM successfully completes the desired program or

block erase operation.

When OE# is at VIH, output from the devices is disabled.

Data input/output are in a high-impedance(High-Z) state.

Standby

When CE# is at VIH, the device is in the standby mode and its

power consumption is reduced. Data input/output are in a

high-impedance(High-Z) state. If the memory is deselected during

block erase or program, the internal control circuits remain active

and the device consume normal active power until the operation

completes.

A Deep Powerdown mode is enabled when the RP# pin is at GND,

minimizing power consumption.

Read

The M5M29FB/T160AVP,RV has three read modes, which

accesses to the memory array, the Device Identifier and the Status

Register. The appropriate read command are required to be

written to the CUI. Upon initial device powerup or after exit from

deep powerdown, the M5M29FB/T160AVP,RV automatically

resets to read array mode. In the read array mode, low level input

to CE# and OE#, high level input to WE and RP#, and address

signals to the address inputs (A0-A19) output the data of the

addressed location to the data input/output(DQ0-15).

Deep Power-Down

When RP# is at VIL, the device is in the deep powerdown

mode and its power consumption is substantially low. During

read modes, the memory is deselected and the data

input/output are in a high-impedance(High-Z) state. After

return from powerdown, the CUI is reset to Read Array , and

the Status Register is cleared to value 80H.

During block erase or program modes, RP# low will abort

either operation. Memory array data of the block being altered

become invalid.

Write

Writes to the CUI enables reading of memory array data, device

identifiers and reading and clearing of the Status Register. They

also enable block erase and program. The CUI is written by

bringing WE# to low level, while CE# is at low level and OE# is at

high level. Address and data are latched on the earlier rising edge

of WE# and CE#. Standard micro-processor write timings are

used.

2

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DATA PROTECTION (WRITE PROTECTION)

SOFTWARE COMMAND DEFINITIONS

The M5M29FB/T160A provides hardware-locking of boot block,

when WP# is fixed to GND,

The device operations are selected by writing specific software

command into the Command User Interface.

and selectable software-locking of parameter/main blocks, when

WP# is at low.

Read Array Command (FFH)

This part prevents any modifications to boot block, when WP# is

fixed to GND.

The device is in Read Array mode on initial device powerup and

after exit from deep powerdown, or by writing FFH to the

Command User Interface. The device remains in Read Array

mode until the other commands are written.

In parameter/main blocks, each block has an associated

nonvolatile lock-bit which determines the lock status of the block.

So that, this part prevents any modifications to parameter/main

blocks whose lock-bits are set to "0".

Read Device Identifier Command (90H)

When WP#and RP# is high or RP# is VIHH, lock-bits can be

programmed (to "0" ), and all blocks can be programmed or erased

regardless of the state of the lock-bits, and the lock-bits are

cleared to "1" by this erase.

The Device Identifier is read after writing the Read Device

Identifier command of 90H to the Command User Interface.

Following the command write, the manufacturer code and the

device code can be read from address 000000H and 000001H,

respectively. Additionally, The Device Identifier is read by rising A9

to high voltage for PROM programmers.

Power Supply Voltage

When the power supply voltage (Vcc) is less than 2.2V, the device

is set to the Read-only mode.

Read Status Register Command (70H)

A delay time of 2 us is required before any device operation is

initiated. The delay time is measured from the time Vcc reaches

2.7V.

The Status Register is read after writing the Read Status Register

command of 70H to the Command User Interface.

The contents of Status Register are latched on the later falling

edge of OE# or CE#. So CE# or OE# must be toggled every status

read.

During power up, RP#=GND is recommended. Falling in Busy

status is not recommended for possibility of damaging the device.

Clear Status Register Command (50H)

The Erase Status and Program Status bits are set to "1"s by the

Write State Machine and can only be reset by the Clear Status

Register command of 50H. These bits indicates various failure

conditions.

Block Erase / Confirm Command (20H/D0H)

Automated block erase is initiated by writing the Block Erase

command of 20H followed by the Confirm command of D0H. An

address within the block to be erased is required. The WSM

executes iterative erase pulse application and erase verify

operation.

Page Program Commands(41H)

Page Program allows fast programming of 128words of data in

word-wide mode. Writing of 41H initiates the page program

operation. From 2nd cycle to 129th cycle write data must be

serially inputted. Address A6-0 have to be incremented from 00H

to 7FH. After completion of data loading, the WSM controls the

program pulse application and verify operation.

Basically re-program must not be done on a page which has

already programmed.

Suspend/Resume Command (B0H/D0H)

Writing the Suspend command of B0H during block erase

operation interrupts the block erase operation and allows read

out from another block of memory. Writing the Suspend

command of B0H during program operation interrupts the

program operation and allows read out from another block of

memory. The device continues to output Status Register data

when read, after the Suspend command is written to it. Polling

the WSM Status and Suspend Status bits will determine when

the erase operation or program operation has been suspended.

At this point, writing of the Read Array command to the CUI

enables reading data from blocks other than that which is

suspended. When the Resume command of D0H is written to the

CUI, the WSM will continue with the erase or program processes.

3

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

MEMORY MAP

x8 ( Bytemode)

x16 ( Wordmode)

F8000H-FFFFFH

x8 ( Bytemode)

x16 ( Wordmode)

1FC000H-1FFFFFH FE000H-FFFFFH

1FA000H-1FBFFFH FD000H-FDFFFH

8Kword BOOT BLOCK

4Kword PARAMETER BLOCK

16Kword BLOCK

32Kword BLOCK

1F0000H-1FFFFFH

1E0000H-1EFFFFH F0000H-F7FFFH

1D0000H-1DFFFFH E8000H-EFFFFH

1C0000H-1CFFFFH E0000H-E7FFFH

1B0000H-1BFFFFH D8000H-DFFFFH

1A0000H-1AFFFFH D0000H-D7FFFH

190000H-19FFFFH C8000H-CFFFFH

180000H-18FFFFH C0000H-C7FFFH

FC000H-FCFFFH

1F8000H-1F9FFFH

1F0000H-1F7FFFH F8000H-FBFFFH

1E0000H-1EFFFFH F0000H-F7FFFH

1D0000H-1DFFFFH E8000H-EFFFFH

1C0000H-1CFFFFH E0000H-E7FFFH

1B0000H-1BFFFFH D8000H-DFFFFH

1A0000H-1AFFFFH D0000H-D7FFFH

32Kword BLOCK

040000H-04FFFFH 20000H-27FFFH

030000H-03FFFFH 18000H-1FFFFH

020000H-02FFFFH 10000H-17FFFH

32Kword BLOCK

060000H-06FFFFH

30000H-37FFFH

32Kword BLOCK

050000H-05FFFFH 28000H-2FFFFH

040000H-04FFFFH 20000H-27FFFH

030000H-03FFFFH 18000H-1FFFFH

020000H-02FFFFH 10000H-17FFFH

010000H-01FFFFH 08000H-0FFFFH

32Kword BLOCK

08000H-0FFFFH

010000H-01FFFFH

008000H-00FFFFH 04000H-07FFFH

16Kword BLOCK

006000H-007FFFH

004000H-005FFFH

03000H-03FFFH

02000H-02FFFH

4Kword PARAMETER BLOCK

8Kword BOOT BLOCK

000000H-00FFFFH

00000H-07FFFH

000000H-003FFFH 00000H-01FFFH

A-1-A19(Bytemode) A0-A19(Wordmode)

M5M29FB160A Memory Map

M5M29FT160A Memory Map

4

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BUS OPERATIONS

Bus Operations for Word-Wide Mode (BYTE#=VIH)

Pins

CE#

OE#

WE#

RP#

DQ0-15

RY/BY#

Mode

Array

VIH

X

Data out

VIL

VIH

VIL

VOH (Hi-Z)

1)

Read

Status Register

Lock Bit Status

Identifier Code

Status Register Data

Lock Bit Data (DQ6)

X

VOH (Hi-Z)

Identifier Code

Hi-Z

Output disable

Stand by

X

2)

X

VIH

X

Hi-Z

X

VIH

VIL

X

Program

VIL

X

Command/Data in

Command

Hi-Z

X

Write

Erase

Others

VOH (Hi-Z)

Deep Power Down

Bus Operations for Byte-Wide Mode (BYTE#=VIL)

DQ0-7

Pins

CE#

OE#

WE#

RP#

RY/BY#

Mode

Array

VOH (Hi-Z)

VIH

X

Data out

Status Register Data

Lock Bit Data (DQ6)

Identifier Code

Hi-Z

VIL

VIH

VIL

X

VIL

VIH

1)

Read

Status Register

Lock Bit Status

Identifier Code

X

VIH

VIL

VOH (Hi-Z)

Output disable

Stand by

X

2)

Hi-Z

X

VIH

X

Program

VIL

X

Command/Data in

Command

X

Write

Erase

Others

X

Command

VOH (Hi-Z)

Deep Power Down

Hi-Z

1) X at RY/BY# is VOL or VOH(Hi-Z).

*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.

A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.

2) X can be VIH or VIL for control pins.

SOFTWARE COMMAND DEFINITION

Command List

1st bus cycle

Address

2nd bus cycle

Address

3rd bus cycle

Address

Command

Read Array

Mode

Write

Data

(DQ7-0)

Data

(DQ7-0)

Data

(DQ7-0)

Write

X

FFH

90H

70H

50H

41H

2)

Read

IA

Device Identifier

Read Status Register

ID

3)

X

SRD

Clear Status Register

4)

Page Program

Block Erase / Confirm

Suspend

Write

WA0

WA1

WD1

WD0

D0H

5)

20H

B0H

BA

Resume

D0H

71H

77H

A7H

F0H

6)

Read Lock Bit Status

Lock Bit Program / Confirm

Read

Write

DQ6

BA

X

7)

Write

D0H

Erase All Unlocked Blocks / Confirm

8)

Sleep

1) In the word-wide mode, upper byte data (DQ8-DQ15) is ignored.

2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code,

BYTE #=VIL : A-1, A1-A19 = VIL, BYTE# =VIH : A1-A19 = VIL

3) SRD = Status Register Data

4) WA=Write Address, WD=Write Data.

BYTE# =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6.

Page size is 256Byte (256byte x 8bit), BYTE# =VIH : Write Address and Write Data must be provided

sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit).

5) BA = Block Address

6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.

7) Must be set RP# to VHH and WP# to VIH.

8) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels.

The Read Array command (FFH) must be written to get the device out of sleep mode.

5

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK LOCKING

Erase/Program Operation

Boot Block

Parameter Block

Main Block

Lock Bit

RP#

Write Protection Provided

WP#

VHH

X

All Blocks/Lock Bits Unlocked (Erase/Program enable)

Boot block (hard)locked,

and other blocks locked by Lock Bit

Unlock

Depend on

Lock Bit data

Unlock

Depend on

Lock Bit data

Unlock

VIH

VIL

VIH

VIL

X

Lock

5)

All Blocks/Lock Bits Locked (Deep Power Down Mode)

Lock

5) When the Lock bit is "0" ,its block cannot be programed and erased.

Lock bit is set to "0" by LOCK BIT PROGRAM.

Locked bit("0") is cleared to "1" with block memory by BLOCK ERASE on setting unlock mode.

6) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).

7) WP# pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).

8) X can be VIH or VIL for control pins.

STATUS REGISTER

Definition

Symbol

Status

"1"

"0"

Write State Machine Status

Suspend Status

Erase Status

SR.7 (DQ7)

SR.6 (DQ6)

SR.5 (DQ5)

SR.4 (DQ4)

SR.3 (DQ3)

SR.2 (DQ2)

SR.1 (DQ1)

SR.0 (DQ0)

Ready

Suspended

Busy

Operation in Progress / Completed

Successful

Error

Program Status

Successful

Block Status after Program

Reserved

-

Reserved

Device in Sleep

Device Not in Sleep

Device Sleep Status

*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.

A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.

*DQ3 indicates the block status after the page programming. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is

block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.

6

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DEVICE IDENTIFIER CODE

Pins

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

A0

Hex. Data

DQ0

Code

Manufacturer Code

1CH

62H

64H

VIL

VIH

0

1

0

1

0

1

0

1

0

1

0

1

0

Device Code (T:top boot type)

M5M29FT160A

Device Code (B:bottom boot type)

M5M29FB160A

In the word-wide mode, DQ15-8 = 00H.

A9 = VHH Mode : A9 = 11.4V~12.6V Set A9 to VHH min.200ns before falling edge of CE# in ready status. Min.200ns after return to VIH ,device can't be accessed.

A1~A8, A10~A19, CE#,OE# = VIL, WE# = VIH

DQ15/A-1 = VIL (BYTE# = L)

ABSOLUTE MAXIMUM RATINGS

Symbol

Conditions

Parameter

Min

Max

Unit

V

Vcc

Vcc voltage

-0.2

-0.6

4.6

1)

All input or output voltage except Vcc,A9,RP#

A9,RP# supply voltage

VI1

With respect to Ground

V

VI2

14.0

-0.6

V

Ta

Ambient temperature (-80,-10 / -8I)

Temperature under bias (-80,-10 / -8I)

0/-40 70/85

°C

Tbs

-10/-40 80/85

°C

Tstg

I OUT

Storage temperature

Output short circuit current

°C

mA

-65

125

100

1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage

on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.

CAPACITANCE

Limits

Parameter

Symbol

Test conditions

Unit

Typ

Min

Max

8

pF

CIN

COUT

Input capacitance (Address, Control Pins)

Output capacitance

Ta = 25°C, f = 1MHz, Vin = Vout = 0V

12

DC ELECTRICAL CHARACTERISTICS

(-80/-10:Ta = 0~70°C, -8I:Ta = -40~85°C, Vcc = 2.7V~3.6V, unless otherwise noted)

Limits

Typ1)

Parameter

Symbol

Test conditions

Unit

Max

±1.0

Min

µA

0V£VIN£VCC

ILI

Input leakage current

Output leakage current

0V£VOUT£VCC

ILO

±10

200

5

50

0.1

5

VCC=3.6V, VIN=VIL/VIH, CE=RP=WP#=VIH

VCC=3.6V, VIN=GNDorVCC, CE#=RP#=WP#=VCC±0.3V

ISB1

ISB2

ISB3

VCC standby current

µA

VCC = 3.6V, VIN=VIL/VIH, RP# = VIL

15

VCC deep powerdown current

VCC = 3.6V, VIN=GND or VCC, RP# =GND±0.3V

ISB4

5

µA

0.1

25

VCC = 3.6V, VIN=VIL/VIH, CE# = VIL,

RP#=OE#=VIH, f = 5MHz, IOUT = 0mA

7

ICC1

mA

VCC read current for Word or Byte

30 (-8I)

ICC2

ICC3

ICC4

ICC5

IRP#

IID

VCC Write current for Word or Byte

VCC program current

mA

µA

V

VCC=3.6V, VIN=VIL/VIH, CE#=WE#=VIL, RP#=OE#=VIH

VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH

RP# = VIHH max

30

VCC erase current

40

VCC suspend current

200

500

RP# block unlock current

A9 intelligent identifier current

RP# block unlock voltage

A9 intelligent identifier voltage

Input low voltage

A9 = VID max

VIHH

VID

11.4

– 0.5

2.0

12.0

12.6

0.8

V

VIL

Vcc+0.5

VIH

Input high voltage

V

Output low voltage

VOL

0.45

V

IOL = 4.0mA

IOH = –2.5mA

IOH = –100µA

VOH1

VOH2

VLKO

0.85Vcc

Vcc–0.4

V

Output high voltage

V

Low VCC Lock-Out voltage 2)

1.5

2.5

V

All currents are in RMS unless otherwise noted.

1) Typical values at Vcc=3.3V, Ta=25°C

2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.

If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents

may occur.

7

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC ELECTRICAL CHARACTERISTICS (-80,-10:Ta = 0~70°C, -8I:Ta = -40~85°C)

Read-Only Mode

Limits

Speed Item : -10

CL=100pF

Speed Item : -80,-8I

CL=30pF

Symbol

Parameter

Unit

Vcc=3.3V±0.3V

Vcc=2.7V~3.6V

Vcc=3.3V±0.3V

Vcc=2.7V~3.6V

Min

80

Max

Min

Max

Min

Max

Min

Max

tRC

tAVAV Read cycle time

ns

100

120

ta (AD) tAVQV Address access time

ta (CE) tELQV Chip enable access time

ta (OE) tGLQV Output enable access time

80

40

100

50

100

50

120

60

tCLZ

tELQX Chip enable to output in low-Z

0

tDF(CE) tEHQZ Chip enable high to output in high Z

tOLZ tGLQX Output enable to output in low-Z

tDF(OE) tGHQZ Output enable high to output in high Z

25

30

25

tPHZ

tPLQZ

RP# low to output high-Z

BYTE# access time

150

300

150

300

120

ta(BYTE) tFL/HQV

ns

80

25

100

30

100

25

BYTE# low to output high-Z

tBHZ

tOH

tFLQZ

tOH

ns

30

Output hold from CE#, OE#, addresses

CE# low to BYTE# high or low

Address to BYTE# high or low

0

tBCD tELFL/H

tBAD tAVFL/H

5

ns

tOEH tWHGL OE# hold from WE# high

tPHEL RP# high recovery to CE# low

80

100

500

100

500

120

500

tPS

500

Timing measurements are made under AC waveforms for read operations.

AC ELECTRICAL CHARACTERISTICS (-80,-10:Ta = 0~70°C, -8I:Ta = -40~85°C)

Write Mode (WE# control)

Limits

Speed Item : -80, -8I

Speed Item : -10

Symbol

Parameter

Unit

Vcc=2.7V~3.6V

Vcc=3.3V±0.3V

Min

80

50

10

50

10

0

Max Min

Max

Typ

tWC

tAS

tAH

tDS

tDH

tCS

tCH

tAVAV

Write cycle time

ns

100

50

10

50

10

0

100

50

10

50

10

0

120

50

10

50

10

0

tAVWH Address set-up time

tWHAX Address hold time

tDVWH Data set-up time

tWHDX Data hold time

tELWL

Chip enable set-up time

tWHEH Chip enable hold time

tWLWH Write pulse width

0

tWP

60

20

50

60

20

50

60

20

50

60

20

50

tWPH tWHWL Write pulse width high

tBS

tFL/HWH Byte enable high or low set-up time

tWHFL/H Byte enable high or low hold time

tPHHWH Block Lock set-up to write enable high

tBH

80

100

0

120

tBLS

tBLH

ns

80

0

tQVPH

Block Lockhold from valid SRD

ns

ms

ns

0

80

0

80

tDAP tWHRH1 Duration of auto-program operation

tDAE tWHRH2 Duration of auto-block erase operation

5

50

5

50

80

600

100

5

50

5

50

80

600

120

600

80

100

tWHRL tWHRL

tPS tPHWL

Write enable high to RY/BY# low

RP# high recovery to WE# low

ns

500

Read timing parameters during command write operations mode are the same as during read-only operations mode.

Typical values at Vcc=3.3V, Ta=25°C

8

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC ELECTRICAL CHARACTERISTICS (-80,-10:Ta = 0~70°C, -8I:Ta = -40~85°C)

Write Mode (CE# control)

Limits

Speed Item : -80, -8I

Speed Item : -10

Symbol

Parameter

Unit

Vcc=2.7V~3.6V

Vcc=3.3V±0.3V

Vcc=2.7V~3.6V

Min

80

50

10

50

10

0

Max Min

Max

Typ

ns

tWC

tAS

tAH

tDS

tAVAV Write cycle time

100

50

10

50

10

0

100

50

10

50

10

0

120

50

10

50

10

0

tAVEH

tEHAX

tDVEH

tEHDX

Address set-up time

Address hold time

Data set-up time

tDH

Data hold time

tWS

tWH

tCEP

tWLEL Write enable set-up time

tEHWH Write enable hold time

0

tELEH

CE# pulse width

60

20

50

60

20

50

60

20

50

60

20

50

tCEPH tEHEL

CE# pulse width high

tBS

Byte enable high or low set-up time

tFL/HEH

tEHFL/H

tBH

tBLS

Byte enable high or low hold time

80

0

100

0

100

0

120

0

Block Lock set-up to write enable high

tPHHEH

ns

tBLH

tQVPH Block Lockhold from valid SRD

ms

ns

tDAP

tDAE

tEHRH1 Duration of auto-program operation

5

50

80

600

80

5

50

80

600

100

5

50

80

600

100

5

50

80

600

120

Duration of auto-block erase operation

CE# enable high to RY/BY# low

tEHRH2

tEHRL tEHRL

tPS

tPHEL

ns

RP# high recovery to write enable low

500

Read timing parameters during command write operations mode are the same as during read-only operations mode.

Typical values at Vcc=3.3V, Ta=25°C

Erase and Program Performance

Typ

Unit

Min

Max

Parameter

ms

sec

ms

Block Erase Time

600

5

40

1.3

4

Main Block Write Time (Page Mode)

Page Write Time

80

Vcc Power Up / Down Timing

Symbol

Parameter

Min

2

Typ

Max

Unit

µs

tVCS

RP#=VIH set-up time from Vcc at 2.7V

During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.

The device must be protected against initiation of write cycle for memory contents during power up/down.

The delay time of min.2usec is always required before read operation or write operation is initiated from the time Vcc reaches

2.7V during power up. By holding RP# VIL, the contents of memory is protected during Vcc power up/down.

During power up, RP# must be held VIL for min.2us from the time Vcc reaches 2.7V.

During power down, RP# must be held VIL until Vcc reaches GND.

RP# doesn't have latch mode ,so RP# must be held VIH during read operation or erase/program operation.

9

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS

VIH

ADDRESSES

ADDRESS VALID

tRC

VIL

VIH

VIL

ta (AD)

CE#

OE#

tDF(CE)

ta (CE)

VIH

VIL

tOEH

tDF(OE)

tOH

VIH

VIL

WE#

DATA

RP#

ta (OE)

tOLZ

VOH

VOL

tCLZ

HIGH-Z

OUTPUT VALID

tPHZ

tPS

VIH

VIL

TEST CONDITIONS FOR AC CHARACTERISTICS

Vcc=2.7V~3.6V

Vcc=3.3V±0.3V

Test Configuration

VIL

0V

3.0V

10ns

1.5V

0V

3.0V

10ns

1.5V

Input voltage

VIH

Input rise and fall times (10%-90%)

Reference voltage at timing measurement

Capacitance Load value

CL

100pF

30pF

Output load : 1TTL gate + CL

or

1.3V

1N914

3.3kW

DUT

CL

10

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Vcc POWER UP / DOWN TIMING

Read /Write Inhibit

3.3V

VCC

GND

tVCS

VIH

RP#

VIL

VIH

CE#

VIL

tPS

VIH

VIL

WE#

BYTE# AC WAVEFORMS FOR READ OPERATION

VIH

ADDRESSES

(A0 ~ A19)

ADDRESS VALID

ta(AD)

ADDRESS VALID

VIL

VIH

VIL

CE#

tDF(CE)

tDF(OE)

ta(CE)

ta(OE)

VIH

VIL

OE#

tOLZ

tCLZ

tBAD

ta(BYTE)

VIH

VIL

BYTE#

tBCD

tOH

tBAD

VIH

VIL

HIGH-Z

DATA

(DQ0 ~ DQ7)

VALID

tBHZ

OUTPUT VALID

ta(AD)

VIH

VIL

DATA

(DQ8 - DQ14)

VALID

VIH

VIL

DQ15 / A-1

A-1

DQ15

A-1

When BYTE#=VIH, CE#=OE#=VIL , DQ15/A-1 is output status. At this time, input signal must not be applied.

11

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)

READ STATUS

WRITE READ

PROGRAM

REGISTER ARRAY COMMAND

VIH

ADDRESSES

ADDRESS VALID

A7~A19

VIL

BYTE#=VIL

(A-1~A6)

00H

01H

02H~FEH

02H~7EH

FFH

7FH

VIH

VIL

BYTE#=VIH

(A0 ~A6)

tAH

tWC

tAS

VIH

VIL

ta(CE)

ta(OE)

CE#

OE#

tCH

tCS

VIH

VIL

tOEH

tDAE,tDAP

tWPH

VIH

VIL

WE#

tDH

tWP

41H

tDS

VIH

VIL

DATA

RY/BY#

BYTE#

FFH

DIN

SRD

tWHRL

VOH

VOL

tBS

tBH

VIH

VIL

tBLH

tBLS

VHH

VIH

tPS

RP#

VIL

VIH

tBLS

WP#

VIL

AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)

READ STATUS

REGISTER

WRITE READ

ARRAY COMMAND

ERASE

VIH

ADDRESSES

ADDRESS VALID

tAS

VIL

tAH

tWC

ta(CE)

VIH

VIL

CE#

OE#

tCS

tCH

ta(OE)

VIH

VIL

tOEH

tDAP,tDAE

tWPH

VIH

VIL

WE#

tDH

tWP

tDS

VIH

VIL

SRD

FFH

20H

D0H

DATA

tWHRL

VOH

VOL

RY/BY#

tBS

tBH

VIH

VIL

BYTE#

RP#

tBLH

tBLS

VHH

VIH

tPS

VIL

VIH

VIL

WP#

12

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)

READ STATUS

REGISTER

WRITE READ

ARRAY COMMAND

PROGRAM

VIH

VIL

ADDRESSES

A7~A19

ADDRESS VALID

BYTE#=VIL

(A-1~A6)

02H~FEH

02H~7EH

00H

01H

FFH

7FH

VIH

VIL

BYTE#=VIH

(A0 ~A6)

tWC

tAS

tAH

VIH

VIL

ta(CE)

ta(OE)

CE#

OE#

tCEPH

VIH

VIL

tCEP

tOEH

tDAE,tDAP

tWS

tWH

VIH

VIL

WE#

tDH

tDS

VIH

VIL

DATA

RY/BY#

BYTE#

FFH

41H

DIN

SRD

tEHRL

VOH

VOL

tBS

tBH

VIH

VIL

tBLH

tBLS

VHH

VIH

tPS

RP

VIL

VIH

tBLH

tBLS

WP#

VIL

AC WAVEFORMS FOR ERASE OPERATIONS (CE# control)

READ STATUS

REGISTER

WRITE READ

ARRAY COMMAND

ERASE

VIH

ADDRESSES

ADDRESS VALID

tAS

VIL

tWC

tAH

ta(CE)

VIH

VIL

CE#

OE#

tCEPH

tCEP

ta(OE)

VIH

VIL

tOEH

tDAP,tDAE

tWS

tWH

VIH

VIL

WE#

tDH

tDS

VIH

VIL

SRD

FFH

20H

D0H

DATA

tEHRL

VOH

VOL

RY/BY#

tBS

tBH

VIH

VIL

BYTE#

RP#

tBLH

tBLS

VHH

VIH

tPS

VIL

VIH

VIL

WP#

13

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

FULL STATUS CHECK PROCEDURE

STATUS REGISTER

READ

SR.4 =1

and

COMMAND SEQUENCE ERROR

BLOCK ERASE ERROR

SR.5 =1

?

YES

NO

SR.5 = 0 ?

YES

PROGRAM ERROR

(PAGE, LOCK BIT)

SR.4 = 0 ?

YES

PROGRAM ERROR

(BLOCK)

SR.3 = 0 ?

YES

SUCCESSFUL

(BLOCK ERASE, PROGRAM)

LOCK BIT PROGRAM FLOW CHART

PAGE PROGRAM FLOW CHART

START

SET RP#=WP#=VIH, or RP#=VIHH

WRITE 41H

WRITE 77H

n = 0

WRITE D0H

BLOCK ADDRESS

n = n+1

WRITE

ADDRESS n, DATA n

SR.7 = 1 ?

NO

n = FFH ?

or

n = 7FH ?

NO

YES

LOCK BIT PROGRAM

FAILED

SR.4 = 0 ?

YES

NO

STATUS REGISTER

READ

SET RP#=VIH, WP#=VIL

LOCK BIT PROGRAM

SUCCESSFUL

NO

SR.7 = 1 ?

WRITE B0H ?

YES

SUSPEND LOOP

WRITE D0H

FULL STATUS CHECK

IF DESIRED

PAGE PROGRAM

COMPLETED

YES

14

Feb. 1998 , Rev.1.7

MITSUBISHI LSIs

M5M29FB/T160AVP,RV-80,-10,-8I

16,777,216-BIT (2,097,152-WORD BY 8-BIT / 1,048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK ERASE FLOW CHART

SUSPEND / RESUME FLOW CHART

START

WRITE 20H

WRITE B0H

SUSPEND

WRITE D0H

BLOCK ADDRESS

STATUS REGISTER

READ

STATUS REGISTER

READ

SR.7 = 1?

YES

NO

PROGRAM / ERASE

COMPLETED

SR.6 =1?

NO

WRITE B0H ?

SR.7 = 1 ?

YES

WRITE FFH

YES

SUSPEND LOOP

WRITE D0H

FULL STATUS CHECK

IF DESIRED

READ ARRAY DATA

BLOCK ERASE

COMPLETED

YES

DONE

READING ?

NO

YES

RESUME

WRITE D0H

OPERATION

RESUMED

15

Feb. 1998 , Rev.1.7


型号：	M5M29FB160AVP-8I
厂家：	Mitsubishi Group
描述：	Flash, 1MX16, 100ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, TSOP1-48 光电二极管
文件：	总15页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M5M29FB160AVP-8I [MITSUBISHI]

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