M5M532R16J-10 [MITSUBISHI]
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM; 524288 - BIT （ 32768 - WORD 16位） CMOS静态RAM
| 型号： | M5M532R16J-10 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
1997.01.22
M5M532R16J,TP-10,-12,-15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M532R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 5V supply, and are directly
TTL compatible.
1
2
44
N.C
A3
A2
A1
A0
A4
A5
ADDRESS
INPUTS
43
42
41
3
4
A6
ADDRESS
INPUTS
OUTPUT
ENABLE
BYTE
CONTROL
INPUTS
/OE
/UB
5
6
7
40
39
38
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
CHIP
SELECT
INPUTS
/S
DQ1
DQ2
/LB
DQ16
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
8
9
35
36
35
DQ15
DQ3
DQ4
DQ14 OUTPUTS
DQ13
10
(5V) Vcc
(0V) GND
DQ5
11
12
13
34
33
32
GND (0V)
Vcc (5V)
DQ12
FEATURES
Fast access time M5M532R16J,TP-10
10ns(max)
12ns(max)
15ns(max)
500mW(typ)
15mW(typ)
M5M532R16J,TP-12
DATA
DATA
DQ6
14
15
16
31
30
29
DQ11
INPUTS/
INPUTS/
M5M532R16J,TP-15
OUTPUTS
DQ7
DQ8
/W
DQ10 OUTPUTS
DQ9
NC
A7
Low power dissipation Active
Stand by
WRITE
CONTROL
INPUT
17
18
19
28
27
26
A14
A13
A12
A11
NC
Single +5V power supply
A8
ADDRESS
INPUTS
ADDRESS
INPUTS
Fully static operation : No clocks, No refresh
Common data I/O
20
21
22
25
24
23
A9
A10
NC
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
Outline 44P0K(J)
44P3W-H(TP)
PACKAGE
APPLICATION
High-speed memory system
M5M532R16J : 44pin 400mil SOJ
M5M532R16VP: 44pin 400mil TSOP(II)
FUNCTION
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
upper-Byte are in a non-selectable mode.
The operation mode of the M5M532R16 is determined
by a combination of the device control inputs /S, /W,
/OE, /LB, and /UB. Each mode is summarized in the
function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle.
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
/S /W /OE /LB /UB
Mode
DQ1 - 8
DQ9 - 16
Icc
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
Read cycle All Bytes
Read cycle Upper Bytes
Read cycle Lower Bytes
Write cycle All Bytes
D OUT
D OUT
D OUT
Active
Active
Active
Active
Active
Active
High-impedance
L
L
H
L
D OUT
D IN
High-impedance
D IN
X
X
X
H
X
X
L
L
H
L
L
Write cycle Upper Bytes
Write cycle Lower Bytes
High-impedance
D IN
D IN
L
H
X
H
X
High-impedance
H
X
X
X
H
X
High-impedance
High-impedance
High-impedance
High-impedance
Output disable
Non selection
Active
Stand by
BLOCK DIAGRAM
DQ1
DQ2
DQ3
DQ4
7
8
A7
27
A6 42
9
A2
A1
A0
3
4
5
10
MEMORY ARRAY
512 ROWS
1024 COLUMNS
ADDRESS
INPUTS
13 DQ5
14 DQ6
A14 18
A13 19
A12 20
A11 21
DQ7
15
16 DQ8
CHIP SELECT
INPUTS
/S
6
COLUMN I/O CIRCUITS
WRITE
/W
CONTROL INPUT
17
29 DQ9
DQ10
DQ11
30
31
32 DQ12
COLUMN ADDRESS
DECODERS
OUTPUT
ENABLE INPUT
/OE 41
DQ13
DQ14
35
36
37 DQ15
DQ16
38
UPPER BYTE
CONTROL INPUTS
COLUMN INPUT BUFFERS
/UB 40
/LB 39
11
33
Vcc
12
34
GND
LOWER BYTE
CONTROL INPUTS
24 25 26 43 44
2
A10 A9 A8 A5 A4 A3
ADDRESS INPUTS
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Ratings
-3.5* ~ 7
Symbol
Vcc
Parameter
Supply voltage
Conditions
With respect to GND
Ta=25 C
Unit
V
VI
Input voltage
-3.5* ~ Vcc+0.3
-3.5* ~ Vcc+0.3
1000
V
VO
Pd
Output voltage
V
Power dissipation
Operating temperature
mW
C
Topr
0 ~ 70
Tstg(bias) Storage temperature(bias)
Tstg Storage temperature
-10 ~ 85
C
-65 ~ 150
C
<
* Pulse width 20ns, In case of DC: - 0.5V
=
(Ta=0 ~ 70 C, Vcc=5V±10% , unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Typ
Symbol
Parameter
Condition
Unit
Min
2.2
-0.3*
Max
Vcc+0.3
0.8
V
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
V
V
V
V
µA
IH
V
V
IL
OH
IOH = - 4mA
IOL= 8mA
2.4
V
0.4
2
OL
I
V = 0 ~ Vcc
I
I
VI (/S)= VIH
VO= 0 ~ Vcc
IOZ
Output current in off-state
10
µA
AC(10ns cycle)
AC(12ns cycle)
AC(15ns cycle)
170
150
130
110
70
VI (/S)= VIL
other inputs VIH or VIL
Output-open(duty 100%)
Active supply current
(TTL level)
mA
I
CC1
100
DC
AC(10ns cycle)
Stand-by supply current
(TTL level)
AC(12ns cycle)
AC(15ns cycle)
DC
65
60
50
I
I
VI (/S)= VIH
mA
mA
CC2
CC3
>
VI (/S)= Vcc 0.2V
=
Stand-by current
(MOS level)
<
other inputs VI 0.2V
5
=
>
or VI Vcc - 0.2V
=
<
* Pulse width 20ns, in case of AC : - 3.0V
=
(Ta=0 ~ 70 C, Vcc=5V±10% , unless otherwise noted)
CAPACITANCE
Limit
Typ Max
Symbol
Parameter
Test Condition
Unit
Min
C I
CO
Input capacitance
Output capacitance
VI =GND,Vi =25mVrms,f=1MHz
Vo =GND,Vo =25mVrms,f=1MHz
6
8
pF
pF
Note 1: Direction for current flowing into an IC is positive (no mark).
C
2: Typical value is Vcc=5V,Ta=25
3: CI,CO are periodically sampled and are not 100% tested.
C
AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 , Vcc=5V±10% , unless otherwise noted)
(1) MEASUREMENT CONDITION
Vcc
Including
scope and JIG
(
)
Input pulse levels
VIH =3.0V, VIL =0.0V
3ns
480W
Input rise and fall time
Input timing reference levels
Output timing reference levels
Output loads
DQ
DQ
VIH =1.5V, VIL =1.5V
VOH =1.5V, VOL =1.5V
Fig1,Fig2
5pF
Including
scope and JIG
50W
VL=1.5V
Fig.1 Output load
255W
(
)
Fig.2 Output load for ten , tdis
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Limits
M5M532R16 -10
M5M532R16 -12
M5M532R16 -15 Unit
Symbol
Parameter
Max
Max
Min
10
Min
12
Min
15
Max
tCR
Read cycle time
ns
ta (A)
ta(S)
Address access time
10
12
15
ns
ns
Chip select access time
10
5
12
6
15
7
(OE)
ta
Output enable access time
/LB,/UB access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta (B)
5
5
5
5
6
6
6
6
7
7
7
7
tdis (S)
tdis (OE)
Output disable time after /S high
Output disable time after /OE high
Output disable time after /LB,/UB high
Output enable time after /S low
0
0
0
4
3
3
0
0
0
4
3
3
0
0
0
4
3
3
tdis (B)
ten (S)
ten (OE) Output enable time after /OE low
ten (B)
tv (A)
tPU
Output enable time after /LB,/UB low
Data valid time after address change
4
4
4
Power-up time after chip selection
Power down time after chip selection
0
0
0
tPD
10
12
15
Write cycle
Limits
M5M532R16 -12
Parameter
Symbol
M5M532R16 -10
M5M532R16 -15 Unit
Min
10
9
Max
Min
12
10
10
0
Max
Min
15
12
12
0
Max
tCW
Write cycle time
Write pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(W)
tsu(B)
tsu(A)1
tsu(A)2
/LB,/UB setup time
9
Address setup time(/W)
Address setup time(/S)
0
0
0
0
(S)
9
10
6
12
7
tsu
tsu(D)
Chip select setup time
Data setup time
5
0
0
th(D)
Data hold time
0
(W)
0
0
trec
Write recovery time
0
0
6
6
0
7
7
(W)
Output disable time after /W low
Output disable time after /OE high
Output enable time after /W high
Output enable time after /OE low
Output enable time after /LB,/UB low
Address to /W High
0
5
5
tdis
tdis (OE)
ten (W)
0
0
0
0
0
0
(OE)
0
0
ten
ten
0
(B)
0
0
0
(A-WH)
tsu
10
10
10
12
12
12
9
(A-SH)
9
tsu
tsu
Address to /S High
(A-BH)
9
Address to /LB,/UB High
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
t CR
VIH
A
0~14
VIL
(A)
ta
(A)
(A)
tv
tv
VOH
VOL
DQ1~16
PREVIOUS DATA VALID
UNKNOWN
DATA VALID
/W=H
/S=L
/LB=L
/UB=L
/OE=L
Read cycle 2 (Note 4)
t CR
VIH
/S
VIL
(Note 5)
(S)
tdis(S)
ta
(Note 5)
ten(S)
VOH
UNKNOWN
DATA VALID
DQ1~16
VOL
tPU
tPD
ICC1
50%
50%
Icc
ICC2
/W=H /UB=L
/OE=L /LB=L
Note 4. Addresses valid prior to or coincident with /S transition low.
5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6)
t CR
VIH
VIL
/OE
(Note 5)
(OE)
ta
tdis(OE)
(Note 5)
ten(OE)
VOH
VOL
UNKNOWN
DATA VALID
DQ1~16
/W=H
/S=L
/UB=L
/LB=L
Note 6. Addresses and /S valid prior to /OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
5
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Read cycle 4 (Note 7)
t CR
VIH
/UB,/LB
VIL
(Note 5)
(B)
(B)
tdis
ta
(Note 5)
ten(B)
VOH
DQ1~16
VOL
UNKNOWN
DATA VALID
/W=H
/S=L
/OE=L
Note 7. Addresses , /S and /OE valid prior to /LB,/UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)).
Write cycle (/W control mode)
tCW
(S)
VIH
VIL
A
0~14
tsu
VIH
VIL
/S
(Note8)
(Note8)
(A-WH)
tsu
VIH
VIL
/OE
/W
(A)
(W)
tsu
(W)
trec
tw
VIH
VIL
(B)
tsu
VIH
VIL
/LB,/UB
(Note8)
(Note8)
(Note 5)
(D)
(D)
tsu
th
(OE)
(OE)
tdis
VIH
VIL
DQ1~16
(Input Data)
DATA STABLE
(W) (Note 5)
tdis
ten(OE)
tdis
(W)
ten
VOH
VOL
DQ1~16
(Output Data)
Hi-Z
Note 8: Hatching indicates the state is don't care.
9: When the falling edge of /W is simultaneous or prior to the falling edge of /S, the output is maintained in the high impedance.
10: ten,tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
6
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle(/S control)
tCW
VIH
VIL
A
0~14
(S)
tsu
(W)
(A)
trec
tsu
VIH
VIL
/S
(W)
tw
VIH
VIL
/W
(Note7)
(Note7)
(Note7)
(B)
tsu
VIH
VIL
/LB,/UB
(Note7)
(D)
(D)
tsu
th
VIH
VIL
DATA STABLE
DQ1~16
(Input Data)
(W)
(Note5)
tdis
(Note5)
(S)
ten
VOH
VOL
Hi-Z
DQ1~16
(Output Data)
(Note9)
Write cycle(/LB,/UB control)
tCW
VIH
A0~14
VIL
(S)
tsu
VIH
/S
VIL
(Note7)
(Note7)
(Note7)
(Note7)
(W)
(B)
tw
VIH
/W
VIL
tsu
(W)
trec
(A)
tsu
VIH
/LB,/UB
VIL
(D)
(D)
tsu
th
VIH
DATA STABLE
DQ1~16
(iInput Data)
VIL
(W)
tdis
(Note5)
(Note5)
(B)
ten
VOH
Hi-Z
DQ1~16
(Output Data)
VOL
(Note9)
MITSUBISHI
ELECTRIC
7
MITSUBISHI LSIs
M5M532R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
'97.01.22 P3
Output loads=50W
k.kubo
MITSUBISHI
ELECTRIC
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