M5M5408BKR-55L [MITSUBISHI]
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, REVERSE, STSOP-32;
| 型号： | M5M5408BKR-55L |
| 厂家： | 
Mitsubishi Group |
| 描述： | Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, REVERSE, STSOP-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
• Single +5V power supply
• Small stand-by current: 0.4µA(3V,typ.)
• No clocks, No refresh
The M5M5408B is a family of 4-Mbit static RAMs organized as
524,288-words by 8-bit, fabricated by
Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5408B is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
• Data retention supply voltage=2.0V to 5.5V
• All inputs and outputs are TTL compatible.
• Easy memory expansion by S
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Process technology: 0.25µm CMOS
• Package:
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of
TSOPs and two types of STSOPs are available , M5M5408BTP
(normal-lead-bend TSOP)
, M5M5408BRT (reverse-lead-bend
TSOP) M5M5408BKV (normal-lead-bend STSOP) and
,
M5M5408BKR (reverse-lead-bend STSOP). These two types
TSOPs and two types STSOPs are suitable for a surface mounting
on double-sided printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "W-version", and "I-version". Those
are summarized in the part name table below.
M5M5408BFP: 32 pin 525 mil SOP
M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
M5M5408BKV/KR: 32 pin 8mm x 13.4mm STSOP
PART NAME TABLE
Active
current
Icc1
Stand-by current Icc(PD), Vcc=3.0V
Access
time
Version,
Part name
(## stands for "FP","TP",
"RT","KV"or"KR")
Power
Supply
typical *
Ratings (max.)
70°C 85°C
Operating
temperature
max.
25°C
(5.0V, typ.)
M5M5408B## -55L
M5M5408B## -70L
M5M5408B## -10L
M5M5408B## -55H
M5M5408B## -70H
M5M5408B## -10H
55ns
70ns
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
---
---
---
50µA
10µA
---
Standard
0 ~ +70°C
100ns
55ns
70ns
0.4µA
---
100ns
M5M5408B## -55LW
M5M5408B## -70LW
M5M5408B## -10LW
M5M5408B## -55HW
M5M5408B## -70HW
M5M5408B## -10HW
55ns
70ns
50mA
(10MHz)
100µA
20µA
W-version
-20 ~ +85°C
100ns
55ns
25mA
(1MHz)
70ns
---
0.4µA
---
100ns
55ns
70ns
M5M5408B## -55LI
M5M5408B## -70LI
M5M5408B## -10LI
M5M5408B## -55HI
M5M5408B## -70HI
M5M5408B## -10HI
---
---
100µA
20µA
100ns
55ns
I-version
-40 ~ +85°C
70ns
0.4µA
100ns
* "typical" parameter is sampled, not 100% tested.
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
1
1
(5V)
32
32
A18
A16
A14
A12
A7
A6
A5
A4
A3
(5V)
A18
A16
A14
A12
A7
A6
A5
A4
A3
VCC
A15
A17
VCC
A15
A17
2
2
3
4
5
31
30
31
30
3
4
29
28
27
26
25
24
23
22
21
20
19
18
17
29
28
27
26
25
W
A13
A8
A9
A11
W
A13
A8
A9
5
6
7
8
6
7
8
A11
9
24
9
OE
A10
OE
A10
S
DQ8
DQ7
DQ6
DQ5
DQ4
10
11
12
13
10
A2
A1
A0
23
22
21
A2
A1
A0
11
12
13
S
DQ8
DQ7
DQ6
DQ5
DQ4
DQ1
DQ2
DQ3
(0V) GND
20
19
18
17
DQ1
DQ2
DQ3
GND (0V)
14
15
16
14
15
16
Outline 32P2M-A (FP)
Outline 32P3Y-J (RT)
32P3Y-H (TP)
A3
A2
A1
A0
DQ1
DQ2
A4
17
16
15
14
13
12
11
10
9
1
2
3
32
31
30
29
28
27
26
25
24
23
22
21
A11
A9
A8
A13
OE
A5
18
19
20
21
22
A10
A6
A7
S
4
5
6
7
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A12
A14
A16
A17
Vcc
A15
A18
W
A18
A15
23 DQ3
24
GND
DQ4
26 DQ5
8
Vcc
A17
A16
A14
A12
M5M5408BKR
M5M5408BKV
25
8
9
10
11
12
13
7
6
27
DQ6
DQ7
DQ8
S
A10
OE
5
28
W
A13
29
4
3
20
19
18
17
A7
A6
A5
A4
A0
A1
A2
A3
A8
30
14
15
16
A9
A11
31
2
1
32
Outline 32P3K-C
Outline 32P3K-B
2
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
When setting S at a high level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips. Setting the OE at a high
level,the output stage is in a high-impedance state, and the
data bus contention problem in the write cycle is eliminated.
The power supply current is reduced as low as 0.4µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure
or power-down operation in the non-selected mode.
The M5M5408BFP,TP,RT,KV,KR is organized as 524,288-
words by 8-bit. These devices operate on a single +5.0V
power supply, and are directly TTL compatible to both input
and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
A write operation is executed during the S low and W low
overlap time. The address(A0~A18) must be set up before
the write cycle
A read operation is executed by setting W at a high level
and OE at a low level while S are in an active state(S=L).
Pin
Function
FUNCTION TABLE
A0 ~ A18
Address input
Mode
Icc
DQ
S
W
OE
DQ1 ~ DQ8 Data input / output
Chip select input
S
Non selection
Write
High-impedance
Standby
Active
H
L
X
L
X
X
Write control input
Output inable input
Power supply
W
Data input (D)
Data output (Q)
Read
OE
Vcc
Active
Active
L
L
H
H
L
High-impedance
H
Read
GND
Ground supply
BLOCK DIAGRAM
M5M5408B
FP/TP/RT
M5M5408BKV/KR
M5M5408BKV/KR
M5M5408B
FP/TP/RT
8
16
15
14
13
12
11
10
9
A4
21
22
23
25
26
27
28
29
13
7
6
A5
DQ1
14
15
17
18
19
20
21
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A6
A7
5
MEMORY ARRAY
4
A12
524288 WORDS
x 8 BITS
3
A14
A16
2
30
1
A17
A18
6
31
7
A15
23
25
26
27
28
31
A10
A11
1
2
3
4
CLOCK
GENERATOR
A9
A8
5
29
22
A13
W
S
30
32
24
OE
12
11
10
9
20
19
18
17
A0
A1
VCC
(3V)
8
32
16
A2
A3
24
GND
(0V)
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Input voltage
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Ratings
Units
V
V
cc
VI
-0.3* ~ +7
-0.3* ~ Vcc + 0.3
0 ~ Vcc
Output voltage
Power dissipation
VO
Pd
700
mW
°C
(-L, -H)
Standard
W-version
I-version
0 ~ +70
Operating
temperature
(-LW, -HW)
(-LI, -HI)
Ta
-20 ~ +85
-40 ~ +85
-65 ~150
Storage temperature
Tstg
°C
* -3.0V in case of AC (Pulse width £ 30ns)
DC ELECTRICAL CHARACTERISTICS
( Vcc=5V±10%, unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Units
V
Min
2.2
Max
Vcc+0.3V
0.8
Typ
High-level input voltage
VIH
Low-level input voltage
VIL
-0.3 *
2.4
VOH1
VOH2
High-level output voltage 1 IOH= -1mA
High-level output voltage 2
Low-level output voltage
Input leakage current
IOH= -0.1mA
Vcc-0.5V
VOL
II
IOL=2mA
0.4
±1
±1
VI =0 ~ Vcc
µA
Output leakage current
S=VIH or OE=VIH, VI/O=0 ~ Vcc
IO
minimum cycle
f= 1MHz
Output-open
Other inputs £0.2V or ³ Vcc-0.2V
-
-
-
S £0.2V
50
25
80
30
Active supply current
( AC,MOS level )
Icc1
mA
minimum cycle
f= 1MHz
Output-open
S=VIL
Other inputs=VIH or VIL
Active supply current
( AC,TTL level )
60
30
-
90
40
Icc2
Icc3
-
-
200
100
-LW, -LI
Stand by supply current
( AC,MOS level )
S ³ Vcc-0.2V
Other inputs=0~Vcc
-
-
-
-
-L
µA
0.4
0.4
40
20
-HW, -HI
-H
Stand by supply current
( AC,TTL level )
Icc4
S=V ,Other inputs= 0 ~ Vcc
-
mA
-
3
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=5.0V and Ta=25°C
* -3.0V in case of AC (Pulse width £ 50ns)
CAPACITANCE
(Vcc=5.0V±10%, unless otherwise noted)
Limits
Units
Parameter
Symbol
Conditions
Typ
Min
Max
8
CI
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
pF
CO
10
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(Vcc=5.0V±10%, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply voltage
Input pulse
5.0V
VIH=2.4V,VIL=0.6V (FP,TP,RT,KV,KR-70,-10 )
VIH=3.0V,VIL=0V (FP,TP,RT,KV,KR-55 )
1.8kW
DQ
Input rise time and fall time
Reference level
5ns
CL
VOH=VOL=1.5V
990W
Transition is measured ±500mV from
steady state voltage.(for ten,tdis)
Fig.1, CL=100pF (FP,TP,RT,KV,KR-70,-10 )
CL=30pF (FP,TP,RT,KV,KR-55 )
CL=5pF (for ten,tdis)
Output loads
CL Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits
M5M5408BFP,TP,RT,
M5M5408BFP,TP,RT, M5M5408BFP,TP,RT,
Parameter
Symbol
Units
KV,KR-55
KV,KR-70
KV,KR-10
Min
55
Max
Min
70
Max
Min
Max
tCR
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
Read cycle time
100
100
50
ta(A)
55
55
25
20
20
70
70
35
25
25
Address access time
Chip select access time
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
Output enable access time
35
Output disable time after S high
Output disable time after OE high
35
10
10
10
Output enable time after S low
Output enable time after OE low
Data valid time after address
ten(OE)
tV(A)
5
10
5
10
5
10
(3) WRITE CYCLE
Limits
M5M5408BFP,TP,RT,
M5M5408BFP,TP,RT,
KV,KR-10
M5M5408BFP,TP,RT,
KV,KR-55
Symbol
Parameter
Units
KV,KR-70
Min
100
60
Max
Min
55
40
0
Max
Min
70
50
0
Max
Write cycle time
Write pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tw(W)
0
tsu(A)
Address set up time
tsu(A-WH)
80
80
35
0
Address set up time with respect to W high
Chip select set up time
50
50
25
0
60
60
30
0
tsu(S)
tsu(D)
th(D)
Data set up time
Data hold time
Write recovery time
0
0
0
trec(W)
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
20
20
25
25
35
35
tdis(W)
tdis(OE)
5
5
5
5
5
5
ten(W)
ten(OE)
5
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~18
ta(A)
ta(S)
tv (A)
S
(Note3)
(Note3)
tdis (S)
(Note3)
ta (OE)
OE
ten (OE)
(Note3)
W = "H" level
DQ1~8
ten (S)
tdis (OE)
VALID DATA
Write cycle
( W control mode )
tCW
A0~18
tsu (S)
S
(Note3)
(Note3)
tsu (A-WH)
tw (W)
OE
W
tsu (A)
trec (W)
ten(OE)
ten (W)
tdis (W)
tdis(OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
6
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S control mode)
tCW
A0~18
tsu (A)
S
tsu (S)
trec (W)
(Note5)
W
(Note4)
(Note3)
(Note3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during the overlap of a low S and a low W.
Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
7
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Units
Symbol
Parameter
Test conditions
Typ.
Min
Max
-
-
Vcc (PD)
VI (S)
V
V
Power down supply voltage
Chip select input S
2
-
-
Vcc(PD) ³ 2.2V
2.2
Vcc(PD)
2.2V ³ Vcc(PD) ³ 2.0V
V
-
-
-
-
-
-
-LW, -LI
-L
-
µA
µA
µA
µA
100
50
20
10
Power down
supply current
-
Vcc=3.0V, S³ Vcc-0.2V,
Other inputs=0 ~ Vcc
Icc (PD)
-HW, -HI
-H
0.4
0.4
Typical value is for Ta=25°C
(2) TIMING REQUIREMINTS
Limits
Units
Symbol
Parameter
Test conditions
Typ
Min
Max
tsu (PD)
trec (PD)
Power down set up time
0
5
ns
ms
Power down recovery time
(3) TIMING DIAGRAM
S control mode
Vcc
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
S
S³ Vcc - 0.2V
8
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
revision-K0.1e, ' 98.07.30
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Revision History
Revision No.
K0.1e
History
Date
The first edition
'98.7.30
Preliminary
9
MITSUBISHI ELECTRIC
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