MF0105M-03ATXX [MITSUBISHI]
null8/16-bit Data Bus Flash ATA PC Card; null8 / 16 - bit数据总线闪存ATA PC卡
| 型号： | MF0105M-03ATXX |
| 厂家： | 
Mitsubishi Group |
| 描述： | null8/16-bit Data Bus Flash ATA PC Card |
| 文件： | 总29页 (文件大小：843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI STORAGE CARD
ATA PC CARDS
MF007M5-03ATxx
MF0015M-03ATxx
MF0030M-03ATxx
MF0045M-03ATxx
MF0060M-03ATxx
MF0075M-03ATxx
MF0090M-03ATxx
MF0105M-03ATxx
8/16-bit Data Bus
Flash ATA PC Card
C o n n e c t o r T y p e
Two- piece 68-pin
FEATURES
DESCRIPTION
Mitsubishi’s Flash ATA cards provide large
memory capacities on a device approximately
the size of a credit card
(85.6mm´ 54mm´ 3.3mm). The cards use a 8/16
bit data bus.
Available in 7.5MB, 15MB, 30MB, 45MB,
60MB, 75MB, 90MB and 105MB capacities,
Mitsubishi’s Flash ATA cards conform to the
JEIDA/PCMCIA standard.
68 pin PC Card Standard Type-I PC Card
Single 5V or 3.3V Supply
Card density of up to 105MB maximum
Four PC Card ATA and IDE ATA modes
Nonvolatile, No Batteries Required
High reliability based on internal ECC
function
Auto power-down mode
In default mode, the ATA card operates in PC
Card compliant sockets. It conforms to
PCMCIA2.1, JEIDA4.2 and PC Card Standard.
APPLICATIONS
Computers
Office automation
Industrial
When the OE# signal is asserted low level by
the Host system in power on cycle, the
Mitsubishi’s Flash ATA cards can be selected
in a IDE ATA interface. It uses the ATA
command set so no software drivers are
required.
Digital Camera
Data Communication
Consumer
MITSUBISHI
ELECTRIC
1
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
PRODUCT LIST
Memory
Data Bus
Memory
Cylinder
Head
Sector
capacity(Bytes)
width(bits)
MF007M5-03ATxx
MF0015M-03ATxx
MF0030M-03ATxx
MF0045M-03ATxx
MF0060M-03ATxx
MF0075M-03ATxx
MF0090M-03ATxx
MF0105M-03ATxx
7,864,320
15,728,640
31,457,280
47,185,920
62,914,560
78,643,200
94,371,840
110,100,480
64Mbit Flash x 1
64Mbit Flash x 2
64Mbit Flash x 4
64Mbit Flash x 6
64Mbit Flash x 8
64Mbit Flash x 10
64Mbit Flash x 12
64Mbit Flash x 14
240
480
480
720
960
600
720
840
2
2
4
4
4
8
8
8
32
32
32
32
32
32
32
32
8/16
PIN ASSIGNMENT
PC Card
Memory Mode
Signal
GND
D3
PC Card I/O
Mode
IDE ATA
Interface
Signal
GND
D3
PC Card
Memory Mode
PC Card I/O
Mode
Signal
IDE ATA
Interface
Signal
Pin
Pin
I/O
Signal
GND
D3
I/O
I/O
Signal
GND
CD1#
D11
I/O
I/O
I/O
-
1
-
-
-
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-
GND
CD1#
D11
-
O
I/O
I/O
I/O
I/O
I/O
I
GND
CD1#
D11
2
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I
3
D4
I/O
D4
I/O
D4
I/O
4
D5
I/O
D5
I/O
D5
I/O
D12
D12
D12
5
D6
I/O
D6
I/O
D6
I/O
D13
D13
D13
6
D7
I/O
D7
I/O
D7
I/O
D14
D14
D14
7
CE1#
A10
OE#
N.C
A9
I
CE1#
A10
OE#
N.C
A9
I
CS0#
N.U
I
D15
D15
D15
8
I
I
-
CE2#
VS1#
N.U
CE2#
VS1#
IORD#
IOWR#
N.C
CS1#
VS1#
IORD#
IOWR#
N.C
9
I
I
ATA SEL#
N.C
N.U
I
O
-
O
I
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
-
-
-
I
I
-
N.U
-
I
I
A8
I
A8
I
N.U
-
N.C
-
-
-
N.C
N.C
WE#
READY
Vcc
N.C
N.C
N.C
N.C
A7
-
N.C
N.C
WE#
IREQ#
Vcc
N.C
N.C
N.C
N.C
A7
-
N.C
N.C
WE#
INTRQ
Vcc
N.C
N.C
N.C
N.C
N.U
-
N.C
-
N.C
-
N.C
-
-
-
-
N.C
-
N.C
-
N.C
-
I
I
I
N.C
-
N.C
-
N.C
-
O
O
O
N.C
-
N.C
-
N.C
-
-
-
-
Vcc
-
Vcc
-
Vcc
-
-
-
-
N.C
-
N.C
-
N.C
-
-
-
-
N.C
-
N.C
-
N.C
-
-
-
-
N.C
-
N.C
-
N.C
-
-
-
-
N.C
-
N.C
-
N.C
-
I
I
-
CSEL
VS2#
RESET
WAIT#
N.U
I
CSEL
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
I
CSEL
VS2#
RESET#
IORDY
INPACK#
REG#
DASP#
PDIAG#
D8
I
A6
I
A6
I
N.U
-
O
I
O
I
O
I
A5
I
A5
I
N.U
-
-
A4
I
I
A4
I
I
N.U
O
-
O
O
I
O
O
I
A3
A3
N.U
-
A2
I
A2
I
A2
I
REG#
BVD2
BVD1
D8
I
A1
I
A1
I
A1
I
O
O
I/O
I/O
I/O
O
-
O
O
I/O
I/O
I/O
O
-
I/O
I/O
I/O
I/O
I/O
O
-
A0
I
A0
I
A0
I
D0
I/O
I/O
I/O
O
-
D0
I/O
I/O
I/O
O
-
D0
I/O
I/O
I/O
O
-
D1
D1
D1
D9
D9
D9
D2
D2
D2
D10
D10
D10
WP
GND
IOIS16#
GND
IOCS16#
GND
CD2#
GND
CD2#
GND
CD2#
GND
N.C = Not connected internally. N.U = Not used.
MITSUBISHI
ELECTRIC
2
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Signal Description
Signal Name
I/O
I
Pin No.
Description
Address bus[A10-A0]
8, 11, 12, 22,
23, 24, 25, 26,
27, 28, 29
Signals A10-A0 are address bus. A0 is invalid in
word mode. A10 is the MSB and A0 is the LSB.
Data bus[D15-D0]
I/O 41, 40, 39, 38,
37, 66, 65, 64,
6, 5, 4, 3,
Signals D15-D0 are data bus. D0 is the LSB of the
Even Byte of the Word. D8 is the LSB of the Odd
Byte of the Word.
2 ,32,31, 30
Card Enable[CE1#, CE2#]
(PC Card Memory Mode)
Card Enable[CE1#, CE2#]
(PC Card I/O Mode)
I
7, 42
CE1# and CE2# are low active card select signals.
Chip Select[CS0#, CS1#]
(IDE ATA Interface)
In IDE ATA Interface, CS0 is used to select the
Command Block Registers. CS1 is used to select
the Control Block Registers.
Output Enable[OE#]
(PC Card Memory Mode)
Output Enable[OE#]
(PC Card I/O Mode)
ATA SEL#
I
I
9
OE# is used to gate Attribute and Common Memory
Read data from the ATA Card.
OE# is used to gate Attribute Memory Read data
from the ATA Card.
To enable IDE ATA Interface, this input should be
grounded by the host.
WE# is used for strobing Attribute and Common
Memory Write data into the ATA Card.
WE# is used for strobing Attribute Memory Write
data into the ATA Card.
(IDE ATA Interface)
Write Enable[WE#]
(PC Card Memory Mode)
Write Enable[WE#]
(PC Card I/O Mode)
Write Enable[WE#]
(IDE ATA Interface)
I/O Read[IORD#]
(PC Card I/O Mode)
I/O Read[IORD#]
(IDE ATA Interface)
I/O Write[IOWR#]
(PC Card I/O Mode)
I/O Write[IOWR#]
(IDE ATA Interface)
Ready[READY]
15
This input should be connected Vcc by the host.
I
I
44
45
16
IORD# is used to read data from the Card’s I/O
space.
IOWR# is used to write data to the Card’s I/O
space.
O
READY signal is set high when the ATA Card is
ready to accept a new data transfer operation.
This signal of low level is indicates that the card is
requesting software service to host, and high level
indicates that the card is not requesting.
This signal is active high interrupt request to the
host.
CD1# and CD2# provided for proper detection of
PC Card insertion.
This signal is held low because this card does not
have a write protect switch.
(PC Card Memory Mode)
IREQ#
(PC Card I/O Mode)
INTRQ
(IDE ATA Interface)
Card Detection[CD1#, CD2#]
O
O
36, 67
33
Write Protect[WP]
(PC Card Memory Mode)
IOIS16#
(PC Card I/O Mode)
IOCS16#
This output signal is asserted when the I/O port
address is capable of 16-bit access.
(IDE ATA Interface)
MITSUBISHI
ELECTRIC
3
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Attribute Memory Select[REG#]
(PC Card Memory Mode)
Attribute Memory Select[REG#]
(PC Card I/O Mode)
Attribute Memory Select[REG#]
(IDE ATA Interface)
Battery Voltage Detect[BVD2]
(PC Card Memory Mode)
Audio Digital Waveform[SPKR#]
(PC Card I/O Mode)
I
61
62
58
59
When this signal is asserted, access is limited to
Attribute Memory with OE#/WE# and I/O Space with
IORD#/IOWR#.
This input signal is not used for this mode and
should be connected to Vcc by the host.
This output is driven to a high-level.
O
SPKR# is kept negated because this Card does not
have digital audio output.
This signal is the DISK Active/Slave Present signal
in the Master/Slave handshake protocol.
By assertion of this signal, all registers of this Card
are cleared. This signal should be kept to High-Z by
the host for at least 1ms after Vcc applied.
DASP#
(IDE ATA Interface)
I/O
I
Card Reset[RESET]
(PC Card Memory Mode)
Card Reset[RESET]
(PC Card I/O Mode)
Card Reset[RESET#]
(IDE ATA Interface)
Wait[WAIT#]
(PC card Memory Mode)
Wait[WAIT#]
This input pin is the active low hardware reset from
the host.
This signal is asserted to delay completion of the
memory or I/O access cycle.
O
(PC card I/O Mode)
IORDY
(IDE ATA Interface)
Input Port Acknowledge[INPACK#]
(PC Card I/O Mode)
Input Port Acknowledge[INPACK#]
(IDE ATA Interface)
Battery Voltage Detect[BVD1]
(PC Card Memory Mode)
STSCHG#
O
O
60
63
This signal is asserted when the Card is selected
and can respond to an I/O Read cycle at the
address on the address bus.
This output is driven to a high-level.
This signal is asserted low to alert the host to
changes in the status of Configuration Status
Register in the Attribute Memory Space.
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
VS1 is grounded so that the Card CIS can be read
at 3.3V and VS2 is N.C.
This signal is not used for this mode.
(PC Card I/O Mode)
PDIAG#
(IDE ATA Interface)
Voltage Sense[VS1, VS2]
I/O
O
-
43, 57
56
Cable Select[CSEL]
(PC card Memory Mode)
Cable Select[CSEL]
(PC card I/O Mode)
Cable Select[CSEL]
(IDE ATA Interface)
-
I
This signal is used to configure this Card as a
Master or a Slave. When this signal is grounded,
this Card is configured as a Master. When this
signal is Open, this Card is configure as a Slave.
5V or 3.3V power.
Vcc
GND
-
-
17, 51
1, 34, 35, 68
Ground.
MITSUBISHI
ELECTRIC
4
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
BLOCK DIAGRAM
Vcc
GND
Internal Vcc
Controller
A10-A0
CE1#/CS0#
CE2#/CS1#
OE#/ATA SEL#
WE#
IORD#
IOWR#
REG#
RESET/RESET#
POR#
RESET Circuit
RES#
64Mbit AND
CE#
OE#
WE#
CDE#
SC
Flash Memory
(x14)
D15-D0
READY/IREQ#/INTRQ
WP/IOIS16#/IOCS16#
INPACK#
I/O7-I/O0
R/B#
BVD1/STSCHG#/PDIAG#
BVD2/SPKR#/DASP#
WAIT#/IORDY
XIN
CSEL
XOUT
X-TAL
VS1
VS2
Open
CD1#
CD2#
MITSUBISHI
ELECTRIC
5
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
FUNCTION TABLE
Function
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D15-D8
D7-D0
Attribute Memory Read Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
Even Byte
Invalid
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
Attribute Memory Write Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
Even Byte
don’t care
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
Common Memory Read Function
Standby
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Odd Byte
Odd Byte
High-Z
Even Byte
Odd Byte
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
Common Memory Write Function
Standby
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
don’t care
don’t care
don’t care
Odd Byte
Odd Byte
don’t care
Even Byte
Odd Byte
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
I/O Read Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
High-Z
High-Z
High-Z
Odd Byte
Odd Byte
High-Z
Even Byte
Odd Byte
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
I/O Write Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
don’t care
don’t care
don’t care
Odd Byte
Odd Byte
don’t care
Even Byte
Odd Byte
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
MITSUBISHI
ELECTRIC
6
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Memory mapped mode(Index=0)
REG# CE2# CE1# A10 A9-A4 A3 A2 A1 A0
Register
OE#=”L”
WE#=“L”
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
1
x
x
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Data Register(D15-D0)
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
x
x
x
x
0
0
0
0
0
0
0
1
1
1
1
0
0
1
x
x
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
x
x
x
x
0
0
0
0
1
1
1
1
0
0
0
1
0
1
x
x
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
x
x
0
1
x
x
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Error Register(D15-D8)
Feature Register(D15-D8)
invalid
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
x
x
x
x
1
1
1
1
1
1
1
1
0
0
0
1
0
1
x
x
invalid
Error Register(D7-D0)
Error Register(D15-D8)
Feature Register(D7-D0)
Feature Register(D15-D8)
Device Control Register(D7-D0)
invalid
Device Control Register(D7-D0)
invalid
invalid
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
x
x
x
x
x
x
x
1
1
1
x
x
x
x
1
1
1
x
x
x
x
1
1
1
x
x
x
x
0
1
x
x
0
1
x
MITSUBISHI
ELECTRIC
7
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Contiguous I/O Map(Index=1)
REG#
CE2# CE1#
A9-A4
A3
A2
A1
A0
Register
IORD#=”L”
IOWR#=“L”
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
1
x
0
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Data Register(D15-D0)
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
0
0
0
0
1
1
0
0
0
0
1
0
x
x
x
x
0
0
0
0
0
0
0
1
1
1
1
0
0
1
x
0
0
0
0
0
1
1
0
0
0
0
1
0
x
x
x
x
0
0
0
0
1
1
1
1
0
0
0
1
0
1
x
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
1
0
x
x
x
x
x
x
x
x
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
x
x
0
1
x
0
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Error Register(D15-D8)
Feature Register(D15-D8)
invalid
0
0
0
0
1
1
0
0
0
0
1
0
x
x
x
x
1
1
1
1
1
1
1
1
0
0
0
1
0
1
x
0
invalid
Error Register(D7-D0)
Error Register(D15-D8)
Feature Register(D7-D0)
Feature Register(D15-D8)
Device Control Register(D7-D0)
invalid
Device Control Register(D7-D0)
invalid
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
0
0
0
1
1
0
0
0
1
x
x
x
1
1
1
1
1
1
1
1
1
0
1
x
invalid
MITSUBISHI
ELECTRIC
8
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Primary(Secondary) I/O(Index=2, 3)
REG# CE2# CE1#
A9-A4
A3 A2 A1 A0
Register
IORD#=”L”
IOWR#=“L”
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1Fh(17h)
1Fh(17h)
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
1
x
0
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Device Control Register(D7-D0)
invalid
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
0
0
0
0
1
1
0
0
0
0
1
0
1Fh(17h)
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
0
0
0
0
1
1
1
1
0
0
1
x
0
0
0
0
0
1
1
0
0
0
0
1
0
1Fh(17h)
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
0
1
1
1
1
0
0
0
1
0
1
x
0
0
0
0
0
1
1
0
0
0
0
1
0
1Fh(17h)
1Fh(17h)
1Fh(17h)
3Fh(37h)
0
0
0
1
1
1
1
1
1
1
1
1
0
1
x
0
0
0
0
1
1
0
0
0
1
3Fh(37h)
3Fh(37h)
3Fh(37h)
1
1
1
1
1
1
1
1
1
0
1
x
Device Control Register(D7-D0)
invalid
invalid
IDE ATA Interface
CS1#
CS0#
A2-A0
Register
IORD#=”L”
IOWR#=“L”
Data Register(D15-D0)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0h
1h
2h
3h
4h
5h
6h
7h
6h
7h
Data Register(D15-D0)
Error Register(D7-D0)
Feature Register(D7-D0)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Device Control Register(D7-D0)
invalid
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Drive Head Register(D7-D0)
Status Register(D7-D0)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
MITSUBISHI
ELECTRIC
9
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Configuration Register Specifications
Pin Replacement Register
This register is used for providing the signal state of
READY signal when the card configured I/O card
interface.
Configuration Option Register
This register is used for the configuration of the card
configuration status and for the issuing soft reset to the
card.
D7
0
D6
0
D5
CREADY
D4
0
D3
1
D2
1
D1
RREADY
D0
0
D7
SRESET
D6
LevIREQ
D5
D4
D3
D2
Index
D1
D0
Name
CREADY
R/W
R/W
Description
This bit is set to “1” when the RREADY bit
changes state. This bit may also be written by
the host.
When read, this bit indicates READY pin
states. When written, this bit acts as a mask
for writing the CREADY bit.
Name
SRESET
R/W
R/W
Description
Setting this bit to “1”, places the card in the reset
state. When the host returns this bit to “0”, the
function shall enter the same unconfigured,
reset state as the card does following a power-
up and hardware reset.
RREADY
R/W
LevIREQ
Index
R/W
R/W
If this bit is set to “0”, card generates pulse
mode interrupt. If this bit is set to “1”, card
generates level mode interrupts.
This bits is used for select operation mode of the
card as follows.
When Power on, Card Hard Reset and Soft
reset, this data is “000000” for the purpose of
Memory card interface recognition.
Index: 0 -> Memory mapped
Socket and Copy Register
This register is used for identification of the card from the
other cards. Host can read and write this register. This
register should be set by host before this card’s
Configuration Option register set.
D7
0
D6
D5
D4
D3
D2
D1
D0
1 -> Contiguous I/O mapped
2 -> Primary I/O mapped
3 -> Secondary I/O mapped
Copy Number
Socket Number
Name
R/W
Description
Configuration and Status Register
Copy Number
R/W
R/W
This bit indicates the drive number of the
card for twin card configuration.
This register is used for observing the card state.
And the host can select and drive one card
by comparing the number in this field with
the drive number of Drive Head Register.
In the way, the host can perform the card’s
master/slave organization.
D7
Changed
D6
SigChg
D5
Iois8
D4
0
D3
0
D2
PwrDwn
D1
Intr
D0
0
Socket
Number
This field indicates to the card that it is
located in the n’th socket.
Name
Changed
R/W
R/O
Description
This bit indicates that CREADY bit on the Pin
Replacement register is set to “1”. When
Changed bit is set to “1”, STSCHG# pin is held
“L” if the SigChg bit is “1” and the card is
configured for the I/O interface.
SigChg
R/W
This bit is set or reset by the host for enabling
and disabling the status change
signal(STSCHG# pin). When the card is
configured I/O card interface and this bit is set
to “1”, STSCHG# pin is controlled by Changed
bit. If this bit is set to “0”, STSCHG# pin is kept
“H”.
Iois8
R/W
R/W
This card is always configured for both 8-bit
and 16-bit I/O, so this bit is ignored.
PwrDwn
When this bit is set to “1”, the card enters
Power Down mode. When this bit is reset to
“0”, the host is requesting the card to enter the
active mode. RREADY bit on Pin Replacement
Register becomes BUSY when this bit is
changed. RREADY will not become Ready until
the power state requested has been entered.
This card automatically powers down when it is
idle, and powers back up when it receives a
command.
Intr
R/W
This bit represents the internal state of the
interrupt request. This bit state is available
whether I/O card interface has been configured
or not. This signal remains true until the
condition which caused the interrupt request
has been serviced. If interrupts are disabled by
the nIEN bit in the Device Control Register, this
bit is a zero.
MITSUBISHI
ELECTRIC
10
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
CIS Information
CIS informatoins are defined as follows.
Offset
0000h
0002h
Data
01h
03h
7
6
5
4
3
2
1
0
Description
Common Memory device information
Link to next tuple
CISTPL_DEVICE
TPL_LINK
Device Type=Dh : Function specific
0004h
D9h
Device Type
1x
WPS
Device Speed
2K
WPS=1
Device Speed=1 : 250ns
2kBytes of address space
: No WPS
0006h
0008h
000Ah
000Ch
000Eh
01h
FFh
1Ch
05h
02h
Marks end of Device Info fields
CISTPL_DEVICE_OC
TPL_LINK
Other Conditions Device information
Link to next tuple
EXT=0, Vcc=5.0V, Wait is not used.
Device Type=Dh : Function specific
WPS=1
Device Speed=250ns
EXT
EXT
Reserved
Device Type
1x
Vcc
MWAIT
0010h
DFh
WPS
Device Speed
2K
: No WPS
0012h
0014h
0016h
0018h
001Ah
01h
FFh
1Ch
04h
02h
2kbytes of address space
Marks end of Other Conditions Device Info
CISTPL_DEVICE_OC
Other Conditions Device information
Link to next tuple
EXT=0, Vcc=3.3V, Wait is not used.
Device Type=Dh : Function specific
WPS=1
Device Speed=250ns
TPL_LINK
Reserved
Device Type
1x
Vcc
MWAIT
001Ch
D9h
WPS
Device Speed
2K
: No WPS
001Eh
0020h
0022h
0024h
0026h
0028h
002Ah
002Ch
002Eh
0030h
0032h
0034h
0036h
0038h
003Ah
003Ch
003Eh
0040h
0042h
0044h
0046h
0048h
004Ah
004Ch
004Eh
0050h
0052h
0054h
0056h
0058h
005Ah
005Ch
005Eh
0060h
0062h
0064h
0066h
0068h
01h
FFh
18h
02h
DFh
01h
20h
04h
1Ch
00h
01h
00h
15h
26h
04h
01h
4Dh
49h
54h
53h
55h
42h
49h
53h
48h
49h
20h
41h
54h
41h
20h
43h
41h
52h
44h
00h
4Dh
46h
2kbytes of address space
Marks end of Other Conditions Device Info
CISTPL_JEDEC_C
JEDEC Identifier Tuples
Link to next tuple
PC Card ATA
with no Vpp require for any operation
Manufacturer Identification Tuple
Link to next tuple
TPL_LINK
JEDEC identifier for first device info entry.
JEDEC identifiers for remaining device info entries.
CISTPL_MANFID
TPL_LINK
PC Card manufacturer code
001Ch
manufacturer information
0001h
CISTPL_VERS_1
TPL_LINK
TPLLV1_MAJOR
TPLLV1_MINOR
TPLLV1_INFO
Level 1 Version / Product Information
Link to next tuple
PCMCIA2.0 / JEIDA4.1
PCMCIA2.0 / JEIDA4.1
M
I
T
S
U
B
I
S
H
I
A
T
A
C
A
R
D
M
F
MITSUBISHI
ELECTRIC
11
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
006Ah
006Ch
006Eh
0070h
0072h
0074h
0076h
0078h
007Ah
007Ch
007Eh
0080h
0082h
0084h
0086h
0088h
008Ah
008Ch
30h
78h
78h
78h
78h
2Dh
30h
33h
41h
54h
58h
78h
00
0
x
x
x
x
-
0
3
A
T
x
x
FFh
21h
02h
04h
01h
Marks end of chain.
Function Identification Tuple
Link to next tuple
PC Card ATA(Fixed Disk)
ROM=0 : No BIOS ROM
CISTPL_FUNCID
TPL_LINK
Card Function Code
Reserved
ROM
POST
POST=1: Configure card at power on
008Eh
0090h
0092h
0094h
0096h
0098h
009Ah
009Ch
22h
02h
01h
01h
22h
03h
02h
04h
CISTPL_FUNCE
TPL_LINK
Disk Function Extension Tuple Type
Disk Interface Type
CISTPL_FUNCE
TPL_LINK
Disk Function Extension Tuple Type
Function Extension Tuple
Link to next tuple
Disk Interface Type
PC Card ATA Interface
Function Extension Tuple
Link to next tuple
Basic PC Card ATA Interface tuple
V=0 : No Vpp Required
RFU
I
D
U
S
V
S=1 : Silicon
U=0 : ID Drive Mfg/SN not Unique
D=0 : Single Drive on Card
P0=1 : Sleep Mode Supported
P1=1 : Standby Mode Supported
P2=1 : Idle Mode Supported
P3=1 : Drive Auto Power Control
N=0 : No Configs exclude I/O port
3F7H/377H
009Eh
0Fh
RFU
E
N
P3
P2
P1
P0
E=0 : Index bit is not emulated
I=0 : IOIS16# use is Unspecified on
Twin Card Configurations
00A0h
00A2h
00A4h
1Ah
05h
01h
CISTPL_CONF
TPL_LINK
RMS
Configuration Tuple
Link to next tuple
RFS
RAS
RFS=0 : No Reserved Field
RMS=0 : 1 Byte Register Mask
RAS=1 : 2 Byte Config Base Address
Last Index = 3
Configuration Registers are located
at 200H in Reg Space
First 4 Configuration Registers present
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 0
Mem Interface; Bvd's and wProt not
used; Ready active and Wait not used
for memory cycles.
00A6h
00A8h
00AAh
00ACh
00AEh
00B0h
00B2h
03h
00h
02h
0Fh
1Bh
08h
C0h
TPCC_LAST
TPCC_RADR (lsb)
TPCC_RADR (msb)
RFU
RFU
RFU
E
S
P
C
I
CISTPL_CFTABLE_ENTRY
TPL_LINK
I
D
R
Configuration Index
00B4h
40h
W
P
B
Interface Type
00B6h
00B8h
00BAh
00BCh
00BEh
00C0h
00C2h
00C4h
00C6h
A1h
01h
55h
08h
00h
21h
1Bh
05h
00h
M
R
X
MS
IR
AI
Mantissa
Length in 256 bytes pages (lsb)
Length in 256 bytes pages (msb)
IO
SI
T
HV
P
Has Vcc, Mem Space and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
Length of Mem Space is 2 KB
Starts at 0 on card
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
DI
PI
LV
NV
Exponent
X
I
RFU
D
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Index
No Interface Byte, Non Default Entry,
MITSUBISHI
ELECTRIC
12
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Configuration Index = 0
00C8h
00CAh
00CCh
00CEh
00D0h
00D2h
00D4h
01h
01h
B5h
1Eh
1Bh
0Ah
C1h
M
R
X
MS
IR
AI
Mantissa
Extension
CISTPL_CFTABLE_ENTRY
TPL_LINK
IO
SI
T
HV
P
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
DI
PI
LV
Exponent
NV
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 1
I/O Interface; Bvd's and wProt not
used; Ready active and Wait not used
for memory cycles.
I
D
R
Configuration Index
00D6h
41h
W
P
B
Interface Type
00D8h
00DAh
00DCh
00DEh
99h
01h
55h
64h
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
P
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
I/O : Range=0, Bus16=1, Bus8=1,
IO AddrLines=4
DI
S
PI
HV
LV
Exponent
IO AddrLines
NV
R
E
00E0h
00E2h
00E4h
00E6h
00E8h
00EAh
00ECh
F0h
FFh
FFh
21h
1Bh
05h
01h
S
IRQ7
P
IRQ6
L
IRQ5
M
IRQ4
Level or Mask
Share=1, Pulse=1, Level=1, Mask=1
IRQ Level to be routed 0 - 15
recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
No Interface Byte, Non Default Entry,
Configuration Index = 1
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
IRQ3
IRQ2
IRQ1
IRQ9
T
IRQ0
IRQ8
IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
X
RFU
P
RO
A
CISTPL_CFTABLE_ENTRY
TPL_LINK
I
D
Configuration Index
00EEh
00F0h
00F2h
00F4h
00F6h
00F8h
00FAh
01h
01h
B5h
1Eh
1Bh
0Fh
C2h
M
R
X
MS
IR
AI
IO
SI
T
P
DI
PI
HV
LV
NV
Mantissa
Exponent
Extension
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 2
I/O Interface; Bvd's and wProt not
used; Ready active and Wait not used
for memory cycles.
I
D
R
Configuration Index
00FCh
41h
W
P
B
Interface Type
00FEh
0100h
0102h
0104h
99h
01h
55h
EAh
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
P
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
I/O : Range=1, Bus16=1, Bus8=1,
IO AddrLines=10
DI
S
PI
HV
LV
Exponent
IO AddrLines
NV
R
E
0106h
61h
LS
AS
N Ranges
Number of Address Ranges = 2
Address Size = 2
Length Size = 1
0108h
010Ah
010Ch
010Eh
0110h
0112h
0114h
F0h
01h
07h
F6h
03h
01h
EEh
First I/O Base Address (LSB)
First I/O Base Address (MSB)
First I/O Length minus 1
Second I/O Base Address (LSB)
Second I/O Base Address (MSB)
Second I/O Length minus 1
First I/O Base Address = 1F0h
First I/O Range is 8 Byte Length
Second I/O Base Address = 3F6h
Second I/O Range is 2 Byte Length
Share=1, Pulse=1, Level=1, Mask=0,
IRQ14 is recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
No Interface Byte, Non Default Entry,
Configuration Index = 2
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
S
X
P
L
M
IRQ Level
0116h
0118h
011Ah
011Ch
21h
1Bh
05h
02h
RFU
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
I
D
Configuration Index
011Eh
0120h
0122h
0124h
0126h
0128h
012Ah
01h
01h
B5h
1Eh
1Bh
0Fh
C3h
M
R
X
MS
IR
AI
IO
SI
T
HV
P
DI
PI
LV
Exponent
NV
Mantissa
Extension
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
I
D
Configuration Index
MITSUBISHI
ELECTRIC
13
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Configuration Index = 3
012Ch
41h
W
R
P
B
Interface Type
T
I/O Interface; Bvd's and wProt not
used; Ready active and Wait not used
for memory cycles.
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
012Eh
0130h
0132h
0134h
99h
01h
55h
EAh
M
R
X
MS
IR
AI
IO
SI
P
DI
S
PI
HV
LV
Exponent
IO AddrLines
NV
Mantissa
E
R
I/O : Range=1, Bus16=1, Bus8=1,
IO AddrLines=10
0136h
61h
LS
AS
N Ranges
Number of Address Ranges = 2
Address Size = 2
Length Size = 1
0138h
013Ah
013Ch
013Eh
0140h
0142h
0144h
70h
01h
07h
76h
03h
01h
EEh
First I/O Base Address (LSB)
First I/O Base Address (MSB)
First I/O Length minus 1
Second I/O Base Address (LSB)
Second I/O Base Address (MSB)
Second I/O Length minus 1
First I/O Base Address = 170h
First I/O Range is 8 Byte Length
Second I/O Base Address = 376h
Second I/O Range is 2 Byte Length
Share=1, Pulse=1, Level=1, Mask=0,
IRQ14 is recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
No Interface Byte, Non Default Entry,
Configuration Index = 3
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
S
X
P
L
M
IRQ Level
0146h
0148h
014Ah
014Ch
21h
1Bh
05h
03h
RFU
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
I
D
Configuration Index
014Eh
0150h
0152h
0154h
0156h
01h
01h
B5h
1Eh
FFh
M
R
X
MS
IR
AI
IO
SI
T
HV
P
DI
PI
LV
Exponent
NV
Mantissa
Extension
CISTPL_END
End of List Tuple
MITSUBISHI
ELECTRIC
14
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
ATA Register Specifications
Sector Number Register
This register is written by the host with the starting sector
number to be used in the subsequent Cylinder-Head-
Sector command. After the command is complete, the
host may read the final sector number from this register.
When logical block addressing is used, this register is
written by the host with bit7 to 0 of the starting logical
block number and contains bit7 to 0 of the final logical
block number after the command is complete.
Data Register
This register is a 16 bit register which is used to transfer
data blocks between the card data buffer and the host.
Data may be transferred by either a series of word
accesses to the Data register or a series of byte accesses
to the Data register.
D15
D14
D13
D12
Data Word
Odd Data Byte
D11
D10
D9
D8
D0
D7
D6
D5
D4
Sector Number
Logical Block Number bits A07-A00(LBA Addressing)
D3
D2
D1
D0
D0
D0
D7
D6
D5
D4
D3
D2
D1
Data Word
Data Byte
Cylinder Low Register
This register is written by the host with the low-order byte
of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the low-order
byte of the final cylinder number from this register. When
logical block addressing is used, this register is written by
the host with bits15 to 8 of the starting logical block
number and contains bits15 to 8 of the final logical block
number after the command complete.
Error Register
This register contains additional information about the
source of an error which has occurred in processing of the
preceding command. This register should be checked by
the host when ERR bit in the Status register is set. The
Error register is a read only register.
D7
BBK
D6
UNC
D5
0
D4
IDNF
D3
0
D2
ABRT
D1
0
D0
AMNF
D7
D6
D5
D4
Cylinder Low Byte
Logical Block Number bits A15-A08(LBA Addressing)
D3
D2
D1
Field
BBK
function
This bit is set when a Bad Block is detected in requested ID
field. Host can not read/write on data area that is marked as
a Bad Block.
Cylinder High Register
This register is written by the host with the high-order byte
of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the high-order
byte of the final cylinder number from this register. When
logical block addressing is used, this register is written by
the host with bits 23 to 16 of the starting logical block
number and contains bits23 to 16 of the final logical block
number after the command is complete.
UNC
This bit is set when Uncorrectable error is occurred at
reading the card.
IDNF
ABRT
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because of
the card status condition. (Not ready, Write fault, etc.) or
when an invalid command has been issued.
This bit is set in case of a general error.
AMNF
Feature Register
This register is written by the host to provide command
specific information to the drive regarding features of the
drive which the host wish to utilize. The Feature register is
a write only register.
D7
D6
D5
D4
Cylinder High Byte
Logical Block Number bits A23-A16(LBA Addressing)
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
D0
Drive/Head Register
Feature byte
The Drive/Head register is used to specify the selected
drive of a pair of drives sharing a set of registers.
Sector Count Register
This register is written by the host with the number of
sectors or blocks to be processed in the subsequent
command. After the command is complete, the host may
read this register to obtain the count of sectors left
unprocessed by the command.
D7
X
D6
LBA
D5
X
D4
DRV
D3
HS3
LBA27
D2
HS2
LBA26
D1
HS1
LBA25
D0
HS0
LBA24
Field
X
LBA
function
D7
D6
D5
D4
D3
D2
D1
D0
Undefined . “0” or “1”.
Sector Count
This bit is “0” for CHS addressing and “1” for Logical
Block addressing.
DRV
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected.
When DRV is set, Drive1 is selected. The card is
selected to be Drive0 or to be Drive1 using the “Copy”
field of the PC Card Socket Copy Register.
MITSUBISHI
ELECTRIC
15
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
HS3-0
LBA27-24
HS3-0 of the head number in CHS addressing or LBA27-
24 of the Logical Block Number in LBA addressing.
D7
X
D6
nWTG
D5
D4
nHS3-0
D3
D2
D1
nDS1
D0
nDS0
Status and Alternate Status Registers
The Status register and the Alternate Status register return
the card status when read by the host. Reading the Status
register clears a pending interrupt request while reading the
Alternate Status register does not. The Status register and
the Alternate Status register are read only registers.
Field
X
nWTG
function
This bit is unknown.
This bit is set to “0” when a Flash write operation is in
progress, otherwise it is set to “1”.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to “0” when Slave drive is active and
selected.
nHS3-0
nDS1
D7
D6
D5
D4
D3
D2
D1
IDX
D0
ERR
nDS0
This bit is set to “0” when Master drive is active and
selected.
BSY
DRDY
DWF
DSC
DRQ
CORR
Field
function
BSY
This bit is set when the card internal operation is
executing. When this bit is set to “1”, other bits in this
register are invalid.
DRDY
DRDY indicates whether the card is capable of
performing card operations.
DWF
DSC
DRQ
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
CORR
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to “0”.
IDX
ERR
This bit is set when the previous command has ended in
some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
Command Register
The Command register contains the command code being
sent to the device. Command execution begins immediately
after this register is written. The Command register is a
write only register.
D7
D6
D5
D4
D3
D2
D1
D0
Command
Device Control Register
This register is used to control the card interrupt request
and to issue a soft reset to the card. The Device Control
register is a write only register.
D7
X
D6
X
D5
X
D4
X
D3
1
D2
SRST
D1
nIEN
D0
0
Field
X
function
don’t care.
1
This bit is set to “1”.
SRST
This bit is set to “1” in order to force the card to perform a
Command Block Reset operation. This does not change the
Card Configuration registers as a Hardware Reset does.
The card remains in Reset until this bit is reset to “0”.
This bit is used for enabling IREQ#. When this bit is set to
“0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is
disabled.
nIEN
0
This bit is set to “0”.
Drive Address Register
This register is provided for compatibility with the AT disk
drive interface.
MITSUBISHI
ELECTRIC
16
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
ATA Command Specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command
codes which are written in command registers.
Command
Check Power Mode
Execute Drive Diagnostic
Erase Sector(s)
Format Track
Code
98h, E5h
90h
C0h
50h
ECh
97h, E3h
95h, E1h
91h
E4h
22h, 23h
C4h
20h, 21h
40h, 41h
1xh
FR
SC
SN
y
CY
DR
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
HD
y
y
y
y
y
y
Identify Drive
Idle
y
y
Idle Immediate
Initialize Drive Parameters
Read Buffer
Read Long Sector
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Recalibrate
Request Sense
Seek
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
03h
7xh
EFh
C6h
y
y
y
Set Features
y
y
y
Set Multiple mode
Set Sleep Mode
Standby
Standby Immediate
Wear Level
Write Buffer
Write Long Sector
Write Multiple
Write Multiple without Erase
Write Sector(s)
Write Sector without Erase
Write Verify
99h, E6h
96h, E2h
94h, E0h
F5h
E8h
32h, 33h
C5h
CDh
30h, 31h
38h
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
3Ch
FR : Feature Register,
SC : Sector Count Register,
SN : Sector Number Register,
DR Drive bit of Drive/Head Register,
CY : Cylinder Low/High Register,
HD : Head No. of Drive/Head Register,
MITSUBISHI
ELECTRIC
17
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Check Power Mode(98h, E5h)
This command checks the power mode.
Read Verify Sector(s)(40h, 41h)
This command is identical to the Read Sector(s)
command, except that DRQ is not asserted, and no data is
transferred to the host.
Execute Drive Diagnostic(90h)
This command performs the internal diagnostic tests
implemented by the card.
Recalibrate(1xh)
Although this command is supported for backward
compatibility, it has no actual function. The card will
always return good status at the completion of this
command.
Erase Sector(s)(C0h)
This command is used to pre-erase and condition data
sectors in advance of a Write without Erase or Write
Multiple without Erase command.
Request Sense(03h)
Format Track(50h)
This command requests extended error information for the
previous command.
This command writes the desired head and cylinder of the
selected drive with a FFh pattern.
Seek(7xh)
Identify Drive(ECh)
This command is supported for backward compatibility.
Although this command has no actual function, it does
perform a range check of valid track, and posts an IDNF
error if the Head or Cylinder specified are out of bounds.
This command enables the host to receive parameter
information from the card. (Refer to the Identify Drive
Information table.)
Idle(97h, E3h)
Set Features(EFh)
This command is used by the host to establish or select
certain features.
This command causes the card to set BSY, enter the Idle
mode, clear BSY and generate an interrupt. If the sector
count is non-zero, the automatic power down mode is
enabled. If the sector count is zero, the automatic power
down mode is disabled.
Set Multiple Mode(C6h)
This command enables the card to perform Read and
Write Multiple operations and establishes the block count
for these commands. This card supports 1 sector block
size.
Idle Immediate(95h, E1h)
This command causes the card to set BSY, enter the idle
mode, clear BSY and generate an interrupt.
Set Sleep Mode(E6h, 99h)
This command causes the card to set BSY, enter the Sleep
mode, clear BSY and generate an interrupt.
Initialize Drive Parameters(91h)
This command allows the host to alter the number of
sectors per track and the number of heads per cylinder.
Standby(96h, E2h)
Read Buffer(E4h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
This command enables the host to read the current
contents of the card’s sector buffer.
Standby Immediate(94h, E0h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
Read Long Sector(22h, 23h)
This command is similar to the Read Sector(s) command
except the contents of the Sector Count register are
ignored and only one sector is read. The 512 data bytes
and 4 ECC bytes are read into the buffer(with no ECC
correction) and then transferred to the host.
Wear Leveling(F5h)
Although this command is supported for backward
compatibility, it has no actual function. The card will
always return good status at the completion of this
command.
Read Multiple(C4h)
This command performs similarly to the Read Sector(s)
command. Interrupt are not generated on each sector, but
on the transfer of a block which contains the number of
sectors defined by a Set Multiple command.
Write Buffer(E8h)
This command enables the host to overwrite contents of
the card’s sector buffer with any data pattern desired. This
command has the same protocol as the Write Sector(s)
command and transfers 512 bytes.
Read Sector(s)(20h, 21h)
This command transfers data from the card to the host.
Data transfer starts at the sector specified by the Cylinder,
Head, and Sector Number registers, and proceeds for the
number of sectors specified in the Sector Count register.
Write Long Sector(32h, 33h)
This command is similar to the Write Sector(s) except the
contents of the Sector Count register are ignored and only
MITSUBISHI
ELECTRIC
18
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
one sector is written. The 512 data bytes and 4 ECC bytes
are transferred from the host and then written from the
buffer to the flash.
Write Multiple(C5h)
This command is similar to the Write Sector(s) command.
Interrupts are not presented on each sector, but on the
transfer of a block which contains the number of sectors
defined by Set Multiple command.
Write Sector(s)(30h, 31h)
This command transfers data from the host to the card.
Data transfer starts at the sector specified by the Cylinder,
Head, and Sector Number registers, and proceeds for the
number of sectors specified in the Sector Count register.
Write Verify(3Ch)
This command is similar to the Write Sector(s) command,
except each sector is verified immediately after being
written.
MITSUBISHI
ELECTRIC
19
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Identify Drive Information
Word Address
Data
Description
0
848Ah
General configuration bit-significant information
15
14
13
12
11
10
9
8
7
6
5
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
Non-rotating disk drive
Format speed tolerance gap not required
Track offset option not available
Data strobe offset option not available
Rotational speed tolerance is < 0.5%
Disk transfer rate > 10Mbs
10Mbs <= Disk transfer rate > 5Mbs
Disk transfer rate <= 5Mbs
Removable cartridge drive
Not a fixed drive
Spindle motor control option not implemented
Head switch time > 15us
Not MFM encoded
Not soft sectored
Hard sectored
4
3
2
1
0
Reserved
1
2
3
4
5
6
xxxxh
0000h
000xh
4000h
0200h
0020h
Number of Cylinders
Reserved
Number of Heads
Number of unformatted bytes per track
Number of unformatted bytes per sector
Number of sectors per track
7-8
9
10-19
20
21
22
23-26
27-46
47
48
49
50
51
52
53
54
55
56
57
xxxxh, xxxxh
0000h
2020h
0001h
0001h
0004h
xxxxh
xxxxh
0001h
0000h
0200h
0000h
0100h
0000h
0001h
xxxxh
xxxxh
xxxxh
xxxxh
0000h
010xh
xxxxh
xxxxh
0000h
Number of sectors per card (word 7 = MSW, word 8 = LSW)
Reserved
Reserved
Buffer type: Single ported, single-sector, w/read cache
Buffer size, in 512 byte increments
ECC length used on Read and Write Long command
Firmware revision, 8 ASCII chars
Model number, 40 ASCII chars.
Maximum Block Count=1 for Read/write Multiple commands
Cannot perform doubleword I/O
Capabilities: LBA supported, DMA not supported
Reserved
PIO timing cycle timing mode 1
DMA transfer not supported
Words 54-58 are valid
Number of Current Cylinders
Number of Current Heads
Number of Current Sectors per Track
LSW of the Current Capacity in Sectors
MSW of the Current Capacity in Sectors
Current Setting for Block Count for R/W Multiple commands
LSW of the total number of user addressable LBA mode
MSW of the total number of user addressable LBA mode
Reserved
58
59
60
61
62-255
MITSUBISHI
ELECTRIC
20
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Vi
Vo
Pd
Parameter
Supply voltage
Input voltage
Conditions
With respect to GND
Ta = 25 °C
Ratings
-0.3~7.0
-0.3~VCC+0.3
-0.3~VCC+0.3
1.2
Unit
V
V
Output voltage
V
Power dissipation
Operating temperature
Storage temperature
W
°C
°C
Topr
Tstg
0~60
-10~80
RECOMMENDED OPERATING CONDITIONS
Limits
Parameter
Symbol
Unit
Min.
4.5
3.135
Typ.
5.0
3.3
0
Max.
5.5
3.465
VCC(5V)
VCC(3.3V)
GND
VCC Supply voltage
VCC Supply voltage
System ground
V
V
V
V
V
VIH
VIL
High input voltage
Low input voltage
0.7VCC
0
VCC
0.8
DC ELECTRICAL CHARACTERISTICS (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5%, unless otherwise noted)
Limits
Symbol
VOH
Parameter
Test Condition
IOH=2.0mA (3.135V)
Min.
3.135V
Typ.
Max.
3.465V
Unit
V
4.5V
5.5V
High output voltage
READY,
INPACK#,
BVD1,
4.0mA (4.5V)
0.8 VCC
-
BVD2
IOH=3.5mA (3.135V)
7.0mA (4.5V)
the other
outputs
VOL
Low output voltage
IOL=-2.5mA (3.465V)
-4.0mA (5.5V)
READY,
INPACK#,
BVD1,
-
-
0.4
±5
V
BVD2
the other
outputs
IOL=-4.0mA (3.465V)
-7.0mA (5.5V)
IOZ
ICCR
ICCW
ICCS
Output current in off
state
µA
mA
mA
mA
CE1# = CE2# = VIH
D15-D0
Active supply current Output open
70
100
5
(Read)
Active supply current
(Write)
Standby current
CE1# = CE2# = VIH
(Auto power down)
MITSUBISHI
ELECTRIC
21
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Limits
Symbol
IIH
Parameter
Test Condition
CE1#,CE2#,
Min.
3.135V
Typ.
Max.
3.465V
Unit
µA
4.5V
5.5V
OE#,WE#,
IORD#,IOWR#,
REG#,
CSEL,RESET,
D15-D0, A10-A0
BVD1,BVD2
CE1#,CE2#,
High input current
VIN=VCC
-1
-5
1
5
VIN=GND
OE#,WE#, REG#,
IORD#,IOWR#
-14
-7
-20
-10
-90
-45
-140
-70
IIL
Low input current
PC card mode RESET
A10-A0, CSEL
µA
-1
-5
1
5
D15-D0
CE1#,CE2#,
IORD#,IOWR#,
A10-A0,RESET
D15-D0
VIN=GND
IDE mode
-1
-5
1
5
OE#,WE#, REG#,
BVD1,BVD2
CSEL
-14
-7
-20
-10
-90
-45
-140
-70
CAPACITANCE
Limits
Min. Typ. Max.
Test conditions
Parameter
Symbol
Unit
pF
CI
CO
Input capacitance
Output capacitance
VI=GND, Vi=25mVrms, f=1 MHZ, Ta=25°C
VO=GND, Vo=25mVrms, f=1 MHZ, Ta=25°C
45
45
Note : These parameters are not 100% tested.
MITSUBISHI
ELECTRIC
22
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
AC ELECTRICAL CHARACTERISTICS
MEMORY TIMING
Read Cycle[Attribute] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Parameter
Symbol
Unit
Min.
300
Max.
tCR
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
Address access time
300
300
150
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Card enable access time
Output enable access time
Output disable time (from CE)
Output disable time (from OE)
Output enable time (from CE)
Output enable time (from OE)
5
5
0
Data valid time (after address change)
Read Cycle[Common] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Parameter
Symbol
Unit
Min.
250
Max.
tCR
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
Address access time
250
250
125
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Card enable access time
Output enable access time
Output disable time (from CE)
Output disable time (from OE)
Output enable time (from CE)
Output enable time (from OE)
Data valid time after address change
5
5
0
MITSUBISHI
ELECTRIC
23
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
Write Cycle[Attribute and Common] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Parameter
Unit
Symbol
Min.
Max.
CW
tw(WE)
Write pulse width
Address setup time
Address setup time with respect to WE high
Card enable setup time with respect to WE high
Data setup time with respect to WE high
Data hold time
150
30
180
180
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(A)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
30
30
trec(WE)
tdis(WE)
tdis(OE)
Write recovery time
Output disable time (from WE)
Output disable time (from OE)
Output enable time (from WE)
Output enable time (from OE)
OE set up time with respect to WE low
OE hold time with respect to WE high
100
100
ten(WE)
5
5
10
10
ten(OE)
tsu(OE-WE)
th(OE-WE)
MITSUBISHI
ELECTRIC
24
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
MEMORY TIMING DIAGRAM
Read Cycle
tCR
VIH
An, REG# VIL
ta(A)
ta(CE)
tV(A)
VIH
CE#
VIL
tdis(CE)
ten(CE)
ta(OE)
VIH
OE#
VIL
ten(OE)
tdis(OE)
VOH
Dm
(DOUT)
Hi-Z
OUTPUT VALID
VOL
WE#=“H” level
Note 5 :
Indicates the don’t care input
Write Cycle
tCW
VIH
An, REG#
VIL
tSU(CE-WEH)
tSU(A-WEH)
VIH
CE#
VIL
VIH
OE#
VIL
VIH
tW(WE)
tSU(A)
trec(WE)
WE#
VIL
VIH
VIL
th(OE-WE)
th(D)
tSU(OE-WE)
tSU(D-WEH)
Dm
(DIN)
Hi-Z
DATA INPUT STABLE
tdis(WE)
tdis(OE)
ten(OE)
ten(WE)
VOH
VOL
Hi-Z
Dm
(DOUT)
MITSUBISHI
ELECTRIC
25
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
I/O READ (INPUT) TIMING
Limit
Symbol
Parameter
Min
Max
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(IORD)
Data Delay after IORD#
th(IORD)
Data Hold following IORD#
IORD# Width Time
0
165
70
20
5
twIORD
tsu A(IORD)
th A(IORD)
Address Setup before IORD#
Address Hold following IORD#
CE# Setup before IORD#
tsu CE(IORD)
th CE(IORD)
tsu REG(IORD)
th REG(IORD)
tdf INPACK(IORD)
tdr INPACK(IORD)
tdf IOIS16(ADR)
tdr IOIS16(ADR)
tdf WT(IORD)
tdr(WT)
CE# Hold following IORD#
REG# Setup before IORD#
REG# Hold following IORD#
INPACK# Delay Falling from IORD#
INPACK# Delay Rising from IORD#
IOIS16# Delay Falling from Address
IOIS16# Delay Rising from Address
WAIT# Delay Falling from IORD#
Data Delay from WAIT# Rising
WAIT# Width Time
20
5
0
0
45
45
35
35
35
0
tw(WT)
350
The maximum load on WAIT#, INPACK# and IOIS16# are 1 LSTTL with 50 pF total load.
I/O WRITE (OUTPUT) TIMING
Limit
Symbol
td(IOWR)
Parameter
Min
60
30
165
70
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup before IOWR#
th(IOWR)
Data Hold following IOWR#
IOWR# Width Time
twIOWR
tsu A((IOWR)
th A((IOWR)
tsu CE((IOWR)
th CE((IOWR)
tsu REG(IOWR)
th REG((IOWR)
tdf IOIS16(ADR)
rdr IOIS16(ADR)
tdf WT(IOWR)
tw(WT)
Address Setup before IOWR#
Address Hold following IOWR#
CE# Setup before IOWR#
CE# Hold following IOWR#
REG# Setup before IOWR#
REG# Hold following IOWR#
IOIS16# Delay Falling from Address
IOIS16# Delay Rising from Address
WAIT# Delay Falling from IOWR#
WAIT# Width Time
20
5
0
35
35
35
350
tdr IOWR(WT)
IOWR# high from WAIT# High
0
The maximum load on WAIT#, INPACK# and IOIS16# are 1 LSTTL with 50 pF total load.
MITSUBISHI
ELECTRIC
26
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
I/O READ (INPUT) TIMING DIAGRAM
A[10::0]
th A(IORD)
tsu REG(IORD)
th REG(IORD)
REG#
th CE(IODR)
tsu CE(IORD)
CE#
tw(IORD)
IORD#
tdr INPACK(ADR)
tsu A(IODR)
INPACK#
IOIS16#
tdf INPACK(IORD)
tdr IOIS16(ADR)
tdf IOIS16(ADR)
td (IORD)
tdr(WT)
WAIT#
tdf WT(IORD)
tw(WT)
th (IORD)
D[15::0]
MITSUBISHI
ELECTRIC
27
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
I/O WRITE (OUTPUT) TIMING DIAGRAM
A[10::0]
th A(IOWR)
tsu REG(IOWR)
th REG(IOWR)
REG#
CE#
th CE(IOWR)
tsu CE(IOWR)
tw(IOWR)
IOWR#
IOIS16#
tsu A(IOWR)
tdf WT(IOWR)
tdr IOIS16(ADR)
tdf IOIS16(ADR)
tdr IOWR(WT)
tw(WT)
WAIT#
th (IOWR)
D[15::0]
tsu(IOWR)
MITSUBISHI
ELECTRIC
28
1997.Nov. Rev. 1.2
MITSUBISHI STORAGE CARD
ATA PC CARDS
RECOMMENDED POWER UP/DOWN CONDITIONS (Ta=0~60°C, unless otherwise noted)
Limits
Typ.
Symbol
Vi(CE)
Parameter
Conditions
Unit
Min.
Max.
VCC
VCC+0.1
VCC+0.1
0
VCC-0.1
VIH
20
V
V
V
ms
ms
µs
ms
0V£ VCC <2V
2V£ VCC <VIH
VIH £ VCC
CE input voltage
VCC
tsu(Vcc)
tsu(RESET)
trec(Vcc)
tpr
CE setup time
RESET setup time
CE recover time
Vcc rising time
20
1
0.1
10%à90% of
Vcc
90% of
100
300
tpf
VCC falling time
RESET width
3
ms
Vccà10%
tw(RESET)
th(Hi-zRESET)
ts(Hi-zRESET)
10
1
0
µs
ms
ms
POWER UP/DOWN TIMING DIAGRAM
tsu(VCC)
tpr
VCC
VCC @ 90%
tsu(RESET)
tsu (RESET)
VIH
2V
VCC @ 10%
CE1#, CE2#
RESET
th (Hi-z RESET)
tw (RESET)
Hi-z
tw (RESET)
tpf
VCC
VCC @ 90%
trec(VCC)
VIH
2V
VCC @ 10%
CE1#, CE2#
ts(Hi-z RESET)
RESET
Hi-z
MITSUBISHI
ELECTRIC
29
1997.Nov. Rev. 1.2
相关型号：
MF02-10-5P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
MF02-10-5S
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Receptacle
AMPHENOL
MF02-10-98P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
©2020 ICPDF网 联系我们和版权申明