MH16V7245BATJ-5 [MITSUBISHI]
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM; HYPER页模式1207959552 - BIT （ 16777216 - WORD 72 - BIT）动态RAM
| 型号： | MH16V7245BATJ-5 |
| 厂家： | 
Mitsubishi Group |
| 描述： | HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM |
| 文件： | 总23页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
DESCRIPTION
The MH16V7245BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
85pin
1pin
94pin
95pin
10pin
11pin
FEATURES
/RAS
access access access access
time time time time
/CAS Address /OE
Cycle
Power
Type name
time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
(typ.W)
18
20
30
35
18
20
84
MH16V7245BATJ-5 50
7.12
MH16V7245BATJ-6
60
5.95
104
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V7245BATJ -5 . . . . . . . . . . . . . . . . . 8.53W(Max)
MH16V7245BATJ -6 . . . . . . . . . . . . . . . . . 7.88W(Max)
All input,output LVTTL compatible
124pin
125pin
40pin
41pin
FRONT SIDE
BACK SIDE
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A11)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
APPLICATION
Main memory unit for computers , Microcomputer memory
168pin
84pin
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
- 5
- 6
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MITSUBISHI
ELECTRIC
MIT-DS-0277-0.0
5/Nov./1998
( 1 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
Pin Name
Vss
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Name
Vss
Pin No.
Pin Name
Pin No.
Pin Name
85
86
Vss
DQ36
DQ37
DQ38
DQ39
Vcc
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
RFU
1
DQ0
DQ1
DQ2
DQ3
Vcc
/OE2
/RAS2
/CAS4
Reserved
/WE2
Vcc
2
3
87
Reserved
Reserved
Reserved
/PDE
Vcc
88
4
89
5
6
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ40
DQ41
DQ42
DQ43
DQ44
Vss
7
Reserved
Reserved
DQ18
DQ19
Vss
92
Reserved
Reserved
DQ54
DQ55
Vss
8
9
93
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
95
96
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ20
DQ21
DQ22
DQ23
Vcc
97
DQ45
DQ46
DQ47
DQ48
DQ49
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ24
RFU
DQ60
RFU
DQ14
DQ15
DQ16
DQ17
Vss
DQ50
DQ51
DQ52
DQ53
Vss
RFU
RFU
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
Vss
DQ61
DQ62
DQ63
Vss
Reserved
Reserved
Vcc
Reserved
Reserved
Vcc
/WE0
/CAS0
Reserved
/RAS0
/OE0
Vss
DQ28
DQ29
DQ30
DQ31
Vcc
RFU
DQ64
DQ65
DQ66
DQ67
Vcc
Reserved
Reserved
Reserved
RFU
Vss
DQ68
DQ69
DQ70
DQ71
Vss
DQ32
DQ33
DQ34
DQ35
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
PD2
PD1
A10
A11
PD4
PD3
NC
Reserved
Vcc
PD6
PD5
Vcc
PD8
PD7
RFU
RFU
RFU
ID1
ID0
B0
Vcc
Vcc
Reserved: Reserved use
RFU: Reserved for future use
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 2 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/RAS2
/CAS4
/WE2
/OE2
/CAS0
/WE0
/OE0
DQ0
DQ1
DQ2
DQ36
DQ37
DQ38
/OE
/W
/CAS
/RAS
/OE
/OE
/OE
/OE
/OE
/OE
/OE
/OE
/OE
/W
/CAS
/RAS
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D1
D10
DQ3
DQ4
DQ39
DQ40
/OE
/OE
/OE
/OE
/OE
/OE
/OE
/OE
/W
/CAS
/RAS
/W
/CAS /RAS
DQ1
DQ5
DQ6
DQ41
DQ42
DQ1
~DQ4
M5M465405B
M5M465405B
~DQ4
D2
D11
DQ7
DQ8
DQ43
DQ44
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ9
DQ45
DQ46
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
DQ10
D3
D12
DQ11
DQ12
DQ47
DQ48
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ13
DQ14
DQ49
DQ50
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D4
D13
DQ15
DQ16
DQ51
DQ52
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ17
DQ18
DQ53
DQ54
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D5
D14
DQ19
DQ20
DQ55
DQ56
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ21
DQ22
DQ57
DQ58
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D6
D15
DQ23
DQ24
DQ59
DQ60
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ25
DQ26
DQ61
DQ62
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D7
D16
DQ27
DQ28
DQ63
DQ64
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ29
DQ30
DQ65
DQ66
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D8
D17
DQ31
DQ32
DQ67
DQ68
/W
/CAS
/RAS
/W
/CAS
/RAS
DQ33
DQ34
DQ35
DQ69
DQ70
DQ71
DQ1
~DQ4
DQ1
~DQ4
M5M465405B
M5M465405B
D9
D18
PIN NAME
FUNCTION
/RAS0, /RAS2 ROW ADDRESS STROBE INPUT
/CAS0, /CAS2 COLUMN ADDRESS STROBE INPUT
A0
B0
D1~D9
Vcc
Vss
D1~D18
& INPUT BUFFER
/WE0, /WE2
/OE0, /OE2
A0~A11, B0
DQ0~DQ71
Vcc
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT
ADDRESS INPUT
DATA I/O
C1~C20
. . .
D10~D18
D1~D18
POWER SUPPLY
A1~A11
Vss
GROUND
MITSUBISHI
ELECTRIC
MIT-DS-0277-0.0
5/Nov./1998
( 3 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V7245BATJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Refresh
Operation
Remark
Row
Column
/RAS
ACT
ACT
ACT
ACT
ACT
ACT
NAC
/CAS
/W
/OE
Input Output
address address
NAC
ACT
ACT
ACT
DNC
NAC
DNC
ACT
DNC
DNC
ACT
ACT
DNC
DNC
VLD
OPN
IVD
VLD
VLD
OPN
OPN
NO
NO
NO
NO
YES
YES
NO
Read
ACT
ACT
ACT
ACT
ACT
ACT
DNC
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
OPN
VLD
VLD
VLD
OPN
DNC
DNC
Hyper page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 4 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
-0.5~4.6
-0.5~ 4.6
-0.5~ 4.6
50
21.6
0~70
Unit
V
Vcc
VI
VO
IO
Pd
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
With respect to Vss
mA
W
°C
°C
Ta=25°C
Topr
Tstg
-40~100
(Ta=0~70°C, unless otherwise noted) (Note 1)
RECOMMENDED OPERATING CONDITIONS
Limits
Nom
3.3
Symbol
Parameter
Unit
Min
3.0
0
2.0
-0.3
Max
3.6
Vcc
Vss
VIH
VIL
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
V
V
V
0
0
Vcc+0.3
0.8
V
Note 1 : All voltage values are with respect to Vss
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
Limits
Min Typ Max
Symbol
VOH
VOL
IOZ
Parameter
Test conditions
Unit
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /RAS)
Input current (/RAS)
IOH=-2mA
IOL=2mA
Q floating 0V£VOUT£Vcc
0V£VIN£Vcc+0.3, Other input pins=0V
2.4
0
-10
-10
-90
Vcc
0.4
10
10
90
V
V
uA
uA
uA
I I
0V£VIN£Vcc+0.3, Other input pins=0V
I I (RAS)
/RAS, /CAS cycling
tRC=tWC=min.
output open
Average supply
ICC1 (AV) current
from Vcc operating
-5
-6
2360
2180
mA
(Note 3,4,5)
/RAS=/CAS =VIH, output open
/RAS=/CAS=/WE ³ Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
38
29
Supply current from Vcc , stand-by
ICC2
mA
mA
Average supply current
from Vcc
-5
-6
-5
-6
1820
1640
2360
2180
ICC4(AV)
output open
Hyper-Page-Mode
(Note 3,4,5)
Average supply current from Vcc
/CAS before /RAS refresh mode
(Note 3)
/CAS before /RAS refresh cycling
tRC=min.
output open
ICC6(AV)
mA
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
(Ta = 0~70°C, Vcc = 3.3V+/-0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Limits
Min Typ Max
Symbol
Parameter
Unit
Test conditions
CI (/RAS) Input capacitance, /RAS input
VI=Vss
f=1MHZ
Vi=25mVrms
80
15
18
pF
pF
pF
CI
Input capacitance, except /RAS input
Input/Output capacitance,DATA
C(DQ)
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 5 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
SWITCHING CHARACTERISTICS
-5
-6
Symbol
Parameter
Unit
Min Max
Min Max
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
18
50
30
33
20
60
35
38
tCAC
tRAC
tAA
Access time from /CAS
Access time from /RAS
Columu address access time
Access time from /CAS precharge
Access time from /OE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
18
20
10
5
10
5
Output hold time /CAS high
Output hold time /RAS high
(Note 13)
(Note 7)
(Note 12)
10
20
20
20
15
10
18
18
18
13
Output low impedance time from /CAS low
Output disable time after /OE high
Output disable time after /WE high
Output disable time after /CAS high
Output disable time after /RAS high
(Note 12)
(Note 12,13)
(Note 12,13)
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS-Only refresh or /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V (VOH) and 0.8V (VOL).
8: Assumes that tRCD³ tRCD(max), tASC³ tASC(max) and tCP³ tCP(max).
9: Assumes that tRCD£tRCD(max) and tRAD£tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD³ tRAD(max) and tASC£tASC(max).
11: Assumes that tCP£tCP(max) and tASC³ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state
(IOUT£ I+/-10uAI) and is not reference to VOH(min) or VOL(max).
13: Output is disable after both /RAS and /CAS go to high
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
-5
Min Max
64
-6
Min Max
64
Symbol
Parameter
Unit
tREF
tRP
Refresh cycle time
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
40
/RAS high pulse width
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
(Note16)
9
10
0
32
9
10
0
40
8
10
7
5
5
5
0
(Note17)
(Note18)
20
10
25
13
0
3
8
0
0
5
10
0
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
Delay time, data to /OE low
0
13
18
18
1
15
20
20
1
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
50
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by
tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 6 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
Parameter
Unit
-5
-6
Min
84
50
8
30
18
0
0
0
30
13
18
13
Max Min Max
tRC
Read cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Read Setup time after /CAS high
Read hold time after /CAS iow
Read hold time after /RAS iow
Column address to /RAS hold time
Column address to /CAS hold time
104
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
10000
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
10000
10000 10 10000
43
20
0
0
0
35
18
20
15
(Note 22)
(Note 22)
tORH
tOCH
/RAS hold time after /OE iow
/CAS hold time after /OE iow
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
-5
-6
Unit
Min Max
84
Min Max
104
60 10000
tWC
Write cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Write setup time before /CAS low
Write hold time after /CAS iow
/CAS hold time after /W iow
/RAS hold time after W iow
Write pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
50
8
10000
10
35
20
0
30
18
0
8
8
13
8
-5
(Note 24)
10
10
15
10
-5
tDS
tDH
Data setup time before /CAS iow or W iow
Data hold time after /CAS iow or W iow
13
15
Read-Write and Read-Modify-Write Cycles
Limits
-5
-6
Unit
Symbol
Parameter
Min Max
Min Max
(Note23)
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS iow to W iow
Delay time, RAS iow to W iow
Delay time, address to W iow
OE hold time after W iow
109
133
89 10000
44 10000
77
49
0
32
72
47
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
75
38
65
43
0
28
60
40
13
(Note24)
(Note24)
(Note24)
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min)
and tCPWD³ tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE
goes back to VIH) is indeteminate.
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 7 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25)
Limits
Symbol
Parameter
Unit
-5
-6
Min Max
25
Min Max
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
/RAS iow pulse width for read write cycle
/CAS high pulse width
tHPC
tHPRWC
tRAS
20
55
65
8
33
43
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66
100000
(Note26)
(Note27)
100000
77
10
38
50
7
tCP
15
18
/RAS hold time after /CAS precharge
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
Delay time, /CAS precharge to W low
Hold time to maintain the data Hi-Z until /CAS access
/OE Pulse Width (Hi-Z control)
(Note24)
7
7
7
7
/W Pulse Width (Hi-Z control)
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS prechargeto /OE high after read
28
40
43
13
25
28
32
47
50
15
30
33
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
26: tRAS(min) is specified as two cycles of CAS input are performed.
27: tCP(max) is specified as a reference point only.
/CAS before /RAS Refresh Cycle (Note 28)
Limits
-6
Symbol
Parameter
Unit
-5
Min Max
Min Max
10
5
15
5
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
10
5
15
5
ns
ns
ns
ns
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 8 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Timing Diagrams (Note 29)
Read Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
/CAS
tRAL
tCAL
tRAD
tASR
tASR
tRAH
tASC
tCAH
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
A0~A11,B0
tRRH
tRCH
tRCS
VIH
VIL
/W
tCDD
tDZC
tRDD
tREZ
VIH
VIL
DQ
(INPUTS)
Hi-Z
tWEZ
tOFF
tOHC
tCAC
tAA
tCLZ
tOHR
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEA
tOEZ
tODD
tOCH
VIH
VIL
/OE
tORH
Indicates the don't care input.
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Note 29
Indicates the invalid output.
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 9 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Early Write Cycle
tWC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tASR
tRCD
tRSH
tCAS
VIH
/CAS
VIL
tASR
tRAH
tCAH
tASC
VIH
A0~A11,B0
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tWCS
tWCH
VIH
/W
VIL
tDH
tDS
VIH
DQ
DATA VALID
(INPUTS)
VIL
VOH
DQ
(OUTPUTS)
VOL
Hi-Z
VIH
/OE
VIL
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 10 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Delayed Write Cycle
tWC
tRP
tRAS
VIH
/RAS
VIL
tCRP
tCSH
tCRP
tASR
tRSH
tCAS
tRCD
VIH
/CAS
VIL
tRAH
tCAH
tASC
tASR
VIH
A0~A11,B0
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
tCWL
tRWL
tWP
tRCS
VIH
/W
VIL
tWCH
tDZC
tDS
tDH
VIH
DQ
(INPUTS)
DATA
VALID
Hi-Z
tCLZ
VIL
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
tOEH
tOEZ
tODD
tDZO
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 11 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tRSH
tCAS
tCRP
VIH
/CAS
VIL
tRAD
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
COLUMN
ADDRESS
tAWD
ROW
ADDRESS
ROW
ADDRESS
A0~A11,B10
tCWL
tRWL
tWP
tCWD
tRWD
tRCS
VIH
VIL
/W
tDH
tDS
tDZC
VIH
VIL
DQ
(INPUTS)
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 12 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tCAS
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A11,B0
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tCAL
COLUMN-1
tRCS
tRRH
tCAL
tCAL
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tDOH
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 13 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCRP
tCP
tCP
VIH
VIL
/CAS
A0~A11,B0
/W
tCAL
tCAH
tCAL
tCAH
tASC
tASC
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
COLUMN-1
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIL
VIH
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 14 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRWL
tCRP
tCRP
tASR
tHPRWC
tCAS
tRCD
tCAS
tCP
VIH
VIL
/CAS
A0~A11,B0
/W
tRAD
tRAH
tCWL
tCAH
tASC
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
tRWD
tCPWD
tDZC
tDH
tDZC
tDH
tDS
tDS
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
tCAC
Hi-Z
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tCPA
tDZO
tODD
tODD
tOEH
tDZO tOEA
tOEZ
tOEZ
tOEA
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 15 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRP
tRAS
tRWL
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tHPC
tCAS
tHPRWC
tCAS
tCRP
tASR
tCAS
tCP
tCP
VIH
VIL
tCWL
/CAS
A0~A11,B0
/W
tRAD
tRAH
tASR
tASC
tCAH
tASC tCAH
COLUMN-3
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-1
tRCS
tCPWD
tAWD
tCWD
tWCH
tCAL
tWCS
tCAL
tWP
VIH
VIL
tDH
tDZ
C
tDZC
tDH
tDS
tDS
VIH
VIL
DQ
(INPUTS)
DATA
VALID-2
DATA
VALID-3
tCAC
tAA
tAA
tCAC
tWEZ
tCLZ
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-3
DATA
VALID-1
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOEA
tOEH
tDZO
tOEZ
tOEZ
VIL
VIH
tOCH
/OE
tODD
tODD
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 16 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH
/RAS
VIL
tHPC
VIH
VIL
/CAS
A0~A11,B0
/W
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tASC
tASC
tCAH
VIH
VIL
COLUMN-1
tCAL
COLUMN-2
COLUMN-3
tRCH
tCAL
tWCH
tWCS
tDS
VIH
VIL
tHCWD
tHAWD
tDH
tDZC
tHPWD
VIH
VIL
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tAA
tCAC
tAA
tCPA
tWEZ
tCPA
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tHCOD
tHAOD
tHPOD
tOEA
tDZC
tOEZ
tODD
VIL
VIH
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 17 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tASR
tCAS
tCRP
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A11,B0
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRAL
tRRH
tRCS
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-1
DQ
(OUTPUTS)
DATA
VALID-3
Hi-Z
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tCHOL
tOCH
tOEA
tOEZ
tOEZ
VIL
VIH
/OE
tODD
tOEPE
tOEPE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 18 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCP
tCP
tCRP
VIH
VIL
/CAS
A0~A11,B0
/W
tCPRH
tCAH
tRAD
tRAH
tASR
tASC
tASC
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tRAL
COLUMN-1
tRRH
tRCS
tRCH
tRCH
tRCS
VIH
VIL
tDZC
tWPE
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tCLZ
tREZ
tOHR
tOFF
tOHC
tDOH
tCLZ
tWEZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-2
DATA
VALID-1
DATA
VALID-3
Hi-Z
tCPA
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 19 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
/CAS before /RAS Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
/RAS
VIL
tCRP
tCSR
tRPC
tCHR
tRPC tCSR
tCHR
tRPC
VIH
VIL
/CAS
tCPN
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
A0~A11,B0
tRRH
tRCH
tRCS
VIH
VIL
/W
VIH
VIL
DQ
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
tOEZ
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 20 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
/RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
/CAS
A0~A11,B0
/W
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
COLUMN
ROW
ADDRESS
ROW
ADDRESS
ADDRESS
tRCS
tDZC
tRRH
tRAL
tRCH
VIH
VIL
tCDD
tRDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tREZ
tCAC
tAA
tOHR
tOFF
tOHC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
/OE
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
( 21 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Package Outline
Unit:mm
133.35
127.35
3.52MAX
3.0
2- +/-2.0
2.0
2.0
1.27
2- +/-3.0
6.35
29x1.27=36.83
9x1.27=11.43
6.35
43x1.27=54.61
8.89
23.50
43.18
MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
(22 / 23 )
MITSUBISHI LSIs
Preliminary Spec.
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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MITSUBISHI
MIT-DS-0277-0.0
5/Nov./1998
ELECTRIC
(23 / 23 )
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