MH2V645CWZPJ-7 [MITSUBISHI]
EDO DRAM Module, 2MX64, 70ns, CMOS, DIMM-168;
| 型号： | MH2V645CWZPJ-7 |
| 厂家： | 
Mitsubishi Group |
| 描述： | EDO DRAM Module, 2MX64, 70ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
PIN CONFIGURATION
DESCRIPTION
The MH2V645CWZPJ module is 2097152-word x 64-bit
dynamic ram module.
This consist of eight industry standard 2M x 8 dynamic
RAMs in SOJ and one industry standard
EEPROM in TSSOP.
85pin
1pin
The mounting of SOJ on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
94pin
95pin
10pin
11pin
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
/RAS
access access access access
time time time time
/CAS Address /OE
Cycle
Power
Type name
time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
(typ.W)
MH2V645CWZPJ-6 60
MH2V645CWZPJ-7
15
20
30
35
15
20
2.88
2.53
110
130
70
Utilizes industry standard 2M x 8 dynamic RAMs in SOJ and
industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . . . 14.4mW(Max)
Low operation power dissipation
40pin
41pin
124pin
125pin
FRONT SIDE
BACK SIDE
MH2V645CWZPJ-6 . . . . . . . . . . . . . . . . . . 3.46W(Max)
MH2V645CWZPJ-7 . . . . . . . . . . . . . . . . . . 3.03W(Max)
All input are directly TTL compatible
All output are three-state and directry TTL compatible
Includes(0.22uF x 8) decoupling capacitors
2048 refresh cycle every 32ms (A0~A10)
Hyper page mode(2048-column random address) oparation
with extended data out
JEDEC proposal pin configration & Serial PD pin
Gold plating contact pads
84pin
168pin
APPLICATION
Main memory unit for computers , Microcomputer memory
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
1
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
PIN CONFIGURATION
Pin Name
Pin Name
Pin Name
Pin Name
Pin No.
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin No.
85
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
Vss
DU
1
86
2
NC
3
87
88
4
/CAS6
/CAS7
DU
89
5
6
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
Vcc
7
NC
92
NC
8
NC
NC
9
93
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
NC
95
NC
Vss
96
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ48
DQ49
DQ50
DQ51
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DQ52
NC
DQ14
DQ15
NC
DQ46
DQ47
NC
DU
DU
NC
NC
NC
Vss
NC
Vss
Vss
Vss
DQ21
DQ22
DQ23
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
NC
NC
Vcc
Vcc
/WE0
/CAS0
/CAS1
/RAS0
/OE0
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DU
DQ56
DQ57
DQ58
DQ59
Vcc
/CAS4
/CAS5
NC
DU
DQ28
DQ29
DQ30
DQ31
Vss
Vss
DQ60
DQ61
DQ62
DQ63
Vss
A0
A1
A2
A3
A4
A5
A6
A7
A8
NC
A9
NC
A10
NC
NC
NC
NC
NC
SA0
SA1
NC
Vcc
Vcc
SDA
SCL
Vcc
Vcc
DU
SA2
Vcc
DU
DU
NC:No Connect
DU:Don't Use
MITSUBISHI
ELECTRIC
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2
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/WE0
/OE0
/RAS2
/WE2
/OE2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/OE
/W
/RAS
/OE
/W
/RAS
/CAS
/CAS4
/CAS5
/CAS6
/CAS7
/CAS
/CAS0
/CAS1
/CAS2
/CAS3
DQ1
~DQ8
DQ1
~DQ8
M5M4V17805
M5M4V17805
D1
D5
DQ8
DQ9
/OE
/CAS
/W
/RAS
/OE
/CAS
/W
/RAS
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ1
~DQ8
DQ1
~DQ8
M5M4V17805
M5M4V17805
D2
D6
/OE
/CAS
/W
/RAS
/OE
/CAS
/W
/RAS
DQ1
~DQ8
DQ1
~DQ8
M5M4V17805
M5M4V17805
D3
D7
/OE
/CAS
/W
/RAS
/OE
/CAS
/W
/RAS
DQ1
~DQ8
DQ1
~DQ8
M5M4V17805
M5M4V17805
D4
D8
SCL
SDA
EEPROM
A0
A1
A2
SA0 SA1 SA2
A0~A10
D1~D8
PIN NAME
FUNCTION
/RAS0, /RAS2 ROW ADDRESS STROBE INPUT
/CAS0~/CAS7 COLUMN ADDRESS STROBE INPUT
/WE0, /WE2
/OE0, /OE2
A0~A10
DQ0~DQ63
Vcc
Vss
SA
SDA
SCL
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT
ADDRESS INPUT
DATA I/O
POWER SUPPLY
Vcc
Vss
C1~C8
. . .
D1~D8
GROUND
EEPROM DEVICE ADDRESS INPUT
EEPROM DATA I/O
EEPROM CLOCK INPUT
MITSUBISHI
MIT-DS-0029-1.5
24/Mar./1997
ELECTRIC
( 3 / 25 )
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Serail Presence Detect TABLE
Bytes
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD entry data
128
SPD DATA entry(Hex)
0
1
2
3
4
5
6
7
8
9
80
256 Bytes
EDO DRAM
A0-A10
08
02
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0B
A0-A9
0A
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
3.3V LVTTL
60ns
02
RAS# access time of this assembly
CAS# access time of this assembly
-6
3C
-7
-6
-7
70ns
46
10
15ns
0F
20ns
14
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
Non-parity
N/R(15.625uS)
x8
00
00
13
DRAM width,Primary DRAM
08
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -6
Check sum for -7
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
36
45
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH2V645CWZPJ-6 4D48325636343543575A504A2D3620202020
MH2V645CWZPJ-7 4D48325636343543575A504A2D3720202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yyww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
MIT-DS-0029-1.5
24/Mar./1997
ELECTRIC
( 4 / 25 )
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
FUNCTION
The 2Mx64bit module provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode, /RAS-
only refresh, and delayed-write. The input conditions for
each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Remark
Operation
Refresh
Column
address
Row
/RAS
/CAS
/W
/OE
Input Output
address
Read
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
APD
APD
APD
APD
APD
APD
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
YES
YES
YES
YES
YES
YES
YES
NO
Hyper page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
/RAS-only refresh
Hidden refresh
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
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5
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Vcc Supply voltage
Conditions
Ratings
-0.5~4.6
-0.5~4.6
Unit
V
V
VI
Input voltage
With respect to Vss
VO
IO
Pd
Topr
Tstg
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature (SOJ)
-0.5~4.6
50
V
mA
W
°C
°C
Ta=25°C
8
0~ 70
-40~ 125
(Ta=0~ 70°C, unless otherwise noted) (Note 1)
RECOMMENDED OPERATING CONDITIONS
Limits
Unit
Symbol
Parameter
Min
3.0
0
2.0
**-0.3
Nom
3.3
0
Max
3.6
Vcc
Vss
VIH
VIL
V
V
V
V
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
0
Vcc+0.3
0.8
Note 1 : All voltage values are with respect to Vss
** : VIL(Min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss)
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
Limits
Min Typ
Symbol
Parameter
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V£VOUT£3.6V
0V£VIN£3.6V, Other input pins=0V -80
/RAS, /CAS cycling
tRC=tWC=min.
Unit
Max
Vcc
0.4
10
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
2.4
0
-10
V
V
uA
uA
80
Average supply
960
840
- 6
- 7
mA
ICC1 (AV)
ICC2
current
(Note 3,4,5)
from Vcc operating
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS³ Vcc -0.2, output open
/RAS cycling, /CAS= VIH
tRC=min.
16
4
Supply current from Vcc , stand-by
Average supply
mA
mA
960
- 6
ICC3 (AV)
current
- 7
- 6
- 7
- 6
- 7
840
920
720
960
840
(Note 3,5)
Average supply current
from Vcc
from Vcc refreshing
output open
/RAS=VIL,/CAS cycling
tPC=min.
mA
mA
ICC4(AV)
ICC6(AV)
Hyper-Page-Mode (Note 3,4,5)
output open
Average supply current
from Vcc
/CAS before /RAS refresh cycling
tRC=min.
output open
/CAS before /RAS refresh
mode
(Note 3,5)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VOH
(Ta = 0~70°C, Vcc = 3.3V+/-0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Limits
Typ Max
Symbol
Parameter
Unit
Test conditions
Min
CI (A)
CI
Input capacitance, address inputs
Input capacitance, except addressinputs
VI=Vss
f=1MHZ
Vi=25mVrms
60
38
23
pF
pF
pF
C(DQ) Input/Output capacitance,DATA
MITSUBISHI
ELECTRIC
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/ 25 )
6
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
SWITCHING CHARACTERISTICS
Symbol
Parameter
- 6
- 7
Unit
Min
Max
15
Min
Max
20
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
tCAC
tRAC
tAA
Access time from /CAS
Access time from /RAS
Columu address access time
Access time from /CAS precharge
Access time from /OE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
30
35
15
70
35
40
20
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
tDOH
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
Output hold time /CAS high
Output hold time /RAS high
Output low impedance time from /CAS low
Output disable time after /OE high
Output disable time after /WE high
5
5
5
5
5
5
15
15
15
15
20
20
20
20
(Note 12,13)
(Note 12,13)
Output disable time after /CAS high
Output disable time after /RAS high
Output hold time from /CAS low
5
5
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 32 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD³ tRCD(max), tASC³ tASC(max) and tCP³ tCP(max).
9: Assumes that tRCD£tRCD(max) and tRAD£tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD³ tRAD(max) and tASC£tASC(max).
11: Assumes that tCP£tCP(max) and tASC³ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state
(IOUT£ I+/-10uAI) and is not reference to VOH(min) or VOL(max).
13: Output is disable after both /RAS and /CAS go to high
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
-6
-7
Symbol
Parameter
Unit
Min
Max
32
Min
Max
32
tREF
tRP
Refresh cycle time
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RAS high pulse width
40
20
5
50
20
5
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low (Note17)
Row address setup time before /RAS low
Column address setup time before /CAS low (Note18)
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
(Note16)
38
42
0
0
10
15
0
13
15
0
30
13
35
13
0
0
10
10
0
10
10
0
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
0
0
15
15
15
1
20
20
20
1
50
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by
tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
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ELECTRIC
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MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
Parameter
-6
-7
Unit
Min
110
60
10
48
15
0
0
0
30
18
15
15
Max
Min
130
70
13
55
20
0
0
0
35
23
20
20
Max
tRC
Read cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Read Setup time after /CAS high
Read hold time after /CAS iow
Read hold time after /RAS iow
Column address to /RAS hold time
Column address to /CAS hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
10000
10000
10000
10000
(Note 22)
(Note 22)
tORH
tOCH
/RAS hold time after /OE iow
/CAS hold time after /OE iow
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
-6
-7
Unit
Min
110
60
10
48
15
0
10
10
10
10
0
Max
Min
130
70
13
55
20
0
13
13
13
13
0
Max
tWC
Write cycle time
/RAS iow pulse width
/CAS iow pulse width
/CAS hold time after /RAS iow
/RAS hold time after /CAS iow
Write setup time before /CAS low
Write hold time after /CAS iow
/CAS hold time after /W iow
/RAS hold time after W iow
Write pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
10000
10000
10000
10000
(Note 22)
tDS
tDH
Data setup time before /CAS iow or W iow
Data hold time after /CAS iow or W iow
10
13
Read-Write and Read-Modify-Write Cycles
Limits
-6
-7
Unit
Symbol
Parameter
Min
133
89
44
82
44
0
32
77
47
15
Max
Min
161
107
57
99
57
0
42
92
57
20
Max
(Note21)
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS iow to W iow
Delay time, RAS iow to W iow
Delay time, address to W iow
OE hold time after W iow
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
10000
10000
(Note22)
(Note22)
(Note22)
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min)
and tCPWD³ tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE
goes back to VIH) is indeteminate.
MITSUBISHI
MIT-DS-0029-1.5
24/Mar./1997
ELECTRIC
( 8 / 25 )
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25)
Limits
Symbol
Parameter
-6
-7
Unit
Min
25
66
77
10
33
50
7
Max
Min
30
79
92
13
38
60
7
Max
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
(Note26)
tHPC
tHPRWC
tRAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RAS iow pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
Hold time to maintain the data Hi-Z until /CAS access
/OE Pulse Width (Hi-Z control)
/W Pulse Width (Hi-Z control)
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS prechargeto /OE high after read
(Note27)
(Note28)
100000
16
100000
16
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
(Note24)
7
7
7
7
32
47
50
15
30
33
42
57
60
20
35
38
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
29: tHPC(min) is specified in the case of read-only and early write only in Hyper Page Mode.
27: tRAS(min) is specified as two cycles of CAS input are performed.
28: tCP(max) is specified as a reference point only.
/CAS before /RAS Refresh Cycle (Note 29)
Limits
-7
Symbol
Parameter
-6
Unit
Min
5
10
17
5
Max
Min
5
15
22
5
Max
tCSR
tCHR
tCAS
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
/CAS low pulse width
Read setup time before /RAS low
Read hold time after /RAS low
ns
ns
ns
ns
ns
10
15
Note 29: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
Hidden Refresh Cycle (note 31)
Limits
Symbol
Parameter
-6
-7
Unit
Min
5
10
Max
Min
5
15
Max
ns
ns
tRSR
tRHR
Read set up time before /RAS low
Read hold time after /RAS low
Note 31: Read, early write, delayed write, read write or read-modify-write cycle is applicable to hidden refresh cycle. In all cases tRSR and
tRHR should be satisfied.
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24/Mar./1997
ELECTRIC
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/ 25 )
9
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Timing Diagrams (Note 30)
Read Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
/CAS
tRAL
tCAL
tRAD
tASR
tASR
tRAH
tASC
tCAH
VIH
VIL
ROW
ADDRESS
A0~A10
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCH
tRCS
VIH
VIL
/W
tCDD
tDZC
tRDD
tREZ
VIH
VIL
DQ
(INPUTS)
Hi-Z
tWEZ
tOFF
tOHC
tCAC
tAA
tCLZ
tOHR
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEA
tOEZ
tODD
tOCH
VIH
VIL
/OE
tORH
Indicates the don't care input.
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Note 30
Indicates the invalid output.
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
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/ 25 )
10
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Early Write Cycle
tWC
tRAS
tRP
VIH
VIL
/RAS
/CAS
tCSH
tCRP
tCRP
tASR
tRCD
tRSH
tCAS
VIH
VIL
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A10
tWCS
tWCH
VIH
VIL
/W
tDH
tDS
VIH
VIL
DQ
(INPUTS)
DATA VALID
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
11
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Delayed Write Cycle
tWC
tRP
tRAS
VIH
VIL
/RAS
tCRP
tCSH
tCRP
tASR
tRSH
tCAS
tRCD
VIH
VIL
/CAS
A0~A10
/W
tRAH
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
tCWL
tRWL
tWP
tRCS
VIH
VIL
tWCH
tDZC
tDS
tDH
VIH
VIL
DQ
(INPUTS)
DATA
VALID
Hi-Z
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
tOEH
tOEZ
tODD
tDZO
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
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/ 25 )
12
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
VIL
/RAS
tCRP
tCSH
tRCD
tRSH
tCAS
tCRP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tASR
tRAH
ROW
tCAH
tASR
tASC
VIH
VIL
COLUMN
ADDRESS
tAWD
ROW
ADDRESS
ADDRESS
tCWL
tRWL
tWP
tCWD
tRWD
tRCS
VIH
VIL
tDH
tDS
tDZC
VIH
VIL
DQ
(INPUTS)
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
/OE
MITSUBISHI
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MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
13
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tCAS
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tCAL
COLUMN-1
tRCS
tRRH
tCAL
tCAL
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tDOH
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
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24/Mar./1997
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14
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCRP
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tCAL
tCAH
tCAL
tCAH
tASC
tASC
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
COLUMN-1
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIL
VIH
/OE
MITSUBISHI
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24/Mar./1997
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/ 25 )
15
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRWL
tCRP
tCRP
tASR
tHPRWC
tCAS
tRCD
tCAS
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCWL
tCAH
tASC
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
tRWD
tCPWD
tDZC
tDH
tDZC
tDH
tDS
tDS
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
tCAC
Hi-Z
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tCPA
tDZO
tODD
tODD
tOEH
tDZO tOEA
tOEZ
tOEZ
tOEA
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
16
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRP
tRAS
tRWL
VIH
VIL
/RAS
tCRP
tCSH
tRCD
tHPC
tCAS
tHPRWC
tCAS
tCRP
tASR
tCAS
tCP
tCP
VIH
VIL
tCWL
/CAS
A0~A10
/W
tRAD
tRAH
tASR
tASC
tCAH
tASC tCAH
COLUMN-3
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-1
tRCS
tCPWD
tAWD
tCWD
tWCH
tCAL
tWCS
tCAL
tWP
VIH
VIL
tDH
tDZ
C
tDZC
tDH
tDS
tDS
VIH
VIL
DQ
(INPUTS)
DATA
VALID-2
DATA
VALID-3
tCAC
tAA
tAA
tCAC
tWEZ
tCLZ
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-3
DATA
VALID-1
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOEA
tOEH
tDZO
tOEZ
tOEZ
VIL
VIH
tOCH
/OE
tODD
tODD
MITSUBISHI
ELECTRIC
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17
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH
VIL
/RAS
tHPC
VIH
VIL
/CAS
A0~A10
/W
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tASC
tASC
tCAH
VIH
VIL
COLUMN-1
tCAL
COLUMN-2
COLUMN-3
tRCH
tCAL
tWCH
tWCS
tDS
VIH
VIL
tHCWD
tHAWD
tDH
tDZC
tHPWD
VIH
VIL
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tAA
tCAC
tAA
tCPA
tWEZ
tCPA
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tHCOD
tHAOD
tHPOD
tOEA
tDZC
tOEZ
tODD
VIL
VIH
/OE
MITSUBISHI
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24/Mar./1997
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18
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tASR
tCAS
tCRP
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRAL
tRRH
tRCS
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-1
DQ
(OUTPUTS)
DATA
VALID-3
Hi-Z
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tCHOL
tOCH
tOEA
tOEZ
tOEZ
VIL
VIH
/OE
tODD
tOEPE
tOEPE
MITSUBISHI
ELECTRIC
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24/Mar./1997
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19
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCP
tCP
tCRP
VIH
VIL
/CAS
A0~A10
/W
tCPRH
tCAH
tRAD
tRAH
tASR
tASC
tASC
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tRAL
COLUMN-1
tRRH
tRCS
tRCH
tRCH
tRCS
VIH
VIL
tDZC
tWPE
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tCLZ
tREZ
tOHR
tOFF
tOHC
tDOH
tCLZ
tWEZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
Hi-Z
tCPA
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
ELECTRIC
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24/Mar./1997
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20
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
tRP
VIH
VIL
/RAS
tRPC
tCRP
tCRP
VIH
VIL
/CAS
A0~A10
/W
tASR
tRAH
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
VIH
VIL
VIH
VIL
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
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21
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
*
/CAS before /RAS Refresh Cycle, Extended Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
VIL
/RAS
tCRP
tCSR
tRPC
tCHR
tRPC tCSR
tCHR
tRPC
VIH
VIL
/CAS
A0~A10
/W
tCPN
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCH
tRCS
VIH
VIL
VIH
VIL
DQ
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
tOEZ
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
22
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
/RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
/CAS
A0~A10
/W
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
COLUMN
ROW
ADDRESS
ROW
ADDRESS
ADDRESS
tRCS
tDZC
tRRH
tRAL
tRCH
VIH
VIL
tCDD
tRDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tREZ
tCAC
tAA
tOHR
tOFF
tOHC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
/OE
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MITSUBISHI
MIT-DS-0029-1.5
24/Mar./1997
ELECTRIC
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MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Self Refresh Cycle
tRASS
tRP
tRPS
VIH
VIL
/RAS
/CAS
tRPC
tRPC
tCRP
tASR
tCSR
tCHS
VIH
VIL
tCPN
VIH
VIL
ROW
ADDRESS
A0~A10
tRRH
tRCH
tRCS
VIH
VIL
/W
tRDD
tCDD
Hi-Z
DQ
(INPUTS)
VIH
VIL
tREZ
tOHR
tOFF
tOHC
Hi-Z
VOH
VOL
DQ
(OUTPUTS)
tOEZ
tODD
VIH
VIL
/OE
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
(
/ 25 )
24
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MH2V645CWZPJ-6,-7
HYPER PAGE MODE 16777216-BIT (2097152-BIT BY 64-BIT) DYNAMIC RAM
Package Outline
Unit:mm
133.35
127.35
3.0
2-R2.0
2.0
2.0
1.27
2-ø3.0
6.35
29x1.27=36.83
9x1.27=11.43
6.35
43x1.27=54.61
8.89
42.18
24.495
MITSUBISHI
ELECTRIC
MIT-DS-0029-1.5
24/Mar./1997
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25
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