MH4V64AXJJ-5 [MITSUBISHI]
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM; 快速页模式268435456 - BIT （ 4194304 - WORD 64位），动态RAM
| 型号： | MH4V64AXJJ-5 |
| 厂家： | 
Mitsubishi Group |
| 描述： | FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
| 文件： | 总25页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
ADDRESS
Part No.
DESCRIPTION
Refresh
Cycle
Refresh
Row Add. Col Add.
This is family of 4194304 - word by 64 - bit dynamic RAM
module. This consists of four industry standard 4Mx16 dynamic
RAMs in TSOP and one industry EEPROM in TSSOP.
The mounting of TSOP on a card edge dual in line package
provides any application where high densities and large of
quantities memory are required.
/RAS only Ref,Normal R/W 8192/64ms
A0~A12
A0~A11
A0~A8
A0~A9
MH4V64AXJJ
MH4V644AXJJ
CBR Ref,Hidden Ref
4096/64ms
4096/64ms
/RAS only Ref,Normal R/W
CBR Ref,Hidden Ref
This is a socket-type memory module,suitable for easy
interchange of addition of modules.
APPLICATION
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
FEATURES
RAS
CAS
Address
access
time
OE
access
time
Cycle
time
(min.ns)
access access
*:Applicable to self refresh version(MH4V64/644AXJJ-5S,-6S)
only
time
time
(max.ns)
(max.ns) (max.ns) (max.ns)
50
60
50
60
13
15
13
15
25
30
25
30
13
15
13
15
MH4V64AXJJ-5,5S
MH4V64AXJJ-6,6S
MH4V644AXJJ-5,5S
MH4V644AXJJ-6,6S
90
110
90
110
single 3.3V± 0.3V supply
Low stand-by power dissipation
7.2mW- - - - - - - - - LVCMOS input level
operating power dissipation
MH4V64AXJJ-5,5S - - - - - 1584 mW(max.)
MH4V64AXJJ-6,6S - - - - - 1440mW(max.)
MH4V644AXJJ-5,5S - - - - 2016 mW(max.)
MH4V644AXJJ-6,6S - - - - 1872 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output LVTTL compatible and low capacitance
Utilizes industry standard 4Mx16 RAMs in TSOP
and industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx4)
Fast page mode , Read-modify-write,
CAS before RAS refresh,Hidden refresh capabilities.
Early-write mode,OE to control output buffer
impedance.
MITSUBISHI
ELECTRIC
MIT-DS-0072-0.5
26/Feb./1997
( 1 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
Front side
Pin Name
Back side
Pin Name
Front side
Pin Name
Back side
Pin Name
PIN
Number
PIN
Number
PIN
Number
PIN
Number
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
2
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
73
75
/OE
Vss
74
76
RFU
Vss
3
4
5
6
Reserved
Reserved
Vcc
78
Reserved
Reserved
Vcc
77
7
8
79
80
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
81
82
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
83
DQ16
DQ17
DQ18
DQ19
Vss
84
DQ48
DQ49
DQ50
DQ51
Vss
DQ4
DQ5
DQ6
DQ7
Vss
DQ36
DQ37
DQ38
DQ39
Vss
86
85
88
87
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
Vcc
94
DQ52
DQ53
DQ54
DQ55
Vcc
/CAS0
/CAS1
Vcc
/CAS4
/CAS5
Vcc
96
95
97
98
99
100
102
104
106
108
A0
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A6
A7
A2
A5
A8
A11
Vss
Vss
Vss
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ40
DQ41
DQ42
DQ43
Vcc
A9
110 A12/NC(note)
A10
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
NC
Vcc
Vcc
/CAS2
/CAS3
Vss
/CAS6
/CAS7
Vss
DQ12
DQ13
DQ14
DQ15
Vss
DQ44
DQ45
DQ46
DQ47
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
Reserved
Reserved
RFU
Vcc
Reserved
Reserved
FRU
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
Vcc
RFU
/WE
RFU
RFU
/RAS0
NC
RFU
SDA
SCL
RFU
Vcc
Vcc
RFU:Reserved Future Use
NC,RFU,Reserved: NO CONNECTION
Note:A12 ... MH4V64AXJJ , NC ... MH4V644AXJJ
MITSUBISHI
ELECTRIC
( 2 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram
Address
/OE
/WE
/RAS0
/CAS0
/CAS4
/LCAS /RAS /WE /OE
/LCAS /RAS /WE /OE
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
/CAS1
/CAS5
D2
/UCAS
/UCAS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O9
I/O9
DQ8
DQ9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CAS2
/CAS6
/LCAS /RAS /WE /OE
/LCAS /RAS /WE /OE
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/CAS3
D1
D3
/UCAS
/UCAS
/CAS7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O9
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
SERIAL PD
A0 A1 A2
Vcc
D0 to D3
D0 to D3
SDA
SCL
C1~C4
Vss
Vss
MITSUBISHI
ELECTRIC
( 3 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5,-6)
Bytes
Function described
SPD entry data
256 Bytes
FPM DRAM
A0-A12
SPD DATA entry(Hex)
1
2
3
4
5
6
7
8
9
Total # bytes of SPD memory device
Fundamental memory type
08
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0D
A0-A8
09
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
RAS# access time of this assembly
3.3V LVTTL
50ns
02
-5
-6
-5
-6
32
60ns
3C
10
CAS# access time of this assembly
13ns
0D
15ns
0F
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non parity
N/R(15.625uS)
x16
00
00
13
DRAM width,Primary DRAM
10
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
Check sum for -6
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
32
3E
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH4V64AXJJ-5 4D483456363441584A4A2D352D35202020202020
MH4V64AXJJ-6 4D483456363441584A4A2D362D36202020202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yy/ww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
ELECTRIC
( 4 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5S,-6S)
Bytes
Function described
SPD entry data
256 Bytes
FPM DRAM
A0-A12
SPD DATA entry(Hex)
1
2
3
4
5
6
7
8
9
Total # bytes of SPD memory device
Fundamental memory type
08
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0D
A0-A8
09
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
RAS# access time of this assembly
3.3V LVTTL
50ns
02
-5S
-6S
-5S
-6S
32
60ns
3C
10
CAS# access time of this assembly
13ns
0D
15ns
0F
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non parity
S/R(15.625uS)
x16
00
80
13
DRAM width,Primary DRAM
10
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
Check sum for -6
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
B2
BE
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH4V64AXJJ-5S 4D483456363441584A4A2D355335532020202020
MH4V64AXJJ-6S 4D483456363441584A4A2D365336532020202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yy/ww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
ELECTRIC
( 5 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5,-6)
Bytes
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD entry data
128
SPD DATA entry(Hex)
0
1
2
3
4
5
6
7
8
9
80
256 Bytes
FPM DRAM
A0-A11
08
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0C
A0-A9
0A
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
3.3V LVTTL
50ns
02
RAS# access time of this assembly
CAS# access time of this assembly
-5
32
-6
-5
-6
60ns
3C
10
13ns
0D
15ns
0F
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non parity
N/R(15.625uS)
x16
00
00
13
DRAM width,Primary DRAM
10
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
Check sum for -6
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
32
3E
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH4V644AXJJ-5 4D48345636343441584A4A2D352D352020202020
MH4V644AXJJ-6 4D48345636343441584A4A2D362D362020202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yy/ww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
ELECTRIC
MIT-DS-0072-0.5
26/Feb./1997
6
(
/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5S,-6S)
Bytes
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD entry data
128
SPD DATA entry(Hex)
0
1
2
3
4
5
6
7
8
9
80
256 Bytes
FPM DRAM
A0-A11
08
01
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
0C
A0-A9
0A
1bank
01
x64
40
... Data Width continuation
0
00
Voltage interface standard of this assembly
3.3V LVTTL
50ns
02
RAS# access time of this assembly
CAS# access time of this assembly
-5S
32
-6S
-5S
-6S
60ns
3C
10
13ns
0D
15ns
0F
11
12
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
non parity
S/R(15.625uS)
x16
00
80
13
DRAM width,Primary DRAM
10
14
Error Checking DRAM data width
Reserved for future offerings
N/A
00
15-31
32-61
62
open
00
Superset Memory type(may be used in future)
SPD Data Revision Code
open
00
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5S
Check sum for -6S
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
B2
BE
64-71
72
Manufacturers JEDEC ID code per JEP-106
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
04
73-90
Manufacturer's Part Number
MH4V644AXJJ-5S 4D48345636343441584A4A2D3553355320202020
MH4V644AXJJ-6S 4D48345636343441584A4A2D3653365320202020
91-92
93-94
Revision Code
Manufacturing date
PCB revision
year/week code
serial number
open
rrrr
yy/ww
ssssssss
00
95-98
Assembly Serial Number
Manufacturer Specific Data
Reserved
99-125
126-127
128-255
open
00
Open User Free-Form area not defined
open
00
MITSUBISHI
ELECTRIC
( 7 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
FUNCTION
The MH4V64/644AXJJ provide, in addition to
normal read, write, and read-modify-write
operations,
a number of other functions, e.g., Fast page mode,
/RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Inputs
Input/Output
Column
Input Output
address address
Refresh
Remark
Row
/RAS
/CAS
/W
/OE
Read
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
ACT
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
NAC
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
DNC
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
YES
YES
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
/RAS-only refresh
Hidden refresh
/CAS before /RAS refresh ACT
Standby
Self refresh
NAC
ACT
YES
*
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
*MH4V64/644AXJJ-5S,-6S only
MITSUBISHI
MIT-DS-0072-0.5
26/Feb./1997
ELECTRIC
(
/ 25 )
8
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Vcc Supply voltage
Conditions
Ratings
-0.5~4.6
-0.5~4.6
Unit
V
V
VI
Input voltage
With respect to Vss
VO
IO
Pd
Topr
Tstg
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature (SOJ)
-0.5~4.6
50
V
mA
W
°C
°C
Ta=25°C
4
0~ 70
-40~ 100
(Ta=0~ 70°C, unless otherwise noted) (Note 1)
RECOMMENDED OPERATING CONDITIONS
Limits
Unit
Symbol
Parameter
Min
3.0
0
2.0
**-0.3
Nom
3.3
0
Max
3.6
Vcc
Vss
VIH
VIL
V
V
V
V
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
0
Vcc+0.3
0.8
Note 1 : All voltage values are with respect to Vss
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
[MH4V64AXJJ]
Limits
Min Typ
Symbol
Parameter
Test conditions
Unit
Max
Vcc
0.4
10
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
IOH=-2.0mA
IOL=2.0mA
Q floating 0V£VOUT£3.6V
0V£VIN£3.6V, Other input pins=0V -40
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS³ Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
2.4
0
-10
V
V
uA
uA
40
Average supply
-5,-5S
-6,-6S
440
mA
ICC1 (AV)
ICC2
current
400
(Note 3,4,5)
from Vcc operating
4
2
Supply current from Vcc , stand-by
mA
mA
Average supply current
-5,-5S
400
360
560
from Vcc
ICC4(AV)
-6,-6S
-5,-5S
Fast-Page-Mode (Note 3,4,5)
Average supply current
output open
/CAS before /RAS refresh cycling
tRC=min.,/W³ Vcc-0.2
output open
from Vcc
mA
ICC6(AV)
/CAS before /RAS refresh
-6,-6S
(Note 3,5)
520
mode
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
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MITSUBISHI LSIs
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
[MH4V644AXJJ]
Limits
Min Typ
Symbol
Parameter
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V£VOUT£3.6V
0V£VIN£3.6V, Other input pins=0V -40
/RAS, /CAS cycling
tRC=tWC=min.
Unit
V
V
uA
Max
Vcc
0.4
10
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
2.4
0
-10
uA
40
Average supply
-5,-5S
-6,-6S
560
520
mA
ICC1 (AV)
ICC2
current
(Note 3,4,5)
output open
from Vcc operating
/RAS=/CAS =VIH, output open
/RAS=/CAS³ Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.,/W³ Vcc-0.2
output open
4
2
Supply current from Vcc , stand-by
mA
mA
Average supply current
-5,-5S
420
from Vcc
ICC4(AV)
-6,-6S
-5,-5S
380
560
Fast-Page-Mode (Note 3,4,5)
Average supply current
/CAS before /RAS refresh cycling
tRC=min.
output open
from Vcc
mA
ICC6(AV)
/CAS before /RAS refresh
-6,-6S
(Note 3,5)
520
mode
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Limits
Typ Max
Symbol
Parameter
Unit
Test conditions
Min
CI (A)
CI
Input capacitance, address inputs
Input capacitance, clock inputs except CAS
40
45
25
25
pF
pF
pF
pF
pF
pF
VI=Vss
f=1MHZ
Vi=25mVrms
C(CAS) Input capacitance, CAS
C(DQ) Input/Output capacitance,DATA
C(SDA)
C(SCL) Input capacitance, SCL
Input/Output capacitance,SDA
12
12
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MIT-DS-0072-0.5
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MITSUBISHI LSIs
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Preliminary
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
SWITCHING CHARACTERISTICS
Limits
-5,-5S
-6,-6S
Symbol
Parameter
Unit
Min Max Min Max
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Access time from /OE
13
50
25
30
13
tCAC
tRAC
tAA
tCPA
tOEA
tCLZ
tOFF
tOEZ
15
60
30
35
15
ns
ns
ns
ns
ns
ns
ns
ns
(Note 7)
5
0
0
5
0
0
Output low impedance time from /CAS low
Output disable time after /CAS high
Output disable time after /OE high
(Note 12)
13
13
15
15
(Note 12)
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD³ tRCD(max), tASC³ tASC(max) and tCP³ tCP(max).
9: Assumes that tRCD£tRCD(max) and tRAD£tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD³ tRAD(max) and tASC£tASC(max).
11: Assumes that tCP£tCP(max) and tASC³ tASC(max).
12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT£ I ±10uAI) and
is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
-5,-5S
-6,-6S
Symbol
Parameter
Unit
Min Max Min Max
tREF
tRP
Refresh cycle time
/RAS high pulse width
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64
64
30
18
5
0
10
40
20
10
0
10
15
0
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
(Note15)
37
45
(Note16) 13
25
5
30
10
0
(Note17)
0
0
8
13
10
15
0
(Note18)
(Note18)
(Note19)
(Note19)
(Note20)
0
0
13
13
1
Delay time, data to /OE low
Delay time, /CAS high to data
Delay time, /OE high to data
0
15
15
1
Transition time
50
50
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics
are 2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min)=tRAH(min)+2tT+tASC(min) .
16: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by
tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
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MITSUBISHI LSIs
Preliminary
Preliminary
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
Parameter
-5,-5S
-6,-6S
Unit
Min Max Min Max
tRC
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
/CAS hold time after /OE low
/RAS hold time after /OE low
90
50
13
50
13
0
110
60
15
60
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tOCH
tORH
10000
10000
10000
10000
(Note 21)
(Note 21)
0
0
10
25
13
13
10
30
15
15
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
-5,-5S
Min Max Min Max
90 110
50 10000 60 10000
13 10000 15 10000
-6,-6S
Unit
tWC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
/OE hold time after /W low
50
13
0
60
15
0
(Note 23)
10
13
13
10
0
10
15
15
10
0
tDS
tDH
tOEH
10
13
10
15
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MIT-DS-0072-0.5
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MITSUBISHI LSIs
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Preliminary
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Limits
-5,-5S
-6,-6S
Unit
Symbol
Parameter
Min Max Min Max
(Note22)
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
130
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85 10000 95 10000
50
85
50
0
30
65
40
15
15
10
0
50
95
50
0
30
75
45
15
15
10
0
10000
10000
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
(Note23)
(Note23)
(Note23)
Data setup time before /W low
Date hold time after /W low
/OE hold time after /W low
tDS
tDH
tOEH
10
10
10
15
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min)
and tCPWD³ tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until
/CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Limits
Symbol
Parameter
-5,-5S
-6,-6S
Unit
Min Max Min Max
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
35
70
85
5
30
30
40
75
100
10
35
35
ns
ns
ns
ns
ns
ns
125000
100000
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to /W low
(Note25)
(Note26)
10
15
(Note23)
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only.If tCP³ tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Limits
Symbol
Parameter
-5,-5S
-6,-6S
Unit
Min Max Min Max
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
5
10
10
10
5
10
10
10
ns
ns
ns
ns
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
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MITSUBISHI LSIs
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item,line -5S / -6S. The other characteristics
and requirements then below are same as normal device.
ELECTRIC CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
Limits
Min Typ
Symbol
Parameter
Test conditions
/RAS=/CAS<0.2V
/OE=/W=A0~A12(A11)=Vcc-0.2V or
0.2V output=Vcc-0.2V,0.2V or open
Unit
µA
Max
Average supply current
from Vcc Self-Refresh mode
ICC9(AV)*
-5S,-6S
1600
(Note 6)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
TIMING REQUIREMENTS
Limits
Symbol
Parameter
-5S
Max
-6S
Max
Unit
Min
100
90
Min
100
110
- 50
tRASS
CBR Self Refresh RAS low pulse width
CBR Self Refresh RAS high precharge time
CBR Self Refresh RAS hold time
us
ns
ns
tRPS
tCHS
- 50
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS£ 64 ms and tSN £ 64 ms.
tSN
tNS
Self refresh period
DISTRIBUTED REFRESH
< 64 ms >
DISTRIBUTED REFRESH
< 64 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS £ 16ms and tSN £ 16 ms.
tSN
tNS
Self refresh period
BURST REFRESH
BURST REFRESH
< 64 ms >
< 64 ms >
MITSUBISHI
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MIT-DS-0072-0.5
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Timing Diagrams (Note 28)
Read Cycle
tRC
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tRPC
tCRP
tASR
tCRP
tASR
tRCD
tRSH
tCAS
VIH
VIL
tRAD
tRAL
tRAH
tASC
tCAH
tCPN
tRCH
VIH
ROW
ADDRESS
COLUMN
ROW
ADDRESS
ADDRESS
Address
VIL
tRRH
tRCS
VIH
VIL
W
tDZC
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tOFF
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA VALID
tOEZ
Hi-Z
Hi-Z
tRAC
tDZO
tODD
tOEA
tOCH
VIH
VIL
OE
tORH
Indicates the don't care input.
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Note 28
Indicates the invalid output.
MITSUBISHI
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Early write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
tWCS
tWCH
VIH
VIL
W
tDH
tDS
VIH
VIL
DQ
(INPUTS)
DATA VALID
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
MITSUBISHI
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26/Feb./1997
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/ 25 )
16
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Delayed write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCRP
tASR
tRCD
tRSH
tCAS
tCRP
VIH
CAS
VIL
tRAH
tCAH
tASC
tASR
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tCWL
tRWL
tWP
tRCS
VIH
W
VIL
tWCH
tDZC
tDS
tDH
VIH
DQ
DATA
VALID
Hi-Z
tCLZ
(INPUTS)
VIL
VOH
DQ
Hi-Z
Hi-Z
(OUTPUTS)
VOL
tOEH
tOEZ
tDZO
tODD
VIH
OE
VIL
MITSUBISHI
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( 17 / 25 )
MIT-DS-0072-0.5
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tRCD
tRSH
tCAS
tCRP
tCRP
VIH
VIL
CAS
tRAD
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
ROW
ADDRESS
COLUMN
ROW
ADDRESS
Address
ADDRESS
tAWD
tCWL
tRWL
tWP
tCWD
tRWD
tRCS
VIH
VIL
W
tDH
tDS
tDZC
VIH
VIL
DQ
(INPUTS)
DATA VALID
Hi-Z
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
OE
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MITSUBISHI LSIs
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Preliminary
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
VIL
RAS
tCRP
tCSR
tRPC tCSR
tRPC
tRPC
tCHR
tCHR
VIH
VIL
CAS
tCPN
tASR
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
Address
tRCH tRSR
tRHR
tRSR
tRHR
tRCS
VIH
VIL
W
VIH
VIL
DQ
(INPUTS)
tOFF
tOEZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
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Preliminary
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 29)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
RAS
CAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
tRCS
tRRH
tRAL
VIH
VIL
W
tDZC
tCDD
tOFF
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEZ
tOEA
tORH
tODD
VIL
VIH
OE
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
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MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS
tRP
VIH
VIL
RAS
tCSH
tPC
tRSH
tCAS
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
VIH
VIL
CAS
tCPRH
tASC
tRAD
tRAH
tASC
tCAH
tCAH
tCAH
tASR
tASC
ROW
ADDRESS
VIH
VIL
ROW
COLUMN-1
COLUMN-2
tRCS
COLUMN-3
Address
ADDRESS
tRAL
tRCS
tRCH
tRCS
tRRH
tRCH
tRCH
VIH
VIL
W
tDZC
tCDD
tDZC
tDZC
VIH
VIL
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tAA
tOFF
tOFF
tCAC
tAA
tOFF
tCAC
tAA
tCLZ
tCLZ
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tOCH
tOEA
tOCH
tOEA
tOCH
tOEZ
tOEZ
VIL
VIH
OE
tODD
tDZO
tDZO
tODD
tODD
tORH
MITSUBISHI
ELECTRIC
(21 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tPC
tRSH
tCAS
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
VIH
VIL
CAS
tRAH
tCAH
tCAH
tCAH
tASC
tASC
tASC
tASR
ROW
ADDRESS
VIH
VIL
ROW
ADDRESS
COLUMN-1
COLUMN-3
COLUMN-2
Address
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
W
tDH
tDS
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
OE
MITSUBISHI
ELECTRIC
(22 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tRSH
tPC
tCRP
tRCD
tCAS
tCP
tCAS
VIH
VIL
CAS
tRWL
tASR
tASC
tRAH
tCAH
tCAH
tCWL
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
Address
COLUMN-2
tCWL
tWP
tPCS
tRCS
tWP
VIH
VIL
W
tWCH
tDS
tWCH
tDS
tDZC
tDZC
tDH
tDH
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCLZ
tDZO
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tOEZ
tOEZ
tOEH
tODD
tDZO
tODD
VIH
VIL
OE
MITSUBISHI
ELECTRIC
( 23 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
RAS
CAS
tCSH
tRWL
tCRP
tASR
tRCD
tCAS
tPRWC
tCAS
tCP
VIH
VIL
tRAD
tRAH
tASC
tCAH
tCAH
tCWL
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
Address
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
W
tRWD
tCPWD
tDZC
tDZC
tDH
tDH
tDS
tDS
DQ
(INPUTS)
VIH
VIL
DATA
VALID-1
DATA
VALID-2
Hi-Z
Hi-Z
tCAC
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-1
DATA
VALID-1
Hi-Z
Hi-Z
Hi-Z
tCPA
tODD
tOEZ
tODD
tDZO tOEA
tOEH
tDZO
tOEZ
tOEA
VIH
VIL
OE
MITSUBISHI
ELECTRIC
(24 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Outline
3.63MAX
67.6
4.6
23.2
29
32.8
32.8
3.3
3.7
1.00
23.2
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ELECTRIC
( 25 / 25 )
MIT-DS-0072-0.5
26/Feb./1997
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