MH8S64AQFC-6L [MITSUBISHI]
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM; 536,870,912位（ 8,388,608 - WORD 64位） SynchronousDRAM
| 型号： | MH8S64AQFC-6L |
| 厂家： | 
Mitsubishi Group |
| 描述： | 536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM |
| 文件： | 总55页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
Utilizes industry standard 8M x 16 Sy nchronous DRAMs
The MH8S64AQFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock rising
edge
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
FEATURES
CLK Access Time
Frequency
(Component SDRAM)
5.4ns(CL=3)
6.0ns(CL=2)
6.0ns(CL=3)
-6,-6L
-7,-7L
-8,-8L
133MHz
100MHz
100MHz
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
143
144
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
Front side
Pin Name
Back side
Pin Name
Front side
Pin Name
Back side
Pin Name
PIN
Number
PIN
Number
PIN
Number
PIN
Number
1
Vss
2
Vss
73
75
NC
Vss
74
76
78
80
82
84
86
88
CLK1
Vss
3
5
DQ0
DQ1
4
6
DQ32
DQ33
NC
77
NC
79
NC
7
9
DQ2
DQ3
8
DQ34
DQ35
NC
10
81
Vcc
Vcc
83
DQ16
DQ17
DQ18
11
13
Vcc
12
14
Vcc
DQ48
DQ49
DQ50
DQ4
DQ36
85
15
17
DQ5
DQ6
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DQ37
DQ38
DQ39
Vss
87
89
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
90
DQ51
Vss
91
19
21
23
DQ7
Vss
92
93
94
DQ52
DQ53
DQ54
DQ55
Vcc
DQMB0
DQMB4
DQMB5
95
96
DQMB1
Vcc
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
97
98
99
Vcc
A3
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A0
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A7
A2
A8
A5
BA0
Vss
Vss
A9
Vss
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ40
DQ41
DQ42
DQ43
Vcc
BA1
A10
A11
Vcc
Vcc
DQMB2
DQMB6
DQMB7
Vss
DQMB3
Vss
DQ12
DQ13
DQ14
DQ15
Vss
DQ44
DQ45
DQ46
DQ47
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
NC
NC
DQ28
DQ29
DQ30
DQ31
Vss
NC
DQ60
DQ61
DQ62
DQ63
Vss
NC
CLK0
Vcc
CKE0
Vcc
/RAS
/WE
/S0
/CAS
CKE1
NC
SDA
SCL
/S1
Vcc
NC
Vcc
NC = No Connection
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB4
DQMB0
DQML
DQML
/CS
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D2
DQMB1
DQMB5
DQMU
DQMU
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB6
DQMB2
DQML
DQML
/CS
/CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D3
DQMB3
DQMB7
DQMU
DQMU
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10W
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CLK0
CKE0
D0 - D3
D0 - D3
CLK1
/RAS
D0 - D3
D0 - D3
D0 - D3
/CAS
/WE
BA0,BA1,A<11:0>
D0 - D3
SERIAL PD
A0 A1 A2
SDA
SCL
Vcc
Vss
D0 - D3
MIT-DS-0374-0.3
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/ 55 )
3
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
Function described
SPD enrty data
128
SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr
80
08
04
0C
256 Bytes
SDRAM
A0-A11
1
Total # bytes of SPD memory device
Fundamental memory type
2
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
3
A0-A8
1BANK
x64
09
01
40
4
5
6
... Data Width continuation
0
00
01
75
A0
7
8
Voltage interface standard of this assembly
LVTTL
7.5ns
10ns
-6,-6L
SDRAM Cycletime at Max.Supported CAS Latency (CL).
Cycle time for CL=3
9
-7,-7L,-8,-8L
-6,-6L
54
10
5.4ns
6ns
SDRAM Access from Clock
tAC for CL=3
-7,-7L,-8,-8L
60
00
80
10
00
01
8F
04
06
Non-PARITY
11
12
13
14
15
16
17
18
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
self refresh(15.625uS)
SDRAM width,Primary DRAM
x16
Error Checking SDRAM data width
N/A
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
1
1/2/4/8/Full page
4bank
# Banks on Each SDRAM device
CAS# Latency
2/3
19
20
21
22
23
CS# Latency
Write Latency
0
01
01
00
0E
0
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Module Attributes
SDRAM Device Attributes:General
-6,-6L,-7,-7L
SDRAM Cycle time(2nd highest CAS latency)
10ns
13ns
6ns
A0
Cycle time for CL=2
-8,-8L
-6,-6L,-7,-7L
-8,-8L
D0
SDRAM Access form Clock(2nd highest CAS latency)
24
60
tAC for CL=2
7ns
N/A
70
00
25
26
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
N/A
22.5ns
00
17
-6,-6L
27
28
29
30
Precharge to Active Minimum
20ns
14
-7,-7L,-8,-8L
-6,-6L
15ns
20ns
0F
14
Row Active to Row Active Min.
-7,-7L,-8,-8L
-6,-6L
22.5ns
20ns
17
14
2D
RAS to CAS Delay Min
Active to Precharge Min
-7,-7L,-8,-8L
-6,-6L
45ns
50ns
32
-7,-7L,-8,-8L
MIT-DS-0374-0.3
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ELECTRIC
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(
/ 55 )
4
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
Density of each bank on module
64MByte
10
-6,-6L
1.5ns
2ns
15
20
Command and Address signal input setup time
-7,-7L,-8,-8L
-6,-6L
08
0.8ns
1ns
Command and Address signal input hold time
Data signal input setup time
33
34
-7,-7L,-8,-8L
10
15
20
1.5ns
2ns
-6,-6L
-7,-7L,-8,-8L
-6,-6L
0.8ns
1ns
08
10
Data signal input hold time
35
-7,-7L,-8,-8L
36-61
62
Superset Information (may be used in future)
SPD Revision
option
00
12
rev 1.2B
Check sum for -6,-6L
Check sum for -7,-7L
Check sum for -8,-8L
MITSUBISHI
AC
63
Checksum for bytes 0-62
0D
4D
64-71
Manufactures Jedec ID code per JEP-108E
1CFFFFFFFFFFFFFF
Miyoshi,Japan
Tajima,Japan
01
02
72
Manufacturing location
NC,USA
03
Germany
04
4D4838533634415146432D36202020202020
4D4838533634415146432D364C2020202020
4D4838533634415146432D37202020202020
4D4838533634415146432D374C2020202020
4D4838533634415146432D38202020202020
4D4838533634415146432D384C2020202020
MH8S64AQFC-6
MH8S64AQFC-6L
MH8S64AQFC-7
MH8S64AQFC-7L
73-90
Manufactures Part Number
MH8S64AQFC-8
MH8S64AQFC-8L
91-92
93-94
95-98
99-125
126
Revision Code
PCB revision
year/week code
serial number
option
rrrr
yyww
ssssssss
00
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
100MHz
64
CL=2/3,AP,CK0,1
-6,-6L,-7,7L
-8,8L
8F
Intel specification CAS# Latency support
Unused storage locations
127
CL=3,AP,CK0,1
open
8D
128+
00
MIT-DS-0374-0.3
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/ 55 )
5
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CLK0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE0
Input
Chip Select: When /S is high,any command means
No Operation.
/S0
Input
Input
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
A0-11
Input
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
BA0,1
Input
Data In and Data out are referenced to the rising edge
of CK
Input/Output
DQ0-63
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Input
Power Supply Power Supply for the memory mounted module.
Vdd,Vss
SCL
Input
Serial clock for serial PD
Serial data for serial PD
SDA
Output
MIT-DS-0374-0.3
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( 6 / 55 )
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S64AQFC provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
Chip Select : L=select, H=deselect
/S
Command
/RAS
Command
Command
define basic commands
/CAS
/WE
CKE
A10
Ref resh Option @ref resh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CKE CKE
/CAS
A11
MNEMONIC
COMMAND
/RAS
/WE BA0,1
A10
A0-9
/S
n-1
n
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
No Operation
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
WRITEA
READ
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
L
V
V
V
V
V
V
V
V
L
V
V
V
V
Column Address Entry
& Write with Auto-
Precharge
L
H
L
Column Address Entry
& Read
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
L
REFSX
H
H
X
X
X
H
H
L
X
H
H
L
X
L
X
Burst Terminate
TERM
MRS
H
H
X
V*1
Mode Register Set
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0374-0.3
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ELECTRIC
22.Sep.2000
( 8 / 55 )
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Command
DESEL
NOP
Current State
IDLE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
L
BA
TBST
ILLEGAL*2
L
X
H
L
BA,CA,A10
BA,RA
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
PRE/PREA NOP*4
L
H
H
L
L
L
BA,A10
X
L
L
H
REFA
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
BA,A10
PRE/PREA Precharge/Precharge All
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
X
TBST
BA
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0374-0.3
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ELECTRIC
( 9 / 55 )
22.Sep.2000
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
BA
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
READ/READA
L
L
H
H
L
L
H
L
BA,CA,A10
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
BA
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
Bank Active/ILLEGAL*2
BA,A10
PRE/PREA ILLEGAL*2
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
WRITE with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
TBST
BA
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
BA,RA
BA,A10
X
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2
PRE/PREA ILLEGAL*2
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
MIT-DS-0374-0.3
MITSUBISHI
ELECTRIC
( 10 / 55 )
22.Sep.2000
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING
L
BA
TBST
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
L
H
H
L
BA,RA
ACT
ILLEGAL*2
L
L
BA,A10
PRE/PREA NOP*4(Idle after tRP)
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
X
BA
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0374-0.3
MITSUBISHI
ELECTRIC
( 11/ 55 )
22.Sep.2000
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
L
H
H
L
BA,RA
ACT
ILLEGAL
L
L
BA,A10
PRE/PREA ILLEGAL
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL
L
PRE/PREA ILLEGAL
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CK
n-1
CK
n
Action
Current State
/RAS /CAS /WE Add
/S
INVALID
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
REFRESH*1
L
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
Enter Power Down
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
ILLEGAL
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0374-0.3
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13
MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE
READ
READA
READ
WRITEA
WRITE
CKEL
CKEL
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
PRE
READA
PRE
POWER
APPLIED
POWER
ON
PRE
Automatic Sequence
Command Sequence
MIT-DS-0374-0.3
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22.Sep.2000
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/CAS
WM
0
0
0
0
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
V
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
LENGTH
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
8
8
R
R
R
FP
R
R
R
R
LATENCY
MODE
3
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
BURST
SINGLE BIT
0
1
WRITE
MODE
MIT-DS-0374-0.3
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22.Sep.2000
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
CK
Command
Address
DQ
Read
Y
Write
Y
Q0
Q1
Q2
Q3
D0
D1
D3
D2
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
MIT-DS-0374-0.3
MITSUBISHI
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22.Sep.2000
( 16/ 55 )
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command ACT
ACT
Xb
READ
Yb
0
PRE
ACT
Xa
tRCD
tRRD
tRP
A0-9,11
A10
Xa
Xa
Xb
1
Xa
BA0,1 00
DQ
01
01
00
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
defined by the Burst Type. Minimum delay time of a READ command after an ACT command
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.
MIT-DS-0374-0.3
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/ 55 )
17
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command
ACT
READ
ACT
READ PRE
Yb
ACT
tRCD
tRCD
tRP
Xa
Xa
Ya
0
Xb
Xb
Xa
Xa
A0-9, 11
0
0
A10
BA0,1
DQ
00
01
00
00
00
01
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
READ with Auto-Precharge (BL=4, CL=2)
CK
Command ACT
READ
ACT
tRCD
tRP
BL
Xa
Xa
Xa
Ya
1
A0-9, 11
A10
Xa
00
BA0,1
DQ
00
00
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
CK
Command
ACT
READ
ACT
tRCD
BL
CL=3 DQ
CL=2 DQ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRCD
BL
tRP
Xa
Xa
Ya
0
Xa
Xa
A0-9, 11
A10
0
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRP
tRCD
BL
Xa
Xa
Xa
Xa
Ya
1
A0-9, 11
A10
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
Internal precharge begins
MIT-DS-0374-0.3
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19
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read oparation can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
A0-9,11
A10
READ
Ya
0
READ READ
Yb
0
Yc
0
BA0,1
DQ
00
00
10
Qa0 Qa1 Qa2 Qb0 Qc0 Qc1
Qc2 Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 1 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command ACT
READ
Ya
0
Write
Ya
0
Xa
A0-9,11
A10
Xa
00
00
00
BA0,1
DQMB0-7
DQ
Qa0
Da0 Da1 Da2 Da3
Output disableby DQM by WRITE
MIT-DS-0374-0.3
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20
(
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by precharge of the same bank. Read to PRE
interval is minimum 1 CK. A PRE command output disable latency is equivalent to the
/CAS Latency.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
READ
PRE
Q0
DQ
Q1
Q1
Q2
CL=3
Command
PRE
DQ
Q0
Q0
Command
READ PRE
DQ
Command
DQ
READ
PRE
Q1
Q0
Q2
CL=2
Command
READ
PRE
Q0
DQ
Q1
Command
READ PRE
DQ
Q0
MIT-DS-0374-0.3
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21
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Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
and disable the data output. The terminated bank remains active,READ to TBST interval is
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.
Read Interrupted by Terminate (BL=4)
CK
Command
DQ
READ
TBST
Q0
Q1
Q1
Q2
Command
DQ
READ
TBST
CL=3
Q0
Q0
Command
DQ
READ TBST
Command
DQ
TBST
Q1
READ
READ
Q0
Q2
Command
DQ
TBST
Q0
CL=2
Q1
Command
DQ
TBST
READ
Q0
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11
A10
Write
Ya
Write Write
Yb
0
Yc
0
0
BA0,1
00
00
10
DQ
Da0 Da1 Da2 Db0 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command
ACT
Write
READ
A0-9,11
A10
Xa
Xa
Ya
0
Yb
0
00
BA0,1
DQ
00
00
Da0 Da1
Qb0 Qb1
Qb2 Qb3
don't care
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRP
Xa
0
Ya
0
Xa
0
A0-9,11
A10
0
00
00
00
00
BA0,1
DQMB0-7
DQ
tWR
Da0 Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
ACT
Xa
0
Write
Ya
0
TBST
Write
Yb
0
A0-9,11
A10
BA0,1
DQ
00
00
00
Da0 Da1
Db0 Db1 Db2 Db3
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank.
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-
precharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
Write
Write
BL
ACT
tRP
Ya
1
Ya
Xa
Xa
A0-9,11
A10
tWR
0
00
10
00
BA0,1
DQ
Da0 Da1 Db0 Db1 Db2 Db3
activate
auto-precharge
interrupted
WRITEA interrupted by READ to another bank (CL=2,BL=4)
CK
Write
Ya
1
Command
Read
BL
ACT
Xa
tRP
Yb
A0-9,11
A10
tWR
0
Xa
BA0,1
DQ
00
10
00
Da0 Da1
Db0 Db1 Db2 Db3
activate
auto-precharge
interrupted
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read toanother bank. Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.
READA Interrupted by READ to another bank (CL=2,BL=4)
CK
Command
Read
Read
BL
ACT
tRP
Ya
1
Ya
Xa
Xa
A0-9,11
A10
tWR
0
00
10
00
BA0,1
DQ
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3
activate
auto-precharge
interrupted
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
issued. In case of the full page burst , a read or write with auto-precharge command
is illegal.
Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
BA0,1
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.
CK
(ext.CLK)
tIH tIS
tIH tIS
CKE
int.CLK
Power Down by CKE
CK
CKE
Standby Power Down
Activ e Power Down
Command
PRE NOP NOP NOP
CKE
Command
NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
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Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQMB0-7
READ
Write
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMB=H
disabled by DQMB=H
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Supply Voltage
Input Voltage
Condition
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
Unit
V
with respect to Vss
VI
with respect to Vss
with respect to Vss
V
-0.5 ~ 4.6
VO
IO
Output Voltage
Output Current
V
mA
W
50
4
Ta=25°C
Pd
Power Dissipation
Operating Temperature
Topr
0 ~ 70
°C
°C
Tstg
Storage Temperature
-40 ~ 100
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Vdd
Vss
VIH
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 f or pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits(max.)
Symbol
Parameter
Test Condition
Unit
CI(A) Input Capacitance, address pin
pF
pF
35
35
35
22
@1MHz
CI(C)
Input Capacitance, /RAS,/CAS,/WE
1.4V bias
200mV swing
pF
pF
CI(K) Input Capacitance, CK pin
Input Capacitance, I/O pin
CI/O
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
(max)
Parameter
Symbol
Test Condition
Unit
-7,-7L
-8,-8L
-6,-6L
520
operating current
tRC=min.tCLK=min, BL=1,CL=3
mA
mA
480
Icc1
one bank activ e (discrete)
precharge stanby
current
in power-down mode
precharge stanby current
in non power-down mode
8
4
8
4
Icc2P
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
mA
mA
mA
Icc2PS
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed)
100
60
100
60
Icc2N
Icc2NS
active stanby current
120
120
mA
mA
mA
mA
CKE=H,tCLK=15ns
Icc3N
Icc3NS
Icc4
in non power-down mode
one bank activ e (discrete)
80
640
640
8
80
520
640
8
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks activ e(discerte)
burst current
tRC=min, tCLK=min
Icc5
auto-refresh current
-6,-7,-8
mA
Icc6
self-refresh current
CKE <0.2V
-6L,-7L,-8L
3.2
3.2
Note)
1:Icc(max) is specified at the output open condition.
2.Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
IOH=-2mA
Unit
Min. Max.
2.4
VOH(DC)
VOL(DC)
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
V
V
0.4
IOL=2mA
Q floating VO=0 ~ Vdd -10
10 uA
IOZ
Off-stare Output Current
-40
Input Current
uA
VIH=0 ~ Vdd+0.3V
40
Ii
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-7,-7L
Min. Max. Min. Max.
-6,-6L
-8,-8L
Unit
Symbol Parameter
Min. Max.
CL=2
10
10
13
ns
tCLK
CK cycle time
CL=3
7.5
2.5
2.5
1
1.5
0.8
10
3
3
1
2
10
3
3
1
2
ns
ns
ns
10 ns
ns
tCH CK High pulse width
tCL
tT
tIS
tIH
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
10
10
1
1
ns
tRC Row cycle time
tRCD Row to Column Delay
tRAS Row Active time
67.5
20
45 100K
70
20
70
20
ns
ns
50 100K
50 100K ns
tRP
tWR Write Recovery time
tRRD
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tPDE Power Down Exit time
tREF Refresh Interval time
Row Precharge time
20
12
15
10
7.5
7.5
64
20
12
20
10
20
12
20
10
10
10
ns
ns
ns
ns
ns
ns
Act to Act Deley time
10
10
64
64 ms
Any AC timing is
1.4V
1.4V
CK
referenced to the input
signal crossing
through 1.4V.
Signal
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
-6
-7
-8
Max. Min. Max.
Symbol Parameter
Unit
ns
Max.
6
Min.
Min.
tAC
Access time from CK
CL=2
CL=3
CL=2
6
6
7
6
5.4
ns
ns
ns
Output Hold time
from CK
tOH
3
3
3
3
3
CL=3 2.7
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
tOLZ
tOHZ
0
0
3
0
3
ns
ns
2.7
5.4
6
6
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VOUT
CK
1.4V
50pF
DQ
1.4V
Output Timing
Measurement
Reference Point
1.4V
1.4V
CK
tOLZ
tAC
DQ
tOHZ
tOH
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-8
A10
X
X
X
0
Y
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
0
D0
D0 D0
D0
D0 D0
WRITE#0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A10
A9,11
0
1
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0
D0
D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRP
tRAS
/RAS
/CAS
/WE
CKE
DQM
A0-7
tRCD
tRCD
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A10
A8,9,11
0
0
0
BA0,1
DQ
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³ BL allows full data out
Italic parameter indicates minimum case
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQM
A0-8
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
X
X
X
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
1
0
0
1
2
0
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
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Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
X
0
X
X
X
1
Y
Y
X
X
X
0
Y
X
X
X
1
Y
A10
A9,11
0
1
0
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0 D0
D0
D0 D1
ACT#0
ACT#1
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
ACT#1
WRITE#1 with
AutoPrecharge
WRITE#1
Italic parameter indicates minimum case
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MITSUBISHI LSIs
Preliminary Spec.
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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
Y
X
X
X
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
1
0
0
1
1
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#1 with
Auto-Precharge
READ#0
ACT#1
Italic parameter indicates minimum case
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
tRCD
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A10
A9,11
0
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D0 D0
D0
D0 D1
D1
D1 D1
D0
D0 D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
DQM read latency=2
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
0
1
0
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
tCCD
tRCD
DQM
A0-8
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
A10
A9,11
0
0
0
1
0
BA0,1
DQ
CL=3
D0
D0 D0
D0
D0 D0
D1
D1
Q0
Q0
Q0 Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
0
0
1
0
0
Q0
Q0 Q0
Q0
Q0 Q0
Q1
Q1 Q0
D0 D0
WRITE#0
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
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/ 55 )
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
1
Y
X
X
1
A10
A9,11
0
1
0
1
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1 D1
ACT#0
WRITE#0
PRE#0
ACT#1
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted
by Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
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45
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
1
0
1
1
Q0
Q0 Q0
Q0
Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
M
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
D0
D0
D0 D0
Auto-Ref (last of 8 cycles)
Mode
ACT#0
WRITE#0
Register
Setting
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
Y
A10
A9,11
0
BA0,1
DQ
D0
D0 D0
D0
Auto-Refresh
Before Auto-Refresh,
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
all banks must be idle state.
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
CLK can be stopped
tRC
/RAS
/CAS
/WE
CKE
DQM
A0-8
tSRX
CKE must be low to maintain Self-Refresh
X
X
X
0
A10
A9,11
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Before Self-Refresh Entry,
all banks must be idle state.
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
tRCD
X
X
X
0
Y
Y
Y
A10
A9,11
0
0
0
BA0,1
DQ
masked
masked
D0
D0 D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
DQM read latency=2
X
X
X
0
Y
Y
Y
A10
A9,11
0
0
0
BA0,1
DQ
masked
masked
Q0
Q0 Q0
READ#0
Q0
Q0
Q0
Q0
ACT#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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(
/ 55 )
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
Standby Power Down
Active Power Down
CKE latency=1
X
X
X
0
A10
A9,11
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
tRCD
CKE latency=1
CKE latency=1
X
X
X
0
Y
Y
A10
A9,11
0
0
BA0,1
DQ
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
CLK suspended
READ#0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0374-0.3
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/ 55 )
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
6.00
4.00
MIT-DS-0374-0.3
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MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-0374-0.3
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