PSS05S92F6-AG [MITSUBISHI]

AC Motor Controller, DIP-25/24;


型号：	PSS05S92F6-AG
厂家：	Mitsubishi Group
描述：	AC Motor Controller, DIP-25/24 电动机控制
文件：	总58页 (文件大小：1573K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

<Dual-In-Line Package Intelligent Power Module>

Super mini DIPIPM Ver.6 Series APPLICATION NOTE

PSS**S92E6-AG/ PSS**S92F6-AG

Table of contents

CHAPTER 1 INTRODUCTION .................................................................................................................................2

1.1 Features of Super mini DIPIPM Ver.6 .................................................................................................................... 2

1.2 Functions................................................................................................................................................................ 2

1.3 Target Applications................................................................................................................................................. 3

1.4 Product Line-up...................................................................................................................................................... 4

1.5 The Differences between Previous Series and This Series (PSS**S92*6)............................................................. 4

CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS ...................................................................................6

2.1 Super Mini DIPIPM Ver.6 Specifications................................................................................................................. 6

2.1.1 Maximum Ratings.................................................................................................................................................................................................... 6

2.1.2 Thermal Resistance................................................................................................................................................................................................. 8

2.1.3 Electric Characteristics and Recommended Conditions ......................................................................................................................................... 9

2.1.4 Mechanical Characteristics and Ratings ............................................................................................................................................................... 11

2.2 Protective Functions and Operating Sequence.................................................................................................... 12

2.2.1 Short Circuit Protection..........................................................................................................................................................................................12

2.2.2 Control Supply UV Protection................................................................................................................................................................................14

2.2.3 OT Protection (PSS**S92E6-AG only) ..................................................................................................................................................................16

2.2.4 Temperature output function V_OT(PSS**S92F6-AG only)..................................................................................................................................... 17

2.3 Package Outlines................................................................................................................................................. 22

2.3.1 Package outlines ...................................................................................................................................................................................................22

2.3.2 Marking ..................................................................................................................................................................................................................23

2.3.3 Terminal Description ..............................................................................................................................................................................................24

2.4 Mounting Method ................................................................................................................................................. 26

2.4.1 Electric Spacing .....................................................................................................................................................................................................26

2.4.2 Mounting Method and Precautions........................................................................................................................................................................26

2.4.3 Soldering Conditions..............................................................................................................................................................................................27

CHAPTER 3 SYSTEM APPLICATION GUIDANCE................................................................................................28

3.1 Application Guidance ........................................................................................................................................... 28

3.1.1 System connection ................................................................................................................................................................................................28

3.1.2 Interface Circuit (Direct Coupling Interface example for using one shunt resistor) .............................................................................................. 29

3.1.3 Interface Circuit (Example of Optocoupler Isolated Interface) .............................................................................................................................. 30

3.1.4 External SC Protection Circuit with Using Three Shunt Resistors........................................................................................................................ 31

3.1.5 Circuits of Signal Input Terminals and Fo Terminal ............................................................................................................................................... 31

3.1.6 Snubber Circuit ......................................................................................................................................................................................................33

3.1.7 Recommended Wiring Method around Shunt Resistor......................................................................................................................................... 33

3.1.8 Precaution for Wiring on PCB................................................................................................................................................................................35

3.1.9 Parallel operation of DIPIPM .................................................................................................................................................................................36

3.1.10 SOA of DIP Ver.6 .................................................................................................................................................................................................36

3.1.11 SCSOA.................................................................................................................................................................................................................37

3.1.12 Power Life Cycles................................................................................................................................................................................................39

3.2 Power Loss and Thermal Dissipation Calculation ................................................................................................ 40

3.2.1 Power Loss Calculation .........................................................................................................................................................................................40

3.2.2 Temperature Rise Considerations and Calculation Example................................................................................................................................ 42

3.2.3 Installation of thermocouple...................................................................................................................................................................................43

3.3 Noise and ESD Withstand Capability................................................................................................................... 44

3.3.1 Evaluation Circuit of Noise Withstand Capability ..................................................................................................................................................44

3.3.2 Countermeasures and Precautions.......................................................................................................................................................................44

3.3.3 Static Electricity Withstand Capability....................................................................................................................................................................45

CHAPTER 4 Bootstrap Circuit Operation ...............................................................................................................46

4.1 Bootstrap Circuit Operation.................................................................................................................................. 46

4.2 Bootstrap Supply Circuit Current at Switching State ............................................................................................ 47

4.3 Note for designing the bootstrap circuit................................................................................................................ 49

4.4 Initial charging in bootstrap circuit........................................................................................................................ 50

CHAPTER 5 Interface Demo Board........................................................................................................................51

5.1 Super mini DIPIPM Ver.6 Interface Demo Board.................................................................................................. 51

5.2 Interface demo board pattern............................................................................................................................... 52

5.3 Circuit Schematic and Parts List .......................................................................................................................... 53

CHAPTER 6 PACKAGE HANDLING ......................................................................................................................55

6.1 Packaging Specification ....................................................................................................................................... 55

6.2 Handling Precautions........................................................................................................................................... 56

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 1 INTRODUCTION

1.1 Features of Super mini DIPIPM Ver.6

Super Mini DIPIPM Ver.6 (hereinafter called DIP Ver.6) is an ultra-small compact intelligent power module with

transfer mold package favorable for larger mass production. Power chips, drive and protection circuits are integrated

in the module, which make it easy for AC100-240V class low power motor inverter control.

DIP Ver.6 takes over the functions of conventional DIP Ver.5 (such as incorporating bootstrap diode with resistor,

analog signal output), additionally, DIP Ver.6 is improved more.

Main features of DIP Ver.6 are as below.

・Newly developed 7th generation CSTBT are integrated for improving efficiency.

・Wider overload operating range by improvement in accuracy of short circuit trip level.

・Expanding line-up up to 35A.

・Easy to replace from conventional Ver.5 due to high pin compatibility.

About detailed differences, please refer Section 1.5. Fig.1-1-1 and Fig.1-1-2 show the outline and internal

cross-section structure respectively.

Cu frame

FWDi

Aluminum wire

IGBT

Insulated thermal

radiating sheet

Mold resin

Gold wire

(Copper foil + insulated resin)

Fig.1-1-1 Package photograph

Fig.1-1-2 Internal cross-section structure

1.2 Functions

DIP Ver.6 has following functions and inner block diagram as described in Fig.1-2-1.

●

For P-side IGBTs:

- Drive circuit;

- High voltage level shift circuit;

- Control supply under voltage (UV) lockout circuit (without fault signal output).

- Built-in bootstrap diode (BSD) with current limiting resistor

For N-side IGBTs:

●

-Drive circuit;

-Short circuit (SC) protection circuit (by inserting external shunt resistor into main current path)

-Control supply under voltage (UV) lockout circuit (with fault signal output)

-Over temperature (OT) protection by monitoring LVIC temperature.（PSS**S92E6 series only）

-Outputting LVIC temperature by analog signal (PSS**S92F6 series only)

Fault Signal Output

●

-Corresponding to N-side IGBT SC, N-side UV and OT protection.

IGBT Drive Supply

(OT:PSS**S92E6 series only)

-Single DC15V power supply (in the case of using bootstrap method)

Control Input Interface

-Schmitt-triggered 3V, 5V input compatible, high active logic.

UL recognized

-UL 1557

File E323585

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

7th generation

Full gate CSTBT

Bootstrap Diode

with current limiting

DIPIPM

HVIC

resistor

V_P1

V_CC

IGBT1

Di1

U_OUT

V_US

V_UFB

U_P

V_UB

U_P

IGBT2

Di2

V_OUT

V_VS

V_VFB

V_P

V_VB

V_P

IGBT3

IGBT4

IGBT5

IGBT6

Di3

Di4

Di5

Di6

V_WFB

V_WB

W_P

W_OUT

V_WS

COM

V_NC

LVIC

U_OUT

V_N1

V_CC

V_OUT

U_N

V_N

U_N

V_N

Temperature output

terminal

W_N

W_OUT

CIN

V_OT

V_NC

V_OT

GND

CIN

Fig.1-2-1 Inner block diagram

1.3 Target Applications

Motor drives for household electric appliances, such as air conditioners, washing machines, refrigerators

Low power industrial motor drive except automotive applications

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

1.4 Product Line-up

Table 1-4-1 DIP Ver.6 Line-up with temperature output function

Type Name ^{(Note 1)}

IGBT Rating

Motor Rating ^{(Note 1)}

0.4kW/220VAC

0.75kW/220VAC

1.5kW/220VAC

2.2kW/220VAC

Isolation Voltage

PSS05S92F6-AG

5A/600V

PSS10S92F6-AG

PSS15S92F6-AG

PSS20S92F6-AG

PSS30S92F6-AG

PSS35S92F6-AG

10A/600V

15A/600V

20A/600V

30A/600V

35A/600V

V_iso= 1500Vrms

(Sine 60Hz, 1min

All shorted pins-heat

sink)

Table 1-4-2 DIP Ver.6 Line-up with over temperature protection function

Type Name ^{(Note 1)}

IGBT Rating

Motor Rating ^(Note1)

0.4kW/220VAC

0.75kW/220VAC

1.5kW/220VAC

2.2kW/220VAC

Isolation Voltage

PSS05S92E6-AG

5A/600V

PSS10S92E6-AG

PSS15S92E6-AG

PSS20S92E6-AG

PSS30S92E6-AG

PSS35S92E6-AG

10A/600V

15A/600V

20A/600V

30A/600V

35A/600V

V_iso= 1500Vrms

(Sine 60Hz, 1min

All shorted pins-heat

sink)

Note 1: The motor ratings are simulation results under following conditions: V_AC=220V, V_D=V_DB=15V, Tc=100°C,

Tj=125°C, f_PWM=5kHz, P.F=0.8, motor efficiency=0.75, current ripple ratio=1.05, motor over load 150% 1min.

1.5 The Differences between Previous Series and This Series (PSS**S92*6)

DIP Ver.6 has some differences against DIP Ver.4 (PS219A*) and DIP Ver.5 (PS219B*)

Main differences are described in Table 1-5-1, Table 1-5-2.

Table 1-5-1 Differences of functions and outlines

Items

Ver.4 with BSD

Ver.5

Built-in

with current

Ver.6

Ref.

Section

4.2

Built-in bootstrap diodes ¹⁾

Built-in



limiting resistor

Section

2.2.4

Temperature protection

OT (-T)

OT or VOT ²⁾



Dummy terminal

Add one terminal

(No. 1-B pin)

Common / Open



Open³⁾



Section

2.3

(Compare with PS2196*) ³⁾

N-side IGBT emitter terminal

(1)DIP Ver.5 and DIP Ver.6 have built-in bootstrap diode (BSD) with current limiting resistor. So there aren't any

limitation about bootstrap capacitance like PS219A* has (22μF or less in the case of one long pulse initial

charging).

(2) Temperature protection function of both DIP Ver.5 and DIP Ver.6 is selectable from two functions. (They have

different model numbers.) One is conventional over temperature protection (OT), and the other is LVIC

temperature output function (V_OT). OT function shutdowns all N-side IGBTs automatically when LVIC temperature

exceeds specified value (typ.120 °C). But V_OTfunction cannot shutdown by itself in that case. So it is necessary

for system controller to monitor this V_OToutput and shutdown when the temperature reaches the protection level.

(3) Because of incorporating bootstrap diodes, a part of package was changed. (Just one dummy terminal was

added) But its package size, pin assignment and pin number weren’t changed, so the same PCB can be used with

small modification when replacing from Super min DIP Ver.4. (External bootstrap diodes and current limit resistors

should be removed in the case of replacing from PS2196*. And also if N-side common emitter type was used in

former PCB, it is necessary to change wiring from common emitter to open emitter wiring because of both DIP

Ver.5 and DIP Ver.6 have open emitter type only.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Table 1-5-2 Differences of specifications and recommended operating conditions

Ver.4 with

Ver.6

Items

Symbol

Ver.5

Current rating

BSD

Current rating 30A, 35A

5~20A

Circuit current for P-side driving

Trip voltage for P-side control

supply under voltage protection

Reset voltage for P-side control

supply under voltage protection

I_D

I_DB

Max. 2.80mA

Max. 0.10mA



Max. 3.40mA

Max. 0.30mA

UV_DBt

UV_DBr

V_F

Min. 7.0V



Min. 10.0V

Min. 10.5V

Typ. 2.8V

@100mA

Min. 1.0μs

Min. 0.5μs

Typ. 1.7V

@10mA



Typ. 1.3V

@10mA

Min.2.0μs

Bootstrap Di forward voltage



¹⁾

Arm-shoot-through blocking time

t_dead

PWIN(on)

Min. 0.7μs

Allowable minimum input pulse

width

Due to current rating¹⁾

Refer each datasheet

PWIN(off)

V_SC(ref)

Min. 0.5μs

Min. 0.7μs

Short circuit trip level

0.48V±0.05V

0.48V±0.025V ²⁾



(1) IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off). Please refer

below about delayed response. (Ver.6 30A,35A products only. In the case of 5~20A products IPM might not make response.

Refer the datasheet for each product.)

Delayed Response against Shorter Input Off Signal than PWIN(off) (30A and 35a products, P-side only)

P Side Control Input

Real line: off pulse width > PWIN(off); turn on time t1

Broken line: off pulse width < PWIN(off); turn on time t2

(t1:Normal switching time)

Internal IGBT Gate

Output Current Ic

(2) Short circuit trip level tolerance of DIP Ver.6 is improved to 0.48±5%. By this improvement, DIP Ver.6 has wider overload

operating range.

If you use short circuit protection as a protection for degauss of motor, you can use at wider overload operating range due to

improve trip level tolerance as in Fig.1-5-1.

Protection level for degauss of motor

Over current protection level (max.)

Range of SC

←Tolerance of OC protection level(Tolerance of Ver.6 is half of Ver.5.)

trip level

(Ver.6)

Range of SC

trip level

Over load operation level of Ver.6 (max.)

(max. peak current for operation)

(Ver.5)

Over load operation level of Ver.5 (max.)

(max. peak current for operation)

Overload operating range

Ver.6 has wider over load operation area than Ver.5.

Normal operating range

Fig.1-5-1 short circuit trip level

For more detail and the other characteristics, please refer the datasheet for each product.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 2 SPECIFICATIONS AND CHARACTERISTICS

2.1 Super Mini DIPIPM Ver.6 Specifications

DIP Ver.6 specifications are described below by using PSS15S92*6-AG(15A/600V) as an example. Please refer to

respective datasheets for the detailed description of other types.

2.1.1 Maximum Ratings

The maximum ratings of PSS15S92*6-AG are shown in Table 2-1-1.

Table 2-1-1 Maximum Ratings

INVERTER PART

Symbol

V_CC

Parameter

Supply voltage

Condition

Applied between P-NU,NV,NW

Ratings

450

Unit

(1)

(2)

(3)

(4)

V_CC(surge)

V_CES

±I_C

Supply voltage (surge)

Applied between P-NU,NV,NW

500

Collector-emitter voltage

Each IGBT collector current

Each IGBT collector current (peak)

Collector dissipation

600

T_C= 25°C

(Note1 )

(Note2 )

±I_CP

P_C

T_C= 25°C, less than 1ms

T_C= 25°C, per 1 chip

27.0

°C

(5)

T_j

Junction temperature

-30~+150

Note1: Pulse width and period are limited due to junction temperature.

Note2: The maximum junction temperature rating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the

average junction temperature should be limited to Tj(Ave)≤125°C (@Tc≤100°C).

CONTROL (PROTECTION) PART

Symbol

V_D

Parameter

Control supply voltage

Input voltage

Condition

Ratings

Unit

Applied between

V_P1-V_NC, V_N1-V_NC

V_UFB-U, V_VFB-V, V_WFB-W

U_P, V_P, W_P, U_N, V_N, W_N-V_NC

F_O-V_NC

V_DB

V_IN

V_FO

I_FO

-0.5~V_D+0.5

Fault output supply voltage

Fault output current

F_Oterminal sink current

Applied between CIN-V_NC

V_SC

Current sensing input voltage

-0.5~V_D+0.5

TOTAL SYSTEM

Symbol

Parameter

Condition

Ratings

400

Unit

Self protection supply voltage limit

(Short circuit protection capability)

V_D= 13.5~16.5V, Inverter Part

T_j= 125°C, non-repetitive, less than 2μs

V_CC(PROT)

(6)

T_C

Module case operation temperature

Storage temperature

Measurement point of Tc is provided in the following figure

-30~+100

-40~+125

°C

T_stg

60Hz, Sinusoidal, AC 1min, between connected all pins

and heat sink plate

V_iso

Isolation voltage

1500

V_rms

(7)

Tc measurement position

DIPIPM

Control terminals

11.6mm

(8)

3mm

IGBT chip position

FWD chip position

Tc point

Heat sink side

Power terminals

(1) Vcc

The maximum voltage can be biased between P-N. A voltage suppressing circuit such as a brake circuit is

necessary if P-N voltage exceeds this value.

(2) Vcc(surge) The maximum P-N surge voltage in switching state. If P-N voltage exceeds this voltage, a snubber circuit is

necessary to absorb the surge under this voltage.

(3) V_CES

(4) +/-I_C

The maximum sustained collector-emitter voltage of built-in IGBT and FWDi.

The allowable current flowing into collect electrode (@Tc=25°C).Pulse width and period are limited due to junction

temperature Tj.

(5) Tj

The maximum junction temperature rating is 150°C. But for safe operation, it is recommended to limit the average

junction temperature up to 125°C. Repetitive temperature variation ΔTj affects the life time of power cycle, so refer

life time curves for safety design.

(6) Vcc(prot) The maximum supply voltage for turning off IGBT safely in the case of an SC or OC fault. The power chip might be

damaged if supply voltage exceeds this specification.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

(7) Isolation voltage Isolation voltage of Super mini DIPIPM is the voltage between all shorted pins and copper surface of DIPIPM.

The maximum rating of isolation voltage of Super mini DIPIPM is 1500Vrms. But if such as convex shape heat

radiation fin will be used for enlarging clearance between outer terminals and heat radiation fin (2.5mm or more

is recommended), it is able to correspond isolation voltage 2500Vrms. Super mini DIPIPM is recognized by UL

at the condition 2500Vrms with convex shape heat radiation fin.

Heat radiation part (Cu surface)

min 1.45

min 2.5

（3.0）

（1.9）

min 1.05

Heat radiation fin

Fig.2-1-1 In the case of using convex fin (unit: mm)

(8) Tc position Tc (case temperature) is defined to be the temperature just beneath the specified power chip. Please mount a

thermocouple on the heat sink surface at the defined position to get accurate temperature information. Due to the

control schemes such different control between P and N-side, there is the possibility that highest Tc point is different

from above point. In such cases, it is necessary to change the measuring point to that under the highest power chip.

[Power chip position]

Fig.2-1-2 indicates the position of the each power chips. (This figure is the view from laser marked side.)

Dimension in mm

Fig.2-1-2 Power chip position

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.1.2 Thermal Resistance

Table 2-1-2 shows the thermal resistance of PSS15S92*6-AG.

Table 2-1-2 Thermal resistance of PSS15S92*6-AG

THERMAL RESISTANCE

Limits

Typ.

Symbol

Parameter

Condition

Unit

Min.

Max.

3.7

4.5

R_th(j-c)Q

R_th(j-c)F

Inverter IGBT part (per 1/6 module)

Inverter FWDi part (per 1/6 module)

K/W

Junction to case thermal

resistance

(Note)

Note : Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of

DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal

conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•K).

The above data shows the thermal resistance between chip junction and case at steady state. The thermal

resistance goes into saturation in about 10 seconds. The unsaturated thermal resistance is called as transient

thermal impedance which is shown in Fig.2-1-3. Zth(j-c)* is the normalized value of the transient thermal

impedance. (Zth(j-c)*= Zth(j-c) / Rth(j-c)max)

For example, the IGBT transient thermal impedance of PSS15S92*6-AG in 0.3s is 3.7×0.8=3.0K/W.

The transient thermal impedance isn’t used for constantly current, but for short period current (ms order).

(E.g. In the cases at motor starting, at motor lock･･･)

1.00

FWDi

IGBT

0.10

0.01

0.1

Time (sec.)

Fig.2-1-3 Typical transient thermal impedance

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.1.3 Electric Characteristics and Recommended Conditions

Table 2-1-3 shows the typical static characteristics and switching characteristics of PSS15S92*6-AG.

Table 2-1-3 Static characteristics and switching characteristics of PSS15S92*6-AG

INVERTER PART (T_j= 25°C, unless otherwise noted)

Limits

Symbol

V_CE(sat)

Parameter

Condition

I_C= 15A , T_j= 25°C

Unit

Min.

Typ.

1.70

1.90

0.90

2.50

1.05

0.40

1.15

0.15

0.30

Max.

2.05

2.25

1.10

3.00

1.45

0.65

1.60

0.30

Collector-emitter saturation

voltage

V_D=V_DB= 15V, V_IN= 5V

V_IN= 0V, -I_C= 15A

I_C= 15A , T_j= 125°C

I_C= 1.5A , T_j= 25°C

V_EC

t_on

FWDi forward voltage

0.65

μs

t_C(on)

t_off

t_C(off)

t_rr

_CC= 300V, V_D= V_DB= 15V

Switching times

I_C= 15A, T_j= 125°C, V_IN= 0↔5V

Inductive Load (upper-lower arm)

T_j= 25°C

Collector-emitter cut-off

current

I_CES

V_CE=V_CES

T_j= 125°C

Switching time definition and performance test method are shown in Fig.2-1-4 and 2-1-5.

Switching characteristics are measured by half bridge circuit with inductance load.

trr

V_CE

P-Side IGBT

Irr

V_P1

90%

V_CIN(P)

V_IN(P)

IN OUT

COM

P-Side Input Signal

V_CC

10%

tc(on)

10%

V_N1

tc(off)

V_D

OUT

V_IN

td(on)

( ton=td(on)+tr )

V_CIN(N)

V_NO

V_IN(N)

CIN

td(off)

N-Side IGBT

V_NC

( toff=td(off)+tf )

N-Side Input Signal

Fig.2-1-4 Switching time definition

Fig.2-1-5 Evaluation circuit (inductive load)

Short A for N-side IGBT, and short B for P-side IGBT evaluation

t:200ns/div

Turn on

Turn off

Ic(5A/div)

V_CE(100V/div)

Ic(5A/div)

Fig.2-1-6 Typical switching waveform (PSS15S92*6-AG)

Conditions: V_CC=300V, V_D=V_DB=15V, Tj=125°C, Ic=15A, Inductive load half-bridge circuit

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Table 2-1-4 shows the typical control part characteristics of PSS15S92*6-AG.

Table 2-1-4 Control (Protection) characteristics of PSS15S92*6-AG

CONTROL (PROTECTION) PART (T_j= 25°C, unless otherwise noted)*

Limits

Symbol

Parameter

Condition

Unit

Min.

Typ.

Max.

2.80

0.10

0.505

12.0

12.5

13.0

2.91

1.39

140

V_D=15V, V_IN=0V

I_D

Total of V_P1-V_NC, V_N1-V_NC

Each part of V_UFB-U,

V_D=15V, V_IN=5V

Circuit current

V_D=V_DB=15V, V_IN=0V

V_D=V_DB=15V, V_IN=5V

I_DB

_VFB-V, V_WFB-W

(Note 1)

V_SC(ref)

UV_DBt

UV_DBr

UV_Dt

Short circuit trip level

V_D= 15V

0.455

7.0

10.3

10.8

2.63

0.88

100

0.480

10.0

Trip level

P-side Control supply

under-voltage protection(UV)

Reset level

T_j≤125°C

Trip level

N-side Control supply

under-voltage protection(UV)

UV_Dr

Reset level

2.77

1.13

120

LVIC Temperature=90°C

LVIC Temperature=25°C

Trip level

Temperature output

(PSS15S92F6-AG only) (Note5)

V_OT

Pull down R=5kΩ (Note 2)

Overt temperature protection

(PSS15S92E6-AG only)

(Note3) (Note5)

OT_t

V_D= 15V

°C

OT_rh

Detect LVIC temperature

Hysteresis of trip-reset

V_FOH

V_FOL

t_FO

V_SC= 0V, F_Oterminal pulled up to 5V by 10kΩ

4.9

Fault output voltage

V_SC= 1V, I_FO= 1mA

0.95

(Note 4)

Fault output pulse width

Input current

μs

I_IN

V_IN= 5V

0.70

0.80

1.00

2.10

1.30

1.50

2.60

V_th(on)

V_th(off)

ON threshold voltage

OFF threshold voltage

ON/OFF threshold

hysteresis voltage

Applied between U_P, V_P, W_P, U_N, V_N, W_N-V_NC

V_th(hys)

0.35

0.65

V_F

Bootstrap Di forward voltage

Built-in limiting resistance

I_F=10mA including voltage drop by limiting resistor

Included in bootstrap Di

1.1

1.7

2.3

100

120

Note 1 : SC protection works only for N-side IGBT. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating.

Note 2 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that

user defined, controller (MCU) should stop the DIPIPM.

3 : When the LVIC temperature exceeds OT trip temperature level(OT_t), OT protection works and Fo outputs. In that case if the heat sink dropped off or fixed

loosely, don't reuse that DIPIPM. (There is a possibility that junction temperature of power chips exceeded maximum Tj(150°C).

4 : Fault signal Fo outputs when SC, UV or OT protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed

width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.)

5 : It is necessary to select from temperature output function or over temperature protection about temperature protection.

Their part numbers are different. (e.g. PSS15S92F6-AG is the type with temperature output function and PSS15S92E6-AG is the type with over temperature

protection.)

*) Some specifications such as circuit current (I_D, I_DB), P-side Control supply under-voltage protection (UV_DBt, UV_DBr),

characteristic of Bootstrap Di (V_F, R) are different between rated current 5A~20A and 30A, 35A. For more detail,

please refer the datasheet for each product.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Recommended operating conditions of PSS15S92*6-AG are given in Table 2-1-5.

Although these conditions are the recommended but not the necessary ones, it is highly recommended to

operate the modules within these conditions so as to ensure DIPIPM safe operation.

Table 2-1-5 Recommended operating conditions of PSS15S92*6-AG

RECOMMENDED OPERATIONAL CONDITIONS

Limits

Symbol

Parameter

Condition

Unit

Min.

Typ.

300

15.0

Max.

400

16.5

18.5

V_CC

Supply voltage

Applied between P-NU, NV, NW

V_D

Control supply voltage

Control supply variation

Arm shoot-through blocking time

PWM input frequency

Applied between V_P1-V_NC, V_N1-V_NC

Applied between V_UFB-U, V_VFB-V, V_WFB-W

13.5

13.0

-1

V_DB

ΔV_D, ΔV_DB

t_dead

V/μs

μs

1.0

For each input signal, Tc≤100°C

T_C≤ 100°C, T_j≤ 125°C

f_PWM

kHz

V_CC= 300V, V_D= V_DB= 15V, P.F = 0.8,

Sinusoidal PWM

f_PWM= 5kHz

7.5

4.5

I_O

Allowable r.m.s. current

Arms

f_PWM= 15kHz

T_C≤ 100°C, T_j≤ 125°C

(Note1)

PWIN(on)

PWIN(off)

V_NC

0.7

-5.0

-20

(Note 2)

Minimum input pulse width

μs

V_NCvariation

Between V_NC-NU, NV, NW (including surge)

+5.0

+125

T_j

Junction temperature

°C

Note 1: Allowable r.m.s. current depends on the actual application conditions.

2: DIPIPM might not make response if the input signal pulse width is less than PWIN(on), PWIN(off).

*) Some specifications are different between rated current 5A~20A and 30A, 35A. For more detail, please refer the

datasheet for each product.

About Control supply variation

If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous

operation. To avoid such problem, line ripple voltage should meet the following specifications:

dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p

2.1.4 Mechanical Characteristics and Ratings

The mechanical characteristics and ratings are shown in Table 2-1-6.

Please refer to Section 2.4 for the detailed mounting instruction of DIP Ver.6.

Table 2-1-6 Mechanical characteristics and ratings of PSS15S92*6-AG

MECHANICAL CHARACTERISTICS AND RATINGS

Limits

Parameter

Mounting torque

Condition

Unit

Min.

0.59

Typ.

0.69

Max.

0.78

Mounting screw : M3 (Note 1)

Recommended 0.69N·m

EIAJ-ED-4701

N·m

Control terminal: Load 4.9N

Power terminal: Load 9.8N

Control terminal: Load 2.45N

Power terminal: Load 4.9N

90deg. bend

Terminal pulling strength

Terminal bending strength

EIAJ-ED-4701

times

Weight

8.5

(Note 2)

Heat-sink flatness

-50

100

μm

Note 1: Plain washers (ISO 7089~7094) are recommended.

Note 2: Measurement point of heat sink flatness

4.6mm

Measurement position

17.5mm

Heat sink side

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.2 Protective Functions and Operating Sequence

DIP Ver.6 has Short circuit (SC), Under Voltage of control supply (UV), Over Temperature (OT) and temperature

output (VOT) for protection function. The operating principle and sequence are described below.

2.2.1 Short Circuit Protection

1. General

DIP Ver.6 uses external shunt resistor for the current detection as shown in Fig.2-2-1. The internal protection

circuit inside the IC captures the excessive large current by comparing the CIN voltage generated at the shunt

resistor with the referenced SC trip voltage, and perform protection automatically. The threshold voltage trip level of

the SC protection Vsc(ref) is typ. 0.48V.

In case of SC protection happens, all the gates of N-side three phase IGBTs will be interrupted together with a

fault signal output. To prevent DIPIPM erroneous protection due to normal switching noise and/or recovery current, it

is necessary to set an RC filter (time constant: 1.5μ ~ 2μs) to the CIN terminal input (Fig.2-2-1, 2-2-2). Also, please

make the pattern wiring around the shunt resistor as short as possible.

Drive circuit

P-side IGBTs

SC protective level

N-side IGBTs

SC Protection External Parts

Shunt resistor

Collector

current

V_NC

CIN

Drive circuit

Input pulse width tw (μs)

SC protection

DIPIPM

Fig.2-2-1 SC protecting circuit

2. SC protection Sequence

Fig.2-2-2 Filter time constant setting

SC protection (N-side only with the external shunt resistor and RC filter)

a1. Normal operation: IGBT ON and carrying current.

a2. Short circuit current detection (SC trigger).

(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs when SC.)

a3. All N-side IGBTs gate are hard interrupted.

a4. All N-side IGBTs turn OFF.

a5. Fo outputs for t_Fo=minimum 20μs.

a6. Input = “L”. IGBT OFF

a7. Fo finishes output, but IGBTs don't turn on until inputting next ON signal (LH).

(IGBT of each phase can return to normal state by inputting ON signal to each phase.)

a8. Normal operation: IGBT ON and outputs current.

Lower-side control

input

SET

RESET

Protection circuit state

Internal IGBT gate

SC trip current level

Output current Ic

SC reference voltage

Sense voltage of

the shunt resistor

Delay by RC filtering

Error output Fo

Fig.2-2-3 SC protection timing chart

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3. Determination of Shunt Resistance

(1) Shunt resistance

The value of current sensing resistance is calculated by the following expression:

R_Shunt= V_SC(ref)/ SC

where V_SC(ref)is the referenced SC trip voltage.

The maximum SC trip level SC(max) should be set less than the IGBT minimum saturation current which is 1.7

times as large as the rated current. For example, the SC(max) of PSS15S92*6-AG should be set to 15x1.7=25.5A.

The parameters (V_SC(ref), R_Shunt) tolerance should be considered when designing the SC trip level.

For example of PSS15S92*6-AG, there is +/-0.025V tolerance in the spec of V_SC(ref)as shown in Table 2-2-1.

Table 2-2-1 Specification for V_SC(ref)

Condition

(unit: V)

Min

Typ

Max

0.455

0.480

0.505

at T_j=25°C, V_D=15V

Then, the range of SC trip level can be calculated by the following expressions:

R_Shunt(min)=V_{SC(ref) max}/SC(max)

R_Shunt(typ)= R_Shunt(min)/ 0.95*

then SC(typ) = V_{SC(ref) typ}/ R_Shunt(typ)

R_Shunt(max)= R_Shunt(typ)x 1.05* then SC(min)= V_{SC(ref) min}/ R_Shunt(max)

*)This is the case that shunt resistance tolerance is within +/-5%.

So the SC trip level range is described as Table 2-2-2.

Table 2-2-2 Operative SC Range (R_Shunt=19.8mΩ (min), 20.8mΩ (typ), 21.8mΩ(max)

Condition

at T_j=25°C

min.

20.9A

typ.

23.1A

Max.

25.5A

(e.g. 19.8mΩ (R_shunt(min))= 0.505V (=V_SC(max)) / 25.5A(=SC(max))

There is the possibility that the actual SC protection level becomes less than the calculated value. This is

considered due to the resonant signals caused mainly by parasitic inductance and parasitic capacity. It is

recommended to make a confirmation of the resistance by prototype experiment.

(2) RC Filter Time Constant

It is necessary to set an RC filter in the SC sensing circuit in order to prevent malfunction of SC protection due to

noise interference. The RC time constant is determined depending on the applying time of noise interference and

the SCSOA of the DIPIPM.

When the voltage drop on the external shunt resistor exceeds the SC trip level, the time (t1) that the CIN terminal

voltage rises to the referenced SC trip level can be calculated by the following expression:

V_SC= R_shunt⋅ I_c⋅ (1− ε ⁻

)

V_SC

t1 = −τ ⋅ ln(1−

R_shunt⋅ I_c

)

Vsc : the CIN terminal input voltage, Ic : the peak current, τ : the RC time constant

On the other hand, the typical time delay t2 (from Vsc voltage reaches Vsc(ref) to IGBT gate shutdown) of IC is

shown in Table 2-2-3.

Table 2-2-3 Internal time delay of IC

Item

min

typ

max

0.5

0.6

Unit

μs

5A~20A

30A, 35A

IC transfer delay time

Therefore, the total delay time from an SC level current happened to the IGBT gate shutdown becomes:

_TOTAL=t1+t2

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.2.2 Control Supply UV Protection

The UV protection is designed to prevent unexpected operating behavior as described in Table 2-2-4.

Both P-side and N-side have UV protecting function. However, fault signal (Fo) output only corresponds to

N-side UV protection. Fo output continuously during UV state.

In addition, there is a noise filter (typ. 10μs) integrated in the UV protection circuit to prevent instantaneous

UV erroneous trip. Therefore, the control signals are still transferred in the initial 10μs after UV happened.

Table 2-2-4 DIPIPM operating behavior versus control supply voltage

Control supply voltage

Operating behavior

In this voltage range, built-in control IC may not work properly. Normal

operating of each protection function (UV, Fo output etc.) is not also assured.

Normally IGBT does not work. But external noise may cause DIPIPM malfunction

(turns ON), so DC-link voltage need to start up after control supply starts-up.

0-4.0V (P, N)

UV function becomes active and output Fo (N-side only).

Even if control signals are applied, IGBT does not work

4.0-UV_Dt(N), UV_DBt(P)

UV_Dt(N)-13.5V

UV_DBt(P)-13.0V

13.5-16.5V (N)

13.0-18.5V (P)

16.5-20.0V (N)

18.5-20.0V (P)

20.0V- (P, N)

IGBT can work. However, conducting loss and switching loss will increase, and

result extra temperature rise at this state.

Recommended conditions.

IGBT works. However, switching speed becomes fast and saturation current

becomes large at this state, increasing SC broken risk.

The control circuit will be destroyed.

Ripple Voltage Limitation of Control Supply

If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause

DIPIPM erroneous operation. To avoid such problem, line ripple voltage should meet the following

specifications:

dV/dt ≤ +/-1V/μs, Vripple≤2Vp-p

[N-side UV Protection Sequence]

a1. Control supply voltage V _Drising: After the voltage level reaches UV_Dr, the circuits start to operate

when next input is applied (LH). (IGBT of each phase can return to normal state by inputting ON signal to

each phase.)

a2. Normal operation: IGBT ON and carrying current.

a3. V_Dlevel dips to under voltage trip level. (UV_Dt).

a4. All N-side IGBTs turn OFF in spite of control input condition.

a5. Fo outputs for t_Fo=minimum 20μs_,but output is extended during V_Dkeeps below UV_Dr.

a6. V_Dlevel reaches UV_Dr.

a7. Normal operation: IGBT ON and outputs current.

Control input

RESET

SET

Protection circuit state

UV_Dr

Control supply voltage V_D

UV_Dt

Output current Ic

Error output Fo

Fig.2-2-4 Timing chart of N-side UV protection

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

[P-side UV Protection Sequence](for rated current 5A~20A products)

a1. Control supply voltage V_DBrises. After the voltage reaches UV_DBr, the circuits start to operate when

next input is applied (LH).

a2. Normal operation: IGBT ON and carrying current.

a3. V_DBlevel dips to under voltage trip level (UV_DBt).

a4. IGBT of corresponding phase only turns OFF in spite of control input signal level,

but there is no F_Osignal output.

a5. V_DBlevel reaches UV_DBr

a6. Normal operation: IGBT ON and outputs current.

Control input

RESET

SET

RESET

Protection circuit state

UV_DBr

UV_DBt

Control supply voltage V_DB

Output current Ic

Keep High-level (no fault output)

Error output Fo

Fig.2-2-5 Timing Chart of P-side UV protection (Rated current 5A~20A)

[P-side UV Protection Sequence](for rated current 30A, 35A products)

a1. Control supply voltage rises: After the voltage reaches UV_DBr, the circuits start to operate when

next input is applied (LH).

a2. Normal operation : IGBT ON and carrying current.

a3. V_DBlevel dips to under voltage trip level (UV_DBt).

a4. IGBT of corresponding phase only turns OFF in spite of control input signal level,

but there is no Fo signal output.

a5. V_DBlevel reaches UV_DBr

a6. Normal operation : IGBT ON and outputs current.

Control input

RESET

SET

RESET

Protection circuit state

UV_DBr

Control supply voltage V_DB

UV_DBt

Output current Ic

High-level (no fault output)

Fault output Fo

Fig.2-2-6 Timing Chart of P-side UV protection (Rated current 30A, 35A)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.2.3 OT Protection (PSS**S92E6-AG only)

PSS**S92E6-AG series have OT (over temperature) protection function by monitoring LVIC temperature rise.

While LVIC temperature exceeds and keeps over OT trip temperature, error signal Fo outputs and all N-side IGBTs

are shut down without reference to input signal. (P-side IGBTs are not shut down)

The specification of OT trip temperature and its sequence are described in Table 2-2-5 and Fig.2-2-7.

Table 2-2-5 OT trip temperature specification

Item

Symbol

OT_t

Condition

Min.

100

Typ.

120

Max.

140

Unit

Trip level

Over temperature

protection

V_D=15V,

At temperature of LVIC

°C

Trip/reset hysteresis

OT_rh

[OT Protection Sequence]

a1. Normal operation: IGBT ON and outputs current.

a2. LVIC temperature exceeds over temperature trip level(OT_t).

a3. All N-side IGBTs turn OFF in spite of control input condition.

a4. Fo outputs for t_Fo=minimum 20μs_,but output is extended during LVIC temperature keeps over OT_t.

a5. LVIC temperature drops to over temperature reset level.

a6. Normal operation: IGBT turns on by next ON signal (LH).

(IGBT of each phase can return to normal state by inputting ON signal to each phase.)

Control input

RESET

SET

Protection circuit state

Temperature of LVIC

Output current Ic

OT_t

OT_t- OT_rh

Error output Fo

Fig.2-2-7 Timing Chart of OT protection

FWDi

LVIC

IGBT

←LVIC

(Detecting point)

Power Chip Area

Temperature of

LIVC is affected

from heatsink.

Heatsink

Fig.2-2-8 Temperature detecting point

Fig.2-2-9 Thermal conducting from power chips

Precaution about this OT protection function

(1)This OT protection will not work effectively in the case of rapid temperature rise like motor lock or over current.

(This protection monitors LVIC temperature, so it cannot respond to rapid temperature rise of power chips.)

(2)If the cooling system is abnormal state (e.g. heat sink comes off, fixed loosely, or cooling fun stops) when OT

protection works, can't reuse the DIPIPM. (Because the junction temperature of power chips will exceeded

the maximum rating of Tj(150°C).)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.2.4 Temperature output function V_OT(PSS**S92F6-AG only)

(1) Usage of this function

This function measures the temperature of control LVIC by built in temperature sensor on LVIC.

The heat generated at IGBT and FWDi transfers to LVIC through molding resin of package and outer heat sink.

So LVIC temperature cannot respond to rapid temperature rise of those power chips effectively. (e.g. motor

lock, short circuit) It is recommended to use this function for protecting from slow excessive temperature rise

by such cooling system down and continuance of overload operation. （Replacement from the thermistor

which was mounted on outer heat sink currently）

[Note]

In this function, DIPIPM cannot shutdown IGBT and output fault signal by itself when temperature rises

excessively. When temperature exceeds the defined protection level, controller (MCU) should stop the DIPIPM.

(2) V_OTcharacteristics

V_OToutput circuit, which is described in Fig.2-2-10, is the output of OP amplifier circuit. The current capability of

V_OToutput is described as Table 2-2-6. The characteristics of V_OToutput vs. LVIC temperature is linear

characteristics described in Fig.2-2-14. There are some cautions for using this function as below.

Inside LVIC

Table 2-2-6 Output capability

of DIPIPM

(Tc=-30°C ~100°C)

min.

Source

Sink

1.7mA

0.1mA

Temperature

signal

V_OT

V_NC

MCU

Ref

Source: Current flow from V_OTto outside.

Sink : Current flow from outside to V_OT

Fig.2-2-10 V_OToutput circuit

• In the case of detecting lower temperature than room temperature

It is recommended to insert 5.1kΩ pull down resistor for getting linear output characteristics at lower temperature

than room temperature. When the pull down resistor is inserted between V_OTand V_NC(control GND), the extra

current calculated by V_OToutput voltage / pull down resistance flows as LVIC circuit current continuously. In the case

of only using V_OTfor detecting higher temperature than room temperature, it isn't necessary to insert the pull down

resistor.

Inside LVIC

of DIPIPM

Temperature

signal

V_OT

V_NC

MCU

Ref

5.1kΩ

Fig.2-2-11 V_OToutput circuit in the case of detecting low temperature

• In the case of using with low voltage controller(MCU)

In the case of using V_OTwith low voltage controller (e.g. 3.3V MCU), V_OToutput might exceed control supply

voltage 3.3V when temperature rises excessively. If system uses low voltage controller, it is recommended to insert

a clamp Di between control supply of the controller and this output for preventing over voltage.

Inside LVIC

of DIPIPM

Temperature

signal

V_OT

V_NC

MCU

Ref

Fig.2-2-12 V_OToutput circuit in the case of using with low voltage controller

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

• In the case that the protection level exceeds control supply of the controller

In the case of using low voltage controller like 3.3V MCU, if it is necessary to set the trip V_OTlevel to control supply

voltage (e.g. 3.3V) or more, there is the method of dividing the V_OToutput by resistance voltage divider circuit and

then inputting to A/D converter on MCU (Fig.2-2-13). In that case, sum of the resistances of divider circuit should be

as much as 5kΩ. About the necessity of clamp diode, we consider that the divided output will not exceed the supply

voltage of controller generally, so it will be unnecessary to insert the clump diode. But it should be judged by the

divided output level finally.

Inside LVIC

of DIPIPM

V_OT

V_NC

DV_OT

Temperature

signal

MCU

Ref

DV_OT=V_OT·R2/(R1+R2) R1+R2≈5kΩ

Fig.2-2-13 V_OToutput circuit in the case with high protection level

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

4.0

3.8

3.6

3.4

3.2

3.0

2.91

2.8

2.77

2.63

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.39

1.2

1.13

1.0

0.88

0.8

Output range without 5kΩ pull down resistor

(Output might be saturated under this level.)

0.6

0.4

0.2

Output range with 5kΩ pull down resistor

Max.

Typ.

Min.

(Output might be saturated under this level.)

0.0

-30

-20

-10

100

110

120

130

LVIC temperature (°C)

Fig.2-2-14 V_OToutput vs. LVIC temperature

As mentioned above, the heat of power chips transfers to LVIC through the heat sink and package, so the

relationship between LVIC temperature: Tic(=V_OToutput), case temperature: Tc(under the chip defined on datasheet),

and junction temperature: Tj depends on the system cooling condition, heat sink, control strategy, etc. For example,

their relationship example in the case of using the heat sink (Table 2-2-7) is described in Fig.2-2-15. This relationship

may be different due to the cooling conditions. So when setting the threshold temperature for protection, it is

necessary to get the relationship between them on your real system. And when setting threshold temperature Tic, it is

important to consider the protection temperature assures Tc≤100°C and Tj ≤150°C.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Table 2-2-7 Outer heat sink

Heat sink size

( W x D x H )

100 x 88 x 40 mm

Thermal resistance

R_th(f-a)

2.20K/W

160

140

120

100

Tic≈Tc

ΔTj-c

Loss [W]

Fig.2-2-15 Example of relationship of Tj, Tc, Tic

(One IGBT chip turns on. DC current Ta=25°C, In this example, Tic and Tc are almost same temperature.)

Procedure about setting the protection level by using Fig.2-2-16 is described as below.

Table 2-2-8 Procedure for setting protection level

Procedure

Setting value example

Set the protection Tj temperature

Set Tj to 120°C as protection level.

Get LVIC temperature Tic that matches to above Tj of

the protection level from the relationship of Tj-Tic in

Fig.2-2-16.

Tic=93°C (@Tj=120°C)

Get V_OTvalue from the VOT output characteristics in

Fig.2-2-17 and the Tic value which was obtained at

phase 2) .

V_OT=2.84V (@Tic=93°C) is decided as the

protection level.

As above procedure, the setting value for V_OToutput is decided to 2.84V. But V_OToutput has some data spread,

so it is important to confirm whether the protection temperature fluctuation of Tj and Tc due to the data spread of

V_OToutput is Tj≤150°C and Tc≤100°C. Procedure about the confirmation of temperature fluctuation is described in

Table 2-2-9.

Table 2-2-9 Procedure for confirmation of temperature fluctuation

Procedure

Confirm the region of Tic fluctuation at above V_OTfrom

Fig.2-2-17.

Confirmation example

Tic=87°C~98.5°C (@V_OT=2.84V)

Tj=113°C~126°C (≤150°C No problem)

Tc=87°C~98.5°C (≤100°C No problem)

In this example, Tic and Tc are almost same temperature,

so Tc fluctuation is also same that of Tic

Confirm the region of Tj and Tc fluctuation at above

region of Tic from Fig.2-2-16.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

160

150

140

5) Tj: 113°C~126°C

130

1) 120°C

120

Tic≈Tc

110

100

4) 98.5°C

4) 87°C

2) 93°C

5) Tc: 87°C~98.5°C

Loss [W]

Fig.2-2-16 Relationship of Tj, Tc, Tic(Enlarged graph of Fig.2-2-15)

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

Max.

Typ.

Min.

3) 2.84V

4)87°C

2) 93°C

4) 98.5°C

100

105

110

LVIC temperature (°C)

Fig.2-2-17 V_OToutput vs. LVIC temperature (Enlarged graph of Fig.2-2-14)

As mentioned above, the relationship between Tic, Tc and Tj depends on the system cooling condition and

control strategy, and so on. So please evaluate about these temperature relationship on your real system when

considering the protection level.

If necessary, it is possible to ship the sample with the individual data of V_OTvs. LVIC temperature.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.3 Package Outlines

2.3.1 Package outlines

Fig.2-3-1 Long pin type package outline drawing

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.3.2 Marking

The laser marking specification of DIP Ver.6 is described in Fig.2-3-2. Mitsubishi Corporate crest, Type name, Lot

number, and QR code mark are marked in the upper side of module.

Marking area

Lot number

↑

QR code area

Marking details

QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN

and other countries.

Fig.2-3-2 Laser marking view

The Lot number indicates production year, month, running number and country of origin.

The detailed is described as below.

(Example) H 4 9 AA1

Running number

Product month (however O: October, N: November, D: December)

Last figure of Product year (e.g. 2014)

Factory identification

No mark : Manufactured at the factory in Japan

: Manufactured at the factory A in China

: Manufactured at the factory B in China

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<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.3.3 Terminal Description

Table 2-3-1 Terminal description

PSS**S92F6-AG(with temperature output function)

PSS**S92E6-AG(with OT protection function)

Name Description

Same as on the left

1-A

Name

Description

(V_NC)*²Inner used terminal. Keep no connection

It has control GND potential.

(V_NC

)

1-B

(V_P1)*²Inner used terminal. Keep no connection.

It has control supply potential.

(V_P1)^*2

Same as on the left

V_UFB

V_VFB

V_WFB

U_P

U-phase P-side drive supply positive terminal

V-phase P-side drive supply positive terminal

W-phase P-side drive supply positive terminal

U-phase P-side control input terminal

V-phase P-side control input terminal

W-phase P-side control input terminal

P-side control supply positive terminal

P-side control supply GND terminal

U-phase N-side control input terminal

V-phase N-side control input terminal

W-phase N-side control input terminal

N-side control supply positive terminal

Fault signal output terminal

V_UFB

V_VFB

V_WFB

U_P

Same as on the left

No connection (There isn't any connection

inside DIPIPM.)

V_P

W_P

V_P1

V_NC

V_NC*

U_N

V_N

U_N

V_N

W_N

V_N1

F_O

W_N

V_N1

F_O

CIN

SC trip voltage detecting terminal

CIN

V_NC

N-side control supply GND terminal

Temperature output

V_NC*

V_OT

Same as on the left

WN-phase IGBT emitter

VN-phase IGBT emitter

UN-phase IGBT emitter

W-phase output terminal(W-phase drive supply GND)

V-phase output terminal (V-phase drive supply GND)

U-phase output terminal (U-phase drive supply GND)

Inverter DC-link positive terminal

No connection (There isn't any connection inside

DIPIPM.)

Same as on the left

*1) Connect only one V_NCterminal to the system GND and leave another one open.

*2) No.1-A,1-B are inner used terminals, so it is necessary to leave no connection.

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<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Table 2-3-2 Detailed description of input and output terminals

Item

Symbol

Description

• Drive supply terminals for P-side IGBTs.

• By mounting bootstrap capacitor, individual isolated power supplies are not

needed for the P-side IGBT drive. Each bootstrap capacitor is charged by the

N-side V_Dsupply when potential of output terminal is almost GND level.

• Abnormal operation might happen if the V_Dsupply is not aptly stabilized or has

insufficient current capability due to ripple or surge. In order to prevent

malfunction, a bypass capacitor with favorable frequency and temperature

characteristics should be mounted very closely to each pair of these terminals.

• Inserting a Zener diode (24V/1W) between each pair of control supply terminals

is helpful to prevent control IC from surge destruction.

P-side drive supply

positive terminal

V_UFB-U

V_VFB-V

V_WFB-W

P-side drive supply

GND terminal

• Control supply terminals for the built-in HVIC and LVIC.

• In order to prevent malfunction caused by noise and ripple in the supply voltage,

a bypass capacitor with favorable frequency characteristics should be mounted

very closely to these terminals.

• Carefully design the supply so that the voltage ripple caused by noise or by

system operation is within the specified minimum limitation.

• It is recommended to insert a Zener diode (24V/1W) between each pair of control

supply terminals to prevent surge destruction.

P-side control

supply terminal

V_P1

V_N1

N-side control

supply terminal

• Control ground terminal for the built-in HVIC and LVIC.

• Ensure that line current of the power circuit does not flow through this terminal in

order to avoid noise influences.

• Connect only one V_NCterminal (9 or 16pin) to the GND, and leave another one

open.

N-side control GND

terminal

V_NC

• Control signal input terminals.Voltage input type.

• These terminals are internally connected to Schmitt trigger circuit.

• The wiring of each input should be as short as possible to protect the DIPIPM

from noise interference.

• Use RC filter in case of signal oscillation. (Pay attention to threshold voltage of

input terminal, because input circuit has pull down resistor (min 3.3kΩ))

• For inverter part SC protection, input the potential of shunt resistor to CIN

terminal through RC filter (for the noise immunity).

• The time constant of RC filter is recommended to be up to 2μs.

• Fault signal output terminal.

• Fo signal line should be pulled up to a 5V logic supply with over 5kΩ resistor (for

limitting the Fo sink current I_Foup to 1mA.) Normally 10kΩ is recommended.

• LVIC temperature is ouput by analog signal.

U_P,V_P,W_P

U_N,V_N,W_N

Control input

terminal

Short-circuit trip

voltage detecting

terminal

CIN

F_O

Fault signal output

terminal

• This terminal is connected ti the ouput of OP amplifer internally.

• It is recommended to connect 5.1kΩ pulldown resistor if output linearlity is

necessary under room temperature.

Temperature output

terminal

V_OT

• DC-link positive power supply terminal.

• Internally connected to the collectors of all P-side IGBTs.

• To suppress surge voltage caused by DC-link wiring or PCB pattern inductance,

smoothing capacitor should be located very closely to the P and N terminal of

DIPIPM. It is also effective to add small film capacitor with good frequency

characteristics.

Inverter DC-link

positive terminal

• Open emitter terminal of each N-side IGBT

• Usually, these terminals are connected to the power GND through individual

shunt resistor.

Inverter DC-link

negative terminal

NU,NV,NW

U, V, W

• Inverter output terminals for connection to inverter load (e.g. motor).

• Each terminal is internally connected to the intermidiate point of the

corresponding IGBT half bridge arm.

Inverter power

output terminal

Note: Use oscilloscope to check voltage waveform of each power supply terminals and P&N terminals, the time division of OSC

should be set to about 1μs/div. Please ensure the voltage (including surge) not exceed the specified limitation.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.4 Mounting Method

This section shows the electric spacing and mounting precautions of DIP Ver.6.

2.4.1 Electric Spacing

The electric spacing specification of DIP Ver.6 is shown in Table 2-4-1

Table 2-4-1 Minimum insulation distance of DIP Ver.6

Clearance (mm)

Creepage (mm)

Between live terminals with high potential

Between terminals and heat sink

2.50

1.45

3.00

1.50

2.4.2 Mounting Method and Precautions

When installing the module to the heat sink, excessive or uneven fastening force might apply stress to inside chips.

Then it will lead to a broken or degradation of the chips or insulation structure. The recommended fastening

procedure is shown in Fig.2-4-1. When fastening, it is necessary to use the torque wrench and fasten up to the

specified torque. And pay attention to the foreign particle on the contact surface between the module and the heat

sink. Even if the fixing of heatsink was done by proper procedure and condition, there is a possibility of damaging the

package because of tightening by unexpected excessive torque or tucking particle. For ensuring safety it is

recommended to conduct the confirmation test(e.g. insulation inspection) on the final product after fixing the DIPIPM

with the heatsink.

(2)

(1)

Temporary fastening

(1)→(2)

Permanent fastening

(1)→(2)

Note: Generally, the temporary fastening torque is

set to 20-30% of the maximum torque rating.

Not care the order of fastening (1) or (2), but need

to fasten alternately.

Fig.2-4-1 Recommended screw fastening order

Table 2-4-2 Mounting torque and heat sink flatness specifications

Item

Condition

Recommended 0.69N·m, Screw : M3

Refer Fig.2-4-2

Min.

0.59

-50

Typ.

Max.

0.78

+100

Unit

N·m

μm

Mounting torque

Flatness of outer heat sink

Note : Recommend to use plain washer (ISO7089-7094) in fastening the screws.

Measurement part

for heat sink flatness

Outer heat sink

Fig.2-4-2 Measurement point of heat sink flatness

In order to get effective heat dissipation, it is necessary to enlarge the contact area as much as possible to

minimize the contact thermal resistance. Regarding the heat sink flatness (warp/concavity and convexity) on the

module installation surface, the surface finishing-treatment should be within Rz12.

Evenly apply thermally-conductive grease with 100μ-200μm thickness over the contact surface between a

module and a heat sink, which is also useful for preventing corrosion. Furthermore, the grease should be with

stable quality and long-term endurance within wide operating temperature range. The contacting thermal

resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal

conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness:

20μm, thermal conductivity: 1.0W/m·k). When applying grease and fixing heat sink, pay attention not to take air into

grease. It might lead to make contact thermal resistance worse or loosen fixing in operation.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

2.4.3 Soldering Conditions

The recommended soldering condition is mentioned as below.

(Note: The reflow soldering cannot be recommended for DIPIPM.)

(1) Flow (wave) Soldering

DIPIPM is tested on the condition described in Table 2-4-3 about the soldering thermostability, so the

recommended conditions for flow (wave) soldering are soldering temperature is up to 265°C and the immersion

time is within 11s.

However, the condition might need some adjustment based on flow condition of solder, the speed of the

conveyer, the land pattern and the through-hole shape on the PCB, etc.

It is necessary to confirm whether it is appropriate or not for your real PCB finally.

Table 2-4-3 Reliability test specification

Item

Condition

Soldering thermostability

260±5°C, 10±1s

(2) Hand soldering

Since the temperature impressed upon the DIPIPM may change based on the soldering iron types (wattages,

shape of soldering tip, etc.) and the land pattern on PCB, the unambiguous hand soldering condition cannot be

decided.

As a general requirement of the temperature profile for hand soldering, the temperature of the root of the

DIPIPM terminal should be kept 150°C or less for considering glass transition temperature (Tg) of the package

molding resin and the thermal withstand capability of internal chips. Therefore, it is necessary to check the

DIPIPM terminal root temperature, solderability and so on in your real PCB, when configure the soldering

temperature profile. (It is recommended to set the soldering time as short as possible.)

For reference, the evaluation example of hand soldering with 50W soldering iron is described as below.

[Evaluation method]

a. Sample: Super mini DIPIPM

b. Evaluation procedure

- Put the soldering tip of 50W iron (temperature set to 350/400°C) on the terminal within 1mm from the toe.

(The lowest heat capacity terminal (=control terminal) is selected.)

- Measure the temperature rise of the terminal root part by the thermocouple installed on the terminal root.

200

Soldering iron

150

1mm

100

350°C

400°C

Thermocouple

DIPIPM

Heating time (s)

Fig.2-4-3 Heating and measuring point

[Note]

Fig.2-4-4 Temperature alteration of the terminal root (Example)

For soldering iron, it is recommended to select one for semiconductor soldering (12~24V low voltage type, and

the earthed iron tip) and with temperature adjustment function.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 3 SYSTEM APPLICATION GUIDANCE

3.1 Application Guidance

This chapter states the DIP Ver.6 application method and interface circuit design hints.

3.1.1 System connection

C1: Electrolytic type with good temperature and frequency

P-side input(PWM)

characteristics.

Note: the capacitance also depends on the PWM control

strategy of the application system

C2:0.22μ-2μF ceramic capacitor with good temperature,

frequency and DC bias characteristics

Input signal

conditioning

Input signal

conditioning

Input signal

conditioning

Level shift

C3:0.1μ-0.22μF Film capacitor (for snubber)

D1:Zener diode 24V/1W for surge absorber

UV lockout

circuit

UV lockout

circuit

UV lockout

circuit

Inrush limiting circuit

Drive circuit

DIPIPM

P-side IGBTs

AC line input

Noise filter

Varistor

AC output

GDT

N-side IGBTs

V_NC

CIN

Drive circuit

C : AC filter(ceramic capacitor 2.2n -6.5nF)

(Common-mode noise filter)

Protection

circuit (SC)

Input signal conditioning

N-side input(PWM)

Fo Logic

UV lockout

circuit

V_D

Fo output

V_NC

(15V line)

Fig.3-1-1 Application System block diagram

Publication Date: May 2014

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.2 Interface Circuit (Direct Coupling Interface example for using one shunt resistor)

Fig.3-1-2 shows a typical application circuit of interface schematic, in which control signals are transferred directly input from

a controller (e.g. MCU, DSP).

Bootstrap negative electrodes

should be connected to U,V,W

terminals directly and separated

from the main output wires

P(24)

IGBT1

C1D1C2

V_UFB(2)

V_VFB(3)

V_WFB(4)

Di1

Di2

U(23)

IGBT2

IGBT3

HVIC

U_P(5)

V_P(6)

V(22)

Di3

W_P(7)

V_P1(8)

W(21)

V_NC(9)

IGBT4

Di4

Di5

Di6

U_N(10)

V_N(11)

W_N(12)

NU(20)

NV(19)

NW(18)

IGBT5

IGBT6

Fo(14)

LVIC

V_OT(17)

5kΩ

PSS**S92F6-AG

with temp. ouput

function only

15V V_D

V_N1(13)

V_NC(16)

Long wiring might cause

short circuit failure

Long wiring might cause SC level

fluctuation and malfunction

CIN(15)

Long GND wiring might generate

noise to input signal and cause

IGBT malfunction

Shunt

resistor

Power GND wiring

Control GND wiring

Fig.3-1-2 Interface circuit example in the case of using with one shunt resistor

(1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.

It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).

(2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.

(3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.

Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.

(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.

The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time

might vary with the wiring pattern, so the enough evaluation on the real system is necessary.

(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.

(6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be

connected at near NU, NV, NW terminals.

(7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic type

and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)

(8) Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring

of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and

turn-off threshold voltage.

(9) Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes I_Foup to 1mA.

(I_FOis estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V,

10kΩ (5kΩ or more) is recommended.)

(10) Thanks to built-in HVIC, direct coupling to MCU without any optocoupler or transformer isolation is possible.

(11) Two V_NCterminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and

leave another one open.

(12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation.

To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.

Publication Date: May 2014

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.3 Interface Circuit (Example of Optocoupler Isolated Interface)

P(24)

U(23)

IGBT1

D1C2

V_UFB(2)

V_VFB(3)

V_WFB(4)

Di1

Di2

IGBT2

IGBT3

HVIC

V(22)

U_P(5)

V_P(6)

W_P(7)

V_P1(8)

Di3

W(21)

V_NC(9)

IGBT4

Di4

Di5

Di6

U_N(10)

V_N(11)

W_N(12)

NU(20)

NV(19)

NW(18)

IGBT5

IGBT6

Fo(14)

LVIC

Comparator

V_OT(17)

OT trip

level

15V V_D

V_N1(13)

V_NC(16)

CIN(15)

Shunt

resistor

Fig.3-1-3 Interface circuit example with optocoupler

Note:

(1) High speed (high CMR) optocoupler is recommended.

(2) Fo terminal sink current for inverter part is max.1mA.

(3) About comparator circuit at V_OToutput, it is recommended to design the input circuit with hysteresis because of preventing output

chattering.

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.4 External SC Protection Circuit with Using Three Shunt Resistors

DIPIPM

Drive circuit

P-side IGBT

External protection circuit

N-side IGBT

Comparators

(Open collector output type)

R_f

C_f

Vref

Drive circuit

OR output

Protection circuit

CIN

Vref

V_NC

Shunt

resistors

Fig.3-1-4 Interface circuit example

Note:

(1) It is necessary to set the time constant R_fC_fof external comparator input so that IGBT stop within 2μs when short circuit occurs.

SC interrupting time might vary with the wiring pattern, comparator speed and so on.

(2) The threshold voltage Vref should be set up the same rating of short circuit trip level (Vsc(ref) typ. 0.48V).

(3) Select the external shunt resistance so that SC trip-level is less than specified value.

(4) To avoid malfunction, the wiring A, B, C should be as short as possible.

(5) The point D at which the wiring to comparator is divided should be near the terminal of shunt resistor.

(6) OR output high level should be over 0.505V (=maximum Vsc(ref)).

(7) GND of Comparator, Vref circuit and Cf should be not connected to noisy power GND but to control GND wiring.

3.1.5 Circuits of Signal Input Terminals and Fo Terminal

(1) Internal Circuit of Control Input Terminals

DIPIPM

1kΩ

Level

Shift

Circuit

Gate

Drive

Circuit

DIPIPM is high-active input logic.

U_P,V_P,W_P

U_N,V_N,W_N

A 3.3kΩ(min) pull-down resistor is built-in each input

circuits of the DIPIPM as shown in Fig.3-1-5 , so

external pull-down resistor is not needed.

Furthermore, by lowering the turn on and turn off

threshold value of input signal as shown in Table 3-1-1,

a direct coupling to 3V class microcomputer or DSP

becomes possible.

3.3kΩ(min)

1kΩ

Gate

Drive

Circuit

3.3kΩ(min)

Fig.3-1-5 Internal structure of control input terminals

Table 3-1-1 Input threshold voltage ratings(Tj=25°C)

Item

Symbol

Vth(on)

Vth(off)

Vth(hys)

Condition

Min.

0.8

0.35

Typ.

2.1

1.3

Max.

2.6

Unit

Turn-on threshold voltage

Turn-off threshold voltage

Threshold voltage hysterisis

U_P,V_P,W_P-V_NCterminals

U_N,V_N,W_N-V_NCterminals

0.65

Note: There are specifications for the minimum input pulse width in DIPIPM Ver.6. DIPIPM might make no response

if the input signal pulse width (both on and off) is less than the specified value. Please refer to the datasheet for

the specification. (The specification of min. width is different due to the current rating.)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

5V line

10kΩ

DIPIPM

U_P,V_P,W_P,U_N,V_N,W_N

MCU/DSP

3.3kΩ (min)

V_NC(Logic)

Fig.3-1-6 Control input connection

Note: The RC coupling (parts shown in the dotted line) at each input depends on user’s PWM control strategy and the wiring

impedance of the printed circuit board.

The DIPIPM signal input section integrates a 3.3kΩ(min) pull-down resistor. Therefore, when using an external filtering

resistor, please pay attention to the signal voltage drop at input terminal.

(2) Internal Circuit of Fo Terminal

F_Oterminal is an open drain type, it should be pulled up to a 5V supply as shown in Fig.3-1-6. Fig.3-1-7 shows the

typical V-I characteristics of Fo terminal. The maximum sink current of Fo terminal is 1mA. If optocoupler is applied

to this output, please pay attention to the optocoupler drive ability.

Table 3-1-2 Electric characteristics of Fo terminal

Item

Symbol

V_FOH

V_FOL

Condition

V_SC=0V,Fo=10kΩ,5V pulled-up

V_SC=1V,Fo=1mA

Min.

4.9

Typ.

Max.

0.95

Unit

Fault output voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.2

0.4

0.6

0.8

1.0

I_FO(mA)

Fig.3-1-7 Fo terminal typical V-I characteristics (V_D=15V, T_j=25°C)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.6 Snubber Circuit

In order to prevent DIPIPM from destruction by extra surge, the wiring length between the smoothing

capacitor and DIPIPM P terminal – N1 points (shunt resistor terminal) should be as short as possible.

Also, a 0.1μ~0.22μF/630V snubber capacitor should be mounted in the DC-link and near to P, N1.

There are two positions ((1)or(2)) to mount a snubber capacitor as shown in Fig.3-1-8. Snubber

capacitor should be installed in the position (2) so as to suppress surge voltage effectively. However,

the charging and discharging currents generated by the wiring inductance and the snubber capacitor

will flow through the shunt resistor, which might cause erroneous protection if this current is large

enough.

In order to suppress the surge voltage maximally, the wiring at part-A (including shunt resistor

parasitic inductance) should be as small as possible. A better wiring example is shown in location (3).

DIPIPM

Wiring Inductance

(1)

(2)

(3)

Shunt resistor

Fig.3-1-8 Recommended snubber circuit location

3.1.7 Recommended Wiring Method around Shunt Resistor

External shunt resistor is employed to detect short-circuit accident. A longer wiring between the shunt resistor and

DIPIPM causes so much large surge that might damage built-in IC. To decrease the pattern inductance, the wiring

between the shunt resistor and DIPIPM should be as short as possible and using low inductance type resistor such

as SMD resistor instead of long-lead type resistor.

NU, NV, NW should be connected each other at near terminals.

DIPIPM

It is recommended to make the inductance of this part

(including the shunt resistor) under 10nH.

e.g.

Inductance of copper pattern (width=3mm,

length=17mm) is about 10nH.

V_NC

Shunt resistor

Connect GND wiring from V_NCterminal to the shunt

resistor terminal as close as possible.

Fig.3-1-9 Wiring instruction (In the case of using with one shunt resistor)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

DIPIPM

It is recommended to make the inductance of each

phase (including the shunt resistor) under 10nH.

e.g.

Inductance of copper pattern (width=3mm,

length=17mm) is about 10nH.

V_NC

Connect GND wiring from V_NCterminal to the shunt

resistor terminal as close as possible.

Shunt resistors

Fig.3-1-10 Wiring instruction (In the case of using with three shunt resistor)

Influence of pattern wiring around the shunt resistor is shown below.

DIPIPM

Drive circuit

P-side

IGBTs

External protection circuit

DC-bus current path

N-side

IGBTs

CIN

Drive circuit

Shunt resistor

SC protection

V_NC

Fig.3-1-11 External protection circuit

(1) Influence of the part-A wiring

The ground of N-side IGBT gate is V_NC. If part-A wiring pattern in Fig.3-1-11 is too long, extra voltage generated by

the wiring parasitic inductance will result the potential of IGBT emitter variation during switching operation. Please

install shunt resistor as close to the N terminal as possible.

(2) Influence of the part-B wiring

The part-B wiring affects SC protection level. SC protection works by detecting the voltage of the CIN terminals. If

part-B wiring is too long, extra surge voltage generated by the wiring inductance will lead to deterioration of SC

protection level. It is necessary to connect CIN and V_NCterminals directly to the two ends of shunt resistor and avoid

long wiring.

(3) Influence of the part-C wiring pattern

C1R2 filter is added to remove noise influence occurring on shunt resistor. Filter effect will dropdown and noise will

easily superimpose on the wiring if part-C wiring is too long. It is necessary to install the C1R2 filter near CIN, V_NC

terminals as close as possible.

(4) Influence of the part-D wiring pattern

Part-D wiring pattern gives influence to all the items described above, maximally shorten the GND wiring is expected.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.8 Precaution for Wiring on PCB

Floating control supply V_*FBand V_*FSwire potential fluctuates between Vcc and

GND potential at switching, so it may cause malfunction if wires for control

(e.g. control input V_IN, control supply) are located near by or cross these wires.

Particularly pay attention when using multi layered PCB.

Supply GND for P-side driving

Power supply

Output

V_UFB,V_VFB

V_WFB

Capacitor and

Zener diode

should be located

at near terminals

UP,VP,W P

UN,VN,WN

(to motor)

Vin

U,V,W

Bootstrap negative electrodes

should be connected to U,V,W

terminals directly and separated

from the main output wires

V_N1,V_P1

V_D1

Locate snubber

capacitor between

P and N1 and as

near by terminals

as possible

Snubber

capacitor

V_NC

Control

GND

Shunt

resistor

CIN

Power GND

Connect CIN filter's

capacitor to control GND

(not to Power GND)

Control

GND

It is recommended to

connect control GND and

power GND at only a point

N1. (Not connect common

broad pattern)

Wiring to CIN terminal

should be divided at near

shunt resistor terminal and

as short as possible.

Wiring between NU, NV, NW

and shunt resistor should be

as short as possible.

Fig.3-1-12 Precaution for wiring on PCB

The case example of trouble due to PCB pattern

Case example

Matter of trouble

•Control GND pattern overlaps

power GND pattern.

The surge, generated by the wiring pattern and di/dt of noncontiguous big

current flows to power GND, transfers to control GND pattern. It causes the

control GND level fluctuation, so that the input signal based on the control

GND fluctuates too. Then the arm short might occur.

Stray current flows to GND loop pattern, so that the control GND level and

input signal level (based on the GND) fluctuates. Then the arm short might

occur.

•Ground loop pattern exists.

•Large inductance of wiring

between N and N1 terminal

Long wiring pattern has big parasitic inductance and generates high surge

when switching. This surge causes the matter as below.

•HVIC malfunction due to VS voltage (output terminal potential) dropping

excessively.

•LVIC surge destruction

Capacitors or zener diodes are

nothing or located far from the

terminals.

IC surge destruction or malfunction might occur.

The input lines are located parallel Cross talk noise might be transferred through the capacitance between

and close to the floating supply

lines for P-side drive.

these floating supply lines and input lines to DIPIPM. Then incorrect signals

are input to DIPIPM input, and arm short (short circuit) might occur.

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.9 Parallel operation of DIPIPM

Fig.3-1-13 shows the circuitry of parallel connection of two DIPIPMs. Route (1) and (2) indicate the gate charging path

of low-side IGBT in DIPIPM No.1 & 2 respectively. In the case of DIPIPM 1, the parasitic inductance becomes large by

long wiring and it might have a negative effect on DIPIPM's switching operation. (Charging operation of bootstrap

capacitor for high-side might be affected too.) Also, such a wiring makes DIPIPM be affected by noise easily, then it might

lead to malfunction. If more DIPIPMs are connected in parallel, GND pattern becomes longer and the influence to other

circuit (protection circuit etc.) by the fluctuation of GND potential is conceivable, therefore parallel connection is not

recommended.

Because DIPIPM doesn't consider the fluctuation of characteristics between each phase definitely, it cannot be

recommended to drive same load by parallel connection with other phase IGBT or IGBT of other DIPIPM.

DIPIPM 1

V_P1

DC15V

U,V,W

AC input

V_N1

Shunt resistor

V_NC

(1)

DIPIPM 2

V_P1

U,V,W

V_N1

Shunt resistor

V_NC

(2)

Fig.3-1-13 Parallel operation

3.1.10 SOA of DIP Ver.6

The following describes the SOA (Safety Operating Area) of the DIP Ver.6.

V_CES

Maximum rating of IGBT collector-emitter voltage

V_CC

Supply voltage applied on P-N terminals

V_CC(surge): Total amount of V_CCand surge voltage generated by the wiring inductance and the DC-link capacitor.

V_CC(PROT): DC-link voltage that DIPIPM can protect itself.

≤V_CC(PROT)

≤V_cc(surge)

Collector current Ic

≤V_CC

≤V_cc(surge)

Short-circuit current

V_CE=0，I_C=0

≤2µs

Fig.3-1-14 SOA at switching mode and short-circuit mode

In Case of switching

V_CESrepresents the maximum voltage rating (600V) of the IGBT. By subtracting the surge voltage (100V or

less) generated by internal wiring inductance from V_CESis V_CC(surge), that is 500V. Furthermore, by subtracting

the surge voltage (50V or less) generated by the wiring inductor between DIPIPM and DC-link capacitor from

V_CC(surge)derives V_CC, that is 450V.

In Case of Short-circuit

V_CESrepresents the maximum voltage rating (600V) of the IGBT. By Subtracting the surge voltage (100V or

less) generated by internal wiring inductor from V_CESis V_CC(surge), that is, 500V. Furthermore, by subtracting the

surge voltage (100V or less) generated by the wiring inductor between the DIPIPM and the electrolytic

capacitor from V_CC(surge)derives V_CC, that is, 400V.

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.11 SCSOA

Fig.3-1-15~18 shows the typical SCSOA performance curves of PSS05S92*6-AG, PSS10S92*6-AG,

PSS15S92*6-AG and PSS20S92*6-AG.

(Conditions: Vcc=400V, Tj=125°C at initial state, Vcc(surge)≤500V(surge included), non-repetitive,2m load.)

In the case of PSS15S92*6-AG, it can shutdown safely an SC current that is about 5.8 times of its current rating

under the conditions only if the IGBT conducting period is less than 2.7μs. Since the SCSOA operation area will

vary with the control supply voltage, DC-link voltage, and etc, it is necessary to set time constant of RC filter with a

margin.

100

V_D=18.5V

V_D=16.5V

V_D=15V

↑

Max. Saturation

Current≈55A

@V_D=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-15 Typical SCSOA curve of PSS05S92*6-AG

100

V_D=18.5V

V_D=16.5V

V_D=15V

↑

Max. Saturation

Current≈60A

@V_D=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-16 Typical SCSOA curve of PSS10S92*6-AG

140

120

V_D=18.5

100

V_D=16.5

↑

Max. Saturation

Current≈87A

V_D=15

@V_D=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-17 Typical SCSOA curve of PSS15S92*6-AG

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

170

VD=18.5V

150

VD=16.5V

130

↑

VD=15V

Max. Saturation

110

Current≈129A

@VD=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-18 Typical SCSOA curve of PSS20S92*6-AG

250

230

VD=18.5V

210

190

VD=16.5V

170

↑

Max. Saturation

150

130

110

VD=15V

Current≈162A

@VD=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-19 Typical SCSOA curve of PSS30S92*6-AG

400

VD=18.5V

350

VD=16.5V

VD=15V

300

250

200

150

100

↑

Max. Saturation

Current≈278A

@VD=16.5V

CSTBT SC operation area

Input pulse width [μs]

Fig.3-1-20 Typical SCSOA curve of PSS35S92*6-AG

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.1.12 Power Life Cycles

When DIPIPM is in operation, repetitive temperature variation will happens on the IGBT junctions (ΔTj). The

amplitude and the times of the junction temperature variation affect the device lifetime.

Fig.3-1-19 shows the IGBT power cycle curve as a function of average junction temperature variation (ΔTj).

(The curve is a regression curve based on 3 points of ΔTj=46, 88, 98K with regarding to failure rate of 0.1%, 1% and

10%. These data are obtained from the reliability test of intermittent conducting operation)

10000000

10%

0.1%

1000000

100000

10000

1000

100

1000

Average junction temperature variation ΔTj(K)

Fig.3-1-19 Power cycle curve

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.2 Power Loss and Thermal Dissipation Calculation

3.2.1 Power Loss Calculation

Simple expressions for calculating average power loss are given below:

● Scope

The power loss calculation intends to provide users a way of selecting a matched power device for their

VVVF inverter application. However, it is not expected to use for limit thermal dissipation design.

● Assumptions

(1) PWM controlled VVVF inverter with sinusoidal output;

(2) PWM signals are generated by the comparison of sine waveform and triangular waveform.

1− D 1+ D

(3) Duty amplitude of PWM signals varies between

～

(%/100), (D: modulation depth).

(4) Output current various with Icp·sinx and it does not include ripple.

(5) Power factor of load output current is cosθ, ideal inductive load is used for switching.

● Expressions Derivation

1+ D×sin x

PWM signal duty is a function of phase angle x as

which is equivalent to the output voltage

variation. From the power factor cosθ, the output current and its corresponding PWM duty at any phase angle x

can be obtained as below:

Output current = Icp×sin x

1+ D ×sin(x +θ )

PWM Duty =

Then, V_CE(sat)and V_ECat the phase x can be calculated by using a linear approximation:

Vce(sat) = Vce(sat)(@ Icp×sin x)

Vec = (−1)×Vec(@ Iecp(= Icp)×sin x)

Thus, the static loss of IGBT is given by:

1+ Dsin(x +θ)

(Icp×sin x)×Vce(sat)(@ Icp×sin x)×

• dx

∫

2π

Similarly, the static loss of free-wheeling diode is given by:

2π

1+ Dsin(x +θ)

((−1)× Icp×sin x)((−1)×Vec(@ Icp×sin x)×

• dx

∫

2π

On the other hand, the dynamic loss of IGBT, which does not depend on PWM duty, is given by:

^π(Psw(on)(@ Icp×sin x) + Psw(off )(@ Icp×sin x))×fc • dx

∫

2π

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

FWDi recovery characteristics can be approximated by the ideal curve shown in Fig.3-2-1, and its dynamic loss

can be calculated by the following expression:

trr

I_EC

V_EC

Irr

Vcc

Fig.3-2-1 Ideal FWDi recovery characteristics curve

Irr ×Vcc×trr

Psw =

Recovery occurs only in the half cycle of the output current, thus the dynamic loss is calculated by:

2π

Irr(@ Icp×sin x)×Vcc×trr(@ Icp×sin x)

× fc • dx

∫

^2πIrr(@ Icp×sin x)×Vcc×trr(@ Icp×sin x)× fc • dx

∫



Attention of applying the power loss simulation for inverter designs

・ Divide the output current period into fine-steps and calculate the losses at each step based on the actual

values of PWM duty, output current, V_CE(sat), V_EC, and Psw corresponding to the output current. The

worst condition is most important.

・ PWM duty depends on the signal generating way.

・ The relationship between output current waveform or output current and PWM duty changes with the

way of signal generating, load, and other various factors. Thus, calculation should be carried out on the

basis of actual waveform data.

・ V_CE(sat),V_ECand Psw(on, off) should be the values at Tj=125°C.

Publication Date: May 2014

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.2.2 Temperature Rise Considerations and Calculation Example

Fig.3-2-2 shows the typical characteristics of allowable motor rms current versus carrier frequency under the

following inverter operating conditions based on power loss simulation results.

Conditions: V_CC=300V, V_D=V_DB=15V, V_CE(sat)=Typ., Switching loss=Typ., Tj=125°C, Tf=100°C, Rth(j-c)=Max.,

Rth(c-f)=0.3°C/W (per 1/6 module), P.F=0.8, 3-phase PWM modulation, 60Hz sine waveform output

PSS35S92*6-AG

PSS30S92*6-AG

PSS20S92*6-AG

PSS15S92*6-AG

PSS10S92*6-AG

PSS05S92*6-AG

fc(kHz)

Fig.3-2-2 Effective current-carrier frequency characteristics

Fig.3-2-2 shows an example of estimating allowable inverter output rms current under different carrier

frequency and permissible maximum operating temperature condition (Tf=100°C. Tj=125°C). The results may

change for different control strategy and motor types. Anyway please ensure that there is no large current

over device rating flowing continuously. The Inverter loss can be calculated by the free power loss simulation

software. The software can be downloaded at Mitsubishi Electric web site.

URL: http://www.mitsubishielectric.com/semiconductors/

Fig.3-2-3 Loss simulator screen image

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.2.3 Installation of thermocouple

Installation of thermocouple for measurement of DIPIPM case temperature is shown below.

Point for installing thermocouple in heat sink is shown in Fig.3-2-4. In some control schemes, temperature

measurement point at the following may not be highest case temperature. In such cases, it is necessary to change

the measurement point to that under the highest power chip. (Refer previous figure of power chip position.)

DIPIPM

Control terminals

11.6m

3mm

Heat sink side

IGBT chip position

The hole diameter approx.0.8mm

（to insert thermocouple）

Power terminals

Tc point

Fig. 3-2-4 Point for installing thermocouple in external heat sink

Installation of thermocouple is shown in Fig. 3-2-5. After making a hole under the chip with largest loss into the heat

sink, the thermocouple is inserted in this hole and fixed by hammering around the hole with a centerpunch. After fixing

the thermocouple, please sandpaper the thermocouple installing surface to make flat surface.

Top view

Hammer this area with a centerpunch

Sanding this area

Fix the thermocouple by using

hammer and centerpunch

Thermocouple

Sandpaper

Thermocouple

Heat sink

Cross-section view

(After fixing the thermocouple)

Centerpunch

After fixing the thermocouple, please sandpaper around

the thermocouple to make flat surface.

Cross-section view

(After fixing the thermocouple)

Fig. 3-2-5 Example of installation of thermocouple

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.3 Noise and ESD Withstand Capability

3.3.1 Evaluation Circuit of Noise Withstand Capability

DIP Ver.6 series have been confirmed to be with over +/-2.0kV noise withstand capability by the noise evaluation

under the conditions shown in Fig.3-3-1. However, noise withstand capability greatly depends on the test environment,

the wiring patterns of control substrate, parts layout, and other factors; therefore an additional confirmation on

prototype is necessary.

DIPIPM

Breaker

AC input

Voltage

slider

Control supply

(15V single power source)

I/F

Isolation

transformer

Heat sink

Inverter

DC supply

Noise simulator

AC100V

Fig.3-3-1 Noise withstand capability evaluation circuit

Note:

C1: AC line common-mode filter 4700pF, PWM signals are input from microcomputer by using optocouplers, 15V

single power supply, Test is performed with IM

Test conditions

V_CC=300V, V_D=15V, Ta=25°C, no load

Scheme of applying noise: From AC line (R, S, T), Period T=16ms, Pulse width tw=0.05-1μs, input in random.

3.3.2 Countermeasures and Precautions

DIPIPM improves noise withstand capabilities by means of reducing parts quantity, lowering internal wiring parasitic

inductance, and reducing leakage current. But when the noise affects on the control terminals of DIPIPM (due to wiring

pattern on PCB), the short circuit or malfunction of SC protection may occur. In that case, below countermeasures are

recommended.

IGBT1

IGBT2

IGBT3

V_UFB(2)

V_VFB(3)

V_WFB(4)

P(24)

U(23)

Di1

Di2

Di3

Increase the capacitance of

C2 and locate it as close to

the terminal as possible.

HVIC

U_P(5)

V_P(6)

V(22)

W_P(7)

V_P1(8)

W(21)

V_NC(9)

IGBT4

Insert the RC filter

Di4

Di5

Di6

U_N(10)

V_N(11)

NU(20)

NV(19)

W_N(12)

IGBT5

IGBT6

LVIC

Fo(14)

Increase the capacitance of

C4 with keeping the same

time constant R1·C4, and

locate the C4 as close to the

terminal as possible.

15V

V_N1(13)

V_NC(16)

NW(18)

CIN(15)

Shunt

resistor

Fig.3-3-2 Example of countermeasures for inverter part

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

3.3.3 Static Electricity Withstand Capability

DIPIPM has been confirmed to be with +/-200V or more withstand capability against static electricity from the

following tests shown in Fig.3-3-3, 4. The results (typical data) are described in Table 3-3-1.

LVIC

HVIC

R=0Ω

V_N1

U_N

V_N

V_P1

U_P

V_UFB

W_N

V_G

C=200pF

V_NC

V_PC

V_UFS(U)

Fig.3-3-3 LVIC terminal Surge Test circuit

Fig.3-3-4 HVIC terminal Surge Test circuit

Conditions: Surge voltage increases by degree and only one-shot surge pulse is impressed at each surge voltage.

(Limit voltage of surge simulator: ±4.0kV, Judgment method; change in V-I characteristic)

Table 3-3-1 Typical ESD capability

[Control terminal part] Common data for PSS**S92*6-AG

Rated current 5A-20A

Rated current 30A, 35A

Terminals

UP, VP, W P-V_NC

V_P1– V_NC

V_UFB-U_,V_VFB-V,V_WFB-W

UN, VN, WN-V_NC

V_N1-V_NC

CIN-V_NC

Fo-V_NC

V_OT-V_NC*

1.2

1.9

1.8

0.7

0.8

1.1

2.5

0.9

0.8

1.5

3.4

1.0

0.9

2.7

2.3

0.7

2.9

0.9

1.1

1.2

4.0 or more

0.6

4.0 or more

0.6

4.0 or more

0.8

0.6

1.1

0.6

0.9

1.0

*) The type with temperature output only (PSS**S92F6-AG)

[Power terminal part]

PSS**S92*6-AG (All rated current)

Terminals

P-NU,NV,NW

U-NU, V-NV, W-NW

4.0 or more

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 4 Bootstrap Circuit Operation

4.1 Bootstrap Circuit Operation

For three phase inverter circuit driving, normally four isolated control supplies (three for P-side driving and

one for N-side driving) are necessary. But using floating control supply with bootstrap circuit can reduce the

number of isolated control supplies from four to one (N-side control supply).

Bootstrap circuit consists of a bootstrap diode(BSD), a bootstrap capacitor(BSC) and a current limiting

resistor. (Super mini DIPIPM Ver.6 series integrates BSD and limiting resistor and can make bootstrap circuit

by adding outer BSC only.) It uses the BSC as a control supply for driving P-side IGBT. The BSC supplies gate

charge when P-side IGBT turning ON and circuit current of logic circuit on P-side driving IC (Fig.4-1-2). Since a

capacitor is used as substitute for isolated supply, its supply capability is limited. This floating supply driving

with bootstrap circuit is suitable for small supply current products like DIPIPM.

Charge consumed by driving circuit is re-charged from N-side 15V control supply to BSC via current limiting

resistor and BSD when voltage of output terminal (U, V or W) goes down to GND potential in inverter operation.

But there is the possibility that enough charge doesn't perform due to the conditions such as switching

sequence, capacitance of BSC and so on. Deficient charge leads to low voltage of BSC and might work under

voltage protection (UV). This situation makes the loss of P-side IGBT increase by low gate voltage or stop

switching. So it is necessary to consider and evaluate enough for designing bootstrap circuit. For more detail

information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap Circuit Design

Manual"

The BSD characteristics for Super mini DIPIPM Ver.6 series and the circuit current characteristics in

switching situation of P-side IGBT are described as below.

Bootstrap capacitor

(BSC)

BSD

Current limiting

resistor

Bootstrap diode

(BSD)

15V

BSC

P(Vcc)

HVIC

P-side

IGBT

V_P1

V_FB

V_P1

V_FB

P(Vcc)

P-side

FWDi

P-side

IGBT

V_PC

U,V,W

V_FS

P-side

FWDi

↑High voltage area

N-side

IGBT

V_D=15V

V_N1

V_FS

N-side

FWDi

V_PC

U,V,W

LVIC

Voltage of VFS that is reference voltage of BSC swings between

VCC and GND level. If voltage of BSC is lower than 15V when

VFS becomes to GND potential, BSC is charged from 15V N-side

control supply.

V_NC

N(GND)

Fig.4-1-1 Bootstrap Circuit Diagram

Fig.4-1-2 Bootstrap Circuit Diagram

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<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

4.2 Bootstrap Supply Circuit Current at Switching State

Bootstrap supply circuit current I_DBat steady state is maximum 0.1mA for PSS**S92*6-AG series (for rated current

5A~20A. I_DBspecification of 30A and 35A product is maximum 0.3mA. For more detail, please refer the datasheet

of each product.). But at switching state, because gate charge and discharge are repeated by switching, the circuit

current exceeds 0.1mA (or 0.3mA) and increases proportional to carrier frequency. For reference, Fig.4-2-1~6

shows I_DB- carrier frequency fc characteristics for each current rating product.

(Conditions: V_D=V_DB=15V, Tj=125°C at which I_DBbecomes larger, IGBT ON Duty=10, 30, 50, 70, 90%)

700

600

500

400

10%

30%

50%

70%

90%

300

200

100

Carrier frequency (kHz)

Fig.4-2-1 I_DBvs. Carrier frequency for PSS05S92*6-AG

800

700

600

500

400

300

200

100

10%

30%

50%

70%

90%

Carrier frequency (kHz)

Fig.4-2-2 I_DBvs. Carrier frequency for PSS10S92*6-AG

1000

900

800

700

600

500

400

300

200

100

10%

30%

50%

70%

90%

Carrier frequency (kHz)

Fig.4-2-3 I_DBvs. Carrier frequency for PSS15S92*6-AG

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Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

1200

1000

800

600

400

200

10%

30%

50%

70%

90%

Carrier frequency (kHz)

Fig.4-2-4 I_DBvs. Carrier frequency for PSS20S92*6-AG

2500

2000

1500

1000

500

10%

30%

50%

70%

90%

Carrier frequency (kHz)

Fig.4-2-5 I_DBvs. Carrier frequency for PSS30S92*6-AG

4000

3500

3000

2500

2000

1500

1000

500

10%

30%

50%

70%

90%

Carrier frequency(kHz)

Fig.4-2-6 I_DBvs. Carrier frequency for PSS35S92*6-AG

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<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

4.3 Note for designing the bootstrap circuit

When each device for bootstrap circuit is designed, it is necessary to consider various conditions such as

temperature characteristics, change by lifetime, variation and so on. Note for designing these devices are listed as

below. For more detail information about driving by the bootstrap circuit, refer the DIPIPM application note "Bootstrap

Circuit Design Manual"

(1) Bootstrap capacitor

Electrolytic capacitors are used for BSC generally. And recently ceramic capacitors with large capacitance are also

applied. But DC bias characteristic of the ceramic capacitor when applying DC voltage is considerably different from

that of electrolytic capacitor. (Especially large capacitance type) Some differences of capacitance characteristics

between electrolytic and ceramic capacitors are listed in Table 4-3-1.

Table 4-3-1 Differences of capacitance characteristics between electrolytic and ceramic capacitors

Ceramic capacitor

(large capacitance type)

Electrolytic capacitor

• Aluminum type:

Different due to temp. characteristics rank

Low temp.: -5%~0%

High temp.: -5%~-10%

Temperature

characteristics

(Ta:-20~ 85°C)

Low temp.: -10% High temp: +10%

• Conductive polymer aluminum solid type:

Low temp.: -5% High temp: +10%

(in the case of B,X5R,X7R ranks)

DC bias

characteristics

(Applying DC15V)

Different due to temp. characteristics,

rating voltage, package size and so on

-70%~-15%

Nothing within rating voltage

DC bias characteristic of electrolytic capacitor is not matter. But it is necessary to note ripple capability by repetitive

charge and discharge, life time which is greatly affected by ambient temperature and so on. Above characteristics are

just example data which are obtained from the WEB, please refer to the capacitor manufacturers about detailed

characteristics.

(2) Bootstrap diode

DIP Ver.6 integrates bootstrap diode for P-side driving supply. This BSD incorporates current limiting resistor. So

there isn't any limitation about bootstrap capacitance like former PS219A* has (22μF or less in the case of one long

pulse initial charging). The VF-IF characteristics (rated current 5A~20A, and rated current 30A, 35A including voltage

drop by built-in current limiting resistor) is shown in Fig.4-3-1, Fig.4-3-2, Table 4-3-2 and Table 4-3-3.

160

140

120

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_F[V]

Fig.4-3-1 V_F-I_Fcurve for bootstrap Diode (rated current 5A~20A, the right figure is enlarged view)

Table 4-3-2 Electric characteristics of built-in bootstrap diode (rated current 5A~20A)

Item

Bootstrap Di forward

voltage

Symbol

Condition

I_F=10mA including voltage

drop by limiting resistor

Min.

1.1

Typ.

1.7

Max.

2.3

Unit

V_F

Included in bootstrap Di

Built-in limiting resistance

100

120

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

240

200

160

120

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V_F[V]

Fig.4-3-2 V_F-I_Fcurve for bootstrap Diode (rated current 30A, 35A, the right figure is enlarged view)

Table 4-3-3 Electric characteristics of built-in bootstrap diode (rated current 30A, 35A)

Item

Bootstrap Di forward

voltage

Symbol

Condition

I_F=10mA including voltage

drop by limiting resistor

Min.

0.9

Typ.

1.3

Max.

1.7

Unit

V_F

Included in bootstrap Di

Built-in limiting resistance

4.4 Initial charging in bootstrap circuit

In the case of applying bootstrap circuit, it is necessary to charge to the BSC initially because voltage of BSC is 0V at

initial state or it may go down to the trip level of under voltage protection after long suspending period (even 1s). BSC

charging is performed by turning on all N-side IGBT normally. When outer load (e.g. motor) is connected to the

DIPIPM, BSC charging may be performed by turning on only one phase N-side IGBT since potential of all output

terminals will go down to GND level through the wiring in the motor. But its charging efficiency might become lower

due to some cause. (e.g. wiring resistance of motor)

There are mainly two procedures for BSC charging. One is performed by one long pulse, and another is conducted

by multiple short pulses. Multi pulse method is used when there are some restriction like control supply capability and

so on.

BSD

P(Vcc)

P-side

IGBT

15V

V_FB

V_P1

V_PC

V_D

V_DB

N-side

input

V_FS

U,V,W

HVIC

Charge

current

N-side

IGBT

15V

V_N1

N-side

FWDi

Voltage of

BSC V_DB

V_NC

LVIC

N(GND)

Fig.4-4-1 Initial charging root

Fig.4-4-2 Example of waveform by one charging pulse

Initial charging needs to be performed until voltage of BSC exceeds recommended minimum supply voltage 13V. (It

is recommended to charge as high as possible with consideration for voltage drop between the end of charging and

start of inverter operation.)

After BSC was charged, it is recommended to input one ON pulse to the P-side input for reset of internal IC state

before starting system. Input pulse width is needed to be longer than allowable minimum input pulse width PWIN(on).

(e.g. 0.7μs or more for Super mini DIPIPM Ver.6. Refer the datasheet for each product.)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 5 Interface Demo Board

5.1 Super mini DIPIPM Ver.6 Interface Demo Board

This chapter describes the interface demo board of Super mini DIPIPM Ver.6 as a reference for the design of user

application PCB with Super mini DIPIPM Ver.6.

(1) Demo Board Outline

The demo board can mount the minimum necessary components of Super mini DIPIPM Ver.6 interface shown in

Fig.5-1-1.

Fig.5-1-1 Demo board interface circuit

(2) Demo Board Photo

Fig.5-1-2 Demo board photo

Note: Board dimension 65.0×48.0 (pattern thickness 70μm)

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

5.2 Interface demo board pattern

(1) Component placement

ZD1

C11

T3-1

Fig.5-2-1 Demo board component layout (DIPIPM is mounted to back side.)

(2) PCB Pattern Layout

22.00

10.00

27.00

65.00

Component side

Back side (The view from the component side)

Fig.5-2-2 Demo board PCB pattern layout

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

5.3 Circuit Schematic and Parts List

(1) Circuit Schematic

T3-1

VUFB

VP1

CN1

C12

VVFB

C13

VWFB

C14

W ₂₁

VN1

C11

C15

C16

C17

R10

+5V

VNC

VOT

ZD1

CIN

+15V

GND

C10

VOT

CN2

T3-2

Fig.5-3-1 Demo board circuit schematic

Note: Although Zener diodes are not installed to P-side three floating drive supplies (between V_UFB-U,

V_VFB-V, V_WFB-W) on this demo board, it is highly recommend to add these zener diodes in actual

system board.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

(2) Parts List

Table 5-3-1 Parts list (only for reference)

Symbol

ZD1

Type Name

U1ZB24

Description

24V 1W Zener Diode

Note

Toshiba

UPW1H220MDD

GRM188R71H102K

UPW1E101MDD

GRM188R71H102K

GRM55DR72J224KW01L

GRM188R71H102K

CR1/16W103F

22μF 50V Al electrolytic capacitor

1000pF 50V ceramic capacitor

100μF 25V Al electrolytic capacitor

1000pF 50V ceramic capacitor

0.22μF 630V snubber capacitor

1000pF 50V ceramic capacitor

1/16W 10kΩ

Nichicon

Murata

Nichicon

Murata

C10

C11

C12

C13

C14

C15

C16

C17

Murata

Hokuriku Denko

KOA

CR1/16W512F

1/16W 5.1kΩ

CR1/16W202F

1/16W 2kΩ

R4-1

R4-2

R4-3

SL2TBK33L0F

2W 33mΩ Current sensing resistor

1/16W 100Ω

SL2TBK33L0F

KOA

SL2TBK33L0F

KOA

CR1/16W101F

Hokuriku Denko

CR1/16W101F

1/16W 100Ω

It is necessary to change the shunt resistances (R4-1, R4-2, R4-3) depends on the rated current of DIPIPM.

The shunt resistances (33mΩ/3=11mΩ) listed above is in the case of using demo board with DIPIPM of rated

current 30A.

4. Caution

This evaluation board is made for your quick and temporary evaluation and above patterns and parts list

are examples. We cannot guarantee the proper operation of this PCB in all case. When selecting parts and

design patterns for your PCB, please comply with your design standard and consider life time, reliability and

so on.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

CHAPTER 6 PACKAGE HANDLING

6.1 Packaging Specification

(44)

(22)

Plastic Tube

Quantity:

DIPIPM

12pcs per 1 tube

(520)

Total amount in one box (max):

5 columns

Tube Quantity: 5 × 7=35pcs

IPM Quantity: 35 × 12=420pcs

When it isn't fully filled by tubes

at top stage, cardboard spacers

or empty tubes are inserted for

filling the space of top stage.

7 stages

(230)

Weight (max):

About 8.5g per 1pcs of DIPIPM

About 200g per 1 tube

(175)

About 8.3kg per 1 box

(545)

Packaging box

Spacers are put on the top and bottom of the box. If there is some space on top of the box, additional buffer materials

are also inserted.

Fig.6-1-1 Packaging Specification

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

6.2 Handling Precautions

！

Cautions

Transportation

·Put package boxes in the correct direction. Putting them upside down, leaning them or giving

them uneven stress might cause electrode terminals to be deformed or resin case to be

damaged.

·Throwing or dropping the packaging boxes might cause the devices to be damaged.

·Wetting the packaging boxes might cause the breakdown of devices when operating. Pay

attention not to wet them when transporting on a rainy or a snowy day.

Storage

·We recommend temperature and humidity in the ranges 5-35°C and 45-75%, respectively, for

the storage of modules. The quality or reliability of the modules might decline if the storage

conditions are much different from the above.

Long storage

Surroundings

·When storing modules for a long time (more than one year), keep them dry. Also, when using

them after long storage, make sure that there is no visible flaw, stain or rust, etc. on their

exterior.

·Keep modules away from places where water or organic solvent may attach to them directly

or where corrosive gas, explosive gas, fine dust or salt, etc. may exist. They might cause

serious problems.

Flame

·The epoxy resin and the case materials are flame-resistant type (UL standard 94-V0), but

resistance

they are not noninflammable.

·ICs and power chips with MOS gate structure are used for the DIPIPM power modules.

Please keep the following notices to prevent modules from being damaged by static

electricity.

Static electricity

(1) Precautions against the device destruction caused by the ESD

When the ESD of human bodies, packaging and etc. are applied to terminal, it may damage

and destroy devices. The basis of anti-electrostatic is to inhibit generating static electricity

possibly and quick dissipation of the charged electricity.

·Containers that charge static electricity easily should not be used for transit and for storage.

·Terminals should be always shorted with a carbon cloth or the like until just before using the

module. Never touch terminals with bare hands.

·Should not be taking out DIPIPM from tubes until just before using DIPIPM and never touch

terminals with bare hands.

·During assembly and after taking out DIPIPM from tubes, always earth the equipment and

your body. It is recommended to cover the work bench and its surrounding floor with earthed

conductive mats.

·When the terminals are open on the printed circuit board with mounted modules, the modules

might be damaged by static electricity on the printed circuit board.

·If using a soldering iron, earth its tip.

(2)Notice when the control terminals are open

·When the control terminals are open, do not apply voltage between the collector and emitter.

It might cause malfunction.

·Short the terminals before taking a module off.

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Revision Record

Rev.

Date

Points

15/ 3/2014

1/ 5/2014

New

· Add circuit current IDB specification of 30,35A products in section 4.2

· Add section 4.4

Publication Date: May 2014

<Dual-In-Line Package Intelligent Power Module>

Super Mini DIPIPM Ver.6 Series APPLICATION NOTE

Keep safety first in your circuit designs!

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more

reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead

to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit

designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of

non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi

semiconductor product best suited to the customer’s application; they do not convey any license under any

intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s

rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application

examples contained in these materials.

•All information contained in these materials, including product data, diagrams, charts, programs and algorithms

represents information on products at the time of publication of these materials, and are subject to change by

Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore

recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor

product distributor for the latest product information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric

Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or

errors.

Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including

the Mitsubishi Semiconductor home page (http://www.MitsubishiElectric.com/).

•When using any or all of the information contained in these materials, including product data, diagrams, charts,

programs, and algorithms, please be sure to evaluate all information as a total system before making a final

decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no

responsibility for any damage, liability or other loss resulting from the information contained herein.

•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system

that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric

Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product

contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,

aerospace, nuclear, or undersea repeater use.

•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part

these materials.

•If these products or technologies are subject to the Japanese export control restrictions, they must be exported

under a license from the Japanese government and cannot be imported into a country other than the approved

destination.

Any diversion or re-export contrary to the export control laws and regulations of Japan and/or the country of

destination is prohibited.

•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for

further details on these materials or the products contained therein.

DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION.

Publication Date: May 2014

PSS05S92F6-AG [MITSUBISHI]

相关型号：

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