MFM8516WMB-15E_技术文档

512K x 8 FLASH

MFM8516 - 70/90/12/15

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (619) 674 2233, Fax No: (619) 674 2230

Issue 4.7 : November 1998

524,288 bit FLASH EEPROM

Description

Features

The MFM8516 is a 4M Bit CMOS 5V only Flash

monolithic device organised : 512K x 8. The device

offersfastaccesstimesof70/90/120and150nsand

5V program/erase.

• 4 Megabit FLASH memory.

• Fast Access Times of 70/90/120/150 ns.

• Operating Power 247.50 mW (max),

Low Power Standby (CMOS) 632.50µW (max).

• AutomaticWrite/ErasebyEmbeddedAlgorithm-endof

Write/Erase indicated by DATA Polling and Toggle Bit.

• Flexible Sector Erase Architecture - 64K byte sector

size,withhardwareprotectionofanynumberofsectors.

• ByteProgramof16µs(Typ),SectorProgramof 2s(Typ)

• Erase/Write Cycle Endurance, Standard 10,000 (min)

Extended 100,000 (min)

Thedevicehasa64KBytesectorsize.TheProgram

and Erase procedure is simplified via automatic

program and erase algorithms.

The MFM8516 has a 10K cycle write erase cycle

endurance (100K cycle E-Part) and a 10 year data

retention time.

• 10 year data retention.

• May be screened in accordance with MIL-STD-883.

Block Diagram

Pin Definitions

DQ0-DQ7

A18

A16

A15

A12

A7

A6

A5

A4

A3

1

2

3

4

5

6

7

8

9

32 V

CC

Vcc

Vss

31 WE

30 A17

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS

21 D7

20 D6

19 D5

Input/Output

Buffers

Erase Voltage

Generator

S,V

PACKAGE

TOP VIEW

WE

State

Control

Command

Register

PGM Voltage

Generator

A2 10

A1 11

A0 12

D0 13

D1 14

D2 15

Data

Latch

Chip Enable

Output Enable

Logic

CE

OE

18 D4

17 D3

GND 16

A

d

r

Y-Decoder

X-Decoder

Y-Gating

STB

Vcc Detector

Timer

L

a

t

Cell Matrix

A7

A6

A5

A4

A3

5

6

7

8

9

29 A14

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS

21 D7

A0-A18

c

h

A2 10

A1 11

A0 12

D0 13

Package Details

Pin Count Description

Pin Functions

A0-A18

D0-D7

CS

Address Inputs

Data Inputs/Outputs

Chip Enable

Package Type

32

Dual In-line

S

WE

OE

Vcc

GND

Write Enable

Output Enable

Power (+5V)

Ground

JLCC (J Leaded Chip Carrier)

J

32

LCC (Leadless Chip Carrier)

Vertical-in-Line

W

V

ISSUE 4.7 : NOVEMBER 1998

MFM8516 - 70/90/12/15

DC OPERATING CONDITIONS

Absolute Maximum Ratings ⁽¹⁾

unit

V

Voltage on any pin w.r.t. Gnd

Supply Voltage⁽²⁾

Voltage on A9 w.r.t. Gnd ⁽³⁾

-2.0 to +7

-2.0 to +14

-65 to +150

V

Storage Temperature

°C

Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at those or any other conditions above those indicated in the operational sections of this

specification is not implied.

(2) Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V

During transitions voltage may overshoot by +/-2V for up to 20ns

(3) Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot Vss to -2V for periods of up to

20ns, maximum DC input voltage in A9 is 13.5V which may overshoot to 14.0V for periods up to 20ns

Recommended Operating Conditions

Parameter

min

typ

max

unit

Supply Voltage

V_CC

V_IH

V_IL

V_IH

V_IL

T_A

4.5

2.0

-0.5

0.7V_CC

-0.5

0

5.0

5.5

V_CC+0.5

0.8

V_CC+0.3

0.8

V

°C

Input High Voltage (TTL)

Input Low Voltage (TTL)

Input High Voltage (CMOS)

Input Low Voltage (CMOS)

Operating Temperature

-

70

85

125

T_AI

T_AM

-40

-55

^OC (-I suffix)

^OC (-M\MB suffix)

DC Electrical Characteristic (T_A=-55°C to +125°C,V_CC=5V ± 10%)

Parameter

I/P Leakage Current Address, OE I_LI1

A9 Input Leakage Current I_LI2

Symbol Test Condition

min

typ max Unit

V_CC= V_CCmax, V_IN= 0V or V_CC

-

±1 µA

50 µA

±1 µA

45 mA

65 mA

1.5 mA

115 µA

V_CC= V_CCmax, A9 = 12.5V

V_CC= V_CCmax, V_IN= 0V or V_CC

V_CC= V_CCmax, V_OUT= 0V or V_CC

CS = V_IL, OS = V_IH, I_OUT= 0mA, f = 6MHz

Programming in Progress

Other Pins I_LI3

I_LO

Output Leakage Current

V_CCOperating Current

I_CCO

I_CCP

TTL I_SB

CMOS I_SB1

V_CCProgram/Erase Current

Standby Supply Current

V_CC= V_CCmax, CS = V_IHOE = V_IH

V_CC= V_CCmax, CS = V_CC+0.5, OE = V_IL

V_CC= 5.0V

Autoselect / Sector Protect Voltage

Output Low Voltage

V_ID

11.5

12.5

0.45

-

V

V_OL

I_OL= 10mA. V_CC= V_CCmin.

I_OH= -2.5mA. V_CC= V_CCmin.

-

2.4

3.2

Output High Voltage

V_OH1

V_LKO

Low V_CCLock-Out Voltage

4.2

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MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

Capacitance (T_A=25°C,f=1MHz)

Parameter

Symbol

C_IN1

Test Condition

V_IN= 0V

typ

max

10

Unit

pF

Input Capacitance

-

Control Pin Capacitance

Output Capacitance

C_IN2

V_PP= 0V

12

pF

C_OUT

V_OUT= 0V

12

pF

Note: These parameters are calculated, not measured.

AC Test Conditions

166

Ω

* Input pulse levels : 0.0V to 3.0V

* Input rise and fall times : 5 ns

* Input and output timing reference levels : 1.5V

* VCC = 5V +/- 10%

I/O Pin

1.76V

30pF

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MFM8516 - 70/90/12/15

AC OPERATING CONDITIONS

Read Cycle

Parameter

Symbol

70

typ

-

90

typ

-

min

70

max

-

min

90

max

-

Unit

ns

Read Cycle Time

tRC

tACC

tCE

Address to output delay

Chip enable to output

-

70

30

20

-

90

35

20

-

ns

Output enable to output

Output enable to output High

Output hold time from address

CS or OE whichever occurs first

tOE

-

ZtDF

tOH

-

0

Parameter

Symbol

120

typ

-

150

typ

-

min

120

max

-

min

150

max

-

Unit

ns

Read Cycle Time

tRC

tACC

tCE

Address to output delay

Chip enable to output

-

120

50

30

-

150

55

35

-

ns

Output enable to output

Output enable to output High

Output hold time from address

CS or OE whichever occurs first

tOE

-

ZtDF

tOH

-

0

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MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

Write/Erase/Program

Parameter

Symbol

70

90

min

typ

max

min

typ

max

unit

Write Cycle time ⁽²⁾

Address Setup time

Address Hold time

Data Setup Time

t_WC

t_AS

70

0

-

90

0

-

ns

µs

sec

µs

-

t_AH

45

30

0

-

45

0

-

t_DS

-

Data hold Time

t_DH

-

Output Enable Setup Time

Read Recover before Write

CS setup time

t_OES

t_GHWL

t_CE

0

-

0

-

0

-

0

-

0

-

0

-

CS hold time

t_CH

0

-

0

-

WE Pulse Width

t_WP

35

20

-

45

20

-

WE Pulse Width High

Byte Programming operation

Sector Erase operation ⁽¹⁾

Chip Erase operation ⁽¹⁾

Vcc setup time ⁽²⁾

t_WPH

t_WHWH1

t_WHWH2

t_WHWH3

t_VCS

-

16

2

14

-

16

2

14

-

30

120

-

30

120

-

50

Parameter

Symbol

120

typ

150

typ

min

max

min

max

unit

Write Cycle time ⁽²⁾

Address Setup time

Address Hold time

Data Setup Time

t_WC

t_AS

120

0

-

150

0

-

ns

µs

sec

µs

-

t_AH

50

0

-

50

0

-

t_DS

-

Data hold Time

t_DH

-

Output Enable Setup Time

Read Recover before Write

CS setup time

t_OES

t_GHWL

t_CE

0

-

0

-

0

-

0

-

0

-

0

-

CS hold time

t_CH

0

-

0

-

WE Pulse Width

t_WP

50

20

-

50

20

-

WE Pulse Width High

Byte Programming operation

Sector Erase operation ⁽¹⁾

Chip Erase operation ⁽¹⁾

Vcc setup time ⁽²⁾

t_WPH

t_WHWH1

t_WHWH2

t_WHWH3

t_VCS

-

16

2

14

-

16

2

14

-

30

120

-

30

120

-

50

Notes: (1) This does not include the preprogramming time.

(2) Not 100% tested.

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MFM8516 - 70/90/12/15

Write/Erase/Program Alternate CS controlled Writes

Parameter

Symbol

70

90

min

typ

max

min

typ

max

unit

Write Cycle time ⁽²⁾

Address Setup time

t_WC

t_AS

70

0

-

90

0

-

ns

Address Hold time

Data Setup Time

t_AH

t_DS

45

30

0

-

45

0

-

ns

us

sec

us

-

Data hold Time

t_DH

-

Output Enable Setup Time

Read Recover before Write

WE setup time

t_OES

0

-

0

-

t_GHEL

t_WS

0

-

0

-

0

-

0

-

WE hold time

t_WH

0

-

0

-

CS Pulse Width

t_CP

35

20

-

45

20

-

CS Pulse Width High

Programming operation

Sector Erase operation ⁽¹⁾

Chip Erase operation ⁽¹⁾

Vcc setup time ⁽²⁾

t_CPH

t_WHWH1

t_WHWH2

t_WHWH3

t_VCS

-

16

2

14

50

-

16

2

14

50

-

30

120

-

30

120

-

Parameter

Symbol

120

typ

150

typ

min

max

min

max

unit

Write Cycle time ⁽²⁾

Address Setup time

t_WC

t_AS

120

0

-

150

0

-

ns

Address Hold time

Data Setup Time

t_AH

t_DS

50

0

-

50

0

-

ns

us

sec

us

-

Data hold Time

t_DH

-

Output Enable Setup Time

Read Recover before Write

WE setup time

t_OES

0

-

0

-

t_GHEL

t_WS

0

-

0

-

0

-

0

-

WE hold time

t_WH

0

-

0

-

CS Pulse Width

t_CP

50

20

-

50

20

-

CS Pulse Width High

Programming operation

Sector Erase operation ⁽¹⁾

Chip Erase operation ⁽¹⁾

Vcc setup time ⁽²⁾

t_CPH

t_WHWH1

t_WHWH2

t_WHWH3

t_VCS

-

16

2

14

50

-

16

2

14

50

-

30

120

-

30

120

-

Note: (1) Does not include pre-programming time.

(2) Not 100% tested.

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ISSUE 4.7 : NOVEMBER 1998

AC Waveforms for Read Operation

t_RC

Address

CS

Address Stable

t_ACC

t_DF

t_OE

OE

WE

t_OH

t_CE

High Z

Output Valid

Outputs

AC Waveforms Program

Data Polling

5555H

PA

Address

t_AS

t_RC

t_WC

t_AH

CS

t_GHWL

OE

t_WP

t_WHP

t_WHWH1

WE

t_CS

t_OE

t_DF

t_DH

PD

A0H

D _OUT

D7

DATA

t_DS

V

t_OH

CC

t_CE

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. D7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

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MFM8516 - 70/90/12/15

A.C Waveforms - Alternate CS controlled Program operation timings

Data Polling

5555H

PA

Address

t_AS

t_GHEL

t_AH

t_RC

t_WC

WE

OE

t_CP

t_CHP

t_WHWH1

CS

t_WS

t_OE

t_DF

t_DH

A0H

PD

D_OUT

D7

DATA

V_CC

t_DS

t_CE

t_OH

NOTES:

1. PA is address of memory location to be programmed.

2. PD is data to be programmed at byte address.

3. D7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

AC Waveforms for Data Polling During Embedded Algorithm Operations

t_CH

CS

t_DF

t_OE

OE

t_OEH

WE

t_CE

t_OH

*

HIGH Z

D7 =

D7

Valid Data

t_{WHWH1 OR 2}

D0-D6

= Invalid

D0-D6=

Vaild Data

D0-D6

t_OE

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ISSUE 4.7 : NOVEMBER 1998

AC Waveforms for Toggle Bit During Embedded Algorithm Operations

CS

WE

t_OEH

OE

*

D6 =

Stop Toggling

D0-D7

Valid

D6 = Toggle

DATA (D0-D7)

D6 = Toggle

t_OE

* D6 stops toggling ( the device has completed the embedded operations)

AC Waveforms Chip / Sector Erase

t_AS

t_AH

Address

5555H

2AAAH

5555H

2AAAH

SA

CS

OE

t

GHWL

t

WP

WE

WPH

t

CS

t

DH

Data

Vcc

55H

AAH

80H

AAH

55H

10H/30H

t

DS

t

VCS

NOTES:

1. SA is the address for sector erase. Addresses = don't care for Chip Erase.

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MFM8516 - 70/90/12/15

EMBEDDED PROGRAMMING ALGORITHM

Start

Write Program Command

Sequence

(see below)

Data Poll Device

Last

Address

?

No

Increment Address

Yes

Programming

Completed

Program Command Sequence (Address /Command)

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program data

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ISSUE 4.7 : NOVEMBER 1998

EMBEDDED ERASE ALGORITHM

START

Write Erase Command Sequence

See below

Data Poll or Toggle Bit

Successfully Completed

Erasure Completed

Individual Sector/Mulitiple Sector

Chip Erase Command Sequence

(Address/Command):

Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

5555H/10H

2AAAH/55H

5555H/80H

5555H/AAH

2AAAH/55H

Sector Address/30H

Additional sector

erase commands

are optional

}

Sector Address/30H

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MFM8516 - 70/90/12/15

DATA POLLING ALGORITHM

Start

VA = Byte Address for programming

Read Byte

(DQ0 - DQ7)

Addr=VA

= Any of the sector addresses

within the sector being erased

during sector erase operation.

= XXXXH during chip erase

Yes

DQ7=Data?

No

DQ5=1?

Yes

Read Byte

(DQ0 - DQ7)

Addr=VA

Yes

DQ7=Data?

Pass

No

Fail

Note : DQ7 is rechecked even if DQ5 = "1" beceause DQ7 may change simultaneousely

with DQ5.

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TOGGLE BIT ALGORITHM

Start

VA = Byte Address for programming

Read Byte

= Any of the sector addresses

within the sector being erased

during sector erase operation.

= XXXXH during chip erase

(D0 - D7)

Addr=VA

No

D6 = Toggle?

Yes

No

D5=1?

Yes

Read Byte

(D0 - D7)

Addr=VA

No

D6 = Toggle?

Pass

Yes

Fail

Note : D6 is rechecked even if D5 = "1" beceause D6 may stop toggling at the same time

as D5 changing to "1"

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DEVICE OPERATION

Read Mode

The MFM8516 has two control functions which must be satisfied in order to obtain data at the outputs

CS is the power control and should be used for device selection.

OE is the output control and should be used to gate data to the output pins if the device is selected.

Standby Mode

Two standby modes are available : CMOS standby : CS held at Vcc +/- 0.5V

TTL standby :

CS held at V_IH

In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is

deselected during erasure or programming the device will draw active current until the operation is completed.

Output Disable

With the OE input at a logic high level (V_IH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

This mode is intended for use by programming equipment. This mode is functional over the full military

temperature range. The autoselect codes as follows :

Type

A18

A17

A16

A6

A1

A0

Code

(HEX)

D7

D6

D5

D4

D3

D2

D1

D0

Sector

Protection

Sector Address

V_IL

V_IH

V_IL

01H*

0

1

* Outputs 01H at protected sector address

To activate this mode the programming equipment must force V_IDon address A9 . All addresses are don't

care apart from A0, A1 & A6.

Write

Device erasure and programming are accomplished via the command register. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The register is a latch used to store the commands along with the address and data information required to

execute the command. The command register is written by bringing WE to V_ILwhile CS is at V_ILand

OE is at V_IH. Addresses are latched on the falling edge of WE or CS, whichever happens later; while data is

latched on the rising edge of WE or CS, whichever happens first.

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COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

The following table defines these register command sequences.

Bus

Write

Cycles

Req'd

Fourth Bus

Read/Write

Cycle

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Command

Sequence

Read/Reset

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

1

4

3

4

XXXH

5555H

F0H

AAH

Read/Reset

Autoselect

2AAAH

55H

5555H

F0H

90H

A0H

80H

RA

RD

Byte Program

Chip Erase

Sector Erase

PA

Data

AAH

2AAAH

5555H

55H

5555H

SA

10H

30H

6

Sector Erase Suspend

Sector Erase Resume

Erase can be suspended during sector erase with Addr (don't care) Data (B0H)

Erase can be resumed after suspend with Addr (Don't Care), Data (30H)

NOTES:

1. Address bit A₁₅,A₁₆,A₁₇, A₁₈=X=Don't care. Write Sequences may be initiated with A₁₅in either state.

2. Address bit A₁₅,A₁₆,A₁₇, A₁₈=X=Don't care for all address commands except for Program Address (PA) and

Sector Address (SA).

3. RA=Address of the memory location to be read.

PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE

pulse.

SA=Address of the sector to be erased. The combination of A₁₈, A₁₇and A₁₆will uniquely select any

sector.

4. RD=Data read from location RA during read operation.

PD=Data to be programmed at location PA. Data is latched on the rising edge of WE

5. Read and byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.

Read / Reset Command

The read or reset operation is initiated by writing the read/reset command sequence into the command

register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for

reads until the command register contents are altered.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for specific timing parameters.

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Sector Protection

The MFM8516 features hardware sector protection. This feature will disable both program and erase opera-

tions in any number of sectors (0 through 8). The sector protect feature is enabled using programming equip-

ment at the users site. The device is shipped with all sectors unprotected.

It is also possible to determine if a sector is protected in the system by writing the Autoselect command.

Performing a read operation at the address location XX02H, where the higher order addresses (A16, A17,

A18) are the sector addresses will produce a logical "1" at D0 for a protected sector.

Sector Address Table

A18

A17

A16

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

Sector Unprotect

The MFM8516 also features a sector unprotect mode so that a potected sector may be unprotected to

incorporate any changes in the code. The sector unprotect is enabled using programming equipment at the

user's site. It is also possible to determine if a sector is unprotected in the system by writing the autoselect

command and A6 is set at V_IH. Performing a read operation at address location XXX2H, where the higher

order addresses (A18, A17, and A16) define a particular sector address, will produce 00H at data outputs (D0

- D7) for an unprotected sector.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally a desired system design practice.

The device contains an autoselect operation to supplement traditional PROM programming methodology. The

operation is initiated by writing the autoselect command sequence into the command register.

Following command write, scanning the sector addresses on A16, A17, & A18 while A6, A1 & A0 = 0, 1, 0 will

produce a logical "1" at device output D0 for a protected sector.

To terminate the operation, it is necessary to write the read/reset command sequence into the register.

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Byte Programming

The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two

"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are

latched on the falling edge of WE or CS, whichever happens later, while the data are latched on the rising edge

of WE or CS whichever happens first. The rising edge of WE or CS begins programming. Upon executing the

Embedded Program Algorithm Command sequence the system is not required to provide further controls or

timings. The device will automatically provide adequate internally generated program pulses and verify the

programmed cell margin. The automatic programming operation is completed when the data on D7 is equiva-

lent to data written to this bit (see Write Operations Status) at which time the device returns to the read mode

and addresses are no longer latched. Data Polling must be performed at the memory location which is being

programmed.

Programming is allowed in any address sequence and across sector boundaries.

Sector Erase

Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing

the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The

sector address (any address location within the desired sector) is latched on the falling edge of WE, while the

command (data) is latched on the rising edge of WE. A time-out of 80µs from the rising edge of the last sector

erase command will initiate the sector erase command(s).

Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This

sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be

concurrently erased. The time between writes must be less than 80µs, otherwise the command will not be

accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.

The interrupts can be-enabled after the last Sector Erase command is written. A time-out of 80µs from the

rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of

the WE occurs within the 80us time-out window the timer is reset. Any command other than Sector Erase or

Erase Suspend during this period and afterwards will reset the device to read mode, ignoring the previous

command string. Resetting the device after it has begun execution will result in the data of the operated

sectors being undefined. In that case, restart the erase on those sectors and allow them to complete. Loading

the sector erase buffer may be done in any sequence and with any number of sectors.

Sector erase doesn't require the user to program the device prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors

the remaining unselected sectors are not affected. The system is not required to provide any controls or

timings during these operations.

The automatic sector erase begins after the 100µs time-out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status

Section) at which time the device returns to read mode. Data polling must be preformed at an address within

any of the sectors being erased.

Chip Erase

Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the

"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.

Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded

Erase Algorithm command sequence the device automatically will program and verify the entire memory for an

all zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings

during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.

17

ISSUE 4.7 : NOVEMBER 1998

MFM8516 - 70/90/12/15

Erase Suspend

Erase suspend allows the user to interrupt a Sector Erase operation and then perform data reads or programs

to a sector not being erased. This command is only applicable during the Sector Erase operation which in-

cludes the time-out period for sector erase. The Erase Suspend command will be ignored if written during Chip

Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector

Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Any other command written during the Erase Suspend mode will be ignored except the Erase Resume

command. Writing the Erase Resume command resumes the erase operation. The addresses are "don't-

cares" when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a

maximum of 15µs to suspend the erase operation. When the device has entered the erase-suspend mode, D7

bit will be a logic '1', and D6 will stop toggling. The user must use the address of the erasing sector for reading

D6 and D7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend

command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Read-

ing data in this mode is the same as reading from the standard read mode except that the data must be read

from sectors that have not been erase-suspended. Successively reading from the erase-suspend sector while

the device is in the erase-suspend-read mode will cause D2 to toggle.

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate

command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.

Again, programming in this mode is the same as programming in the regular Byte Program mode except that

the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-

suspended sector while the device is in the erase-suspend-program mode will cause D2 to toggle. The end of

the erase-suspend-program operation is detected by Data Polling of D7, or by the Toggle bit (D6) which is the

same as the regular Byte Program operation. Note that D7 must be read from the byte program address while

D6 can be read from any address.

To resume the operation of Sector Erase, the Resume command should be written. Any further writes of the

Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip

has resumed erasing.

WRITE OPERATIONS STATUS

Status

D7

0

D6

D5

D3

In Progress

Byte Programming in Embedded Algorithm

Embedded Erase Algorithm

Toggle

No Tog

Data

0

1

Erase

Erase Suspended Sector

1

0

1

Suspended Mode

Non-Erase Suspended Sector

Data

D7

0

Data

1

Data

0

Exceeded

Byte-Programming in Embedded Algorithm

Embedded Erase Algorithm

Toggle

Time Limits

1

Program in Erase Suspended Mode

D7

1

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MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

Operating Modes

The following modes are used to control the device.

OPERATION

CS

L

OE

L

WE

H

A0

X

A1

X

A6

X

A9

X

I /O

D_OUT

Read⁽¹⁾

Standby

H

L

X

High Z

Din

Output Disable

H

L

H

X

Write

L

A0

L

A1

H

A6

L

A9

V_ID

Verify Sector Protect

Auto-Select Device Unprotected Code

L

H

Code

L

H

L

1) L=V_IL, H=V_IH,X=Don't Care

NOTE:

1) WE can be V_ILif OE is V_IL, OE at V_IHinitiates write operation.

D7 Data Polling

The MFM8516 features Data Polling as a method to indicate to the host system that the Embedded Algo-

rithms are in progress or completed. During the Embedded Programming Algorithm, an attempt to read the

device will produce complement data of the data last written to D7. Upon completion of the Embedded Pro-

gramming Algorithm an attempt to read the device will produce the true data last written to D7. During the

Embedded Erase Algorithm, During the Embedded Erase Algorithm, an attempt to read the device will pro-

duce a "0" at the D7 output.

For chip erase, the Data Polling is valid after the rising edge of the six WE pulse in the six write pulse se-

quence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data

Polling must be performed at sector address within any of the sectors being erased or not a protected sector.

Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed,

the device data pins (D7) may change asynchronously while OE is asserted low. This means that the device is

driving status information on D7 at one instant of time and then that byte's valid data at the next instant of time.

Depending on when the system samples the D7 output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and D7 has a valid data, the data outputs on D0-D6 may

still be invalid. The valid data on D0-D7 will be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase

Algorithm, or sector erase time-out.

19

ISSUE 4.7 : NOVEMBER 1998

MFM8516 - 70/90/12/15

D6 Toggle Bit

The MFM8516 also features the "toggle bit" as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device

will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is

completed, D6 will stop toggling and valid data will be read on the next successive attempts. During program-

ming, the Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For

chip erase, the Toggle bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.

For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erare WE pulse. The Toggle Bit

is active during the sector time-out.

D5 Exceeding Time Limits

D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5will

produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only

operating function of the device under this condition. The CS circuit will partially power down the device under

these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions .

If this failure occurs during sector erase operations, it specifies that a particular sector is bad and may not be

re-used. The device must be reset to use other sectors. Write the reset command sequence and execute

program or erase command sequence. This allows the system to continue to use the other active sectors in

the device.

If this failure occurs during chip erase operation , it specifies that the device chip or combination of sectors

are bad.

If this failure occurs during the byte programming operation, it specifies that the entire sectors containing that

byte is bad and may not be re-used.

The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In

this case the device locks out and never completes the embedded algorithm operation. Hence the system

never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the

D5 bit will indicate '1'

D3 Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3

will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may

be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase

cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera-

tion is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional

sector erase commands. To insure the command has been accepted, the system software should check the

status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second

status check, the command may not have been accepted.

20

MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

DATA PROTECTION

The MFM8516 is designed to offer protection against accidental erasure or programming caused by spurious

system level signals that may exist during power transition. During power up the device automatically resets

the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up

and power down transitions or system noise.

Low V_ccWrite Inhibit

To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for

VCC<VLKO. When VCC<VLKO, the command register is disabled and all internal program/erase circuits are disa-

bled, and the device resets to the read mode. Subsequent writes will be ignored until the VCC>VLKO.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle

Logical Inhibit

Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE

must be logical zero while OE is a logical one.

Power Up Write Inhibit

Power-up of the device with WE = CS = VIL and OE = VIH will not accept commands on the rising edge of

WE. The internal state machine is automatically reset to the read mode on power-up.

Sector Protect

Sectors of the MFM8516 may be hardware protected at the users factory. The protection circuitry will disable

both program and erase functions for the protected sector(s). Requests to program or erase a protected sector

will be ignored by the device.

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Min

Typ

Max

Unit

Comments

Sector Erase Time

1

(Note 1)

8

15

sec

Excludes 00H programming

prior to erasure.

Chip Erase Time

120

1000

25

sec

µs

Excludes 00H programming

prior to erasure.

Byte Programming Time

Chip Programming Time

7

Excludes System-level overhead.

(Note 1)

3.6

sec

Excludes system-level overhead.

(Note 1) (Note 2)

Notes: (1) 25^OC, 5V V_CC, 10,000 cycles.

(2) The Embedded Algorithms allow for 2.5ms byte program time.

21

ISSUE 4.7 : NOVEMBER 1998

MFM8516 - 70/90/12/15

PACKAGEDETAILS

32 pin Ceramic Vertical in Line - 'V' Package

41.02 (1.615)

40.26 (1.585)

3.18 (0.125)

2.67 (0.105)

4.00 (0.157)

3.00 (0.117)

1.54 (0.060)

1.02 (0.040)

2.67 (0.105)

2.41 (0.095)

0.51 (0.020)

0.41 (0.016)

2.54 (0.100)

Minimum order product - Refer to factory

32 pin 0.6" Dual-In-Line (DIL) - 'S' Package

41.05 (1.615)

40.26 (1.585)

1.52 (0.060)

1.02 (0.040)

4.30 (0.170)

3.30 (0.130)

4.00 (0.157)

3.00 (0.117)

0.51 (0.020)

0.41 (0.016)

2.67 (0.105)

2.41 (0.095)

22

MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

PACKAGEDETAILS

32 Pin J-Leaded Chip Carrier (JLCC) - 'J' Package

0.71 (0.028) typ

1.27 (0.050) typ

1.90 (0.075)

1.65 (0.065)

11.70 (0.460)

11.30 (0.445)

No. 1 Index

0.43 (0.017)

typ

4.32 (0.170)

3.80 (0.150)

7.87 (0.310)

7.37 (0.290)

32 Pad Leadless Chip Carrier (LCC) - 'W' Package

1.27 (0.050) typ

0.64 (0.025) typ

11.70 (0.460)

2.03 (0.080)

11.30 (0.445)

max

No. 1 Index

1.27 (0.050)

typ

7.87 (0.310)

7.37 (0.290)

Minimum order product - Refer to factory

23

ISSUE 4.7 : NOVEMBER 1998

MFM8516 - 70/90/12/15

SCREENING

Military Screening Procedure

Component Screening Flow for high reliability product using methods from 5004.

MB COMPONENT SCREENING FLOW

SCREEN

TEST METHOD

LEVEL

Mechanical

Temperature cycle

Constant acceleration

Pre-Burn-in electrical

Burn-in

1010 Condition C (10 Cycles,-65^°C to +150^°C)

2001 Condition E (Y, only) (30,000g)

100%

Per applicable device specifications at T_A=+25^°C

Method 1015,Condition D,T_A=+125^°C,160hrs min

Endurance

As per internal specification

Write Cycle endurance and

Data Retention performance

Final Electrical Tests

Per applicable Device Specification

Static (dc)

a) @ T_A=+25^°C and power supply extremes

b) @ temperature and power supply extremes

100%

Functional

a) @ T_A=+25^°C and power supply extremes

b) @ temperature and power supply extremes

100%

Switching (ac)

a) @ T_A=+25^°C and power supply extremes

b) @ temperature and power supply extremes

100%

Percent Defective allowable (PDA)

Hermeticity

Calculated at post-burn-in at T_A=+25^°C

5%

1014

Fine

Gross

Condition A

Condition C

100%

External Visual

2009 Per vendor or customer specification

100%

24

MFM8516 - 70/90/12/15

ISSUE 4.7 : NOVEMBER 1998

ORDERING INFORMATION

MFM8516JMB - 90E

Write Cycle Endurance

Speed

E

= 100,000 cycles (min)

Blank = 10,000 cycles (min)

70

90

12

15

= 70 ns

= 90 ns

= 120 ns

= 150 ns

Temp. range/screening Blank = Commercial Temperature

I

M

= Industrial Temperature

= Military Temperature

MB = Processed in accordance with

MIL-STD-883

Packages

V

S

J

= 32 pin Ceramic Vertical in Line

= 32 pin Ceramic Dual In-line

= 32 pad Ceramic JLCC

W

= 32 pad Ceramic LCC

Organisation

Technology

8516 = 512Kx 8 Flash Memory

F

= FLASH Memory

Althoughthisdataisbelievedtobeaccuratetheinformationcontainedhereinisnotintendedtoanddoesnotcreate

any warranty of merchantability or fitness for a particular purpose.

Our Products are subject to a constant process of development. Data may be changed at any time without notice.

Products are not authorised for use as critical components in life support devices without the express approval of

a company director.

25


型号：	MFM8516WMB-15E
厂家：	MOSAIC
描述：	Flash, 512KX8, 150ns, CQCC32, CERAMIC, LCC-32 内存集成电路
文件：	总25页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MFM8516WMB-15E [MOSAIC]

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