MSM8128SX-10 [MOSAIC]
Standard SRAM, 128KX8, 100ns, CMOS, CDIP32, DIP-32;
| 型号： | MSM8128SX-10 |
| 厂家： | 
MOSAIC |
| 描述： | Standard SRAM, 128KX8, 100ns, CMOS, CDIP32, DIP-32 CD 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 8 SRAM
MSM8128 - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 4.4 : February 2000
Description
131,072 x 8 CMOS Static RAM
Features
Access Times of 70/85/100/120 ns
JEDEC standard Dual CS footprints.
The MSM8128 is a 1Mbit monolithic SRAM
organised as 128K x 8. It is currently available in
2 standard formats, with access times of 70, 85,
100, 120ns. It has a low power standby version
and has 3.0V battery backup capability. It is
directly TTL compatible and has common data
inputs and outputs.
Two pinout variants (single and dual CS) are
available.
All versions may be screened in accordance with
MIL-STD-883.
Operating Power
550 mW (max)
Low Power Standby (-L) 2.2 mW (max)
Low Voltage Data Retention.
Completely Static Operation
Directly TTL compatible.
May be processed in accordance with MIL-STD-883
Block Diagram
Pin Definition
VCC
A15
CS2
WE
A13
A8
1
2
3
4
5
32
31
30
29
28
27
26
NC
A16
A14
A12
A7
MEMORY ARRAY
512 X 2048
6
7
A6
A5
A9
A11
OE
A10
CS1
D7
D6
D5
D4
D3
8
9
TOP VIEW 25
A4
A3
A2
A1
A0
D0
D1
D2
S,V
24
10
11
12
13
14
15
16
23
22
21
20
19
18
17
GND
See Page 9 for SX, VX
Pin Functions
Package Details
A0-A16
D0-7
CS1
CS2
OE
Address Inputs
Data Input/Output
Chip Select 1
Chip Select 2
Output Enable
Write Enable
No Connect
Power (+5V)
Ground
Pin Count
Description
Package Type
32
0.6" Dual-in-Line (DIP)
S
WE
NC
VCC
GND
32
0.1" Vertical-in-LIne (VILTM)
V
Package details on pages 8 & 9.
MSM8128-70/85/10/12
Issue 4.4 : February 2000
DC OPERATING CONDITIONS
Absolute Maximum Ratings
Voltage on any pin relative to VSS
Power Dissipation
VT
-0.5V
-55
to
1
+7.0
V
PT
W
oC
Storage Temperature
TSTG
to
+150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) VT can be -3.0V pulse of less than 50ns.
Recommended Operating Conditions
min
typ
max
Supply Voltage
VCC
VIH
VIL
4.5
2.2
-0.3
0
5.0
5.5
5.8
0.8
70
V
V
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
-
V
o
TA
C
o
TAI
TAM
-40
-55
85
C (I suffix)
o
125
C (M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol Test Condition
min
typ
max Unit
Input Leakage Current
Output Leakage Current
ILI
VIH=0V to Vcc
-1
-1
-
-
1
1
µA
µA
Il/O
CS1=VIH, CS2 =VIL, VI/O=0V to Vcc ,OE=VIH
Average Supply Current
Standby Supply Current
ICC1 Min. Cycle, VIN=VIL or VIH
-
-
-
-
100 mA
mA
400 mA
ISB1
CS1=VIH,CS2 = VIL , I/P's static
3
-L Part
ISB2
CS1≥VCC-0.2V, 0.2V≥CS2≥VCC-0.2V , VIN ≥ 0.2V
-
-
Output Voltage
VOL IOL = 2.1 mA
VOH IOH = -1.0 mA
-
-
-
0.4
-
V
V
2.4
Capacitance (VCC=5V±10%,TA=25oC)
Parameter
Symbol
Test Condition
typ
max
Unit
I/P Capacitance
I/O Capacitance
CIN
VIN=0V
VI/O=0V
-
-
8
pF
pF
CI/O
10
Note: This parameter is sampled and not 100% tested.
2
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Operating Modes
The table below shows the logic inputs required to control the MSM8128 SRAM.
Mode
CS1 CS2 OE WE
VCC Current
I/O Pin Reference Cycle
Not Selected
Not Selected
Output Disable
Read
1
X
0
0
0
X
0
1
1
1
X
X
1
X
X
1
1
0
ISB1,ISB2
ISB,ISB1
ICC
High Z
High Z
High Z
DOUT
Power Down
Power Down
0
ICC
Read Cycle
Write Cycle
Write
X
ICC
DIN
1 = VIH,
0 = VIL,
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol Test Condition
VDR CS1 ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or
0V ≤ CS2 ≤ 0.2V. VIN ≥ 0V
min
typ
-
max Unit
VCC for Data Retention
2.0
-
V
Data Retention Current
ICCDR VCC=3.0V,VIN ≥ 0V, CS1 ≥VCC-0.2V,
CS2 ≥ VCC-0.2V or 0V ≤ CS2 ≤ 0.2V.
-
0
5
-
-
-
600
µA
ns
Chip Deselect to Data Retention tCDR
Operation Recovery Time tR
See Retention Waveform
See Retention Waveform
-
-
ms
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be ≥ VCC - 0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the
high impedance state.
AC Test Conditions
Output Load
I/O Pin
Ω
166
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
1.76V
30pF
3
MSM8128-70/85/10/12
Issue 4.4 : February 2000
AC OPERATING CONDITIONS
Read Cycle
70
85
10
12
Parameter
Symbol
min max min max min max min max Unit
Read Cycle Time
Address Access Time
Chip Select (CS1) Access Time(2)
Chip Select (CS2) Access Time(2)
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection (CS1) to Output in Low Z
Chip Selection (CS2) to Output in Low Z
Output Enable to Output in Low Z
Chip Disable (CS1) to Output in High Z(3)
Chip Disable (CS2) to Output in High Z(3)
Output Disable to Output in High Z(3)
tRC
tAA
tACS1
tACS2
tOE
70
-
-
-
-
-
85
-
-
-
-
-
100
-
-
-
-
10
10
10
5
0
0
-
100
100
100
50
-
-
-
-
120
-
-
-
-
10
10
10
5
0
0
-
ns
70
70
70
35
-
-
-
-
85
85
85
45
-
-
-
-
120 ns
120 ns
120 ns
60
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tOH
5
5
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
10
10
5
0
0
10
10
5
0
0
35
35
30
35
35
30
35
35
35
45
45
45
0
0
0
0
Write Cycle
70
85
10
12
Parameter
Symbol
min max min max min max min max Unit
Write Cycle Time
tWC
tCW
tAW
tAS
tWP
tWR1
tWR2
tWHZ
tDW
tDH
70
60
60
0
50
5
5
0
30
0
5
-
-
-
-
-
-
-
30
-
-
85
75
75
0
60
5
5
0
35
0
5
-
-
-
-
-
-
-
30
-
-
100
85
85
0
70
5
5
0
40
0
5
-
-
-
-
-
-
-
35
-
-
120
100
100
0
70
5
5
0
45
0
5
-
-
-
-
-
-
-
40
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time (WE, CS1)
(CS2)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
tOW
-
-
-
-
4
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Read Cycle Timing Waveform (1,2 )
t
RC
Address
t AA
OE
t OE
t
OH
t OLZ
t CLZ1
CS1
t ACS1 (2)
t
CHZ1 (3)
CS2
t ACS2 (2)
t CLZ2
tOHZ (3)
Data Valid
t CHZ2 (3)
Dout
Notes:
(1) WE is High for Read Cycle.
(2) Address valid prior to or coincident with CS1 transition low or CS2 high.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. At any given temperature and voltage condition, tCHZ max is less than
tCLZ min both for a given device and from device to device. This parameter is sampled and not 100% tested.
5
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Write Cycle No.1 Timing Waveform
tWC
Address
CS1
tWR1,2 (2)
t AW
t AS (3)
(6)
tCW (4)
(6)
CS2
OE
WE
t OHZ(3,9)
t WP(1)
High - Z
Dout
Din
tDH
tDW
Data Valid
Write Cycle No.2 Timing Waveform (5)
tWC
Address
CS1
t AW
tWR1,2 (2)
(6)
(6)
tCW (4)
CS2
tAS (3)
tWP (1)
tOH
WE
Dout
Din
tWHZ(3,9)
tOW
(7)
(8)
High - Z
tDH
tDW
High - Z
Data Valid
6
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Low VCC Data Retention Timing Waveform 1 (CS1 controlled)
Vcc
DATA RETENTION MODE
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS1≥Vcc-0.2V
CS1
0V
Low VCC Data Retention Timing Waveform 2 (CS2 controlled)
Vcc
DATA RETENTION MODE
4.5V
4.5V
tCDR
t R
CS2
VDR2
0.4V
CS2 0.2V
≤
0V
AC Characteristics Notes
(1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among
CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2
going low and WE going high. tWP is measured from the beginning of write to the end of write.
(2) tWR is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) Dout is in the same phase as written data of this write cycle.
(7) Dout is the read data of next address.
(8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be
applied to I/O pins.
(9) tWHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage
levels. These parameters are sampled and not 100% tested.
7
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Package Details
32 pin 0.6" Dual-in-Line (DIP) - 'S' Package
41.05 (1.615)
40.26 (1.585)
1.52 (0.060)
1.02 (0.040)
4.30 (0.170)
3.30 (0.130)
4.00 (0.157)
3.00 (0.117)
0.51 (0.020)
0.41 (0.016)
2.67 (0.105)
2.41 (0.095)
32 pin 0.1" Vertical-in-Line (VILTM) - 'V' Package
3.18 (0.125)
2.67 (0.105)
41.02 (1.615)
40.26 (1.585)
4.00 (0.157)
3.00 (0.117)
1.54 (0.060)
1.02 (0.040)
2.67 (0.105)
2.41 (0.095)
0.51 (0.020)
0.41 (0.016)
2.54 (0.100)
All dimensions in mm (inches).
8
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Alternate Pin Definition
NC
A16
A14
A12
A7
1
2
3
4
5
32
31
30
29
28
27
26
VCC
A15
NC
WE
A13
A8
A6
A5
6
7
A9
A4
A3
A2
A1
A0
D0
D1
D2
8
9
TOP VIEW 25
A11
OE
A10
CS
D7
D6
D5
D4
D3
VX,SX
24
23
22
21
20
19
18
17
10
11
12
13
14
15
16
GND
Military Screening Procedure
Component Screening Flow for high reliability product is in accordance with Mil-883 method 5004
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65oC to +150oC)
2001 Condition E (Y, only) (30,000g)
100%
100%
100%
100%
100%
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25oC
Method 1015,Condition D,TA=+125oC,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25oC and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Hermeticity
Calculated at post-burn-in at TA=+25oC
1014
5%
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
MSM8128-70/85/10/12
Issue 4.4 : February 2000
Ordering Information
MSM8128SLMB - 70
Speed
70 = 70 ns
85 = 85 ns
10 = 100 ns
12 = 120 ns
Temp. range/screening Blank = Commercial
I = Industrial
M = Military
MB = Screened in accordance
with MIL-STD-883.
Power Consumption
Package
Blank = Standard Power
L = Low Power
S = 32 pin 0.6" DIP
V = 32 pin 0.1" VIL
SX = 32 pin 0.6" DIP (Single CS)
VX = 32 pin 0.6" VIL (Single CS
Organisation
8128 = 128K x 8 SRAM
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subjected to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
10
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