MSM8512JL-025 [MOSAIC]
Standard SRAM, 512KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32;
| 型号： | MSM8512JL-025 |
| 厂家： | 
MOSAIC |
| 描述： | Standard SRAM, 512KX8, 25ns, CMOS, CQCC32, CERAMIC, LCC-32 静态存储器 |
| 文件： | 总8页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512K x 8 SRAM
MSM8512 - 020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.0 : January 1999
Description
524,288 x 8 CMOS Static RAM
The MSM8512 is a 4Mbit monolithic SRAM organised Features
as 512K x 8 with access times from 20ns to 35ns
• Fast Access Times of 020/025/35 ns
• High Density Packages.
• OperatingPower 950 mW (nom)
available. Thedeviceisavailableintwo32pinceramic
surface mount packages. The device has a low power
standby version which supports data retention mode
and is directly TTL compatible.
• StandbyPower
75 mW (nom) -L version
• Lowvoltagedataretention.
• Completely Static Operation
• DirectlyTTLcompatible
• May be processed in accordance with
MIL-STD-883C
All versions can be screened in accordance with MIL-
STD-883C.
Block Diagram
Pin Definition
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
4,194,304
BIT
20
18 17 16 15 14
19
MEMORY
ARRAY
D7
CS
21
22
23
24
25
26
27
28
29
D0
A0
A1
A2
A3
A4
A5
A6
A7
13
12
11
10
9
A10
OE
A11
A9
J / W
8
A8
7
D0
COLUMN I/O
I/O
BUFFER
A13
WE
6
COLUMN DECODER
5
D7
32
2 3 4
30
31
Y ADDRESS BUFFER
WE
OE
CS
PinFunctions
Package Details
A0~A18
D0~7
CS
AddressInputs
DataInput/Output
Chip Select
Output Enable
Write Enable
Power (+5V)
Ground
Pin Count
Descripion
Package Type
32
32
JLCCPackage
LCCPackage
J
OE
WE
VCC
GND
W
ISSUE1.0:January1999
MSM8512 - 020/025/30
DCOPERATINGCONDITIONS
Absolute Maximum Ratings (1)
(2)
Voltage on any pin relative to VSS
PowerDissipation
VT
-0.5
-55
to
1
+7.0
V
W
OC
PT
StorageTemperature
TSTG
to
+150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
min
4.5
2.2
-0.3
0
typ
max
5.5
6.0
0.8
70
unit
V
SupplyVoltage
5.0
InputHighVoltage
InputLowVoltage
OperatingTemperature
-
-
-
-
-
V
VIL
V
o
TA
C
o
TAI
-40
-55
85
C
(Isuffix)
o
TAM
125
C
(M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol TestCondition
min
typ
max Unit
InputLeakageCurrent
OutputLeakageCurrent
ILI
VIN=0VtoVCC
-2
-2
-
-
2
2
µA
µA
ILO
CS=VIH, VI/O=0VtoVCC, OE=VIHorWE=VIL
Operating SupplyCurrent ICC1 CS=VIL, VIN=VIH orVIL
II/O=0mA, min cycle, duty=100%
Min Cycle, CS=VIH
-L version only ISB1 CS≥VCC-0.2V, VIN≥VCC -0.2V or 0.2V≥VINf=0MHZ
-
-
-
-
-
185
65
mA
mA
mA
StandbySupplyCurrent
ISB
-
15
OutputVoltage
VOL IOL=8.0mA
VOH IOH=-4.0mA
-
-
-
0.4
-
V
V
2.4
Capacitance(VCC=5V±10%,TA=25°C)
Parameter
Symbol
TestCondition
typ
max
Unit
InputCapacitance:
I/OCapacitance:
CIN
VIN = 0V
VI/O= 0V
-
-
8
8
pF
pF
CI/O
Note : This parameter is sampled and not 100% tested.
ACTestConditions
Output Load
* Input pulse levels : 0V to 3.0V
* Input rise and fall times : 3ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
I/O Pin
166Ω
1.76V
30pF
2
MSM8512 - 020/025/35
ISSUE1.0 :January1999
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol TestCondition
min
typ
max
Unit
VCC for Data Retention
DataRetentionCurrent
Chip Deselect to Data Retention tCDR
VDR
ICCDR
CS≥VCC-0.2V
2.0
-
0
-
-
-
5.5
8
-
V
mA
ns
VCC=3.0V,CS≥VCC-0.2V,
See Retention Waveform
OperationRecoveryTime
tR
See Retention Waveform
5
-
-
ms
ACOPERATINGCONDITIONS
Read Cycle
20
min max
25
35
min max
Parameter
Symbol
min max
Units
ReadCycleTime
tRC
tAA
20
-
-
20
20
10
-
25
-
-
25
25
15
-
35
-
-
35
35
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
tACS
tOE
-
-
-
-
-
-
OutputHoldfromAddressChange
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z(3) tCHZ
Output Disable to Output in High Z(3) tOHZ
tOH
tCLZ
tOLZ
5
5
0
-
5
5
0
0
0
5
5
0
0
0
-
-
-
-
-
-
10
10
10
10
10
10
0
Write Cycle
20
min max
25
min max
35
min max
Parameter
Symbol
Unit
Write Cycle Time
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
20
15
15
0
15
0
0
10
0
-
-
-
-
-
-
10
-
-
-
25
15
15
0
15
0
0
10
0
-
-
-
-
-
-
10
-
-
-
35
15
15
0
15
0
0
10
0
-
-
-
-
-
-
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
WriteRecoveryTime
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
tOW
5
5
5
3
ISSUE1.0:January1999
MSM8512 - 020/025/30
Read Cycle Timing Waveform (1,2)
t
RC
Address
OE
t AA
tOE
t OH
t OLZ
tCLZ
CS
t ACS
t CHZ(3)
tOHZ(3)
High-Z
D0~7
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
t
Write Cycle No.1 Timing Waveform
tWC
Address
OE
t AS(3)
tAW
tCW(4)
tWR
(2)
(6)
CS
tWP(1)
WE
tOHZ(3,9)
tOW
tDH
High-Z
D0~7 out
D0~7 in
tDW
High-Z
4
MSM8512 - 020/025/35
ISSUE1.0 :January1999
Write Cycle No.2 Timing Waveform (5)
tWC
Address
CS
(4)
tCW
(6)
tAW
tWP(1)
tWR(2)
WE
tAS(3)
tOH
tWHZ(3,9)
tOW
(8)
(7)
High-Z
D0~7 out
tDW
tDH
High-Z
D0~7 in
ACCharacteristicsNotes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) IftheCSlowtransitionoccurssimultaneouslywiththeWElowtransitionoraftertheWElowtransition,outputs
remain in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. These parameters are sampled and not 100% tested.
Low VCC Data Retention Timing Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS>Vcc-0.2V
CS
0V
5
ISSUE1.0:January1999
MSM8512 - 020/025/30
Package Details
32 pin J Leaded Chip Carrier - 'J' Package
0.71 (0.028) typ
1.27 (0.050) typ
1.90 (0.075)
1.65 (0.065)
11.70 (0.460)
11.30 (0.445)
No. 1 Index
0.43 (0.017)
typ
4.32 (0.170)
3.80 (0.150)
7.87 (0.310)
7.37 (0.290)
All dimensions in mm (inches).
32 pad Leadless Chip Carrier (LCC) - 'W' Package
1.27 (0.050) typ
0.64 (0.025) typ
11.70 (0.460)
2.03 (0.080)
11.30 (0.445)
max
No. 1 Index
1.27 (0.050)
typ
7.87 (0.310)
7.37 (0.290)
Note : Minimum Order Product - Consult Factory for Details
All dimensions in mm (inches).
MSM8512 - 020/025/35
ISSUE1.0 :January1999
Military Screening Procedure
Screening Flow for high reliability product in accordance with MIL-STD-883 method 5004 is shown below.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition E (Y, only) (30,000g)
100%
100%
100%
100%
100%
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Hermeticity
Calculated at post-burn-in at TA=+25°C
5%
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
7
ISSUE1.0:January1999
MSM8512 - 020/025/30
Ordering Information
MSM8512JLMB - 020
Speed
020
025
35
=
=
=
25ns
25ns
35ns
Temp.Range/Screening Blank
=
=
=
=
Commercial
Industrial
Military
Screened in accordance with
MIL-STD-883
I
M
MB
PowerConsumption
Package
Blank
L
=
=
StandardPower
LowPower
J
W
=
=
32pinJLCC
32 pin LCC
MemoryOrganisation
8512
=
512K x 8 SRAM
Note:
Although this data is believed to be accurate, the information contained herein, is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
8
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