PUMA84SV32000-015 [MOSAIC]
SRAM Module, 1MX32, 15ns, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | PUMA84SV32000-015 |
| 厂家： | 
MOSAIC |
| 描述： | SRAM Module, 1MX32, 15ns, CMOS, PQCC84, PLASTIC, LCC-84 静态存储器 |
| 文件： | 总11页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1x32SaticRAM
PUMA 84SV32000 - 012/015/020
Issue 5.0 February 2000
Description
Block Diagram
The PUMA 84 range of devices provide a high
density, surface mount memory solution with
density up to twice that of standard monolithic
devices.
A0 ~A18
/WE
/OE
512K x 8
SRAM
512K x 8
SRAM
D0 ~ 7
/CS1
D0 ~ 7
/CS5
The PUMA 84 may accomodate various memory
technologies including SRAM, FLASH and
EEPROM. The devices are designed to offer a
definedupgradepathandmaybeuserconfiguredas
8, 16 or 32 bits wide using eight Chip Selects
(/CS1~8).
512K x 8
SRAM
512K x 8
SRAM
D8 ~ 15
/CS2
D8 ~ 15
/CS6
The PUMA84SV32000 is a 1Mx32 SRAM module
housed in a JEDEC 84 pin surface mount J-leaded
PLCC.Accesstimesof12,15or20nsareavailable.
The 3.3V low voltage device is available to
commercialandindustrialtemperaturegrade.
512K x 8
SRAM
512K x 8
SRAM
D16 ~ 23
/CS3
D16 ~ 23
/CS7
512K x 8
SRAM
512K x 8
SRAM
D24 ~ 31
/CS4
D24 ~ 31
/CS8
The-Lversionhasdataretentioncapabilityandcan
be used in battery backup applications.
Features
Pin Definition
• Access times of 12/15/20 ns.
See page 2.
• 3.3V + 10%.
• ComercialandIndustrialtemperaturegrades
• JEDEC 84 ‘J’ Leaded surface mount package.
• Industrystandardpinout.
• May be organised as 1M x 32, 2M x 16 and 4M X 8
Pin Functions
• OperatingPower
(32 Bit) 3.53W (max)
• Lowpowerstandby. (CMOS) 360mW (max)
• Lowvoltagedataretentionmode.
• Completely Static Operation.
Description
Signal
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
A0~A18
D0~D31
/CS1~8
/WE
Package Details
/OE
NC
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
Max. Dimensions - 30.35 x 30.35 x 8.50 (max)
All Dimensions in mm.
VCC
Ground
GND
11403 West Bernardo Court, Suite 100, San Diego, CA92127.
TEL (001) 858 674 2233, Fax No. (001) 858 674 2230 E-mail: sales@mosaicsemi.com
Pin Definition - PUMA84SV32000
Pin
1
Signal
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
VCC
A13
A12
A11
A10
A9
VCC
NC
2
3
/CS1
/CS2
/CS3
/CS4
A17
A18
D16
NC
4
5
6
7
A8
8
A7
9
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
NC
NC
NC
NC
NC
NC
D17
D18
D19
VSS
D1
D2
D3
VSS
D20
D21
D22
D23
VCC
D24
D25
D26
D27
VSS
D4
D5
D6
D7
VCC
D8
D9
D10
D11
VSS
D28
D29
D30
NC
D12
D13
D14
NC
NC
NC
NC
D15
A14
A15
A16
/WE
/OE
/CS5
/CS6
/CS7
/CS8
NC
D31
A6
A5
A4
A3
A2
A1
A0
Issue 5.0 February 2000
PAGE 2
Absolute Maximum Ratings(1)
DOperagCdtions
Parameter
Symbol
Min
-0.5
Max
+4.6
Unit
V
(2)
Voltage on any pin relative to VSS
Power Dissipation
VT
to
4.0
to
PT
W
Storage Temperature
TSTG
-55
+125
OC
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
(2) VT can be -2.0V pulse of less than 8ns
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Min
3.0
2.0
-0.3
0
Typ
Max
3.6
Unit
V
Supply Voltage
3.3
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
VCC+0.3
0.8
V
VIL
V
TA
70
OC
OC
TAI
-40
85
(I Suffix)
Notes : (1) Pulse Width : -2.0V for less than 10ns.
DC Electrical Characteristics
(VCC=3.3V+10%, TA=-40OC to +85OC)
Parameter
Symbol Test Condition
Min Typ Max Unit
µ
Address, /OE, /WE
Input Leakage Current
ILI
0V < VIN < VCC
-20
-20
-
-
20
20
A
/CS=VIH,VI/O = GND to
VCC
µ
A
Output Leakage Current
ILO
Min Cycle /CS(2)=VIL,
f=fmax, IOUT=0mA
Average Supply Current(1)
Standby Supply Current
32 Bit ICC32
-
-
980
mA
16 Bit ICC16 As Above.
-
-
-
-
-
-
690
545
400
mA
mA
mA
8 Bit
TTL
ICC8
ISB
As Above.
/CS=VIH , f=fmax
/CS>VCC-0.2V, 0.2
<VIN<VCC-0.2V, f=0
CMOS ISB1
-
-
100
mA
Output Voltage Low
Output Voltage High
VOL
VOH
IOL=8.0mA
IOH=-4.0mA
-
-
-
0.4
-
V
V
2.4
Notes (1) Typical values are at VCC=3.3V, TA=25OC and specified loading.
(2) /CS above refers to /CS1~4 for 16 Bit mode and /CS5~8 for 32 bit mode.
(3) At f=fMAX address and data inputs are cycling at max frequency.
Issue 5.0 February 2000
PAGE 3
Capacitance
(VCC = 3.3V + 10%, TA = 25OC)
Parameter
Symbol Test Condition Min Typ Max Unit
Address, /OE, /WE
Input Capacitance
Input Capacitance
Output Capacitance
CIN1
CIN2
CI/O
VIN=0V
VIN=0V
VI/O=0V
-
-
-
-
-
-
70
12
70
pF
pF
pF
(Other)
8 bit mode (worst case)
Note : These Parameters are calculated not measured.
Test Conditions
Output Load
166Ω
I/O Pin
• Input pulse levels : 0V to 3.0V
• Input rise and fall times : 3ns
• Input and Output timing reference levels : 1.5V
• Output Load : See Load Diagram.
• VCC = 3.3V+10%
1.76V
30pF
Operation Truth Table
/CS
H
L
/OE
X
/WE
X
Data Pins
Supply Current
Mode
Standby
Read
High Impedance
Data Out
ISB,ISB1
L
H
ICC32,ICC16,ICC8
ICC32,ICC16,ICC8
ICC32,ICC16,ICC8
ISB,ISB1
L
H
L
Data In
Write
L
L
L
Data In
Write
L
H
H
High Impedance
High Z
Notes : H = VIH : L = VIL : X = VIH or VIL
The above table reflects the operation of each of the RAMS on the module. Care should be taken to avoid
bus contention on data lines using chip select signals.
Issue 5.0 February 2000
PAGE 4
AOperagCdtions
Read Cycle
012
015
020
Parameter
Symbol Min Max Min Max Min Max Units
Read Cycle Time
tRC
12
-
-
12
12
6
15
-
-
15
15
7
20
-
-
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold From Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
-
-
-
tOH
3
3
0
0
0
-
3
3
0
0
0
-
3
3
0
0
0
-
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
6
7
9
6
7
9
Write Cycle
012
015
020
Parameter
Symbol Min Max Min Max Min Max Units
Write Cycle Time
tWC
tCW
tAW
tAS
12
10
10
0
-
-
-
-
-
-
-
6
-
-
-
15
12
12
0
-
-
-
-
-
-
-
7
-
-
-
20
15
15
0
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
tWP
tWP
tWR
tWHZ
tDW
tDH
10
12
0
12
15
0
12
20
0
Write Pulse Width (/OE Low)
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold time from Write Time
Output Active from End of Write
0
0
0
6
7
9
0
0
0
tOW
3
3
3
Issue 5.0 February 2000
PAGE 5
Read Cycle 1
TingWaveforms
(Address Controlled, /CS=/OE=VIL, /WE=VIH)
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
Read Cycle 2
(/WE = VIH)
tRC
Address
/CS
tAA
tCO
tHZ(3,4,5)
tOHZ
tOE
/OE
tOLZ
tOH
tLZ(4,5)
Valid Data
Data Out
tPU
tPD
50%
ICC
ISB
VCC
50%
Current
(READ CYCLE)
NOTES
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
OL levels.
V
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
±
6. Device is continuously selected with /CS=VIL.
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Issue 5.0 February 2000
PAGE 6
Write Cycle 1
(/OE = Clock)
tWC
Address
tAW
tWR(5)
/OE
/CS
tCW(3)
tAS(4)
tWP(2)
/WE
Data In
tDW
tDH
High Z
Valid Data
tOHZ(6)
High Z(8)
Data Out
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Issue 5.0 February 2000
PAGE 7
Write Cycle 2
(/OE = Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
/CS
/WE
tAS(4)
tWP(2)
tDW
tDH
High Z
Data In
Data Out
Valid Data
tOW
tWHZ(6)
(10)
(9)
High Z(8)
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Issue 5.0 February 2000
PAGE 8
Write Cycle 3
(/CS = Controlled)
tWC
Address
/CS
tAW
tWR(5)
tCW(3)
tAS(4)
tWP(2)
/WE
Data In
tDW
tDH
High Z
High Z
High Z
Valid Data
tLZ
tWHZ(6)
High Z(8)
Data Out
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Data Retention
tSDR
tRDR
Data Retention Mode
/CS Controlled
VCC
3.0V
2.2V
VDR
/CS>VCC - 0.2V
/CS
GND
Note: /CS = /CS1~4
Issue 5.0 February 2000
PAGE 9
PckgDetails
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
30.20 (1.189)
29.95 (1.179)
8.90
(0.350)
max
0.89
(0.035)
typ.
1.27
0.46
(0.050) typ
(0.018) typ
29.20 (1.150)
28.20 (1.110)
PAGE 10
Issue 5.0 February 2000
Ordering Information
OdegIfrmation
PUMA 84SV32000LI-012
Speed
012 = 12ns
015 = 15ns
020 = 20ns
Temp.Range/Screening Blank = Commercial
I = Industrial
PowerConsumption
Blank = Standard
L = LowPower
MemoryOrganisation
32000 = 1M x 32 configurable
as 2M x 16 and 4M x 8
Technology
Package
SV = SRAM 3.3V+10% VCC
PUMA 84 = Plastic 84 ‘J’ Leaded
Package.
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
PAGE 11
http://www.mosaicsemi.com/
Issue 5.0 February 2000
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