SYS161000FKX-85 [MOSAIC]
SRAM Module, 1MX16, 85ns, CMOS, PDIP44, PLASTIC, DIP-44;型号: | SYS161000FKX-85 |
厂家: | MOSAIC |
描述: | SRAM Module, 1MX16, 85ns, CMOS, PDIP44, PLASTIC, DIP-44 静态存储器 光电二极管 |
文件: | 总7页 (文件大小:120K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1M x 16 SRAM MODULE
SYS161000FKX - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.4 : January 1999
Description
Features
•
•
•
•
Access Times of 70/85/100/120 ns.
44 pin DIL Package.
The SYS161000FKX is a plastic 16Mbit Static
RAM Module in a 44 pin DIP package. The module
utilises four 512Kx8 SRAMs housed in TSOPII
packages, surface mounted onto an FR4 epoxy
substrate. The RAMs are organised as two banks
of 512Kx16 each. The upper address line is used
to select one of the two banks, and using LB and
UB as two extra chip select functions for Lower
Byte and Upper Byte control, respectively.
5 Volt Supply ± 10%
Power Dissipation:
Operating
1.20 W (Max.)
Standby -L Version (CMOS) 2.64 mW (Max.)
Completely Static Operation.
•
•
•
•
Low Voltage VCC Data Retention.
On-board Supply Decoupling Capacitors.
Provides upgrade from JEDEC Standard 64Kx16
40 pin modules..
The module is completely asynchronous, static
design requiring no clocks or refreshing.
Block Diagram
Pin Definition
A0 - A18
D8-D15
A17
A16
A15
CS
D15
D14
D13
D12
D11
D10
D9
D8
GND
D7
D6
D5
1
2
3
4
5
6
7
8
A19
A18
Vcc
WE
UB
LB
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
D0 - D7
WE
OE
512K X 8
SRAM
512K X 8 512K X 8 512K X 8
SRAM
SRAM
SRAM
9
10
CS
CS
CS
CS
11TOP VIEW
12
13
14
15
16
17
18
19
20
21
22
LB
UB
A19
DECODER
CS
D4
D3
D2
D1
D0
OE
A4
A3
A2
A1
Pin Functions
A0
Address Inputs
A0 - A19
D0 - D15
CS
Data Input/Output
Chip Select
Write Enable
WE
Package Details
Lower Byte Enable
Upper Byte Enable
Output Enable
Power (+5V)
LB
UB
Plastic 44 Pin Dual-In-Line (DIP)
OE
VCC
Ground
GND
ISSUE 1.4 January 1999
SYS161000FKX - 70/85/10/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
Min
Typ
Max
Unit
Voltage on any pin relative to VSS
Power Dissipation
VT(2)
PT
-0.3
-
-
-
-
7.0
2.0
125
V
W
oC
Storage Temperature
TSTG
-55
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) VT can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VIH
VIL
TA
4.5
2.2
-0.3
0
5.0
5.5
VCC+0.3
0.8
V
V
Input High Voltage
Input Low Voltage
Operating Temperature (Commercial)
(Industrial)
-
-
-
-
V
70
oC
oC
TAI
-40
85
DC Electrical Characteristics
(VCC=5V±10%)
TA 0 to 70 oC
Parameter
Symbol Test Condition
Min Typ max Unit
I/P Leakage Current
Address,OE,WE ILI
0V < VIN < VCC
CS = VIH, VI/O = GND to VCC
-4
-2
-
-
-
-
-
-
-
-
-
4
2
µA
µA
Output Leakage Current
ILO
Operating Supply Current 16-bitmode ICC1 Min. Cycle, CS = VIL,VIL<VIN<VIH
215 mA
Standby Supply Current
TTLlevels ISB1
CS = VIH
-
20
8
mA
mA
CMOSlevels ISB2
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V
-
-L Version (CMOS) ISB3
-
480 mA
Output Voltage
VOL IOL = 8.0mA
VOH IOH = -4.0mA
-
0.4
-
V
V
2.4
Typical values are at VCC=5.0V,TA=25oC and specified loading.
Capacitance (VCC=5V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Symbol Test Condition
max
Unit
Input Capacitance (Address,OE,WE)
I/P Capacitance (other)
I/O Capacitance
CIN1 VIN = 0V
CIN2 VIN = 0V
CI/O VI/O = 0V
48
12
24
pF
pF
pF
2
SYS161000FKX - 70/85/10/12
ISSUE 1.4 January 1999
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
I/O Pin
Ω
645
1.76V
100pF
* VCC=5V±10%
Operation Truth Table
CS
UB
LB
OE
WE
DATA PINS
SUPPLY CURRENT
MODE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
L
X
X
L
X
X
L
High Impedance
High Impedance
D0-15 IN
ISB1 , ISB2 , ISB3 , ISB4
ISB1 , ISB2 , ISB3 , ISB4
ICC1 / 2
Standby
Standby
Write
L
L
L
H
L
D0-15 OUT
D0-15 IN
ICC1 / 2
Read
L
L
H
H
L
ICC1 / 2
Write
L
L
H
L
High-Impedance
D0-7 IN
ICC1
High-Z
H
H
H
H
L
L
ICC1 / 2
Write LB
Read LB
Write LB
High-Z
L
L
H
L
D0-7 OUT
ICC1 / 2
L
H
H
L
D0-7 IN
ICC1 / 2
L
H
L
High-Impedance
D8-15 IN
ICC1 / 2
H
H
H
H
ICC1 / 2
Write UB
Read UB
Write UB
High-Z
L
L
H
L
D8-15 OUT
D8-15 IN
ICC1 / 2
L
H
H
ICC1 / 2
L
H
High-Impedance
ICC1 / 2
Notes : H = VIH : L =VIL : X = VIH or VIL
Low Vcc Data Retention Characteristics - L & P Version's Only.
Parameter
Symbol Test Condition
min typ(1) max Unit
VCC for Data Retention
VDR
ICCDR1
tCDR
tR
CS>VCC-0.2V
2.0
-
-
-
V
(2)
Data Retention Current -L Version
CS High to Data Retention Time
Operation Recovery Time
VCC=3.0V, VIN>0, CS>VCC-0.2V
See Retention Waveform
See Retention Waveform
280 mA
0
-
-
-
-
ns
5
ms
Notes (1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
ISSUE 1.4 January 1999
SYS161000FKX - 70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-70
-85
-10
-12
Parameter
Symbol min max min max min max min max Unit
Read Cycle Time
tRC
70
-
-
85
-
-
100
-
-
100
100
50
-
120
-
-
120
120
55
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
70
70
35
-
85
85
45
-
CS, LB, UB Access Time
tACS
tOE
-
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-
-
-
-
tOH
10
10
5
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
-
-
0
30
25
0
35
30
0
40
35
0
45
40
0
0
0
0
Write Cycle
-70
-85
-10
-12
Parameter
Symbol min max min max min max min max Unit
Write Cycle Time
tWC
tCW
tAW
tAS
70
60
60
0
-
-
85
75
75
0
-
-
100
80
80
0
-
-
120
90
90
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS, LB, UB to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
-
-
-
-
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
50
5
-
55
5
-
70
5
-
80
5
-
Write Recovery Time
-
-
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
0
30
-
0
30
-
0
35
-
0
40
-
30
0
35
0
40
0
45
0
-
-
-
-
tOW
5
-
5
-
5
-
5
-
4
SYS161000FKX - 70/85/10/12
ISSUE 1.4 January 1999
Read Cycle Timing Waveform (1,2)
t RC
Address
tAA
OE
CS,LB,UB
Dout
tOE
tOLZ
tOH
Don't
care.
tACS
tCLZ (4,5)
tOHZ (3)
Data Valid
tCHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
tWR(7)
tAS(6)
OE
tAW
tCW
CS,LB,UB
Don't
Care
WE
tOHZ(3,9)
tOW
tWP(2)
(8)
High-Z
Dout
Din
tDW
Data Valid
tDH
High-Z
5
ISSUE 1.4 January 1999
SYS161000FKX - 70/85/10/12
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
tAS(6)
tWR(7)
tCW
CS,LB,UB
tAW
tWP(2)
WE
tOH
Don't
Care
tWHZ(3,9)
tOW
(4)
(8)
High-Z
Dout
tDH
tDW
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS/LB/UB and WE low.
(3) If OE, CS/LB/UB, and WE are in the Read mode during this period, the I/O pins are low impedance
state. Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS/LB/UB and WE low, too avoid inadvertant writes.
(7) CS/LB/UB or WE must be high during address transitions.
(8) When CS/LB/UB is low : I/O pins are in the output state. Input signals of opposite phase leading to
the output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS > Vcc -0.2V
CS
0V
6
SYS161000FKX - 70/85/10/12
ISSUE 1.4 January 1999
Package Information
Dimensions in mm
Plastic 44 Pin 0.6" Dual-In-Line (DIP)
56.00 MAX
15.92 MAX
15.24 TYP.
2.54 TYP.
Ordering Information
SYS161000FKXLI - 70
Speed
70 = 70 ns
85 = 85 ns
10 = 100 ns
12 = 120 ns
Temperature range
Power Consumption
Blank = Commercial Temp.
I = Industrial Temp.
Blank = Standard Part
L = Low Power Part
Package
FKX = Plastic 44 Pin DIP
161000 = 1M x 16
Organisation
Memory Type
SYS = Static RAM
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
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